<div dir="ltr"><div class="gmail_quote"><div>Really sorry, as this is a great improvement, but we've found a regression caused by it. Well, more likely uncovered by it, but the crux of the issue is the same.</div><div><br></div><div>I've filed <a href="http://llvm.org/PR33833">http://llvm.org/PR33833</a> with a minimal test case.</div><div><br></div><div>I've temporarily reverted in r308271 while you investigate. If you need any more details, don't hesitate to reach out.</div><div><br></div><div>-Chandler</div><div><br></div><div dir="ltr">On Fri, Jul 14, 2017 at 6:56 AM Nirav Dave via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: niravd<br>
Date: Fri Jul 14 06:56:21 2017<br>
New Revision: 308025<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=308025&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=308025&view=rev</a><br>
Log:<br>
Improve Aliasing of operations to static alloca<br>
<br>
Recommiting after adding check to avoid miscomputing alias information<br>
on addresses of the same base but different subindices.<br>
<br>
Memory accesses offset from frame indices may alias, e.g., we<br>
may merge write from function arguments passed on the stack when they<br>
are contiguous. As a result, when checking aliasing, we consider the<br>
underlying frame index's offset from the stack pointer.<br>
<br>
Static allocs are realized as stack objects in SelectionDAG, but its<br>
offset is not set until post-DAG causing DAGCombiner's alias check to<br>
consider access to static allocas to frequently alias. Modify isAlias<br>
to consider access between static allocas and access from other frame<br>
objects to be considered aliasing.<br>
<br>
Many test changes are included here. Most are fixes for tests which<br>
indirectly relied on our aliasing ability and needed to be modified to<br>
preserve their original intent.<br>
<br>
The remaining tests have minor improvements due to relaxed<br>
ordering. The exception is CodeGen/X86/2011-10-19-widen_vselect.ll<br>
which has a minor degradation dispite though the pre-legalized DAG is<br>
improved.<br>
<br>
Reviewers: rnk, mkuper, jonpa, hfinkel, uweigand<br>
<br>
Reviewed By: rnk<br>
<br>
Subscribers: sdardis, nemanjai, javed.absar, llvm-commits<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D33345" rel="noreferrer" target="_blank">https://reviews.llvm.org/D33345</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/alias-static-alloca.ll<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll<br>
llvm/trunk/test/CodeGen/AArch64/arm64-vext.ll<br>
llvm/trunk/test/CodeGen/AArch64/dag-combine-invaraints.ll<br>
llvm/trunk/test/CodeGen/AArch64/swifterror.ll<br>
llvm/trunk/test/CodeGen/ARM/atomic-op.ll<br>
llvm/trunk/test/CodeGen/MSP430/vararg.ll<br>
llvm/trunk/test/CodeGen/Mips/dins.ll<br>
llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll<br>
llvm/trunk/test/CodeGen/X86/clobber-fi0.ll<br>
llvm/trunk/test/CodeGen/X86/hipe-cc.ll<br>
llvm/trunk/test/CodeGen/X86/hipe-cc64.ll<br>
llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll<br>
llvm/trunk/test/CodeGen/X86/machine-outliner-debuginfo.ll<br>
llvm/trunk/test/CodeGen/X86/machine-outliner.ll<br>
llvm/trunk/test/CodeGen/X86/statepoint-invoke.ll<br>
llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll<br>
llvm/trunk/test/CodeGen/X86/statepoint-vector.ll<br>
llvm/trunk/test/CodeGen/X86/widen_arith-2.ll<br>
llvm/trunk/test/CodeGen/X86/widen_cast-4.ll<br>
llvm/trunk/test/CodeGen/XCore/varargs.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Jul 14 06:56:21 2017<br>
@@ -11375,12 +11375,8 @@ SDValue DAGCombiner::visitLOAD(SDNode *N<br>
SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),<br>
MVT::Other, Chain, ReplLoad.getValue(1));<br>
<br>
- // Make sure the new and old chains are cleaned up.<br>
- AddToWorklist(Token.getNode());<br>
-<br>
- // Replace uses with load result and token factor. Don't add users<br>
- // to work list.<br>
- return CombineTo(N, ReplLoad.getValue(0), Token, false);<br>
+ // Replace uses with load result and token factor<br>
+ return CombineTo(N, ReplLoad.getValue(0), Token);<br>
}<br>
}<br>
<br>
@@ -16705,6 +16701,20 @@ bool DAGCombiner::isAlias(LSBaseSDNode *<br>
if (BasePtr0.equalBaseIndex(BasePtr1, DAG, PtrDiff))<br>
return !((NumBytes0 <= PtrDiff) || (PtrDiff + NumBytes1 <= 0));<br>
<br>
+ // If both BasePtr0 and BasePtr1 are FrameIndexes, we will not be<br>
+ // able to calculate their relative offset if at least one arises<br>
+ // from an alloca. However, these allocas cannot overlap and we<br>
+ // can infer there is no alias.<br>
+ if (auto *A = dyn_cast<FrameIndexSDNode>(BasePtr0.getBase()))<br>
+ if (auto *B = dyn_cast<FrameIndexSDNode>(BasePtr1.getBase())) {<br>
+ MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();<br>
+ // If the base are the same frame index but the we couldn't find a<br>
+ // constant offset, (indices are different) be conservative.<br>
+ if (A != B && (!MFI.isFixedObjectIndex(A->getIndex()) ||<br>
+ !MFI.isFixedObjectIndex(B->getIndex())))<br>
+ return false;<br>
+ }<br>
+<br>
// FIXME: findBaseOffset and ConstantValue/GlobalValue/FrameIndex analysis<br>
// modified to use BaseIndexOffset.<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll Fri Jul 14 06:56:21 2017<br>
@@ -11,9 +11,8 @@ define void @fn9(i32* %a1, i32 %a2, i32<br>
; CHECK: add {{x[0-9]+}}, [[ARGS]], #8<br>
; First vararg<br>
; CHECK: ldr {{w[0-9]+}}, [sp, #72]<br>
-; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #8<br>
; Second vararg<br>
-; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]<br>
+; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}], #8<br>
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #8<br>
; Third vararg<br>
; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-abi_align.ll Fri Jul 14 06:56:21 2017<br>
@@ -280,10 +280,10 @@ entry:<br>
define i32 @caller42() #3 {<br>
entry:<br>
; CHECK-LABEL: caller42<br>
-; CHECK: str {{x[0-9]+}}, [sp, #48]<br>
-; CHECK: str {{q[0-9]+}}, [sp, #32]<br>
-; CHECK: str {{x[0-9]+}}, [sp, #16]<br>
-; CHECK: str {{q[0-9]+}}, [sp]<br>
+; CHECK-DAG: str {{x[0-9]+}}, [sp, #48]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #32]<br>
+; CHECK-DAG: str {{x[0-9]+}}, [sp, #16]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp]<br>
; CHECK: add x1, sp, #32<br>
; CHECK: mov x2, sp<br>
; Space for s1 is allocated at sp+32<br>
@@ -318,10 +318,10 @@ entry:<br>
; CHECK-LABEL: caller42_stack<br>
; CHECK: sub sp, sp, #112<br>
; CHECK: add x29, sp, #96<br>
-; CHECK: stur {{x[0-9]+}}, [x29, #-16]<br>
-; CHECK: stur {{q[0-9]+}}, [x29, #-32]<br>
-; CHECK: str {{x[0-9]+}}, [sp, #48]<br>
-; CHECK: str {{q[0-9]+}}, [sp, #32]<br>
+; CHECK-DAG: stur {{x[0-9]+}}, [x29, #-16]<br>
+; CHECK-DAG: stur {{q[0-9]+}}, [x29, #-32]<br>
+; CHECK-DAG: str {{x[0-9]+}}, [sp, #48]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #32]<br>
; Space for s1 is allocated at x29-32 = sp+64<br>
; Space for s2 is allocated at sp+32<br>
; CHECK: add x[[B:[0-9]+]], sp, #32<br>
@@ -388,10 +388,10 @@ entry:<br>
define i32 @caller43() #3 {<br>
entry:<br>
; CHECK-LABEL: caller43<br>
-; CHECK: str {{q[0-9]+}}, [sp, #48]<br>
-; CHECK: str {{q[0-9]+}}, [sp, #32]<br>
-; CHECK: str {{q[0-9]+}}, [sp, #16]<br>
-; CHECK: str {{q[0-9]+}}, [sp]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #48]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #32]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #16]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp]<br>
; CHECK: add x1, sp, #32<br>
; CHECK: mov x2, sp<br>
; Space for s1 is allocated at sp+32<br>
@@ -430,10 +430,10 @@ entry:<br>
; CHECK-LABEL: caller43_stack<br>
; CHECK: sub sp, sp, #112<br>
; CHECK: add x29, sp, #96<br>
-; CHECK: stur {{q[0-9]+}}, [x29, #-16]<br>
-; CHECK: stur {{q[0-9]+}}, [x29, #-32]<br>
-; CHECK: str {{q[0-9]+}}, [sp, #48]<br>
-; CHECK: str {{q[0-9]+}}, [sp, #32]<br>
+; CHECK-DAG: stur {{q[0-9]+}}, [x29, #-16]<br>
+; CHECK-DAG: stur {{q[0-9]+}}, [x29, #-32]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #48]<br>
+; CHECK-DAG: str {{q[0-9]+}}, [sp, #32]<br>
; Space for s1 is allocated at x29-32 = sp+64<br>
; Space for s2 is allocated at sp+32<br>
; CHECK: add x[[B:[0-9]+]], sp, #32<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll Fri Jul 14 06:56:21 2017<br>
@@ -1,10 +1,8 @@<br>
; RUN: llc -mtriple=arm64-eabi -mcpu=cyclone < %s | FileCheck %s<br>
<br>
; CHECK: foo<br>
-; CHECK: str w[[REG0:[0-9]+]], [x19, #264]<br>
-; CHECK: mov w[[REG1:[0-9]+]], w[[REG0]]<br>
-; CHECK: str w[[REG1]], [x19, #132]<br>
-<br>
+; CHECK-DAG: str w[[REG0:[0-9]+]], [x19, #132]<br>
+; CHECK-DAG: str w[[REG0]], [x19, #264]<br>
define i32 @foo(i32 %a) nounwind {<br>
%retval = alloca i32, align 4<br>
%a.addr = alloca i32, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-vext.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vext.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vext.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/arm64-vext.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/arm64-vext.ll Fri Jul 14 06:56:21 2017<br>
@@ -116,7 +116,7 @@ define void @test_vext_p16() nounwind ss<br>
<br>
define void @test_vext_s32() nounwind ssp {<br>
; CHECK-LABEL: test_vext_s32:<br>
- ; CHECK: {{ext.8.*#4}}<br>
+ ; CHECK: {{rev64.2s.*}}<br>
%xS32x2 = alloca <2 x i32>, align 8<br>
%__a = alloca <2 x i32>, align 8<br>
%__b = alloca <2 x i32>, align 8<br>
@@ -137,7 +137,7 @@ define void @test_vext_s32() nounwind ss<br>
<br>
define void @test_vext_u32() nounwind ssp {<br>
; CHECK-LABEL: test_vext_u32:<br>
- ; CHECK: {{ext.8.*#4}}<br>
+ ; CHECK: {{rev64.2s.*}}<br>
%xU32x2 = alloca <2 x i32>, align 8<br>
%__a = alloca <2 x i32>, align 8<br>
%__b = alloca <2 x i32>, align 8<br>
@@ -158,7 +158,7 @@ define void @test_vext_u32() nounwind ss<br>
<br>
define void @test_vext_f32() nounwind ssp {<br>
; CHECK-LABEL: test_vext_f32:<br>
- ; CHECK: {{ext.8.*#4}}<br>
+ ; CHECK: {{rev64.2s.*}}<br>
%xF32x2 = alloca <2 x float>, align 8<br>
%__a = alloca <2 x float>, align 8<br>
%__b = alloca <2 x float>, align 8<br>
@@ -179,7 +179,7 @@ define void @test_vext_f32() nounwind ss<br>
<br>
define void @test_vext_s64() nounwind ssp {<br>
; CHECK-LABEL: test_vext_s64:<br>
- ; CHECK_FIXME: {{ext.8.*#1}}<br>
+ ; CHECK_FIXME: {{rev64.2s.*}}<br>
; this just turns into a load of the second element<br>
%xS64x1 = alloca <1 x i64>, align 8<br>
%__a = alloca <1 x i64>, align 8<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/dag-combine-invaraints.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/dag-combine-invaraints.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/dag-combine-invaraints.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/dag-combine-invaraints.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/dag-combine-invaraints.ll Fri Jul 14 06:56:21 2017<br>
@@ -9,7 +9,7 @@ main_:<br>
%i32T = alloca i32, align 4<br>
%i32F = alloca i32, align 4<br>
%i32X = alloca i32, align 4<br>
- store i32 0, i32* %tmp<br>
+ store i32 %argc, i32* %tmp<br>
store i32 15, i32* %i32T, align 4<br>
store i32 5, i32* %i32F, align 4<br>
%tmp6 = load i32, i32* %tmp, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/swifterror.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swifterror.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/swifterror.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/swifterror.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/swifterror.ll Fri Jul 14 06:56:21 2017<br>
@@ -309,17 +309,17 @@ define float @foo_vararg(%swift_error**<br>
; CHECK-APPLE-LABEL: foo_vararg:<br>
; CHECK-APPLE: orr w0, wzr, #0x10<br>
; CHECK-APPLE: malloc<br>
-; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1<br>
-; CHECK-APPLE: add [[ARGS:x[0-9]+]], [[TMP:x[0-9]+]], #16<br>
-; CHECK-APPLE: strb [[ID]], [x0, #8]<br>
+; CHECK-APPLE-DAG: orr [[ID:w[0-9]+]], wzr, #0x1<br>
+; CHECK-APPLE-DAG: add [[ARGS:x[0-9]+]], [[TMP:x[0-9]+]], #16<br>
+; CHECK-APPLE-DAG: strb [[ID]], [x0, #8]<br>
<br>
; First vararg<br>
; CHECK-APPLE-DAG: orr {{x[0-9]+}}, [[ARGS]], #0x8<br>
; CHECK-APPLE-DAG: ldr {{w[0-9]+}}, [{{.*}}[[TMP]], #16]<br>
-; CHECK-APPLE: add {{x[0-9]+}}, {{x[0-9]+}}, #8<br>
+; CHECK-APPLE-DAG: add {{x[0-9]+}}, {{x[0-9]+}}, #8<br>
; Second vararg<br>
-; CHECK-APPLE: ldr {{w[0-9]+}}, [{{x[0-9]+}}]<br>
-; CHECK-APPLE: add {{x[0-9]+}}, {{x[0-9]+}}, #8<br>
+; CHECK-APPLE-DAG: ldr {{w[0-9]+}}, [{{x[0-9]+}}], #8<br>
+; CHECK-APPLE-DAG: add {{x[0-9]+}}, {{x[0-9]+}}, #16<br>
; Third vararg<br>
; CHECK-APPLE: ldr {{w[0-9]+}}, [{{x[0-9]+}}]<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Fri Jul 14 06:56:21 2017<br>
@@ -26,6 +26,7 @@ entry:<br>
store i32 3855, i32* %xort<br>
store i32 4, i32* %temp<br>
%tmp = load i32, i32* %temp<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: add<br>
; CHECK: strex<br>
@@ -35,6 +36,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%0 = atomicrmw add i32* %val1, i32 %tmp monotonic<br>
store i32 %0, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: sub<br>
; CHECK: strex<br>
@@ -44,6 +46,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%1 = atomicrmw sub i32* %val2, i32 30 monotonic<br>
store i32 %1, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: add<br>
; CHECK: strex<br>
@@ -53,6 +56,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%2 = atomicrmw add i32* %val2, i32 1 monotonic<br>
store i32 %2, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: sub<br>
; CHECK: strex<br>
@@ -62,6 +66,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%3 = atomicrmw sub i32* %val2, i32 1 monotonic<br>
store i32 %3, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: and<br>
; CHECK: strex<br>
@@ -71,6 +76,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%4 = atomicrmw and i32* %andt, i32 4080 monotonic<br>
store i32 %4, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: or<br>
; CHECK: strex<br>
@@ -80,6 +86,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%5 = atomicrmw or i32* %ort, i32 4080 monotonic<br>
store i32 %5, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: eor<br>
; CHECK: strex<br>
@@ -89,6 +96,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%6 = atomicrmw xor i32* %xort, i32 4080 monotonic<br>
store i32 %6, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: cmp<br>
; CHECK: strex<br>
@@ -98,6 +106,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%7 = atomicrmw min i32* %val2, i32 16 monotonic<br>
store i32 %7, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
%neg = sub i32 0, 1<br>
; CHECK: ldrex<br>
; CHECK: cmp<br>
@@ -108,6 +117,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%8 = atomicrmw min i32* %val2, i32 %neg monotonic<br>
store i32 %8, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: cmp<br>
; CHECK: strex<br>
@@ -117,6 +127,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%9 = atomicrmw max i32* %val2, i32 1 monotonic<br>
store i32 %9, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: cmp<br>
; CHECK: strex<br>
@@ -126,6 +137,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%10 = atomicrmw max i32* %val2, i32 0 monotonic<br>
store i32 %10, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: cmp<br>
; CHECK: strex<br>
@@ -135,6 +147,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%11 = atomicrmw umin i32* %val2, i32 16 monotonic<br>
store i32 %11, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
%uneg = sub i32 0, 1<br>
; CHECK: ldrex<br>
; CHECK: cmp<br>
@@ -145,6 +158,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%12 = atomicrmw umin i32* %val2, i32 %uneg monotonic<br>
store i32 %12, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: cmp<br>
; CHECK: strex<br>
@@ -154,6 +168,7 @@ entry:<br>
; CHECK-BAREMETAL-NOT: __sync<br>
%13 = atomicrmw umax i32* %val2, i32 1 monotonic<br>
store i32 %13, i32* %old<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: ldrex<br>
; CHECK: cmp<br>
; CHECK: strex<br>
<br>
Modified: llvm/trunk/test/CodeGen/MSP430/vararg.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/vararg.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/vararg.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MSP430/vararg.ll (original)<br>
+++ llvm/trunk/test/CodeGen/MSP430/vararg.ll Fri Jul 14 06:56:21 2017<br>
@@ -39,11 +39,11 @@ entry:<br>
; CHECK-LABEL: va_copy:<br>
%vl.addr = alloca i8*, align 2<br>
%vl2 = alloca i8*, align 2<br>
-; CHECK: mov.w r12, 2(r1)<br>
+; CHECK-DAG: mov.w r12, 2(r1)<br>
store i8* %vl, i8** %vl.addr, align 2<br>
%0 = bitcast i8** %vl2 to i8*<br>
%1 = bitcast i8** %vl.addr to i8*<br>
-; CHECK-NEXT: mov.w r12, 0(r1)<br>
+; CHECK-DAG: mov.w r12, 0(r1)<br>
call void @llvm.va_copy(i8* %0, i8* %1)<br>
ret void<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/dins.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/dins.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/dins.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Mips/dins.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/dins.ll Fri Jul 14 06:56:21 2017<br>
@@ -59,9 +59,9 @@ entry:<br>
; CHECK-LABEL: f123:<br>
; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 123<br>
; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 27, 37<br>
-; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 5<br>
; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 4<br>
; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 28, 6<br>
+; MIPS64R2: daddiu $[[R0:[0-9]+]], $zero, 5<br>
; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50, 14<br>
; MIPS64R2: dsrl $[[R0:[0-9]+]], $[[R1:[0-9]+]], 50<br>
; MIPS64R2: dins $[[R0:[0-9]+]], $[[R1:[0-9]+]], 34, 16<br>
@@ -94,4 +94,4 @@ entry:<br>
; MIPS32R2: ori $[[R0:[0-9]+]], $[[R0:[0-9]+]], 8<br>
; MIPS32R2-NOT: ins {{[[:space:]].*}}<br>
; MIPS64R2N32: ori $[[R0:[0-9]+]], $[[R0:[0-9]+]], 8<br>
-; MIPS64R2N32-NOT: ins {{[[:space:]].*}}<br>
\ No newline at end of file<br>
+; MIPS64R2N32-NOT: ins {{[[:space:]].*}}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/2011-10-19-widen_vselect.ll Fri Jul 14 06:56:21 2017<br>
@@ -83,10 +83,11 @@ define void @full_test() {<br>
; X32-NEXT: cmpeqps %xmm2, %xmm1<br>
; X32-NEXT: movaps %xmm1, %xmm0<br>
; X32-NEXT: blendvps %xmm0, %xmm2, %xmm4<br>
-; X32-NEXT: extractps $1, %xmm4, {{[0-9]+}}(%esp)<br>
; X32-NEXT: movss %xmm4, {{[0-9]+}}(%esp)<br>
-; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero<br>
-; X32-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)<br>
+; X32-NEXT: movshdup {{.*#+}} xmm0 = xmm4[1,1,3,3]<br>
+; X32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)<br>
+; X32-NEXT: movss %xmm4, {{[0-9]+}}(%esp)<br>
+; X32-NEXT: movss %xmm0, {{[0-9]+}}(%esp)<br>
; X32-NEXT: addl $60, %esp<br>
; X32-NEXT: retl<br>
;<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/alias-static-alloca.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/alias-static-alloca.ll?rev=308025&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/alias-static-alloca.ll?rev=308025&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/alias-static-alloca.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/alias-static-alloca.ll Fri Jul 14 06:56:21 2017<br>
@@ -0,0 +1,37 @@<br>
+; RUN: llc -o - -mtriple=x86_64-linux-gnu %s | FileCheck %s<br>
+<br>
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"<br>
+target triple = "x86_64-unknown-linux-gnu"<br>
+<br>
+; We should be able to bypass the load values to their corresponding<br>
+; stores here.<br>
+<br>
+; CHECK-LABEL: foo<br>
+; CHECK-DAG: movl %esi, -8(%rsp)<br>
+; CHECK-DAG: movl %ecx, -16(%rsp)<br>
+; CHECK-DAG: movl %edi, -4(%rsp)<br>
+; CHECK-DAG: movl %edx, -12(%rsp)<br>
+; CHECK: leal<br>
+; CHECK: addl<br>
+; CHECK: addl<br>
+; CHECK: retq<br>
+<br>
+define i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) {<br>
+entry:<br>
+ %a0 = alloca i32<br>
+ %a1 = alloca i32<br>
+ %a2 = alloca i32<br>
+ %a3 = alloca i32<br>
+ store i32 %b, i32* %a1<br>
+ store i32 %d, i32* %a3<br>
+ store i32 %a, i32* %a0<br>
+ store i32 %c, i32* %a2<br>
+ %l0 = load i32, i32* %a0<br>
+ %l1 = load i32, i32* %a1<br>
+ %l2 = load i32, i32* %a2<br>
+ %l3 = load i32, i32* %a3<br>
+ %add0 = add nsw i32 %l0, %l1<br>
+ %add1 = add nsw i32 %add0, %l2<br>
+ %add2 = add nsw i32 %add1, %l3<br>
+ ret i32 %add2<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/clobber-fi0.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/clobber-fi0.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/clobber-fi0.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/clobber-fi0.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/clobber-fi0.ll Fri Jul 14 06:56:21 2017<br>
@@ -15,22 +15,22 @@ bb:<br>
%tmp = alloca i32, align 4 ; [#uses=3 type=i32*]<br>
%tmp2 = alloca i32, align 4 ; [#uses=3 type=i32*]<br>
%tmp3 = alloca i32 ; [#uses=1 type=i32*]<br>
- store i32 1, i32* %tmp, align 4<br>
- store i32 1, i32* %tmp2, align 4<br>
+ store volatile i32 1, i32* %tmp, align 4<br>
+ store volatile i32 1, i32* %tmp2, align 4<br>
br label %bb4<br>
<br>
bb4: ; preds = %bb4, %bb<br>
- %tmp6 = load i32, i32* %tmp2, align 4 ; [#uses=1 type=i32]<br>
+ %tmp6 = load volatile i32, i32* %tmp2, align 4 ; [#uses=1 type=i32]<br>
%tmp7 = add i32 %tmp6, -1 ; [#uses=2 type=i32]<br>
- store i32 %tmp7, i32* %tmp2, align 4<br>
+ store volatile i32 %tmp7, i32* %tmp2, align 4<br>
%tmp8 = icmp eq i32 %tmp7, 0 ; [#uses=1 type=i1]<br>
- %tmp9 = load i32, i32* %tmp ; [#uses=1 type=i32]<br>
+ %tmp9 = load volatile i32, i32* %tmp ; [#uses=1 type=i32]<br>
%tmp10 = add i32 %tmp9, -1 ; [#uses=1 type=i32]<br>
- store i32 %tmp10, i32* %tmp3<br>
+ store volatile i32 %tmp10, i32* %tmp3<br>
br i1 %tmp8, label %bb11, label %bb4<br>
<br>
bb11: ; preds = %bb4<br>
- %tmp12 = load i32, i32* %tmp, align 4 ; [#uses=1 type=i32]<br>
+ %tmp12 = load volatile i32, i32* %tmp, align 4 ; [#uses=1 type=i32]<br>
ret i32 %tmp12<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/hipe-cc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hipe-cc.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hipe-cc.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/hipe-cc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/hipe-cc.ll Fri Jul 14 06:56:21 2017<br>
@@ -48,11 +48,7 @@ entry:<br>
store i32 %arg0, i32* %arg0_var<br>
store i32 %arg1, i32* %arg1_var<br>
store i32 %arg2, i32* %arg2_var<br>
-<br>
- ; CHECK: movl 16(%esp), %esi<br>
- ; CHECK-NEXT: movl 12(%esp), %ebp<br>
- ; CHECK-NEXT: movl 8(%esp), %eax<br>
- ; CHECK-NEXT: movl 4(%esp), %edx<br>
+ ; These loads are loading the values from their previous stores and are optimized away.<br>
%0 = load i32, i32* %hp_var<br>
%1 = load i32, i32* %p_var<br>
%2 = load i32, i32* %arg0_var<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/hipe-cc64.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hipe-cc64.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hipe-cc64.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/hipe-cc64.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/hipe-cc64.ll Fri Jul 14 06:56:21 2017<br>
@@ -57,11 +57,7 @@ entry:<br>
store i64 %arg2, i64* %arg2_var<br>
store i64 %arg3, i64* %arg3_var<br>
<br>
- ; CHECK: movq 40(%rsp), %r15<br>
- ; CHECK-NEXT: movq 32(%rsp), %rbp<br>
- ; CHECK-NEXT: movq 24(%rsp), %rsi<br>
- ; CHECK-NEXT: movq 16(%rsp), %rdx<br>
- ; CHECK-NEXT: movq 8(%rsp), %rcx<br>
+ ; Loads are reading values just writen from corresponding register and are therefore noops.<br>
%0 = load i64, i64* %hp_var<br>
%1 = load i64, i64* %p_var<br>
%2 = load i64, i64* %arg0_var<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/legalize-shift-64.ll Fri Jul 14 06:56:21 2017<br>
@@ -148,8 +148,7 @@ define i32 @test6() {<br>
; CHECK-NEXT: andl $-8, %esp<br>
; CHECK-NEXT: subl $16, %esp<br>
; CHECK-NEXT: movl $1, {{[0-9]+}}(%esp)<br>
-; CHECK-NEXT: movl $0, {{[0-9]+}}(%esp)<br>
-; CHECK-NEXT: movl $1, (%esp)<br>
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: movl $1, %eax<br>
; CHECK-NEXT: xorl %ecx, %ecx<br>
; CHECK-NEXT: shldl $32, %eax, %ecx<br>
@@ -175,9 +174,8 @@ define i32 @test6() {<br>
; CHECK-NEXT: retl<br>
%x = alloca i32, align 4<br>
%t = alloca i64, align 8<br>
- store i32 1, i32* %x, align 4<br>
- store i64 1, i64* %t, align 8 ;; DEAD<br>
- %load = load i32, i32* %x, align 4<br>
+ store volatile i32 1, i32* %x, align 4<br>
+ %load = load volatile i32, i32* %x, align 4<br>
%shl = shl i32 %load, 8<br>
%add = add i32 %shl, -224<br>
%sh_prom = zext i32 %add to i64<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/machine-outliner-debuginfo.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-outliner-debuginfo.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-outliner-debuginfo.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/machine-outliner-debuginfo.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/machine-outliner-debuginfo.ll Fri Jul 14 06:56:21 2017<br>
@@ -17,6 +17,7 @@ define i32 @main() #0 !dbg !11 {<br>
call void @llvm.dbg.value(metadata i32 10, i64 0, metadata !15, metadata !16), !dbg !17<br>
store i32 4, i32* %5, align 4<br>
store i32 0, i32* @x, align 4, !dbg !24<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; This is the same sequence of instructions without a debug value. It should be outlined<br>
; in the same way.<br>
; CHECK: callq l_OUTLINED_FUNCTION_0<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/machine-outliner.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-outliner.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-outliner.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/machine-outliner.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/machine-outliner.ll Fri Jul 14 06:56:21 2017<br>
@@ -85,6 +85,7 @@ define i32 @main() #0 {<br>
store i32 3, i32* %4, align 4<br>
store i32 4, i32* %5, align 4<br>
store i32 1, i32* @x, align 4<br>
+ call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()<br>
; CHECK: callq [[OFUNC2]]<br>
store i32 1, i32* %2, align 4<br>
store i32 2, i32* %3, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/statepoint-invoke.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-invoke.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-invoke.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/statepoint-invoke.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/statepoint-invoke.ll Fri Jul 14 06:56:21 2017<br>
@@ -95,8 +95,8 @@ left.relocs:<br>
<br>
right:<br>
; CHECK-LABEL: %right<br>
- ; CHECK: movq<br>
; CHECK: movq %rdx, (%rsp)<br>
+ ; CHECK: movq<br>
; CHECK: callq some_call<br>
%sp2 = invoke token (i64, i32, void (i64 addrspace(1)*)*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidp1i64f(i64 0, i32 0, void (i64 addrspace(1)*)* @some_call, i32 1, i32 0, i64 addrspace(1)* %val1, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i64 addrspace(1)* %val2, i64 addrspace(1)* %val3)<br>
to label %right.relocs unwind label %exceptional_return.right<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/statepoint-stack-usage.ll Fri Jul 14 06:56:21 2017<br>
@@ -11,9 +11,9 @@ target triple = "x86_64-pc-linux-gnu"<br>
define i32 @back_to_back_calls(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspace(1)* %c) #1 gc "statepoint-example" {<br>
; CHECK-LABEL: back_to_back_calls<br>
; The exact stores don't matter, but there need to be three stack slots created<br>
-; CHECK: movq %rdi, 16(%rsp)<br>
-; CHECK: movq %rdx, 8(%rsp)<br>
-; CHECK: movq %rsi, (%rsp)<br>
+; CHECK-DAG: movq %rdi, 16(%rsp)<br>
+; CHECK-DAG: movq %rdx, 8(%rsp)<br>
+; CHECK-DAG: movq %rsi, (%rsp)<br>
; There should be no more than three moves<br>
; CHECK-NOT: movq<br>
%safepoint_token = tail call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspace(1)* %c)<br>
@@ -36,9 +36,9 @@ define i32 @back_to_back_calls(i32 addrs<br>
define i32 @reserve_first(i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspace(1)* %c) #1 gc "statepoint-example" {<br>
; CHECK-LABEL: reserve_first<br>
; The exact stores don't matter, but there need to be three stack slots created<br>
-; CHECK: movq %rdi, 16(%rsp)<br>
-; CHECK: movq %rdx, 8(%rsp)<br>
-; CHECK: movq %rsi, (%rsp)<br>
+; CHECK-DAG: movq %rdi, 16(%rsp)<br>
+; CHECK-DAG: movq %rdx, 8(%rsp)<br>
+; CHECK-DAG: movq %rsi, (%rsp)<br>
%safepoint_token = tail call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspace(1)* %c)<br>
%a1 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %safepoint_token, i32 12, i32 12)<br>
%b1 = tail call coldcc i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %safepoint_token, i32 12, i32 13)<br>
@@ -61,21 +61,21 @@ define i32 @back_to_back_deopt(i32 %a, i<br>
gc "statepoint-example" {<br>
; CHECK-LABEL: back_to_back_deopt<br>
; The exact stores don't matter, but there need to be three stack slots created<br>
-; CHECK: movl %ebx, 12(%rsp)<br>
-; CHECK: movl %ebp, 8(%rsp)<br>
-; CHECK: movl %r14d, 4(%rsp)<br>
-; CHECK: callq<br>
-; CHECK: movl %ebx, 12(%rsp)<br>
-; CHECK: movl %ebp, 8(%rsp)<br>
-; CHECK: movl %r14d, 4(%rsp)<br>
-; CHECK: callq<br>
-; CHECK: movl %ebx, 12(%rsp)<br>
-; CHECK: movl %ebp, 8(%rsp)<br>
-; CHECK: movl %r14d, 4(%rsp)<br>
-; CHECK: callq<br>
-; CHECK: movl %ebx, 12(%rsp)<br>
-; CHECK: movl %ebp, 8(%rsp)<br>
-; CHECK: movl %r14d, 4(%rsp)<br>
+; CHECK-DAG: movl %ebx, 12(%rsp)<br>
+; CHECK-DAG: movl %ebp, 8(%rsp)<br>
+; CHECK-DAG: movl %r14d, 4(%rsp)<br>
+; CHECK: callq<br>
+; CHECK-DAG: movl %ebx, 12(%rsp)<br>
+; CHECK-DAG: movl %ebp, 8(%rsp)<br>
+; CHECK-DAG: movl %r14d, 4(%rsp)<br>
+; CHECK: callq<br>
+; CHECK-DAG: movl %ebx, 12(%rsp)<br>
+; CHECK-DAG: movl %ebp, 8(%rsp)<br>
+; CHECK-DAG: movl %r14d, 4(%rsp)<br>
+; CHECK: callq<br>
+; CHECK-DAG: movl %ebx, 12(%rsp)<br>
+; CHECK-DAG: movl %ebp, 8(%rsp)<br>
+; CHECK-DAG: movl %r14d, 4(%rsp)<br>
; CHECK: callq<br>
call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 3, i32 %a, i32 %b, i32 %c)<br>
call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 3, i32 %a, i32 %b, i32 %c)<br>
@@ -89,9 +89,9 @@ define i32 @back_to_back_invokes(i32 add<br>
; CHECK-LABEL: back_to_back_invokes<br>
entry:<br>
; The exact stores don't matter, but there need to be three stack slots created<br>
- ; CHECK: movq %rdi, 16(%rsp)<br>
- ; CHECK: movq %rdx, 8(%rsp)<br>
- ; CHECK: movq %rsi, (%rsp)<br>
+ ; CHECK-DAG: movq %rdi, 16(%rsp)<br>
+ ; CHECK-DAG: movq %rdx, 8(%rsp)<br>
+ ; CHECK-DAG: movq %rsi, (%rsp)<br>
; CHECK: callq<br>
%safepoint_token = invoke token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* undef, i32 0, i32 0, i32 0, i32 5, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 addrspace(1)* %c)<br>
to label %normal_return unwind label %exceptional_return<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/statepoint-vector.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-vector.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/statepoint-vector.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/statepoint-vector.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/statepoint-vector.ll Fri Jul 14 06:56:21 2017<br>
@@ -49,8 +49,8 @@ entry:<br>
; CHECK: subq $40, %rsp<br>
; CHECK: testb $1, %dil<br>
; CHECK: movaps (%rsi), %xmm0<br>
-; CHECK: movaps %xmm0, 16(%rsp)<br>
-; CHECK: movaps %xmm0, (%rsp)<br>
+; CHECK-DAG: movaps %xmm0, (%rsp)<br>
+; CHECK-DAG: movaps %xmm0, 16(%rsp)<br>
; CHECK: callq do_safepoint<br>
; CHECK: movaps (%rsp), %xmm0<br>
; CHECK: addq $40, %rsp<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/widen_arith-2.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-2.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_arith-2.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/widen_arith-2.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/widen_arith-2.ll Fri Jul 14 06:56:21 2017<br>
@@ -16,20 +16,17 @@ define void @update(i64* %dst_i, i64* %s<br>
; CHECK-NEXT: .LBB0_2: # %forbody<br>
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1<br>
; CHECK-NEXT: movl (%esp), %eax<br>
-; CHECK-NEXT: shll $3, %eax<br>
-; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax<br>
-; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)<br>
-; CHECK-NEXT: movl (%esp), %eax<br>
-; CHECK-NEXT: shll $3, %eax<br>
-; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax<br>
-; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)<br>
-; CHECK-NEXT: movl (%esp), %ecx<br>
+; CHECK-NEXT: leal (,%eax,8), %ecx<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx<br>
+; CHECK-NEXT: addl %ecx, %edx<br>
+; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)<br>
+; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx<br>
+; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)<br>
; CHECK-NEXT: pmovzxbw {{.*#+}} xmm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero<br>
; CHECK-NEXT: psubw %xmm0, %xmm3<br>
; CHECK-NEXT: pand %xmm1, %xmm3<br>
; CHECK-NEXT: pshufb %xmm2, %xmm3<br>
-; CHECK-NEXT: movq %xmm3, (%edx,%ecx,8)<br>
+; CHECK-NEXT: movq %xmm3, (%edx,%eax,8)<br>
; CHECK-NEXT: incl (%esp)<br>
; CHECK-NEXT: .LBB0_1: # %forcond<br>
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/widen_cast-4.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-4.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-4.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/widen_cast-4.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/widen_cast-4.ll Fri Jul 14 06:56:21 2017<br>
@@ -16,22 +16,19 @@ define void @update(i64* %dst_i, i64* %s<br>
; NARROW-NEXT: .LBB0_2: # %forbody<br>
; NARROW-NEXT: # in Loop: Header=BB0_1 Depth=1<br>
; NARROW-NEXT: movl (%esp), %eax<br>
-; NARROW-NEXT: shll $3, %eax<br>
-; NARROW-NEXT: addl {{[0-9]+}}(%esp), %eax<br>
-; NARROW-NEXT: movl %eax, {{[0-9]+}}(%esp)<br>
-; NARROW-NEXT: movl (%esp), %eax<br>
-; NARROW-NEXT: shll $3, %eax<br>
-; NARROW-NEXT: addl {{[0-9]+}}(%esp), %eax<br>
-; NARROW-NEXT: movl %eax, {{[0-9]+}}(%esp)<br>
-; NARROW-NEXT: movl (%esp), %ecx<br>
+; NARROW-NEXT: leal (,%eax,8), %ecx<br>
; NARROW-NEXT: movl {{[0-9]+}}(%esp), %edx<br>
+; NARROW-NEXT: addl %ecx, %edx<br>
+; NARROW-NEXT: movl %edx, {{[0-9]+}}(%esp)<br>
+; NARROW-NEXT: addl {{[0-9]+}}(%esp), %ecx<br>
+; NARROW-NEXT: movl %ecx, {{[0-9]+}}(%esp)<br>
; NARROW-NEXT: pmovzxbw {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero<br>
; NARROW-NEXT: psubw %xmm0, %xmm2<br>
; NARROW-NEXT: psllw $8, %xmm2<br>
; NARROW-NEXT: psraw $8, %xmm2<br>
; NARROW-NEXT: psraw $2, %xmm2<br>
; NARROW-NEXT: pshufb %xmm1, %xmm2<br>
-; NARROW-NEXT: movq %xmm2, (%edx,%ecx,8)<br>
+; NARROW-NEXT: movq %xmm2, (%edx,%eax,8)<br>
; NARROW-NEXT: incl (%esp)<br>
; NARROW-NEXT: .LBB0_1: # %forcond<br>
; NARROW-NEXT: # =>This Inner Loop Header: Depth=1<br>
@@ -54,24 +51,21 @@ define void @update(i64* %dst_i, i64* %s<br>
; WIDE-NEXT: .LBB0_2: # %forbody<br>
; WIDE-NEXT: # in Loop: Header=BB0_1 Depth=1<br>
; WIDE-NEXT: movl (%esp), %eax<br>
-; WIDE-NEXT: shll $3, %eax<br>
-; WIDE-NEXT: addl {{[0-9]+}}(%esp), %eax<br>
-; WIDE-NEXT: movl %eax, {{[0-9]+}}(%esp)<br>
-; WIDE-NEXT: movl (%esp), %eax<br>
-; WIDE-NEXT: shll $3, %eax<br>
-; WIDE-NEXT: addl {{[0-9]+}}(%esp), %eax<br>
-; WIDE-NEXT: movl %eax, {{[0-9]+}}(%esp)<br>
-; WIDE-NEXT: movl (%esp), %ecx<br>
+; WIDE-NEXT: leal (,%eax,8), %ecx<br>
; WIDE-NEXT: movl {{[0-9]+}}(%esp), %edx<br>
+; WIDE-NEXT: addl %ecx, %edx<br>
+; WIDE-NEXT: movl %edx, {{[0-9]+}}(%esp)<br>
+; WIDE-NEXT: addl {{[0-9]+}}(%esp), %ecx<br>
+; WIDE-NEXT: movl %ecx, {{[0-9]+}}(%esp)<br>
; WIDE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero<br>
-; WIDE-NEXT: pinsrd $1, 4(%eax,%ecx,8), %xmm3<br>
+; WIDE-NEXT: pinsrd $1, 4(%ecx,%eax,8), %xmm3<br>
; WIDE-NEXT: psubb %xmm0, %xmm3<br>
; WIDE-NEXT: psrlw $2, %xmm3<br>
; WIDE-NEXT: pand %xmm1, %xmm3<br>
; WIDE-NEXT: pxor %xmm2, %xmm3<br>
; WIDE-NEXT: psubb %xmm2, %xmm3<br>
-; WIDE-NEXT: pextrd $1, %xmm3, 4(%edx,%ecx,8)<br>
-; WIDE-NEXT: movd %xmm3, (%edx,%ecx,8)<br>
+; WIDE-NEXT: pextrd $1, %xmm3, 4(%edx,%eax,8)<br>
+; WIDE-NEXT: movd %xmm3, (%edx,%eax,8)<br>
; WIDE-NEXT: incl (%esp)<br>
; WIDE-NEXT: .LBB0_1: # %forcond<br>
; WIDE-NEXT: # =>This Inner Loop Header: Depth=1<br>
<br>
Modified: llvm/trunk/test/CodeGen/XCore/varargs.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/varargs.ll?rev=308025&r1=308024&r2=308025&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/varargs.ll?rev=308025&r1=308024&r2=308025&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/XCore/varargs.ll (original)<br>
+++ llvm/trunk/test/CodeGen/XCore/varargs.ll Fri Jul 14 06:56:21 2017<br>
@@ -26,10 +26,10 @@ entry:<br>
; CHECK-LABEL: test_vararg<br>
; CHECK: extsp 6<br>
; CHECK: stw lr, sp[1]<br>
-; CHECK: stw r3, sp[6]<br>
-; CHECK: stw r0, sp[3]<br>
-; CHECK: stw r1, sp[4]<br>
-; CHECK: stw r2, sp[5]<br>
+; CHECK-DAG: stw r3, sp[6]<br>
+; CHECK-DAG: stw r0, sp[3]<br>
+; CHECK-DAG: stw r1, sp[4]<br>
+; CHECK-DAG: stw r2, sp[5]<br>
; CHECK: ldaw r0, sp[3]<br>
; CHECK: stw r0, sp[2]<br>
%list = alloca i8*, align 4<br>
<br>
<br>
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</blockquote></div></div>