<div dir="ltr">This has been in tree for 12 hours spamming. Reverting now.<br><br>Sam, please be more careful when committing to watch for followup on the list.<br><br><div class="gmail_quote"><div dir="ltr">On Mon, Jul 17, 2017 at 1:57 PM Eric Christopher via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">This is causing a lot of warnings/errors in tablegen. Can you please fix or revert?<div><br></div><div><div>Too few operands in record V_DIV_SCALE_F64_vi (no match for variable omod):</div><div>V_DIV_SCALE_F64_vi {<span style="white-space:pre-wrap"> </span>// Instruction AMDGPUInst PredicateControl InstSI SIMCInstr VOP3_Real Enc64 VOP3be VOP3be_vi _vi</div><div> field bit isRegisterLoad = 0;</div><div> field bit isRegisterStore = 0;</div><div> field bits<64> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,</div></div><div><br></div><div>Thanks!</div></div><div dir="ltr"><div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr">On Mon, Jul 17, 2017 at 7:24 AM Sam Kolton via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: skolton<br>
Date: Mon Jul 17 07:23:38 2017<br>
New Revision: 308179<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=308179&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=308179&view=rev</a><br>
Log:<br>
[AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions<br>
<br>
Summary:<br>
Previously, CodeGen checked first src operand type to determine if omod is supported by instruction. This isn't correct for some instructions: e.g. V_CMP_EQ_F32 has floating-point src operands but desn't support omod.<br>
Changed .td files to check if dst operand instead of src operand.<br>
<br>
Reviewers: arsenm, vpykhtin<br>
<br>
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D35350" rel="noreferrer" target="_blank">https://reviews.llvm.org/D35350</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td<br>
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td<br>
llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td<br>
llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td<br>
llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td<br>
llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td<br>
llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir<br>
llvm/trunk/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir<br>
llvm/trunk/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir<br>
llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir<br>
llvm/trunk/test/MC/AMDGPU/vop3-errs.s<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Mon Jul 17 07:23:38 2017<br>
@@ -1436,7 +1436,7 @@ class VOPProfile <list<ValueType> _ArgVT<br>
<br>
field bit IsPacked = isPackedType<Src0VT>.ret;<br>
field bit HasOpSel = IsPacked;<br>
- field bit HasOMod = !if(HasOpSel, 0, HasModifiers);<br>
+ field bit HasOMod = !if(HasOpSel, 0, isFloatType<DstVT>.ret);<br>
field bit HasSDWAOMod = isFloatType<DstVT>.ret;<br>
<br>
field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Mon Jul 17 07:23:38 2017<br>
@@ -1060,7 +1060,7 @@ def : Pat <<br>
<br>
class FPToI1Pat<Instruction Inst, int KOne, ValueType kone_type, ValueType vt, SDPatternOperator fp_to_int> : Pat <<br>
(i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),<br>
- (i1 (Inst 0, (kone_type KOne), $src0_modifiers, $src0, DSTCLAMP.NONE, DSTOMOD.NONE))<br>
+ (i1 (Inst 0, (kone_type KOne), $src0_modifiers, $src0, DSTCLAMP.NONE))<br>
>;<br>
<br>
def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_ONE, i32, f32, fp_to_uint>;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td Mon Jul 17 07:23:38 2017<br>
@@ -117,7 +117,10 @@ class VOP2_SDWA_Pseudo <string OpName, V<br>
class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {<br>
list<dag> ret = !if(P.HasModifiers,<br>
[(set P.DstVT:$vdst,<br>
- (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),<br>
+ (node (P.Src0VT<br>
+ !if(P.HasOMod,<br>
+ (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),<br>
+ (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),<br>
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],<br>
[(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);<br>
}<br>
@@ -813,9 +816,11 @@ let SubtargetPredicate = isVI in {<br>
<br>
// Aliases to simplify matching of floating-point instructions that<br>
// are VOP2 on SI and VOP3 on VI.<br>
-class SI2_VI3Alias <string name, Instruction inst> : InstAlias <<br>
+class SI2_VI3Alias <string name, VOP3_Real inst> : InstAlias <<br>
name#" $dst, $src0, $src1",<br>
- (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0)<br>
+ !if(inst.Pfl.HasOMod,<br>
+ (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0),<br>
+ (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0))<br>
>, PredicateControl {<br>
let UseInstAsmMatchConverter = 0;<br>
let AsmVariantName = AMDGPUAsmVariants.VOP3;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td Mon Jul 17 07:23:38 2017<br>
@@ -12,17 +12,21 @@<br>
//===----------------------------------------------------------------------===//<br>
<br>
class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {<br>
+ dag src0 = !if(P.HasOMod,<br>
+ (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),<br>
+ (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));<br>
+<br>
list<dag> ret3 = [(set P.DstVT:$vdst,<br>
- (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),<br>
+ (node (P.Src0VT src0),<br>
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),<br>
(P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];<br>
<br>
list<dag> ret2 = [(set P.DstVT:$vdst,<br>
- (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),<br>
+ (node (P.Src0VT src0),<br>
(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];<br>
<br>
list<dag> ret1 = [(set P.DstVT:$vdst,<br>
- (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))];<br>
+ (node (P.Src0VT src0)))];<br>
<br>
list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,<br>
!if(!eq(P.NumSrcArgs, 2), ret2,<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/VOPCInstructions.td Mon Jul 17 07:23:38 2017<br>
@@ -148,6 +148,19 @@ class VOPCInstAlias <VOP3_Pseudo ps, Ins<br>
let SubtargetPredicate = AssemblerPredicate;<br>
}<br>
<br>
+class getVOPCPat64 <PatLeaf cond, VOPProfile P> : LetDummies {<br>
+ list<dag> ret = !if(P.HasModifiers,<br>
+ [(set i1:$sdst,<br>
+ (setcc (P.Src0VT<br>
+ !if(P.HasOMod,<br>
+ (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),<br>
+ (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))),<br>
+ (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),<br>
+ cond))],<br>
+ [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]);<br>
+}<br>
+<br>
+<br>
multiclass VOPC_Pseudos <string opName,<br>
VOPC_Profile P,<br>
PatLeaf cond = COND_NULL,<br>
@@ -163,14 +176,7 @@ multiclass VOPC_Pseudos <string opName,<br>
let isCommutable = 1;<br>
}<br>
<br>
- def _e64 : VOP3_Pseudo<opName, P,<br>
- !if(P.HasModifiers,<br>
- [(set i1:$sdst,<br>
- (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,<br>
- i1:$clamp, i32:$omod)),<br>
- (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),<br>
- cond))],<br>
- [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))])>,<br>
+ def _e64 : VOP3_Pseudo<opName, P, getVOPCPat64<cond, P>.ret>,<br>
Commutable_REV<revOp#"_e64", !eq(revOp, opName)> {<br>
let Defs = !if(DefExec, [EXEC], []);<br>
let SchedRW = P.Schedule;<br>
@@ -634,7 +640,7 @@ class FCMP_Pattern <PatLeaf cond, Instru<br>
(i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)),<br>
(vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)),<br>
(inst $src0_modifiers, $src0, $src1_modifiers, $src1,<br>
- DSTCLAMP.NONE, DSTOMOD.NONE)<br>
+ DSTCLAMP.NONE)<br>
>;<br>
<br>
def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>;<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td Mon Jul 17 07:23:38 2017<br>
@@ -136,6 +136,8 @@ class VOP3_Real <VOP3_Pseudo ps, int Enc<br>
let TSFlags = ps.TSFlags;<br>
let UseNamedOperandTable = ps.UseNamedOperandTable;<br>
let Uses = ps.Uses;<br>
+<br>
+ VOPProfile Pfl = ps.Pfl;<br>
}<br>
<br>
// XXX - Is there any reason to distingusih this from regular VOP3<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir Mon Jul 17 07:23:38 2017<br>
@@ -34,7 +34,7 @@ body: |<br>
bb.0:<br>
successors: %bb.2, %bb.1<br>
<br>
- %7 = V_CMP_NEQ_F32_e64 0, 0, 0, undef %3, 0, 0, implicit %exec<br>
+ %7 = V_CMP_NEQ_F32_e64 0, 0, 0, undef %3, 0, implicit %exec<br>
%vcc = COPY killed %7<br>
S_CBRANCH_VCCZ %bb.2, implicit killed %vcc<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir Mon Jul 17 07:23:38 2017<br>
@@ -332,7 +332,7 @@ body: |<br>
<br>
<br>
# VI: %vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit %exec<br>
-# VI: %{{[0-9]+}} = V_CMPX_GT_F32_e64 0, 23, 0, killed %{{[0-9]+}}, 0, 0, implicit-def %exec, implicit %exec<br>
+# VI: %{{[0-9]+}} = V_CMPX_GT_F32_e64 0, 23, 0, killed %{{[0-9]+}}, 0, implicit-def %exec, implicit %exec<br>
# VI: %vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %3, 0, 6, 4, implicit-def %vcc, implicit %exec<br>
# VI: %{{[0-9]+}} = V_CMPX_EQ_I32_e64 23, killed %{{[0-9]+}}, implicit-def %exec, implicit %exec<br>
<br>
@@ -345,20 +345,21 @@ body: |<br>
<br>
<br>
# VI: %vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 1, 6, 4, implicit-def %vcc, implicit %exec<br>
-# VI: %vcc = V_CMPX_GT_F32_e64 0, 23, 0, killed %{{[0-9]+}}, 0, 2, implicit-def %exec, implicit %exec<br>
-# VI: %vcc = V_CMP_EQ_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 1, 2, implicit %exec<br>
+# VI: %vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
+# VI: %vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 1, 6, 4, implicit-def %vcc, implicit %exec<br>
# VI: %vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
# VI: %vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
# VI: %vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
-# VI: %vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %{{[0-9]+}}, 1, 2, implicit-def %exec, implicit %exec<br>
+# VI: %vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
<br>
-# GFX9: %vcc = V_CMP_EQ_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 1, 0, implicit %exec<br>
-# GFX9: %vcc = V_CMPX_GT_F32_e64 0, 23, 0, killed %{{[0-9]+}}, 0, 2, implicit-def %exec, implicit %exec<br>
-# GFX9: %vcc = V_CMP_EQ_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 1, 2, implicit %exec<br>
+# GFX9: %vcc = V_CMP_EQ_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 1, implicit %exec<br>
+# GFX9: %vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
+# GFX9: %vcc = V_CMP_EQ_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 1, implicit %exec<br>
# GFX9: %vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
# GFX9: %vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
# GFX9: %vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
-# GFX9: %vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %{{[0-9]+}}, 1, 2, implicit-def %exec, implicit %exec<br>
+# GFX9: %vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %{{[0-9]+}}, 1, implicit-def %exec, implicit %exec<br>
+<br>
<br>
<br>
name: vopc_instructions<br>
@@ -415,28 +416,28 @@ body: |<br>
V_CMPX_EQ_I32_e32 123, killed %13, implicit-def %vcc, implicit-def %exec, implicit %exec<br>
<br>
%14 = V_AND_B32_e64 %5, %3, implicit %exec<br>
- %vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %14, 0, 0, implicit %exec<br>
+ %vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %14, 0, implicit %exec<br>
%15 = V_AND_B32_e64 %5, %3, implicit %exec<br>
- %18 = V_CMPX_GT_F32_e64 0, 23, 0, killed %15, 0, 0, implicit-def %exec, implicit %exec<br>
+ %18 = V_CMPX_GT_F32_e64 0, 23, 0, killed %15, 0, implicit-def %exec, implicit %exec<br>
%16 = V_AND_B32_e64 %5, %3, implicit %exec<br>
%vcc = V_CMP_LT_I32_e64 %6, killed %16, implicit %exec<br>
%17 = V_AND_B32_e64 %5, %3, implicit %exec<br>
%19 = V_CMPX_EQ_I32_e64 23, killed %17, implicit-def %exec, implicit %exec<br>
<br>
%20 = V_AND_B32_e64 %5, %3, implicit %exec<br>
- %vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %20, 1, 0, implicit %exec<br>
+ %vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %20, 1, implicit %exec<br>
%21 = V_AND_B32_e64 %5, %3, implicit %exec<br>
- %vcc = V_CMPX_GT_F32_e64 0, 23, 0, killed %21, 0, 2, implicit-def %exec, implicit %exec<br>
+ %vcc = V_CMPX_GT_F32_e64 0, 23, 0, killed %21, 0, implicit-def %exec, implicit %exec<br>
%23 = V_AND_B32_e64 %5, %3, implicit %exec<br>
- %vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %23, 1, 2, implicit %exec<br>
+ %vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %23, 1, implicit %exec<br>
%24 = V_AND_B32_e64 %5, %3, implicit %exec<br>
- %vcc = V_CMPX_GT_F32_e64 1, 23, 0, killed %24, 0, 0, implicit-def %exec, implicit %exec<br>
+ %vcc = V_CMPX_GT_F32_e64 1, 23, 0, killed %24, 0, implicit-def %exec, implicit %exec<br>
%25 = V_AND_B32_e64 %5, %3, implicit %exec<br>
- %vcc = V_CMPX_GT_F32_e64 0, 23, 1, killed %25, 0, 0, implicit-def %exec, implicit %exec<br>
+ %vcc = V_CMPX_GT_F32_e64 0, 23, 1, killed %25, 0, implicit-def %exec, implicit %exec<br>
%26 = V_AND_B32_e64 %5, %3, implicit %exec<br>
- %vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %26, 0, 0, implicit-def %exec, implicit %exec<br>
+ %vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %26, 0, implicit-def %exec, implicit %exec<br>
%27 = V_AND_B32_e64 %5, %3, implicit %exec<br>
- %vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %27, 1, 2, implicit-def %exec, implicit %exec<br>
+ %vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %27, 1, implicit-def %exec, implicit %exec<br>
<br>
<br>
%100 = V_MOV_B32_e32 %vcc_lo, implicit %exec<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir Mon Jul 17 07:23:38 2017<br>
@@ -8,7 +8,7 @@<br>
<br>
# GCN: %{{[0-9]+}} = V_BCNT_U32_B32_e64 %{{[0-9]+}}, killed %{{[0-9]+}}, implicit-def %vcc, implicit %exec<br>
# GCN: %{{[0-9]+}} = V_BFM_B32_e64 %{{[0-9]+}}, killed %{{[0-9]+}}, implicit-def %vcc, implicit %exec<br>
-# GCN: %{{[0-9]+}} = V_CVT_PKNORM_I16_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, 0, implicit-def %vcc, implicit %exec<br>
+# GCN: %{{[0-9]+}} = V_CVT_PKNORM_I16_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 0, implicit-def %vcc, implicit %exec<br>
# GCN: %{{[0-9]+}} = V_READLANE_B32 killed %{{[0-9]+}}, 0, implicit-def %vcc, implicit %exec<br>
<br>
---<br>
@@ -50,7 +50,7 @@ body: |<br>
%15 = V_BFM_B32_e64 %13, killed %14, implicit-def %vcc, implicit %exec<br>
<br>
%16 = V_LSHRREV_B32_e64 16, %15, implicit %exec<br>
- %17 = V_CVT_PKNORM_I16_F32_e64 0, %15, 0, killed %16, 0, 0, implicit-def %vcc, implicit %exec<br>
+ %17 = V_CVT_PKNORM_I16_F32_e64 0, %15, 0, killed %16, 0, implicit-def %vcc, implicit %exec<br>
<br>
%18 = V_LSHRREV_B32_e64 16, %17, implicit %exec<br>
%19 = V_READLANE_B32 killed %18, 0, implicit-def %vcc, implicit %exec<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir Mon Jul 17 07:23:38 2017<br>
@@ -81,7 +81,7 @@ body: |<br>
%sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 11, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`)<br>
%sgpr7 = S_MOV_B32 61440<br>
%sgpr6 = S_MOV_B32 -1<br>
- %vcc = V_CMP_EQ_F32_e64 0, 0, 0, %sgpr2, 0, 0, implicit %exec<br>
+ %vcc = V_CMP_EQ_F32_e64 0, 0, 0, %sgpr2, 0, implicit %exec<br>
S_CBRANCH_VCCZ %bb.1.else, implicit killed %vcc<br>
<br>
bb.2.if:<br>
<br>
Modified: llvm/trunk/test/MC/AMDGPU/vop3-errs.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop3-errs.s?rev=308179&r1=308178&r2=308179&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop3-errs.s?rev=308179&r1=308178&r2=308179&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/AMDGPU/vop3-errs.s (original)<br>
+++ llvm/trunk/test/MC/AMDGPU/vop3-errs.s Mon Jul 17 07:23:38 2017<br>
@@ -1,35 +1,47 @@<br>
-// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s<br>
-// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s<br>
+// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=GFX67 --check-prefix=GCN<br>
+// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=GFX67 --check-prefix=GCN<br>
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck %s --check-prefix=GFX89 --check-prefix=GCN<br>
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=GFX89 --check-prefix=GCN<br>
<br>
v_add_f32_e64 v0, v1<br>
-// CHECK: error: too few operands for instruction<br>
+// GCN: error: too few operands for instruction<br>
<br>
v_div_scale_f32 v24, vcc, v22, 1.1, v22<br>
-// CHECK: error: invalid operand for instruction<br>
+// GCN: error: invalid operand for instruction<br>
<br>
v_mqsad_u32_u8 v[0:3], s[2:3], v4, v[0:3]<br>
-// CHECK: error: instruction not supported on this GPU<br>
+// GFX67: error: instruction not supported on this GPU<br>
+// GFX89: error: destination must be different than all sources<br>
<br>
v_mqsad_pk_u16_u8 v[0:1], v[1:2], v9, v[4:5]<br>
-// CHECK: error: destination must be different than all sources<br>
+// GCN: error: destination must be different than all sources<br>
<br>
v_mqsad_pk_u16_u8 v[1:2], v[1:2], v9, v[4:5]<br>
-// CHECK: error: destination must be different than all sources<br>
+// GCN: error: destination must be different than all sources<br>
<br>
v_mqsad_pk_u16_u8 v[2:3], v[1:2], v9, v[4:5]<br>
-// CHECK: error: destination must be different than all sources<br>
+// GCN: error: destination must be different than all sources<br>
<br>
v_mqsad_pk_u16_u8 v[3:4], v[0:1], v9, v[4:5]<br>
-// CHECK: error: destination must be different than all sources<br>
+// GCN: error: destination must be different than all sources<br>
<br>
v_mqsad_pk_u16_u8 v[4:5], v[1:2], v9, v[4:5]<br>
-// CHECK: error: destination must be different than all sources<br>
+// GCN: error: destination must be different than all sources<br>
<br>
v_mqsad_pk_u16_u8 v[5:6], v[1:2], v9, v[4:5]<br>
-// CHECK: error: destination must be different than all sources<br>
+// GCN: error: destination must be different than all sources<br>
<br>
v_mqsad_pk_u16_u8 v[8:9], v[1:2], v9, v[4:5]<br>
-// CHECK: error: destination must be different than all sources<br>
+// GCN: error: destination must be different than all sources<br>
<br>
v_mqsad_pk_u16_u8 v[9:10], v[1:2], v9, v[4:5]<br>
-// CHECK: error: destination must be different than all sources<br>
+// GCN: error: destination must be different than all sources<br>
+<br>
+v_cmp_eq_f32_e64 vcc, v0, v1 mul:2<br>
+// GCN: error: invalid operand for instruction<br>
+<br>
+v_cmp_le_f64_e64 vcc, v0, v1 mul:4<br>
+// GCN: error: invalid operand for instruction<br>
+<br>
+v_cvt_u32_f32_e64 v0, v1 div:2<br>
+// GCN: error: invalid operand for instruction<br>
\ No newline at end of file<br>
<br>
<br>
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