<div dir="ltr"><div>Hello Simon,<br><br>This commit broke one of our builders:<br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win</a><br><br>Failing Tests (1):<br> LLVM :: MC/Mips/mt/invalid.s<br><br>Please have a look?<br><br>Thanks<br><br></div>Galina<br><br><br><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jul 12, 2017 at 12:47 PM, Simon Dardis via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: sdardis<br>
Date: Wed Jul 12 12:47:45 2017<br>
New Revision: 307836<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=307836&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=307836&view=rev</a><br>
Log:<br>
[mips][mt][6/7] Add support for mftr, mttr instructions.<br>
<br>
Unlike many other instructions, these instructions have aliases which<br>
take coprocessor registers, gpr register, accumulator (and dsp accumulator)<br>
registers, floating point registers, floating point control registers and<br>
coprocessor 2 data and control operands.<br>
<br>
For the moment, these aliases are treated as pseudo instructions which are<br>
expanded into the underlying instruction. As a result, disassembling these<br>
instructions shows the underlying instruction and not the alias.<br>
<br>
Reviewers: slthakur, atanasyan<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D35253" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D35253</a><br>
<br>
Added:<br>
llvm/trunk/test/MC/Mips/mt/<wbr>invalid-wrong-error.s<br>
llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases-invalid-<wbr>wrong-error.s<br>
llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases-invalid.s<br>
llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases.s<br>
llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-reserved-valid.s<br>
Modified:<br>
llvm/trunk/lib/Target/Mips/<wbr>AsmParser/MipsAsmParser.cpp<br>
llvm/trunk/lib/Target/Mips/<wbr>MCTargetDesc/<wbr>MipsTargetStreamer.cpp<br>
llvm/trunk/lib/Target/Mips/<wbr>MipsMTInstrFormats.td<br>
llvm/trunk/lib/Target/Mips/<wbr>MipsMTInstrInfo.td<br>
llvm/trunk/lib/Target/Mips/<wbr>MipsSchedule.td<br>
llvm/trunk/lib/Target/Mips/<wbr>MipsTargetStreamer.h<br>
llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2-<wbr>el.txt<br>
llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2.<wbr>txt<br>
llvm/trunk/test/MC/Mips/mt/<wbr>invalid.s<br>
llvm/trunk/test/MC/Mips/mt/<wbr>valid.s<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/<wbr>AsmParser/MipsAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Mips/AsmParser/MipsAsmParser.<wbr>cpp?rev=307836&r1=307835&r2=<wbr>307836&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/<wbr>AsmParser/MipsAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/<wbr>AsmParser/MipsAsmParser.cpp Wed Jul 12 12:47:45 2017<br>
@@ -304,6 +304,9 @@ class MipsAsmParser : public MCTargetAsm<br>
bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,<br>
const MCSubtargetInfo *STI);<br>
<br>
+ bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,<br>
+ const MCSubtargetInfo *STI);<br>
+<br>
bool reportParseError(Twine ErrorMsg);<br>
bool reportParseError(SMLoc Loc, Twine ErrorMsg);<br>
<br>
@@ -2511,6 +2514,16 @@ MipsAsmParser::<wbr>tryExpandInstruction(MCIn<br>
return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;<br>
case Mips::SEQIMacro:<br>
return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;<br>
+ case Mips::MFTC0: case Mips::MTTC0:<br>
+ case Mips::MFTGPR: case Mips::MTTGPR:<br>
+ case Mips::MFTLO: case Mips::MTTLO:<br>
+ case Mips::MFTHI: case Mips::MTTHI:<br>
+ case Mips::MFTACX: case Mips::MTTACX:<br>
+ case Mips::MFTDSP: case Mips::MTTDSP:<br>
+ case Mips::MFTC1: case Mips::MTTC1:<br>
+ case Mips::MFTHC1: case Mips::MTTHC1:<br>
+ case Mips::CFTC1: case Mips::CTTC1:<br>
+ return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;<br>
}<br>
}<br>
<br>
@@ -4882,6 +4895,212 @@ bool MipsAsmParser::expandSeqI(<wbr>MCInst &I<br>
return false;<br>
}<br>
<br>
+// Map the DSP accumulator and control register to the corresponding gpr<br>
+// operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions<br>
+// do not map the DSP registers contigously to gpr registers.<br>
+static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {<br>
+ switch (Inst.getOpcode()) {<br>
+ case Mips::MFTLO:<br>
+ case Mips::MTTLO:<br>
+ switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {<br>
+ case Mips::AC0:<br>
+ return Mips::ZERO;<br>
+ case Mips::AC1:<br>
+ return Mips::A0;<br>
+ case Mips::AC2:<br>
+ return Mips::T0;<br>
+ case Mips::AC3:<br>
+ return Mips::T4;<br>
+ default:<br>
+ llvm_unreachable("Unknown register for 'mttr' alias!");<br>
+ }<br>
+ case Mips::MFTHI:<br>
+ case Mips::MTTHI:<br>
+ switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {<br>
+ case Mips::AC0:<br>
+ return Mips::AT;<br>
+ case Mips::AC1:<br>
+ return Mips::A1;<br>
+ case Mips::AC2:<br>
+ return Mips::T1;<br>
+ case Mips::AC3:<br>
+ return Mips::T5;<br>
+ default:<br>
+ llvm_unreachable("Unknown register for 'mttr' alias!");<br>
+ }<br>
+ case Mips::MFTACX:<br>
+ case Mips::MTTACX:<br>
+ switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {<br>
+ case Mips::AC0:<br>
+ return Mips::V0;<br>
+ case Mips::AC1:<br>
+ return Mips::A2;<br>
+ case Mips::AC2:<br>
+ return Mips::T2;<br>
+ case Mips::AC3:<br>
+ return Mips::T6;<br>
+ default:<br>
+ llvm_unreachable("Unknown register for 'mttr' alias!");<br>
+ }<br>
+ case Mips::MFTDSP:<br>
+ case Mips::MTTDSP:<br>
+ return Mips::S0;<br>
+ default:<br>
+ llvm_unreachable("Unknown instruction for 'mttr' dsp alias!");<br>
+ }<br>
+}<br>
+<br>
+// Map the floating point register operand to the corresponding register<br>
+// operand.<br>
+static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {<br>
+ switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) {<br>
+ case Mips::F0: return Mips::ZERO;<br>
+ case Mips::F1: return Mips::AT;<br>
+ case Mips::F2: return Mips::V0;<br>
+ case Mips::F3: return Mips::V1;<br>
+ case Mips::F4: return Mips::A0;<br>
+ case Mips::F5: return Mips::A1;<br>
+ case Mips::F6: return Mips::A2;<br>
+ case Mips::F7: return Mips::A3;<br>
+ case Mips::F8: return Mips::T0;<br>
+ case Mips::F9: return Mips::T1;<br>
+ case Mips::F10: return Mips::T2;<br>
+ case Mips::F11: return Mips::T3;<br>
+ case Mips::F12: return Mips::T4;<br>
+ case Mips::F13: return Mips::T5;<br>
+ case Mips::F14: return Mips::T6;<br>
+ case Mips::F15: return Mips::T7;<br>
+ case Mips::F16: return Mips::S0;<br>
+ case Mips::F17: return Mips::S1;<br>
+ case Mips::F18: return Mips::S2;<br>
+ case Mips::F19: return Mips::S3;<br>
+ case Mips::F20: return Mips::S4;<br>
+ case Mips::F21: return Mips::S5;<br>
+ case Mips::F22: return Mips::S6;<br>
+ case Mips::F23: return Mips::S7;<br>
+ case Mips::F24: return Mips::T8;<br>
+ case Mips::F25: return Mips::T9;<br>
+ case Mips::F26: return Mips::K0;<br>
+ case Mips::F27: return Mips::K1;<br>
+ case Mips::F28: return Mips::GP;<br>
+ case Mips::F29: return Mips::SP;<br>
+ case Mips::F30: return Mips::FP;<br>
+ case Mips::F31: return Mips::RA;<br>
+ default: llvm_unreachable("Unknown register for mttc1 alias!");<br>
+ }<br>
+}<br>
+<br>
+// Map the coprocessor operand the corresponding gpr register operand.<br>
+static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {<br>
+ switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) {<br>
+ case Mips::COP00: return Mips::ZERO;<br>
+ case Mips::COP01: return Mips::AT;<br>
+ case Mips::COP02: return Mips::V0;<br>
+ case Mips::COP03: return Mips::V1;<br>
+ case Mips::COP04: return Mips::A0;<br>
+ case Mips::COP05: return Mips::A1;<br>
+ case Mips::COP06: return Mips::A2;<br>
+ case Mips::COP07: return Mips::A3;<br>
+ case Mips::COP08: return Mips::T0;<br>
+ case Mips::COP09: return Mips::T1;<br>
+ case Mips::COP010: return Mips::T2;<br>
+ case Mips::COP011: return Mips::T3;<br>
+ case Mips::COP012: return Mips::T4;<br>
+ case Mips::COP013: return Mips::T5;<br>
+ case Mips::COP014: return Mips::T6;<br>
+ case Mips::COP015: return Mips::T7;<br>
+ case Mips::COP016: return Mips::S0;<br>
+ case Mips::COP017: return Mips::S1;<br>
+ case Mips::COP018: return Mips::S2;<br>
+ case Mips::COP019: return Mips::S3;<br>
+ case Mips::COP020: return Mips::S4;<br>
+ case Mips::COP021: return Mips::S5;<br>
+ case Mips::COP022: return Mips::S6;<br>
+ case Mips::COP023: return Mips::S7;<br>
+ case Mips::COP024: return Mips::T8;<br>
+ case Mips::COP025: return Mips::T9;<br>
+ case Mips::COP026: return Mips::K0;<br>
+ case Mips::COP027: return Mips::K1;<br>
+ case Mips::COP028: return Mips::GP;<br>
+ case Mips::COP029: return Mips::SP;<br>
+ case Mips::COP030: return Mips::FP;<br>
+ case Mips::COP031: return Mips::RA;<br>
+ default: llvm_unreachable("Unknown register for mttc0 alias!");<br>
+ }<br>
+}<br>
+<br>
+/// Expand an alias of 'mftr' or 'mttr' into the full instruction, by producing<br>
+/// an mftr or mttr with the correctly mapped gpr register, u, sel and h bits.<br>
+bool MipsAsmParser::<wbr>expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,<br>
+ const MCSubtargetInfo *STI) {<br>
+ MipsTargetStreamer &TOut = getTargetStreamer();<br>
+ unsigned rd = 0;<br>
+ unsigned u = 1;<br>
+ unsigned sel = 0;<br>
+ unsigned h = 0;<br>
+ bool IsMFTR = false;<br>
+ switch (Inst.getOpcode()) {<br>
+ case Mips::MFTC0:<br>
+ IsMFTR = true;<br>
+ LLVM_FALLTHROUGH;<br>
+ case Mips::MTTC0:<br>
+ u = 0;<br>
+ rd = getRegisterForMxtrC0(Inst, IsMFTR);<br>
+ sel = Inst.getOperand(2).getImm();<br>
+ break;<br>
+ case Mips::MFTGPR:<br>
+ IsMFTR = true;<br>
+ LLVM_FALLTHROUGH;<br>
+ case Mips::MTTGPR:<br>
+ rd = Inst.getOperand(IsMFTR ? 1 : 0).getReg();<br>
+ break;<br>
+ case Mips::MFTLO:<br>
+ case Mips::MFTHI:<br>
+ case Mips::MFTACX:<br>
+ case Mips::MFTDSP:<br>
+ IsMFTR = true;<br>
+ LLVM_FALLTHROUGH;<br>
+ case Mips::MTTLO:<br>
+ case Mips::MTTHI:<br>
+ case Mips::MTTACX:<br>
+ case Mips::MTTDSP:<br>
+ rd = getRegisterForMxtrDSP(Inst, IsMFTR);<br>
+ sel = 1;<br>
+ break;<br>
+ case Mips::MFTHC1:<br>
+ h = 1;<br>
+ LLVM_FALLTHROUGH;<br>
+ case Mips::MFTC1:<br>
+ IsMFTR = true;<br>
+ rd = getRegisterForMxtrFP(Inst, IsMFTR);<br>
+ sel = 2;<br>
+ break;<br>
+ case Mips::MTTHC1:<br>
+ h = 1;<br>
+ LLVM_FALLTHROUGH;<br>
+ case Mips::MTTC1:<br>
+ rd = getRegisterForMxtrFP(Inst, IsMFTR);<br>
+ sel = 2;<br>
+ break;<br>
+ case Mips::CFTC1:<br>
+ IsMFTR = true;<br>
+ LLVM_FALLTHROUGH;<br>
+ case Mips::CTTC1:<br>
+ rd = getRegisterForMxtrFP(Inst, IsMFTR);<br>
+ sel = 3;<br>
+ break;<br>
+ }<br>
+ unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd;<br>
+ unsigned Op1 =<br>
+ IsMFTR ? rd<br>
+ : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()<br>
+ : Inst.getOperand(0).getReg());<br>
+<br>
+ TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc,<br>
+ STI);<br>
+ return false;<br>
+}<br>
+<br>
unsigned<br>
MipsAsmParser::<wbr>checkEarlyTargetMatchPredicate<wbr>(MCInst &Inst,<br>
const OperandVector &Operands) {<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/<wbr>MCTargetDesc/<wbr>MipsTargetStreamer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Mips/MCTargetDesc/<wbr>MipsTargetStreamer.cpp?rev=<wbr>307836&r1=307835&r2=307836&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/<wbr>MCTargetDesc/<wbr>MipsTargetStreamer.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/<wbr>MCTargetDesc/<wbr>MipsTargetStreamer.cpp Wed Jul 12 12:47:45 2017<br>
@@ -193,6 +193,21 @@ void MipsTargetStreamer::emitRRI(<wbr>unsigne<br>
emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);<br>
}<br>
<br>
+void MipsTargetStreamer::emitRRIII(<wbr>unsigned Opcode, unsigned Reg0,<br>
+ unsigned Reg1, int16_t Imm0, int16_t Imm1,<br>
+ int16_t Imm2, SMLoc IDLoc,<br>
+ const MCSubtargetInfo *STI) {<br>
+ MCInst TmpInst;<br>
+ TmpInst.setOpcode(Opcode);<br>
+ TmpInst.addOperand(MCOperand::<wbr>createReg(Reg0));<br>
+ TmpInst.addOperand(MCOperand::<wbr>createReg(Reg1));<br>
+ TmpInst.addOperand(MCOperand::<wbr>createImm(Imm0));<br>
+ TmpInst.addOperand(MCOperand::<wbr>createImm(Imm1));<br>
+ TmpInst.addOperand(MCOperand::<wbr>createImm(Imm2));<br>
+ TmpInst.setLoc(IDLoc);<br>
+ getStreamer().EmitInstruction(<wbr>TmpInst, *STI);<br>
+}<br>
+<br>
void MipsTargetStreamer::emitAddu(<wbr>unsigned DstReg, unsigned SrcReg,<br>
unsigned TrgReg, bool Is64Bit,<br>
const MCSubtargetInfo *STI) {<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/<wbr>MipsMTInstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Mips/MipsMTInstrFormats.td?<wbr>rev=307836&r1=307835&r2=<wbr>307836&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/<wbr>MipsMTInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/Mips/<wbr>MipsMTInstrFormats.td Wed Jul 12 12:47:45 2017<br>
@@ -35,6 +35,8 @@ class FIELD5<bits<5> Val> {<br>
def FIELD5_1_DMT_EMT : FIELD5<0b00001>;<br>
def FIELD5_2_DMT_EMT : FIELD5<0b01111>;<br>
def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;<br>
+def FIELD5_MFTR : FIELD5<0b01000>;<br>
+def FIELD5_MTTR : FIELD5<0b01100>;<br>
<br>
class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {<br>
bits<32> Inst;<br>
@@ -50,6 +52,25 @@ class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 O<br>
let Inst{2-0} = 0b001;<br>
}<br>
<br>
+class COP0_MFTTR_MT<FIELD5 Op> : MipsMTInst {<br>
+ bits<32> Inst;<br>
+<br>
+ bits<5> rt;<br>
+ bits<5> rd;<br>
+ bits<1> u;<br>
+ bits<1> h;<br>
+ bits<3> sel;<br>
+ let Inst{31-26} = 0b010000; // COP0<br>
+ let Inst{25-21} = Op.Value; // MFMC0<br>
+ let Inst{20-16} = rt;<br>
+ let Inst{15-11} = rd;<br>
+ let Inst{10-6} = 0b00000; // rx - currently unsupported.<br>
+ let Inst{5} = u;<br>
+ let Inst{4} = h;<br>
+ let Inst{3} = 0b0;<br>
+ let Inst{2-0} = sel;<br>
+}<br>
+<br>
class SPECIAL3_MT_FORK : MipsMTInst {<br>
bits<32> Inst;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/<wbr>MipsMTInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMTInstrInfo.td?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Mips/MipsMTInstrInfo.td?rev=<wbr>307836&r1=307835&r2=307836&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/<wbr>MipsMTInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/Mips/<wbr>MipsMTInstrInfo.td Wed Jul 12 12:47:45 2017<br>
@@ -6,6 +6,13 @@<br>
// License. See LICENSE.TXT for details.<br>
//<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
+//<br>
+// This file describes the MIPS MT ASE as defined by MD00378 1.12.<br>
+//<br>
+// TODO: Add support for the microMIPS encodings for the MT ASE and add the<br>
+// instruction mappings.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
// MIPS MT Instruction Encodings<br>
@@ -27,6 +34,10 @@ class FORK_ENC : SPECIAL3_MT_FORK;<br>
<br>
class YIELD_ENC : SPECIAL3_MT_YIELD;<br>
<br>
+class MFTR_ENC : COP0_MFTTR_MT<FIELD5_MFTR>;<br>
+<br>
+class MTTR_ENC : COP0_MFTTR_MT<FIELD5_MTTR>;<br>
+<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
// MIPS MT Instruction Descriptions<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
@@ -39,6 +50,22 @@ class MT_1R_DESC_BASE<string instr_asm,<br>
InstrItinClass Itinerary = Itin;<br>
}<br>
<br>
+class MFTR_DESC {<br>
+ dag OutOperandList = (outs GPR32Opnd:$rd);<br>
+ dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);<br>
+ string AsmString = "mftr\t$rd, $rt, $u, $sel, $h";<br>
+ list<dag> Pattern = [];<br>
+ InstrItinClass Itinerary = II_MFTR;<br>
+}<br>
+<br>
+class MTTR_DESC {<br>
+ dag OutOperandList = (outs GPR32Opnd:$rd);<br>
+ dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);<br>
+ string AsmString = "mttr\t$rt, $rd, $u, $sel, $h";<br>
+ list<dag> Pattern = [];<br>
+ InstrItinClass Itinerary = II_MTTR;<br>
+}<br>
+<br>
class FORK_DESC {<br>
dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);<br>
dag InOperandList = (ins GPR32Opnd:$rt);<br>
@@ -79,9 +106,74 @@ let hasSideEffects = 1, isNotDuplicable<br>
def FORK : FORK_ENC, FORK_DESC, ASE_MT;<br>
<br>
def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT;<br>
+<br>
+ def MFTR : MFTR_ENC, MFTR_DESC, ASE_MT;<br>
+<br>
+ def MTTR : MTTR_ENC, MTTR_DESC, ASE_MT;<br>
}<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
+// MIPS MT Pseudo Instructions - used to support mtfr & mttr aliases.<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+def MFTC0 : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins COP0Opnd:$rt,<br>
+ uimm3:$sel),<br>
+ "mftc0 $rd, $rt, $sel">, ASE_MT;<br>
+<br>
+def MFTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rt,<br>
+ uimm3:$sel),<br>
+ "mftgpr $rd, $rt">, ASE_MT;<br>
+<br>
+def MFTLO : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),<br>
+ "mftlo $rt, $ac">, ASE_MT;<br>
+<br>
+def MFTHI : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),<br>
+ "mfthi $rt, $ac">, ASE_MT;<br>
+<br>
+def MFTACX : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),<br>
+ "mftacx $rt, $ac">, ASE_MT;<br>
+<br>
+def MFTDSP : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins),<br>
+ "mftdsp $rt">, ASE_MT;<br>
+<br>
+def MFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),<br>
+ "mftc1 $rt, $ft">, ASE_MT;<br>
+<br>
+def MFTHC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),<br>
+ "mfthc1 $rt, $ft">, ASE_MT;<br>
+<br>
+def CFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGRCCOpnd:$ft),<br>
+ "cftc1 $rt, $ft">, ASE_MT;<br>
+<br>
+<br>
+def MTTC0 : MipsAsmPseudoInst<(outs COP0Opnd:$rd), (ins GPR32Opnd:$rt,<br>
+ uimm3:$sel),<br>
+ "mttc0 $rt, $rd, $sel">, ASE_MT;<br>
+<br>
+def MTTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins GPR32Opnd:$rd),<br>
+ "mttgpr $rd, $rt">, ASE_MT;<br>
+<br>
+def MTTLO : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),<br>
+ "mttlo $rt, $ac">, ASE_MT;<br>
+<br>
+def MTTHI : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),<br>
+ "mtthi $rt, $ac">, ASE_MT;<br>
+<br>
+def MTTACX : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),<br>
+ "mttacx $rt, $ac">, ASE_MT;<br>
+<br>
+def MTTDSP : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rt),<br>
+ "mttdsp $rt">, ASE_MT;<br>
+<br>
+def MTTC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),<br>
+ "mttc1 $rt, $ft">, ASE_MT;<br>
+<br>
+def MTTHC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),<br>
+ "mtthc1 $rt, $ft">, ASE_MT;<br>
+<br>
+def CTTC1 : MipsAsmPseudoInst<(outs FGRCCOpnd:$ft), (ins GPR32Opnd:$rt),<br>
+ "cttc1 $rt, $ft">, ASE_MT;<br>
+<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
// MIPS MT Instruction Definitions<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
@@ -95,4 +187,22 @@ let AdditionalPredicates = [NotInMicroMi<br>
def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;<br>
<br>
def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;<br>
+<br>
+ def : MipsInstAlias<"mftc0 $rd, $rt", (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0),<br>
+ 1>, ASE_MT;<br>
+<br>
+ def : MipsInstAlias<"mftlo $rt", (MFTLO GPR32Opnd:$rt, AC0), 1>, ASE_MT;<br>
+<br>
+ def : MipsInstAlias<"mfthi $rt", (MFTHI GPR32Opnd:$rt, AC0), 1>, ASE_MT;<br>
+<br>
+ def : MipsInstAlias<"mftacx $rt", (MFTACX GPR32Opnd:$rt, AC0), 1>, ASE_MT;<br>
+<br>
+ def : MipsInstAlias<"mttc0 $rd, $rt", (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0),<br>
+ 1>, ASE_MT;<br>
+<br>
+ def : MipsInstAlias<"mttlo $rt", (MTTLO AC0, GPR32Opnd:$rt), 1>, ASE_MT;<br>
+<br>
+ def : MipsInstAlias<"mtthi $rt", (MTTHI AC0, GPR32Opnd:$rt), 1>, ASE_MT;<br>
+<br>
+ def : MipsInstAlias<"mttacx $rt", (MTTACX AC0, GPR32Opnd:$rt), 1>, ASE_MT;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/<wbr>MipsSchedule.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSchedule.td?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Mips/MipsSchedule.td?rev=<wbr>307836&r1=307835&r2=307836&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/<wbr>MipsSchedule.td (original)<br>
+++ llvm/trunk/lib/Target/Mips/<wbr>MipsSchedule.td Wed Jul 12 12:47:45 2017<br>
@@ -226,6 +226,7 @@ def II_MFC1 : InstrItinClass<br>
def II_MFHC1 : InstrItinClass;<br>
def II_MFC2 : InstrItinClass;<br>
def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo<br>
+def II_MFTR : InstrItinClass;<br>
def II_MOD : InstrItinClass;<br>
def II_MODU : InstrItinClass;<br>
def II_MOVE : InstrItinClass;<br>
@@ -255,6 +256,7 @@ def II_MTC1 : InstrItinClass<br>
def II_MTHC1 : InstrItinClass;<br>
def II_MTC2 : InstrItinClass;<br>
def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo<br>
+def II_MTTR : InstrItinClass;<br>
def II_MUL : InstrItinClass;<br>
def II_MUH : InstrItinClass;<br>
def II_MUHU : InstrItinClass;<br>
@@ -664,12 +666,14 @@ def MipsGenericItineraries : ProcessorIt<br>
InstrItinData<II_MFHC0 , [InstrStage<2, [ALU]>]>,<br>
InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>,<br>
InstrItinData<II_MFC2 , [InstrStage<2, [ALU]>]>,<br>
+ InstrItinData<II_MFTR , [InstrStage<2, [ALU]>]>,<br>
InstrItinData<II_MTC0 , [InstrStage<2, [ALU]>]>,<br>
InstrItinData<II_MTHC0 , [InstrStage<2, [ALU]>]>,<br>
InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>,<br>
InstrItinData<II_MTC2 , [InstrStage<2, [ALU]>]>,<br>
InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>,<br>
InstrItinData<II_MTHC1 , [InstrStage<2, [ALU]>]>,<br>
+ InstrItinData<II_MTTR , [InstrStage<2, [ALU]>]>,<br>
InstrItinData<II_CACHE , [InstrStage<1, [ALU]>]>,<br>
InstrItinData<II_PREF , [InstrStage<1, [ALU]>]>,<br>
InstrItinData<II_CACHEE , [InstrStage<1, [ALU]>]>,<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/<wbr>MipsTargetStreamer.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetStreamer.h?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Mips/MipsTargetStreamer.h?rev=<wbr>307836&r1=307835&r2=307836&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/<wbr>MipsTargetStreamer.h (original)<br>
+++ llvm/trunk/lib/Target/Mips/<wbr>MipsTargetStreamer.h Wed Jul 12 12:47:45 2017<br>
@@ -119,6 +119,9 @@ public:<br>
SMLoc IDLoc, const MCSubtargetInfo *STI);<br>
void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,<br>
SMLoc IDLoc, const MCSubtargetInfo *STI);<br>
+ void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,<br>
+ int16_t Imm1, int16_t Imm2, SMLoc IDLoc,<br>
+ const MCSubtargetInfo *STI);<br>
void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit,<br>
const MCSubtargetInfo *STI);<br>
void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,<br>
<br>
Modified: llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2-<wbr>el.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2-el.txt?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2-<wbr>el.txt?rev=307836&r1=307835&<wbr>r2=307836&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2-<wbr>el.txt (original)<br>
+++ llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2-<wbr>el.txt Wed Jul 12 12:47:45 2017<br>
@@ -10,4 +10,23 @@<br>
0x08 0x10 0x65 0x7c # CHECK: fork $2, $3, $5<br>
0x09 0x00 0x80 0x7c # CHECK: yield $4<br>
0x09 0x20 0xa0 0x7c # CHECK: yield $4, $5<br>
-<br>
+0x02 0x20 0x05 0x41 # CHECK: mftr $4, $5, 0, 2, 0<br>
+0x20 0x20 0x05 0x41 # CHECK: mftr $4, $5, 1, 0, 0<br>
+0x21 0x20 0x00 0x41 # CHECK: mftr $4, $zero, 1, 1, 0<br>
+0x21 0x20 0x0a 0x41 # CHECK: mftr $4, $10, 1, 1, 0<br>
+0x22 0x20 0x0a 0x41 # CHECK: mftr $4, $10, 1, 2, 0<br>
+0x32 0x20 0x0a 0x41 # CHECK: mftr $4, $10, 1, 2, 1<br>
+0x23 0x20 0x1a 0x41 # CHECK: mftr $4, $26, 1, 3, 0<br>
+0x23 0x20 0x1f 0x41 # CHECK: mftr $4, $ra, 1, 3, 0<br>
+0x24 0x20 0x0e 0x41 # CHECK: mftr $4, $14, 1, 4, 0<br>
+0x25 0x20 0x0f 0x41 # CHECK: mftr $4, $15, 1, 5, 0<br>
+0x02 0x28 0x84 0x41 # CHECK: mttr $4, $5, 0, 2, 0<br>
+0x20 0x28 0x84 0x41 # CHECK: mttr $4, $5, 1, 0, 0<br>
+0x21 0x00 0x84 0x41 # CHECK: mttr $4, $zero, 1, 1, 0<br>
+0x21 0x50 0x84 0x41 # CHECK: mttr $4, $10, 1, 1, 0<br>
+0x22 0x50 0x84 0x41 # CHECK: mttr $4, $10, 1, 2, 0<br>
+0x32 0x50 0x84 0x41 # CHECK: mttr $4, $10, 1, 2, 1<br>
+0x23 0xd0 0x84 0x41 # CHECK: mttr $4, $26, 1, 3, 0<br>
+0x23 0xf8 0x84 0x41 # CHECK: mttr $4, $ra, 1, 3, 0<br>
+0x24 0x70 0x84 0x41 # CHECK: mttr $4, $14, 1, 4, 0<br>
+0x25 0x78 0x84 0x41 # CHECK: mttr $4, $15, 1, 5, 0<br>
<br>
Modified: llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2.<wbr>txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mt/valid-r2.txt?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2.<wbr>txt?rev=307836&r1=307835&r2=<wbr>307836&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2.<wbr>txt (original)<br>
+++ llvm/trunk/test/MC/<wbr>Disassembler/Mips/mt/valid-r2.<wbr>txt Wed Jul 12 12:47:45 2017<br>
@@ -10,4 +10,23 @@<br>
0x7c 0x65 0x10 0x08 # CHECK: fork $2, $3, $5<br>
0x7c 0x80 0x00 0x09 # CHECK: yield $4<br>
0x7c 0xa0 0x20 0x09 # CHECK: yield $4, $5<br>
-<br>
+0x41 0x05 0x20 0x02 # CHECK: mftr $4, $5, 0, 2, 0<br>
+0x41 0x05 0x20 0x20 # CHECK: mftr $4, $5, 1, 0, 0<br>
+0x41 0x00 0x20 0x21 # CHECK: mftr $4, $zero, 1, 1, 0<br>
+0x41 0x0a 0x20 0x21 # CHECK: mftr $4, $10, 1, 1, 0<br>
+0x41 0x0a 0x20 0x22 # CHECK: mftr $4, $10, 1, 2, 0<br>
+0x41 0x0a 0x20 0x32 # CHECK: mftr $4, $10, 1, 2, 1<br>
+0x41 0x1a 0x20 0x23 # CHECK: mftr $4, $26, 1, 3, 0<br>
+0x41 0x1f 0x20 0x23 # CHECK: mftr $4, $ra, 1, 3, 0<br>
+0x41 0x0e 0x20 0x24 # CHECK: mftr $4, $14, 1, 4, 0<br>
+0x41 0x0f 0x20 0x25 # CHECK: mftr $4, $15, 1, 5, 0<br>
+0x41 0x84 0x28 0x02 # CHECK: mttr $4, $5, 0, 2, 0<br>
+0x41 0x84 0x28 0x20 # CHECK: mttr $4, $5, 1, 0, 0<br>
+0x41 0x84 0x00 0x21 # CHECK: mttr $4, $zero, 1, 1, 0<br>
+0x41 0x84 0x50 0x21 # CHECK: mttr $4, $10, 1, 1, 0<br>
+0x41 0x84 0x50 0x22 # CHECK: mttr $4, $10, 1, 2, 0<br>
+0x41 0x84 0x50 0x32 # CHECK: mttr $4, $10, 1, 2, 1<br>
+0x41 0x84 0xd0 0x23 # CHECK: mttr $4, $26, 1, 3, 0<br>
+0x41 0x84 0xf8 0x23 # CHECK: mttr $4, $ra, 1, 3, 0<br>
+0x41 0x84 0x70 0x24 # CHECK: mttr $4, $14, 1, 4, 0<br>
+0x41 0x84 0x78 0x25 # CHECK: mttr $4, $15, 1, 5, 0<br>
<br>
Added: llvm/trunk/test/MC/Mips/mt/<wbr>invalid-wrong-error.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/invalid-wrong-error.s?rev=307836&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Mips/mt/invalid-wrong-error.s?<wbr>rev=307836&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/mt/<wbr>invalid-wrong-error.s (added)<br>
+++ llvm/trunk/test/MC/Mips/mt/<wbr>invalid-wrong-error.s Wed Jul 12 12:47:45 2017<br>
@@ -0,0 +1,3 @@<br>
+# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt < %s 2>&1 | FileCheck %s<br>
+ mftr 0($4), $5, 0, 0, 0 # CHECK: error: unexpected token in argument list<br>
+ mttr 0($4), $5, 0, 0, 0 # CHECK: error: unexpected token in argument list<br>
<br>
Modified: llvm/trunk/test/MC/Mips/mt/<wbr>invalid.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/invalid.s?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Mips/mt/invalid.s?rev=307836&<wbr>r1=307835&r2=307836&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/mt/<wbr>invalid.s (original)<br>
+++ llvm/trunk/test/MC/Mips/mt/<wbr>invalid.s Wed Jul 12 12:47:45 2017<br>
@@ -1,13 +1,27 @@<br>
# RUN: not llvm-mc -arch=mips -mcpu=mips32 -mattr=+mt < %s 2>&1 | FileCheck %s<br>
- dmt 4 # CHECK: error: invalid operand for instruction<br>
- dmt $4, $5 # CHECK: error: invalid operand for instruction<br>
- dmt $5, 0($4) # CHECK: error: invalid operand for instruction<br>
- emt 4 # CHECK: error: invalid operand for instruction<br>
- emt $4, $5 # CHECK: error: invalid operand for instruction<br>
- emt $5, 0($5) # CHECK: error: invalid operand for instruction<br>
- dvpe 4 # CHECK: error: invalid operand for instruction<br>
- dvpe $4, $5 # CHECK: error: invalid operand for instruction<br>
- dvpe $5, 0($4) # CHECK: error: invalid operand for instruction<br>
- evpe 4 # CHECK: error: invalid operand for instruction<br>
- evpe $4, $5 # CHECK: error: invalid operand for instruction<br>
- evpe $5, 0($5) # CHECK: error: invalid operand for instruction<br>
+ dmt 4 # CHECK: error: invalid operand for instruction<br>
+ dmt $4, $5 # CHECK: error: invalid operand for instruction<br>
+ dmt $5, 0($4) # CHECK: error: invalid operand for instruction<br>
+ emt 4 # CHECK: error: invalid operand for instruction<br>
+ emt $4, $5 # CHECK: error: invalid operand for instruction<br>
+ emt $5, 0($5) # CHECK: error: invalid operand for instruction<br>
+ dvpe 4 # CHECK: error: invalid operand for instruction<br>
+ dvpe $4, $5 # CHECK: error: invalid operand for instruction<br>
+ dvpe $5, 0($4) # CHECK: error: invalid operand for instruction<br>
+ evpe 4 # CHECK: error: invalid operand for instruction<br>
+ evpe $4, $5 # CHECK: error: invalid operand for instruction<br>
+ evpe $5, 0($5) # CHECK: error: invalid operand for instruction<br>
+ mftr $4, 0($5), 0, 0, 0 #Â CHECK: error: invalid operand for instruction<br>
+ mftr $4, $5, 2, 0, 0 #Â CHECK: error: expected 1-bit unsigned immediate<br>
+ mftr $4, $5, -1, 0, 0 #Â CHECK: error: expected 1-bit unsigned immediate<br>
+ mftr $4, $5, 0, 8, 0 #Â CHECK: error: expected 3-bit unsigned immediate<br>
+ mftr $4, $5, 0, -1, 0 #Â CHECK: error: expected 3-bit unsigned immediate<br>
+ mftr $4, $4, 0, 0, 2 #Â CHECK: error: expected 1-bit unsigned immediate<br>
+ mftr $4, $5, 0, 0, -1 #Â CHECK: error: expected 1-bit unsigned immediate<br>
+ mttr $4, 0($5), 0, 0, 0 #Â CHECK: error: invalid operand for instruction<br>
+ mttr $4, $5, 2, 0, 0 #Â CHECK: error: expected 1-bit unsigned immediate<br>
+ mttr $4, $5, -1, 0, 0 #Â CHECK: error: expected 1-bit unsigned immediate<br>
+ mttr $4, $5, 0, 8, 0 #Â CHECK: error: expected 3-bit unsigned immediate<br>
+ mttr $4, $5, 0, -1, 0 #Â CHECK: error: expected 3-bit unsigned immediate<br>
+ mttr $4, $4, 0, 0, 2 #Â CHECK: error: expected 1-bit unsigned immediate<br>
+ mttr $4, $5, 0, 0, -1 #Â CHECK: error: expected 1-bit unsigned immediate<br>
<br>
Added: llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases-invalid-<wbr>wrong-error.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/mftr-mttr-aliases-invalid-wrong-error.s?rev=307836&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Mips/mt/mftr-mttr-aliases-<wbr>invalid-wrong-error.s?rev=<wbr>307836&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases-invalid-<wbr>wrong-error.s (added)<br>
+++ llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases-invalid-<wbr>wrong-error.s Wed Jul 12 12:47:45 2017<br>
@@ -0,0 +1,18 @@<br>
+# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \<br>
+# RUN: 2>&1 | FileCheck %s<br>
+<br>
+# The integrated assembler produces a wrong or misleading error message.<br>
+<br>
+ mftc0 0($4), $5 # CHECK: error: unexpected token in argument list<br>
+ mftc0 0($4), $5, 1 # CHECK: error: unexpected token in argument list<br>
+ mftgpr 0($4), $5 # CHECK: error: unexpected token in argument list<br>
+ mftlo 0($3) # CHECK: error: unexpected token in argument list<br>
+ mftlo 0($3), $ac1 # CHECK: error: unexpected token in argument list<br>
+ mfthi 0($3) # CHECK: error: unexpected token in argument list<br>
+ mfthi 0($3), $ac1 # CHECK: error: unexpected token in argument list<br>
+ mftacx 0($3) # CHECK: error: unexpected token in argument list<br>
+ mftacx 0($3), $ac1 # CHECK: error: unexpected token in argument list<br>
+ mftdsp 0($4) # CHECK: error: unexpected token in argument list<br>
+ mftc1 0($4), $f4 # CHECK: error: unexpected token in argument list<br>
+ mfthc1 0($4), $f4 # CHECK: error: unexpected token in argument list<br>
+ cftc1 0($4), $f8 # CHECK: error: unexpected token in argument list<br>
<br>
Added: llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases-invalid.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/mftr-mttr-aliases-invalid.s?rev=307836&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Mips/mt/mftr-mttr-aliases-<wbr>invalid.s?rev=307836&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases-invalid.s (added)<br>
+++ llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases-invalid.s Wed Jul 12 12:47:45 2017<br>
@@ -0,0 +1,23 @@<br>
+# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \<br>
+# RUN: 2>&1 | FileCheck %s<br>
+<br>
+ mftc0 $4, 0($5) # CHECK: error: invalid operand for instruction<br>
+ mftc0 $4, 0($5), 1 # CHECK: error: invalid operand for instruction<br>
+ mftc0 $4, $5, -1 # CHECK: error: expected 3-bit unsigned immediate<br>
+ mftc0 $4, $5, 9 # CHECK: error: expected 3-bit unsigned immediate<br>
+ mftc0 $4, $5, $6 # CHECK: error: expected 3-bit unsigned immediate<br>
+ mftgpr $4, 0($5) # CHECK: error: invalid operand for instruction<br>
+ mftgpr $4, $5, $6 # CHECK: error: invalid operand for instruction<br>
+ mftlo $3, 0($ac1) # CHECK: error: invalid operand for instruction<br>
+ mftlo $4, $ac1, $4 # CHECK: error: invalid operand for instruction<br>
+ mfthi $3, 0($ac1) # CHECK: error: invalid operand for instruction<br>
+ mfthi $4, $ac1, $4 # CHECK: error: invalid operand for instruction<br>
+ mftacx $3, 0($ac1) # CHECK: error: invalid operand for instruction<br>
+ mftacx $4, $ac1, $4 # CHECK: error: invalid operand for instruction<br>
+ mftdsp $4, $5 # CHECK: error: invalid operand for instruction<br>
+ mftdsp $4, $f5 # CHECK: error: invalid operand for instruction<br>
+ mftdsp $4, $ac0 # CHECK: error: invalid operand for instruction<br>
+ mftc1 $4, 0($f4) # CHECK: error: invalid operand for instruction<br>
+ mfthc1 $4, 0($f4) # CHECK: error: invalid operand for instruction<br>
+ cftc1 $4, 0($f4) # CHECK: error: invalid operand for instruction<br>
+ cftc1 $4, $f4, $5 # CHECK: error: invalid operand for instruction<br>
<br>
Added: llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/mftr-mttr-aliases.s?rev=307836&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Mips/mt/mftr-mttr-aliases.s?<wbr>rev=307836&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases.s (added)<br>
+++ llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-aliases.s Wed Jul 12 12:47:45 2017<br>
@@ -0,0 +1,47 @@<br>
+# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s<br>
+<br>
+# Check the various aliases of the m[ft]tr instruction.<br>
+<br>
+ mftc0 $4, $5 # CHECK: mftr $4, $5, 0, 0, 0 # encoding: [0x41,0x05,0x20,0x00]<br>
+ mftc0 $6, $7, 1 # CHECK: mftr $6, $7, 0, 1, 0 # encoding: [0x41,0x07,0x30,0x01]<br>
+ mftgpr $5, $9 # CHECK: mftr $5, $9, 1, 0, 0 # encoding: [0x41,0x09,0x28,0x20]<br>
+ mftlo $3 # CHECK: mftr $3, $zero, 1, 1, 0 # encoding: [0x41,0x00,0x18,0x21]<br>
+ mftlo $3, $ac0 # CHECK: mftr $3, $zero, 1, 1, 0 # encoding: [0x41,0x00,0x18,0x21]<br>
+ mftlo $3, $ac1 # CHECK: mftr $3, $4, 1, 1, 0 # encoding: [0x41,0x04,0x18,0x21]<br>
+ mftlo $3, $ac2 # CHECK: mftr $3, $8, 1, 1, 0 # encoding: [0x41,0x08,0x18,0x21]<br>
+ mftlo $3, $ac3 # CHECK: mftr $3, $12, 1, 1, 0 # encoding: [0x41,0x0c,0x18,0x21]<br>
+ mfthi $3, $ac0 # CHECK: mftr $3, $1, 1, 1, 0 # encoding: [0x41,0x01,0x18,0x21]<br>
+ mfthi $3, $ac1 # CHECK: mftr $3, $5, 1, 1, 0 # encoding: [0x41,0x05,0x18,0x21]<br>
+ mfthi $3, $ac2 # CHECK: mftr $3, $9, 1, 1, 0 # encoding: [0x41,0x09,0x18,0x21]<br>
+ mfthi $3, $ac3 # CHECK: mftr $3, $13, 1, 1, 0 # encoding: [0x41,0x0d,0x18,0x21]<br>
+ mftacx $3, $ac0 # CHECK: mftr $3, $2, 1, 1, 0 # encoding: [0x41,0x02,0x18,0x21]<br>
+ mftacx $3, $ac1 # CHECK: mftr $3, $6, 1, 1, 0 # encoding: [0x41,0x06,0x18,0x21]<br>
+ mftacx $3, $ac2 # CHECK: mftr $3, $10, 1, 1, 0 # encoding: [0x41,0x0a,0x18,0x21]<br>
+ mftacx $3, $ac3 # CHECK: mftr $3, $14, 1, 1, 0 # encoding: [0x41,0x0e,0x18,0x21]<br>
+ mftdsp $4 # CHECK: mftr $4, $16, 1, 1, 0 # encoding: [0x41,0x10,0x20,0x21]<br>
+ mftc1 $4, $f5 # CHECK: mftr $4, $5, 1, 2, 0 # encoding: [0x41,0x05,0x20,0x22]<br>
+ mfthc1 $4, $f5 # CHECK: mftr $4, $5, 1, 2, 1 # encoding: [0x41,0x05,0x20,0x32]<br>
+ cftc1 $4, $f9 # CHECK: mftr $4, $9, 1, 3, 0 # encoding: [0x41,0x09,0x20,0x23]<br>
+<br>
+ mttc0 $4, $5 # CHECK: mttr $4, $5, 0, 0, 0 # encoding: [0x41,0x84,0x28,0x00]<br>
+ mttc0 $6, $7, 1 # CHECK: mttr $6, $7, 0, 1, 0 # encoding: [0x41,0x86,0x38,0x01]<br>
+ mttgpr $5, $9 # CHECK: mttr $5, $9, 1, 0, 0 # encoding: [0x41,0x85,0x48,0x20]<br>
+ mttlo $3 # CHECK: mttr $3, $zero, 1, 1, 0 # encoding: [0x41,0x83,0x00,0x21]<br>
+ mttlo $3, $ac0 # CHECK: mttr $3, $zero, 1, 1, 0 # encoding: [0x41,0x83,0x00,0x21]<br>
+ mttlo $3, $ac1 # CHECK: mttr $3, $4, 1, 1, 0 # encoding: [0x41,0x83,0x20,0x21]<br>
+ mttlo $3, $ac2 # CHECK: mttr $3, $8, 1, 1, 0 # encoding: [0x41,0x83,0x40,0x21]<br>
+ mttlo $3, $ac3 # CHECK: mttr $3, $12, 1, 1, 0 # encoding: [0x41,0x83,0x60,0x21]<br>
+ mtthi $3 # CHECK: mttr $3, $1, 1, 1, 0 # encoding: [0x41,0x83,0x08,0x21]<br>
+ mtthi $3, $ac0 # CHECK: mttr $3, $1, 1, 1, 0 # encoding: [0x41,0x83,0x08,0x21]<br>
+ mtthi $3, $ac1 # CHECK: mttr $3, $5, 1, 1, 0 # encoding: [0x41,0x83,0x28,0x21]<br>
+ mtthi $3, $ac2 # CHECK: mttr $3, $9, 1, 1, 0 # encoding: [0x41,0x83,0x48,0x21]<br>
+ mtthi $3, $ac3 # CHECK: mttr $3, $13, 1, 1, 0 # encoding: [0x41,0x83,0x68,0x21]<br>
+ mttacx $3 # CHECK: mttr $3, $2, 1, 1, 0 # encoding: [0x41,0x83,0x10,0x21]<br>
+ mttacx $3, $ac0 # CHECK: mttr $3, $2, 1, 1, 0 # encoding: [0x41,0x83,0x10,0x21]<br>
+ mttacx $3, $ac1 # CHECK: mttr $3, $6, 1, 1, 0 # encoding: [0x41,0x83,0x30,0x21]<br>
+ mttacx $3, $ac2 # CHECK: mttr $3, $10, 1, 1, 0 # encoding: [0x41,0x83,0x50,0x21]<br>
+ mttacx $3, $ac3 # CHECK: mttr $3, $14, 1, 1, 0 # encoding: [0x41,0x83,0x70,0x21]<br>
+ mttdsp $4 # CHECK: mttr $4, $16, 1, 1, 0 # encoding: [0x41,0x84,0x80,0x21]<br>
+ mttc1 $4, $f5 # CHECK: mttr $4, $5, 1, 2, 0 # encoding: [0x41,0x84,0x28,0x22]<br>
+ mtthc1 $4, $f5 # CHECK: mttr $4, $5, 1, 2, 1 # encoding: [0x41,0x84,0x28,0x32]<br>
+ cttc1 $4, $f9 # CHECK: mttr $4, $9, 1, 3, 0 # encoding: [0x41,0x84,0x48,0x23]<br>
<br>
Added: llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-reserved-valid.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/mftr-mttr-reserved-valid.s?rev=307836&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Mips/mt/mftr-mttr-reserved-<wbr>valid.s?rev=307836&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-reserved-valid.s (added)<br>
+++ llvm/trunk/test/MC/Mips/mt/<wbr>mftr-mttr-reserved-valid.s Wed Jul 12 12:47:45 2017<br>
@@ -0,0 +1,8 @@<br>
+# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s | FileCheck %s<br>
+<br>
+# The selector value and register values here are marked as reserved in the<br>
+# documentation, but GAS accepts them without warning.<br>
+ mftr $31, $31, 1, 1, 0 # CHECK: mftr $ra, $ra, 1, 1, 0 # encoding: [0x41,0x1f,0xf8,0x21]<br>
+ mttr $31, $31, 1, 1, 0 # CHECK: mttr $ra, $ra, 1, 1, 0 # encoding: [0x41,0x9f,0xf8,0x21]<br>
+ mftr $31, $13, 1, 6, 0 # CHECK: mftr $ra, $13, 1, 6, 0 # encoding: [0x41,0x0d,0xf8,0x26]<br>
+ mttr $31, $13, 1, 6, 0 # CHECK: mttr $ra, $13, 1, 6, 0 # encoding: [0x41,0x9f,0x68,0x26]<br>
<br>
Modified: llvm/trunk/test/MC/Mips/mt/<wbr>valid.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mt/valid.s?rev=307836&r1=307835&r2=307836&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Mips/mt/valid.s?rev=307836&r1=<wbr>307835&r2=307836&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/mt/<wbr>valid.s (original)<br>
+++ llvm/trunk/test/MC/Mips/mt/<wbr>valid.s Wed Jul 12 12:47:45 2017<br>
@@ -1,13 +1,33 @@<br>
# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mt -show-encoding < %s \<br>
# RUN: | FileCheck %s<br>
- dmt # CHECK: dmt # encoding: [0x41,0x60,0x0b,0xc1]<br>
- dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1]<br>
- emt # CHECK: emt # encoding: [0x41,0x60,0x0b,0xe1]<br>
- emt $4 # CHECK: emt $4 # encoding: [0x41,0x64,0x0b,0xe1]<br>
- dvpe # CHECK: dvpe # encoding: [0x41,0x60,0x00,0x01]<br>
- dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01]<br>
- evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21]<br>
- evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21]<br>
- fork $2, $3, $5 # CHECK: fork $2, $3, $5 # encoding: [0x7c,0x65,0x10,0x08]<br>
- yield $4 # CHECK: yield $4 # encoding: [0x7c,0x80,0x00,0x09]<br>
- yield $4, $5 # CHECK: yield $4, $5 # encoding: [0x7c,0xa0,0x20,0x09]<br>
+ dmt # CHECK: dmt # encoding: [0x41,0x60,0x0b,0xc1]<br>
+ dmt $5 # CHECK: dmt $5 # encoding: [0x41,0x65,0x0b,0xc1]<br>
+ emt # CHECK: emt # encoding: [0x41,0x60,0x0b,0xe1]<br>
+ emt $4 # CHECK: emt $4 # encoding: [0x41,0x64,0x0b,0xe1]<br>
+ dvpe # CHECK: dvpe # encoding: [0x41,0x60,0x00,0x01]<br>
+ dvpe $6 # CHECK: dvpe $6 # encoding: [0x41,0x66,0x00,0x01]<br>
+ evpe # CHECK: evpe # encoding: [0x41,0x60,0x00,0x21]<br>
+ evpe $4 # CHECK: evpe $4 # encoding: [0x41,0x64,0x00,0x21]<br>
+ fork $2, $3, $5 # CHECK: fork $2, $3, $5 # encoding: [0x7c,0x65,0x10,0x08]<br>
+ yield $4 # CHECK: yield $4 # encoding: [0x7c,0x80,0x00,0x09]<br>
+ yield $4, $5 # CHECK: yield $4, $5 # encoding: [0x7c,0xa0,0x20,0x09]<br>
+ mftr $4, $5, 0, 2, 0 # CHECK: mftr $4, $5, 0, 2, 0 # encoding: [0x41,0x05,0x20,0x02]<br>
+ mftr $4, $5, 1, 0, 0 # CHECK: mftr $4, $5, 1, 0, 0 # encoding: [0x41,0x05,0x20,0x20]<br>
+ mftr $4, $0, 1, 1, 0 # CHECK: mftr $4, $zero, 1, 1, 0 # encoding: [0x41,0x00,0x20,0x21]<br>
+ mftr $4, $10, 1, 1, 0 # CHECK: mftr $4, $10, 1, 1, 0 # encoding: [0x41,0x0a,0x20,0x21]<br>
+ mftr $4, $10, 1, 2, 0 # CHECK: mftr $4, $10, 1, 2, 0 # encoding: [0x41,0x0a,0x20,0x22]<br>
+ mftr $4, $10, 1, 2, 1 # CHECK: mftr $4, $10, 1, 2, 1 # encoding: [0x41,0x0a,0x20,0x32]<br>
+ mftr $4, $26, 1, 3, 0 # CHECK: mftr $4, $26, 1, 3, 0 # encoding: [0x41,0x1a,0x20,0x23]<br>
+ mftr $4, $31, 1, 3, 0 # CHECK: mftr $4, $ra, 1, 3, 0 # encoding: [0x41,0x1f,0x20,0x23]<br>
+ mftr $4, $14, 1, 4, 0 # CHECK: mftr $4, $14, 1, 4, 0 # encoding: [0x41,0x0e,0x20,0x24]<br>
+ mftr $4, $15, 1, 5, 0 # CHECK: mftr $4, $15, 1, 5, 0 # encoding: [0x41,0x0f,0x20,0x25]<br>
+ mttr $4, $5, 0, 2, 0 # CHECK: mttr $4, $5, 0, 2, 0 # encoding: [0x41,0x84,0x28,0x02]<br>
+ mttr $4, $5, 1, 0, 0 # CHECK: mttr $4, $5, 1, 0, 0 # encoding: [0x41,0x84,0x28,0x20]<br>
+ mttr $4, $0, 1, 1, 0 # CHECK: mttr $4, $zero, 1, 1, 0 # encoding: [0x41,0x84,0x00,0x21]<br>
+ mttr $4, $10, 1, 1, 0 # CHECK: mttr $4, $10, 1, 1, 0 # encoding: [0x41,0x84,0x50,0x21]<br>
+ mttr $4, $10, 1, 2, 0 # CHECK: mttr $4, $10, 1, 2, 0 # encoding: [0x41,0x84,0x50,0x22]<br>
+ mttr $4, $10, 1, 2, 1 # CHECK: mttr $4, $10, 1, 2, 1 # encoding: [0x41,0x84,0x50,0x32]<br>
+ mttr $4, $26, 1, 3, 0 # CHECK: mttr $4, $26, 1, 3, 0 # encoding: [0x41,0x84,0xd0,0x23]<br>
+ mttr $4, $31, 1, 3, 0 # CHECK: mttr $4, $ra, 1, 3, 0 # encoding: [0x41,0x84,0xf8,0x23]<br>
+ mttr $4, $14, 1, 4, 0 # CHECK: mttr $4, $14, 1, 4, 0 # encoding: [0x41,0x84,0x70,0x24]<br>
+ mttr $4, $15, 1, 5, 0 # CHECK: mttr $4, $15, 1, 5, 0 # encoding: [0x41,0x84,0x78,0x25]<br>
<br>
<br>
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</blockquote></div><br></div></div>