<div dir="ltr">Thanks a lot for the heads-up. The patch was committed in r306473.<div><br></div><div>Dehao</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jun 27, 2017 at 10:20 AM, Zaks, Ayal <span dir="ltr"><<a href="mailto:ayal.zaks@intel.com" target="_blank">ayal.zaks@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div lang="EN-US" link="blue" vlink="purple">
<div class="m_-7361148986451431947WordSection1">
<pre><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Agreed, r306331 caused such<u></u><u></u></span></pre>
<pre><span style="color:black"> “TBAA is only for loads, stores and calls!<u></u><u></u></span></pre>
<p class="MsoNormal"><span style="color:black"> %reverse = shufflevector <16 x i8> %wide.load84, …”</span><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u><u></u></span></p>
<p class="MsoNormal"><a name="m_-7361148986451431947__MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">failures; it was reverted in r306338 and fixed in r306381. Sorry it caught r306336.<u></u><u></u></span></a></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><a name="m_-7361148986451431947______replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Matthew Simpson [mailto:<a href="mailto:mssimpso@codeaurora.org" target="_blank">mssimpso@codeaurora.<wbr>org</a>]
<br>
<b>Sent:</b> Tuesday, June 27, 2017 19:57<br>
<b>To:</b> Dehao Chen <<a href="mailto:dehao@google.com" target="_blank">dehao@google.com</a>><br>
<b>Cc:</b> llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>>; Zaks, Ayal <<a href="mailto:ayal.zaks@intel.com" target="_blank">ayal.zaks@intel.com</a>><br>
<b>Subject:</b> Re: [llvm] r306336 - Enable vectorizer-maximize-bandwidth by default.<u></u><u></u></span></p><div><div class="h5">
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<p class="MsoNormal">Dehao,<u></u><u></u></p>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">I think that PPC failure may have been due to r306331, and not your patch. Ayal fixed a TBAA metadata issue when recommitting his patch in r306381.<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">-- Matt<u></u><u></u></p>
</div>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<p class="MsoNormal">On Mon, Jun 26, 2017 at 7:01 PM, Dehao Chen via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<u></u><u></u></p>
<blockquote style="border:none;border-left:solid #cccccc 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm">
<div>
<p class="MsoNormal">Reverting this again:<u></u><u></u></p>
<div>
<p class="MsoNormal"><a href="http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/4285/steps/build%20stage%202/logs/stdio" target="_blank">http://lab.llvm.org:8011/<wbr>builders/clang-ppc64be-linux-<wbr>multistage/builds/4285/steps/<wbr>build%20stage%202/logs/stdio</a><u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">Looks like it exposes some bug in ppc, reverting the patch for now, need to have a reproducible to investigate the bug.<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><span style="color:#888888"><u></u> <u></u></span></p>
</div>
<div>
<p class="MsoNormal"><span style="color:#888888">Dehao<u></u><u></u></span></p>
</div>
<div>
<div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<p class="MsoNormal">On Mon, Jun 26, 2017 at 2:41 PM, Dehao Chen via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<u></u><u></u></p>
<blockquote style="border:none;border-left:solid #cccccc 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm">
<p class="MsoNormal">Author: dehao<br>
Date: Mon Jun 26 14:41:09 2017<br>
New Revision: 306336<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=306336&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project?rev=306336&view=rev</a><br>
Log:<br>
Enable vectorizer-maximize-bandwidth by default.<br>
<br>
Summary:<br>
vectorizer-maximize-bandwidth is generally useful in terms of performance. I've tested the impact of changing this to default on speccpu benchmarks on sandybridge machines. The result shows non-negative impact:<br>
<br>
spec/2006/fp/C++/444.namd 26.84 -0.31%<br>
spec/2006/fp/C++/447.dealII 46.19 +0.89%<br>
spec/2006/fp/C++/450.soplex 42.92 -0.44%<br>
spec/2006/fp/C++/453.povray 38.57 -2.25%<br>
spec/2006/fp/C/433.milc 24.54 -0.76%<br>
spec/2006/fp/C/470.lbm 41.08 +0.26%<br>
spec/2006/fp/C/482.sphinx3 47.58 -0.99%<br>
spec/2006/int/C++/471.omnetpp 22.06 +1.87%<br>
spec/2006/int/C++/473.astar 22.65 -0.12%<br>
spec/2006/int/C++/483.<wbr>xalancbmk 33.69 +4.97%<br>
spec/2006/int/C/400.perlbench 33.43 +1.70%<br>
spec/2006/int/C/401.bzip2 23.02 -0.19%<br>
spec/2006/int/C/403.gcc 32.57 -0.43%<br>
spec/2006/int/C/429.mcf 40.35 +0.27%<br>
spec/2006/int/C/445.gobmk 26.96 +0.06%<br>
spec/2006/int/C/456.hmmer 24.4 +0.19%<br>
spec/2006/int/C/458.sjeng 27.91 -0.08%<br>
spec/2006/int/C/462.<wbr>libquantum 57.47 -0.20%<br>
spec/2006/int/C/464.h264ref 46.52 +1.35%<br>
<br>
geometric mean +0.29%<br>
<br>
The regression on 453.povray seems real, but is due to secondary effects as all hot functions are bit-identical with and without the flag.<br>
<br>
I started this patch to consult upstream opinions on this. It will be greatly appreciated if the community can help test the performance impact of this change on other architectures so that we can decided if this should be target-dependent.<br>
<br>
Reviewers: hfinkel, mkuper, davidxl, chandlerc<br>
<br>
Reviewed By: chandlerc<br>
<br>
Subscribers: rengolin, sanjoy, javed.absar, bjope, dorit, magabari, RKSimon, llvm-commits, mzolotukhin<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D33341" target="_blank">
https://reviews.llvm.org/<wbr>D33341</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Transforms/<wbr>Vectorize/LoopVectorize.cpp<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/AArch64/loop-<wbr>vectorization-factors.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/AArch64/<wbr>reduction-small-size.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/ARM/gcc-<wbr>examples.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/fp64_to_<wbr>uint32-cost-model.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/gcc-<wbr>examples.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/masked_load_<wbr>store.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/no_fpmath.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/no_fpmath_<wbr>with_hotness.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/reduction-<wbr>crash.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/<wbr>vectorization-remarks-loopid-<wbr>dbg.ll<br>
llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/<wbr>vectorization-remarks.ll<br>
<br>
Modified: llvm/trunk/lib/Transforms/<wbr>Vectorize/LoopVectorize.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>Transforms/Vectorize/<wbr>LoopVectorize.cpp?rev=306336&<wbr>r1=306335&r2=306336&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Transforms/<wbr>Vectorize/LoopVectorize.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/<wbr>Vectorize/LoopVectorize.cpp Mon Jun 26 14:41:09 2017<br>
@@ -122,7 +122,7 @@ static cl::opt<unsigned> TinyTripCountVe<br>
"value."));<br>
<br>
static cl::opt<bool> MaximizeBandwidth(<br>
- "vectorizer-maximize-<wbr>bandwidth", cl::init(false), cl::Hidden,<br>
+ "vectorizer-maximize-<wbr>bandwidth", cl::init(true), cl::Hidden,<br>
cl::desc("Maximize bandwidth when selecting vectorization factor which "<br>
"will be determined by the smallest type in loop."));<br>
<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/AArch64/loop-<wbr>vectorization-factors.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/<wbr>AArch64/loop-vectorization-<wbr>factors.ll?rev=306336&r1=<wbr>306335&r2=306336&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/AArch64/loop-<wbr>vectorization-factors.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/AArch64/loop-<wbr>vectorization-factors.ll Mon Jun 26 14:41:09 2017<br>
@@ -88,9 +88,9 @@ for.body:<br>
}<br>
<br>
; CHECK-LABEL: @add_c(<br>
-; CHECK: load <8 x i8>, <8 x i8>*<br>
-; CHECK: add <8 x i16><br>
-; CHECK: store <8 x i16><br>
+; CHECK: load <16 x i8>, <16 x i8>*<br>
+; CHECK: add <16 x i16><br>
+; CHECK: store <16 x i16><br>
; Function Attrs: nounwind<br>
define void @add_c(i8* noalias nocapture readonly %p, i16* noalias nocapture %q, i32 %len) #0 {<br>
entry:<br>
@@ -116,9 +116,9 @@ for.body:<br>
}<br>
<br>
; CHECK-LABEL: @add_d(<br>
-; CHECK: load <4 x i16><br>
-; CHECK: add nsw <4 x i32><br>
-; CHECK: store <4 x i32><br>
+; CHECK: load <8 x i16><br>
+; CHECK: add nsw <8 x i32><br>
+; CHECK: store <8 x i32><br>
define void @add_d(i16* noalias nocapture readonly %p, i32* noalias nocapture %q, i32 %len) #0 {<br>
entry:<br>
%cmp7 = icmp sgt i32 %len, 0<br>
@@ -187,16 +187,16 @@ for.body:<br>
}<br>
<br>
; CHECK-LABEL: @add_f<br>
-; CHECK: load <8 x i16><br>
-; CHECK: trunc <8 x i16><br>
-; CHECK: shl <8 x i8><br>
-; CHECK: add <8 x i8><br>
-; CHECK: or <8 x i8><br>
-; CHECK: mul <8 x i8><br>
-; CHECK: and <8 x i8><br>
-; CHECK: xor <8 x i8><br>
-; CHECK: mul <8 x i8><br>
-; CHECK: store <8 x i8><br>
+; CHECK: load <16 x i16><br>
+; CHECK: trunc <16 x i16><br>
+; CHECK: shl <16 x i8><br>
+; CHECK: add <16 x i8><br>
+; CHECK: or <16 x i8><br>
+; CHECK: mul <16 x i8><br>
+; CHECK: and <16 x i8><br>
+; CHECK: xor <16 x i8><br>
+; CHECK: mul <16 x i8><br>
+; CHECK: store <16 x i8><br>
define void @add_f(i16* noalias nocapture readonly %p, i8* noalias nocapture %q, i8 %arg1, i8 %arg2, i32 %len) #0 {<br>
entry:<br>
%cmp.32 = icmp sgt i32 %len, 0<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/AArch64/<wbr>reduction-small-size.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/AArch64/reduction-small-size.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/<wbr>AArch64/reduction-small-size.<wbr>ll?rev=306336&r1=306335&r2=<wbr>306336&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/AArch64/<wbr>reduction-small-size.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/AArch64/<wbr>reduction-small-size.ll Mon Jun 26 14:41:09 2017<br>
@@ -123,16 +123,16 @@ for.body:<br>
; }<br>
;<br>
; CHECK: vector.body:<br>
-; CHECK: phi <8 x i16><br>
-; CHECK: [[Ld1:%[a-zA-Z0-9.]+]] = load <8 x i8><br>
-; CHECK: zext <8 x i8> [[Ld1]] to <8 x i16><br>
-; CHECK: [[Ld2:%[a-zA-Z0-9.]+]] = load <8 x i8><br>
-; CHECK: zext <8 x i8> [[Ld2]] to <8 x i16><br>
-; CHECK: add <8 x i16><br>
-; CHECK: add <8 x i16><br>
+; CHECK: phi <16 x i16><br>
+; CHECK: [[Ld1:%[a-zA-Z0-9.]+]] = load <16 x i8><br>
+; CHECK: zext <16 x i8> [[Ld1]] to <16 x i16><br>
+; CHECK: [[Ld2:%[a-zA-Z0-9.]+]] = load <16 x i8><br>
+; CHECK: zext <16 x i8> [[Ld2]] to <16 x i16><br>
+; CHECK: add <16 x i16><br>
+; CHECK: add <16 x i16><br>
;<br>
; CHECK: middle.block:<br>
-; CHECK: [[Rdx:%[a-zA-Z0-9.]+]] = call i16 @llvm.experimental.vector.<wbr>reduce.add.i16.v8i16(<8 x i16><br>
+; CHECK: [[Rdx:%[a-zA-Z0-9.]+]] = call i16 @llvm.experimental.vector.<wbr>reduce.add.i16.v16i16(<16 x i16><br>
; CHECK: zext i16 [[Rdx]] to i32<br>
;<br>
define i16 @reduction_i16_2(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %n) {<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/ARM/gcc-<wbr>examples.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/ARM/gcc-examples.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/ARM/<wbr>gcc-examples.ll?rev=306336&r1=<wbr>306335&r2=306336&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/ARM/gcc-<wbr>examples.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/ARM/gcc-<wbr>examples.ll Mon Jun 26 14:41:09 2017<br>
@@ -35,9 +35,9 @@ define void @example1() nounwind uwtable<br>
}<br>
<br>
;CHECK-LABEL: @example10b(<br>
-;CHECK: load <4 x i16><br>
-;CHECK: sext <4 x i16><br>
-;CHECK: store <4 x i32><br>
+;CHECK: load <8 x i16><br>
+;CHECK: sext <8 x i16><br>
+;CHECK: store <8 x i32><br>
;CHECK: ret void<br>
define void @example10b(i16* noalias nocapture %sa, i16* noalias nocapture %sb, i16* noalias nocapture %sc, i32* noalias nocapture %ia, i32* noalias nocapture %ib, i32* noalias nocapture %ic) nounwind uwtable ssp {<br>
br label %1<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/fp64_to_<wbr>uint32-cost-model.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/fp64_to_uint32-cost-model.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/X86/<wbr>fp64_to_uint32-cost-model.ll?<wbr>rev=306336&r1=306335&r2=<wbr>306336&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/fp64_to_<wbr>uint32-cost-model.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/fp64_to_<wbr>uint32-cost-model.ll Mon Jun 26 14:41:09 2017<br>
@@ -9,7 +9,9 @@ target triple = "x86_64-apple-macosx"<br>
<br>
; If we need to scalarize the fptoui and then use inserts to build up the<br>
; vector again, then there is certainly no value in going 256-bit wide.<br>
-; CHECK-NOT: vpinsrd<br>
+; But as we default to maximize bandwidth, we should convert it to 256-bit<br>
+; anyway.<br>
+; CHECK: vpinsrd<br>
<br>
define void @convert() {<br>
entry:<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/gcc-<wbr>examples.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/gcc-examples.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/X86/<wbr>gcc-examples.ll?rev=306336&r1=<wbr>306335&r2=306336&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/gcc-<wbr>examples.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/gcc-<wbr>examples.ll Mon Jun 26 14:41:09 2017<br>
@@ -44,17 +44,16 @@ define void @example1() nounwind uwtable<br>
ret void<br>
}<br>
<br>
-; Select VF=4 because sext <8 x i1> to <8 x i32> is expensive.<br>
;CHECK-LABEL: @example10b(<br>
-;CHECK: load <4 x i16><br>
-;CHECK: sext <4 x i16><br>
-;CHECK: store <4 x i32><br>
+;CHECK: load <8 x i16><br>
+;CHECK: sext <8 x i16><br>
+;CHECK: store <8 x i32><br>
;CHECK: ret void<br>
;UNROLL-LABEL: @example10b(<br>
-;UNROLL: load <4 x i16><br>
-;UNROLL: load <4 x i16><br>
-;UNROLL: store <4 x i32><br>
-;UNROLL: store <4 x i32><br>
+;UNROLL: load <8 x i16><br>
+;UNROLL: load <8 x i16><br>
+;UNROLL: store <8 x i32><br>
+;UNROLL: store <8 x i32><br>
;UNROLL: ret void<br>
define void @example10b(i16* noalias nocapture %sa, i16* noalias nocapture %sb, i16* noalias nocapture %sc, i32* noalias nocapture %ia, i32* noalias nocapture %ib, i32* noalias nocapture %ic) nounwind uwtable ssp {<br>
br label %1<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/masked_load_<wbr>store.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/masked_load_store.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/X86/<wbr>masked_load_store.ll?rev=<wbr>306336&r1=306335&r2=306336&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/masked_load_<wbr>store.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/masked_load_<wbr>store.ll Mon Jun 26 14:41:09 2017<br>
@@ -260,20 +260,28 @@ for.end:<br>
; }<br>
;}<br>
<br>
-;AVX-LABEL: @foo3<br>
-;AVX: icmp slt <4 x i32> %wide.load, <i32 100, i32 100,<br>
-;AVX: call <4 x double> @llvm.masked.load.v4f64.<wbr>p0v4f64<br>
-;AVX: sitofp <4 x i32> %wide.load to <4 x double><br>
-;AVX: fadd <4 x double><br>
-;AVX: call void @llvm.masked.store.v4f64.<wbr>p0v4f64<br>
-;AVX: ret void<br>
+;AVX1-LABEL: @foo3<br>
+;AVX1: icmp slt <4 x i32> %wide.load, <i32 100, i32 100,<br>
+;AVX1: call <4 x double> @llvm.masked.load.v4f64.<wbr>p0v4f64<br>
+;AVX1: sitofp <4 x i32> %wide.load to <4 x double><br>
+;AVX1: fadd <4 x double><br>
+;AVX1: call void @llvm.masked.store.v4f64.<wbr>p0v4f64<br>
+;AVX1: ret void<br>
+<br>
+;AVX2-LABEL: @foo3<br>
+;AVX2: icmp slt <8 x i32> %wide.load, <i32 100, i32 100,<br>
+;AVX2: call <8 x double> @llvm.masked.load.v8f64.<wbr>p0v8f64<br>
+;AVX2: sitofp <8 x i32> %wide.load to <8 x double><br>
+;AVX2: fadd <8 x double><br>
+;AVX2: call void @llvm.masked.store.v8f64.<wbr>p0v8f64<br>
+;AVX2: ret void<br>
<br>
;AVX512-LABEL: @foo3<br>
-;AVX512: icmp slt <8 x i32> %wide.load, <i32 100, i32 100,<br>
-;AVX512: call <8 x double> @llvm.masked.load.v8f64.<wbr>p0v8f64<br>
-;AVX512: sitofp <8 x i32> %wide.load to <8 x double><br>
-;AVX512: fadd <8 x double><br>
-;AVX512: call void @llvm.masked.store.v8f64.<wbr>p0v8f64<br>
+;AVX512: icmp slt <16 x i32> %wide.load, <i32 100, i32 100,<br>
+;AVX512: call <16 x double> @llvm.masked.load.v16f64.<wbr>p0v16f64<br>
+;AVX512: sitofp <16 x i32> %wide.load to <16 x double><br>
+;AVX512: fadd <16 x double><br>
+;AVX512: call void @llvm.masked.store.v16f64.<wbr>p0v16f64<br>
;AVX512: ret void<br>
<br>
<br>
@@ -502,19 +510,19 @@ for.end:<br>
; }<br>
;}<br>
;AVX2-LABEL: @foo6<br>
-;AVX2: icmp sgt <4 x i32> %reverse, zeroinitializer<br>
-;AVX2: shufflevector <4 x i1>{{.*}}<4 x i32> <i32 3, i32 2, i32 1, i32 0><br>
-;AVX2: call <4 x double> @llvm.masked.load.v4f64.<wbr>p0v4f64<br>
-;AVX2: fadd <4 x double><br>
-;AVX2: call void @llvm.masked.store.v4f64.<wbr>p0v4f64<br>
+;AVX2: icmp sgt <8 x i32> %reverse, zeroinitializer<br>
+;AVX2: shufflevector <8 x i1>{{.*}}<8 x i32> <i32 7, i32 6, i32 5, i32 4<br>
+;AVX2: call <8 x double> @llvm.masked.load.v8f64.<wbr>p0v8f64<br>
+;AVX2: fadd <8 x double><br>
+;AVX2: call void @llvm.masked.store.v8f64.<wbr>p0v8f64<br>
;AVX2: ret void<br>
<br>
;AVX512-LABEL: @foo6<br>
-;AVX512: icmp sgt <8 x i32> %reverse, zeroinitializer<br>
-;AVX512: shufflevector <8 x i1>{{.*}}<8 x i32> <i32 7, i32 6, i32 5, i32 4<br>
-;AVX512: call <8 x double> @llvm.masked.load.v8f64.<wbr>p0v8f64<br>
-;AVX512: fadd <8 x double><br>
-;AVX512: call void @llvm.masked.store.v8f64.<wbr>p0v8f64<br>
+;AVX512: icmp sgt <16 x i32> %reverse, zeroinitializer<br>
+;AVX512: shufflevector <16 x i1>{{.*}}<16 x i32> <i32 15, i32 14, i32 13, i32 12<br>
+;AVX512: call <16 x double> @llvm.masked.load.v16f64.<wbr>p0v16f64<br>
+;AVX512: fadd <16 x double><br>
+;AVX512: call void @llvm.masked.store.v16f64.<wbr>p0v16f64<br>
;AVX512: ret void<br>
<br>
<br>
@@ -582,8 +590,8 @@ for.end:<br>
; }<br>
<br>
;AVX512-LABEL: @foo7<br>
-;AVX512: call <8 x double*> @llvm.masked.load.v8p0f64.<wbr>p0v8p0f64(<8 x double*>*<br>
-;AVX512: call void @llvm.masked.store.v8f64.<wbr>p0v8f64<br>
+;AVX512: call <64 x double*> @llvm.masked.load.v64p0f64.<wbr>p0v64p0f64(<64 x double*>*<br>
+;AVX512: call void @llvm.masked.store.v64f64.<wbr>p0v64f64<br>
;AVX512: ret void<br>
<br>
define void @foo7(double* noalias %out, double** noalias %in, i8* noalias %trigger, i32 %size) #0 {<br>
@@ -654,8 +662,8 @@ for.end:<br>
;}<br>
<br>
;AVX512-LABEL: @foo8<br>
-;AVX512: call <8 x i32 ()*> @llvm.masked.load.v8p0f_i32f.<wbr>p0v8p0f_i32f(<8 x i32 ()*>* %<br>
-;AVX512: call void @llvm.masked.store.v8f64.<wbr>p0v8f64<br>
+;AVX512: call <64 x i32 ()*> @llvm.masked.load.v64p0f_i32f.<wbr>p0v64p0f_i32f(<64 x i32 ()*>* %<br>
+;AVX512: call void @llvm.masked.store.v64f64.<wbr>p0v64f64<br>
;AVX512: ret void<br>
<br>
define void @foo8(double* noalias %out, i32 ()** noalias %in, i8* noalias %trigger, i32 %size) #0 {<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/no_fpmath.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/no_fpmath.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/X86/<wbr>no_fpmath.ll?rev=306336&r1=<wbr>306335&r2=306336&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/no_fpmath.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/no_fpmath.ll Mon Jun 26 14:41:09 2017<br>
@@ -2,7 +2,7 @@<br>
<br>
; CHECK: remark: no_fpmath.c:6:11: loop not vectorized: cannot prove it is safe to reorder floating-point operations<br>
; CHECK: remark: no_fpmath.c:6:14: loop not vectorized<br>
-; CHECK: remark: no_fpmath.c:17:14: vectorized loop (vectorization width: 2, interleaved count: 2)<br>
+; CHECK: remark: no_fpmath.c:17:14: vectorized loop (vectorization width: 4, interleaved count: 2)<br>
<br>
target datalayout = "e-m:o-i64:64-f80:128-n8:16:<wbr>32:64-S128"<br>
target triple = "x86_64-apple-macosx10.10.0"<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/no_fpmath_<wbr>with_hotness.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/no_fpmath_with_hotness.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/X86/<wbr>no_fpmath_with_hotness.ll?rev=<wbr>306336&r1=306335&r2=306336&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/no_fpmath_<wbr>with_hotness.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/no_fpmath_<wbr>with_hotness.ll Mon Jun 26 14:41:09 2017<br>
@@ -3,7 +3,7 @@<br>
<br>
; CHECK: remark: no_fpmath.c:6:11: loop not vectorized: cannot prove it is safe to reorder floating-point operations (hotness: 300)<br>
; CHECK: remark: no_fpmath.c:6:14: loop not vectorized<br>
-; CHECK: remark: no_fpmath.c:17:14: vectorized loop (vectorization width: 2, interleaved count: 2) (hotness: 300)<br>
+; CHECK: remark: no_fpmath.c:17:14: vectorized loop (vectorization width: 4, interleaved count: 2) (hotness: 300)<br>
<br>
target datalayout = "e-m:o-i64:64-f80:128-n8:16:<wbr>32:64-S128"<br>
target triple = "x86_64-apple-macosx10.10.0"<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/reduction-<wbr>crash.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/reduction-crash.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/X86/<wbr>reduction-crash.ll?rev=306336&<wbr>r1=306335&r2=306336&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/reduction-<wbr>crash.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/reduction-<wbr>crash.ll Mon Jun 26 14:41:09 2017<br>
@@ -7,7 +7,7 @@ target triple = "i386-apple-darwin"<br>
define void @test1(float* nocapture %arg, i32 %arg1) nounwind {<br>
; CHECK-LABEL: @test1(<br>
; CHECK: preheader<br>
-; CHECK: insertelement <2 x double> zeroinitializer, double %tmp, i32 0<br>
+; CHECK: insertelement <4 x double> zeroinitializer, double %tmp, i32 0<br>
; CHECK: vector.memcheck<br>
<br>
bb:<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/<wbr>vectorization-remarks-loopid-<wbr>dbg.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/vectorization-remarks-loopid-dbg.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/X86/<wbr>vectorization-remarks-loopid-<wbr>dbg.ll?rev=306336&r1=306335&<wbr>r2=306336&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/<wbr>vectorization-remarks-loopid-<wbr>dbg.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/<wbr>vectorization-remarks-loopid-<wbr>dbg.ll Mon Jun 26 14:41:09 2017<br>
@@ -6,7 +6,7 @@<br>
; DEBUG-OUTPUT-NOT: .loc<br>
; DEBUG-OUTPUT-NOT: {{.*}}.debug_info<br>
<br>
-; VECTORIZED: remark: vectorization-remarks.c:17:8: vectorized loop (vectorization width: 4, interleaved count: 1)<br>
+; VECTORIZED: remark: vectorization-remarks.c:17:8: vectorized loop (vectorization width: 16, interleaved count: 1)<br>
; UNROLLED: remark: vectorization-remarks.c:17:8: interleaved loop (interleaved count: 4)<br>
; NONE: remark: vectorization-remarks.c:17:8: loop not vectorized: vectorization and interleaving are explicitly disabled, or vectorize width and interleave count are both set to 1<br>
<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/<wbr>vectorization-remarks.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll?rev=306336&r1=306335&r2=306336&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/LoopVectorize/X86/<wbr>vectorization-remarks.ll?rev=<wbr>306336&r1=306335&r2=306336&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/<wbr>vectorization-remarks.ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>LoopVectorize/X86/<wbr>vectorization-remarks.ll Mon Jun 26 14:41:09 2017<br>
@@ -6,7 +6,7 @@<br>
; DEBUG-OUTPUT-NOT: .loc<br>
; DEBUG-OUTPUT-NOT: {{.*}}.debug_info<br>
<br>
-; VECTORIZED: remark: vectorization-remarks.c:17:8: vectorized loop (vectorization width: 4, interleaved count: 1)<br>
+; VECTORIZED: remark: vectorization-remarks.c:17:8: vectorized loop (vectorization width: 16, interleaved count: 1)<br>
; UNROLLED: remark: vectorization-remarks.c:17:8: interleaved loop (interleaved count: 4)<br>
; NONE: remark: vectorization-remarks.c:17:8: loop not vectorized: vectorization and interleaving are explicitly disabled, or vectorize width and interleave count are both set to 1<br>
<br>
<br>
<br>
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