<div dir="ltr">Hi Matthias,<div><br></div><div>Working on getting you something, but I did find this:</div><div><br></div><div><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif">fatal error: error in backend: Error while trying to spill X0 from class G8RC: Cannot scavenge register without an emergency spill slot!</span><br style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif"></div><div><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif"><br></span></div><div><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif">on a testcase. Guess we can try to revert for now and I'll work on a testcase?</span></div><div><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif"><br></span></div><div><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif">-eric</span></div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Jun 15, 2017 at 3:15 PM Matthias Braun via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: matze<br>
Date: Thu Jun 15 17:14:55 2017<br>
New Revision: 305516<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=305516&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=305516&view=rev</a><br>
Log:<br>
RegScavenging: Add scavengeRegisterBackwards()<br>
<br>
Re-apply r276044/r279124. Trying to reproduce or disprove the ppc64<br>
problems reported in the stage2 build last time, which I cannot<br>
reproduce right now.<br>
<br>
This is a variant of scavengeRegister() that works for<br>
enterBasicBlockEnd()/backward(). The benefit of the backward mode is<br>
that it is not affected by incomplete kill flags.<br>
<br>
This patch also changes<br>
PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register<br>
scavenger in backwards mode.<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D21885" rel="noreferrer" target="_blank">http://reviews.llvm.org/D21885</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h<br>
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp<br>
llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir<br>
llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll<br>
llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll<br>
llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll<br>
llvm/trunk/test/CodeGen/ARM/alloca-align.ll<br>
llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll<br>
llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir<br>
llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll<br>
llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll<br>
llvm/trunk/test/CodeGen/PowerPC/scavenging.mir<br>
llvm/trunk/test/CodeGen/Thumb/large-stack.ll<br>
llvm/trunk/test/CodeGen/X86/scavenger.mir<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Thu Jun 15 17:14:55 2017<br>
@@ -156,12 +156,24 @@ public:<br>
/// available and do the appropriate bookkeeping. SPAdj is the stack<br>
/// adjustment due to call frame, it's passed along to eliminateFrameIndex().<br>
/// Returns the scavenged register.<br>
+ /// This is deprecated as it depends on the quality of the kill flags being<br>
+ /// present; Use scavengeRegisterBackwards() instead!<br>
unsigned scavengeRegister(const TargetRegisterClass *RegClass,<br>
MachineBasicBlock::iterator I, int SPAdj);<br>
unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {<br>
return scavengeRegister(RegClass, MBBI, SPAdj);<br>
}<br>
<br>
+ /// Make a register of the specific register class available from the current<br>
+ /// position backwards to the place before \p To. If \p RestoreAfter is true<br>
+ /// this includes the instruction following the current position.<br>
+ /// SPAdj is the stack adjustment due to call frame, it's passed along to<br>
+ /// eliminateFrameIndex().<br>
+ /// Returns the scavenged register.<br>
+ unsigned scavengeRegisterBackwards(const TargetRegisterClass &RC,<br>
+ MachineBasicBlock::iterator To,<br>
+ bool RestoreAfter, int SPAdj);<br>
+<br>
/// Tell the scavenger a register is used.<br>
void setRegUsed(unsigned Reg, LaneBitmask LaneMask = LaneBitmask::getAll());<br>
<br>
@@ -202,6 +214,12 @@ private:<br>
<br>
/// Mark live-in registers of basic block as used.<br>
void setLiveInsUsed(const MachineBasicBlock &MBB);<br>
+<br>
+ /// Spill a register after position \p After and reload it before position<br>
+ /// \p UseMI.<br>
+ ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,<br>
+ MachineBasicBlock::iterator After,<br>
+ MachineBasicBlock::iterator &UseMI);<br>
};<br>
<br>
/// Replaces all frame index virtual registers with physical registers. Uses the<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Thu Jun 15 17:14:55 2017<br>
@@ -35,6 +35,7 @@<br>
#include "llvm/Target/TargetInstrInfo.h"<br>
#include "llvm/Target/TargetRegisterInfo.h"<br>
#include "llvm/Target/TargetSubtargetInfo.h"<br>
+#include <algorithm><br>
#include <cassert><br>
#include <iterator><br>
#include <limits><br>
@@ -260,6 +261,14 @@ void RegScavenger::backward() {<br>
const MachineInstr &MI = *MBBI;<br>
LiveUnits.stepBackward(MI);<br>
<br>
+ // Expire scavenge spill frameindex uses.<br>
+ for (ScavengedInfo &I : Scavenged) {<br>
+ if (I.Restore == &MI) {<br>
+ I.Reg = 0;<br>
+ I.Restore = nullptr;<br>
+ }<br>
+ }<br>
+<br>
if (MBBI == MBB->begin()) {<br>
MBBI = MachineBasicBlock::iterator(nullptr);<br>
Tracking = false;<br>
@@ -356,6 +365,76 @@ unsigned RegScavenger::findSurvivorReg(M<br>
return Survivor;<br>
}<br>
<br>
+/// Given the bitvector \p Available of free register units at position<br>
+/// \p From. Search backwards to find a register that is part of \p<br>
+/// Candidates and not used/clobbered until the point \p To. If there is<br>
+/// multiple candidates continue searching and pick the one that is not used/<br>
+/// clobbered for the longest time.<br>
+/// Returns the register and the earliest position we know it to be free or<br>
+/// the position MBB.end() if no register is available.<br>
+static std::pair<unsigned, MachineBasicBlock::iterator><br>
+findSurvivorBackwards(const TargetRegisterInfo &TRI,<br>
+ MachineBasicBlock::iterator From, MachineBasicBlock::iterator To,<br>
+ BitVector &Available, BitVector &Candidates) {<br>
+ bool FoundTo = false;<br>
+ unsigned Survivor = 0;<br>
+ MachineBasicBlock::iterator Pos;<br>
+ MachineBasicBlock &MBB = *From->getParent();<br>
+ unsigned InstrLimit = 25;<br>
+ unsigned InstrCountDown = InstrLimit;<br>
+ for (MachineBasicBlock::iterator I = From;; --I) {<br>
+ const MachineInstr &MI = *I;<br>
+<br>
+ // Remove any candidates touched by instruction.<br>
+ bool FoundVReg = false;<br>
+ for (const MachineOperand &MO : MI.operands()) {<br>
+ if (MO.isRegMask()) {<br>
+ Candidates.clearBitsNotInMask(MO.getRegMask());<br>
+ continue;<br>
+ }<br>
+ if (!MO.isReg() || MO.isUndef() || MO.isDebug())<br>
+ continue;<br>
+ unsigned Reg = MO.getReg();<br>
+ if (TargetRegisterInfo::isVirtualRegister(Reg)) {<br>
+ FoundVReg = true;<br>
+ } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {<br>
+ for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)<br>
+ Candidates.reset(*AI);<br>
+ }<br>
+ }<br>
+<br>
+ if (I == To) {<br>
+ // If one of the available registers survived this long take it.<br>
+ Available &= Candidates;<br>
+ int Reg = Available.find_first();<br>
+ if (Reg != -1)<br>
+ return std::make_pair(Reg, MBB.end());<br>
+ // Otherwise we will continue up to InstrLimit instructions to find<br>
+ // the register which is not defined/used for the longest time.<br>
+ FoundTo = true;<br>
+ Pos = To;<br>
+ }<br>
+ if (FoundTo) {<br>
+ if (Survivor == 0 || !Candidates.test(Survivor)) {<br>
+ int Reg = Candidates.find_first();<br>
+ if (Reg == -1)<br>
+ break;<br>
+ Survivor = Reg;<br>
+ }<br>
+ if (--InstrCountDown == 0 || I == MBB.begin())<br>
+ break;<br>
+ if (FoundVReg) {<br>
+ // Keep searching when we find a vreg since the spilled register will<br>
+ // be usefull for this other vreg as well later.<br>
+ InstrCountDown = InstrLimit;<br>
+ Pos = I;<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ return std::make_pair(Survivor, Pos);<br>
+}<br>
+<br>
static unsigned getFrameIndexOperandNum(MachineInstr &MI) {<br>
unsigned i = 0;<br>
while (!MI.getOperand(i).isFI()) {<br>
@@ -365,44 +444,16 @@ static unsigned getFrameIndexOperandNum(<br>
return i;<br>
}<br>
<br>
-unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,<br>
- MachineBasicBlock::iterator I,<br>
- int SPAdj) {<br>
- MachineInstr &MI = *I;<br>
- const MachineFunction &MF = *MI.getParent()->getParent();<br>
- // Consider all allocatable registers in the register class initially<br>
- BitVector Candidates = TRI->getAllocatableSet(MF, RC);<br>
-<br>
- // Exclude all the registers being used by the instruction.<br>
- for (const MachineOperand &MO : MI.operands()) {<br>
- if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&<br>
- !TargetRegisterInfo::isVirtualRegister(MO.getReg()))<br>
- for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)<br>
- Candidates.reset(*AI);<br>
- }<br>
-<br>
- // Try to find a register that's unused if there is one, as then we won't<br>
- // have to spill.<br>
- BitVector Available = getRegsAvailable(RC);<br>
- Available &= Candidates;<br>
- if (Available.any())<br>
- Candidates = Available;<br>
-<br>
- // Find the register whose use is furthest away.<br>
- MachineBasicBlock::iterator UseMI;<br>
- unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);<br>
-<br>
- // If we found an unused register there is no reason to spill it.<br>
- if (!isRegUsed(SReg)) {<br>
- DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");<br>
- return SReg;<br>
- }<br>
-<br>
+RegScavenger::ScavengedInfo &<br>
+RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,<br>
+ MachineBasicBlock::iterator Before,<br>
+ MachineBasicBlock::iterator &UseMI) {<br>
// Find an available scavenging slot with size and alignment matching<br>
// the requirements of the class RC.<br>
+ const MachineFunction &MF = *Before->getParent()->getParent();<br>
const MachineFrameInfo &MFI = MF.getFrameInfo();<br>
- unsigned NeedSize = TRI->getSpillSize(*RC);<br>
- unsigned NeedAlign = TRI->getSpillAlignment(*RC);<br>
+ unsigned NeedSize = TRI->getSpillSize(RC);<br>
+ unsigned NeedAlign = TRI->getSpillAlignment(RC);<br>
<br>
unsigned SI = Scavenged.size(), Diff = std::numeric_limits<unsigned>::max();<br>
int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();<br>
@@ -437,39 +488,72 @@ unsigned RegScavenger::scavengeRegister(<br>
}<br>
<br>
// Avoid infinite regress<br>
- Scavenged[SI].Reg = SReg;<br>
+ Scavenged[SI].Reg = Reg;<br>
<br>
// If the target knows how to save/restore the register, let it do so;<br>
// otherwise, use the emergency stack spill slot.<br>
- if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {<br>
- // Spill the scavenged register before I.<br>
+ if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {<br>
+ // Spill the scavenged register before \p Before.<br>
int FI = Scavenged[SI].FrameIndex;<br>
if (FI < FIB || FI >= FIE) {<br>
std::string Msg = std::string("Error while trying to spill ") +<br>
- TRI->getName(SReg) + " from class " + TRI->getRegClassName(RC) +<br>
+ TRI->getName(Reg) + " from class " + TRI->getRegClassName(&RC) +<br>
": Cannot scavenge register without an emergency spill slot!";<br>
report_fatal_error(Msg.c_str());<br>
}<br>
- TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,<br>
- RC, TRI);<br>
- MachineBasicBlock::iterator II = std::prev(I);<br>
+ TII->storeRegToStackSlot(*MBB, Before, Reg, true, Scavenged[SI].FrameIndex,<br>
+ &RC, TRI);<br>
+ MachineBasicBlock::iterator II = std::prev(Before);<br>
<br>
unsigned FIOperandNum = getFrameIndexOperandNum(*II);<br>
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);<br>
<br>
// Restore the scavenged register before its use (or first terminator).<br>
- TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,<br>
- RC, TRI);<br>
+ TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,<br>
+ &RC, TRI);<br>
II = std::prev(UseMI);<br>
<br>
FIOperandNum = getFrameIndexOperandNum(*II);<br>
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);<br>
}<br>
+ return Scavenged[SI];<br>
+}<br>
+<br>
+unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,<br>
+ MachineBasicBlock::iterator I,<br>
+ int SPAdj) {<br>
+ MachineInstr &MI = *I;<br>
+ const MachineFunction &MF = *MI.getParent()->getParent();<br>
+ // Consider all allocatable registers in the register class initially<br>
+ BitVector Candidates = TRI->getAllocatableSet(MF, RC);<br>
+<br>
+ // Exclude all the registers being used by the instruction.<br>
+ for (const MachineOperand &MO : MI.operands()) {<br>
+ if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&<br>
+ !TargetRegisterInfo::isVirtualRegister(MO.getReg()))<br>
+ for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)<br>
+ Candidates.reset(*AI);<br>
+ }<br>
+<br>
+ // Try to find a register that's unused if there is one, as then we won't<br>
+ // have to spill.<br>
+ BitVector Available = getRegsAvailable(RC);<br>
+ Available &= Candidates;<br>
+ if (Available.any())<br>
+ Candidates = Available;<br>
+<br>
+ // Find the register whose use is furthest away.<br>
+ MachineBasicBlock::iterator UseMI;<br>
+ unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);<br>
<br>
- Scavenged[SI].Restore = &*std::prev(UseMI);<br>
+ // If we found an unused register there is no reason to spill it.<br>
+ if (!isRegUsed(SReg)) {<br>
+ DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");<br>
+ return SReg;<br>
+ }<br>
<br>
- // Doing this here leads to infinite regress.<br>
- // Scavenged[SI].Reg = SReg;<br>
+ ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);<br>
+ Scavenged.Restore = &*std::prev(UseMI);<br>
<br>
DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<<br>
"\n");<br>
@@ -477,85 +561,200 @@ unsigned RegScavenger::scavengeRegister(<br>
return SReg;<br>
}<br>
<br>
-void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {<br>
- // FIXME: Iterating over the instruction stream is unnecessary. We can simply<br>
- // iterate over the vreg use list, which at this point only contains machine<br>
- // operands for which eliminateFrameIndex need a new scratch reg.<br>
+unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,<br>
+ MachineBasicBlock::iterator To,<br>
+ bool RestoreAfter, int SPAdj) {<br>
+ const MachineBasicBlock &MBB = *To->getParent();<br>
+ const MachineFunction &MF = *MBB.getParent();<br>
+ // Consider all allocatable registers in the register class initially<br>
+ BitVector Candidates = TRI->getAllocatableSet(MF, &RC);<br>
<br>
- // Run through the instructions and find any virtual registers.<br>
- MachineRegisterInfo &MRI = MF.getRegInfo();<br>
- for (MachineBasicBlock &MBB : MF) {<br>
- RS.enterBasicBlock(MBB);<br>
+ // Try to find a register that's unused if there is one, as then we won't<br>
+ // have to spill.<br>
+ BitVector Available = getRegsAvailable(&RC);<br>
<br>
- int SPAdj = 0;<br>
+ // Find the register whose use is furthest away.<br>
+ MachineBasicBlock::iterator UseMI;<br>
+ std::pair<unsigned, MachineBasicBlock::iterator> P =<br>
+ findSurvivorBackwards(*TRI, MBBI, To, Available, Candidates);<br>
+ unsigned Reg = P.first;<br>
+ MachineBasicBlock::iterator SpillBefore = P.second;<br>
+ assert(Reg != 0 && "No register left to scavenge!");<br>
+ // Found an available register?<br>
+ if (SpillBefore != MBB.end()) {<br>
+ MachineBasicBlock::iterator ReloadAfter =<br>
+ RestoreAfter ? std::next(MBBI) : MBBI;<br>
+ MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);<br>
+ DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');<br>
+ ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);<br>
+ Scavenged.Restore = &*std::prev(SpillBefore);<br>
+ LiveUnits.removeReg(Reg);<br>
+ DEBUG(dbgs() << "Scavenged register with spill: " << PrintReg(Reg, TRI)<br>
+ << " until " << *SpillBefore);<br>
+ } else {<br>
+ DEBUG(dbgs() << "Scavenged free register: " << PrintReg(Reg, TRI) << '\n');<br>
+ }<br>
+ return Reg;<br>
+}<br>
<br>
- // The instruction stream may change in the loop, so check MBB.end()<br>
- // directly.<br>
- for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {<br>
- // We might end up here again with a NULL iterator if we scavenged a<br>
- // register for which we inserted spill code for definition by what was<br>
- // originally the first instruction in MBB.<br>
- if (I == MachineBasicBlock::iterator(nullptr))<br>
- I = MBB.begin();<br>
-<br>
- const MachineInstr &MI = *I;<br>
- MachineBasicBlock::iterator J = std::next(I);<br>
- MachineBasicBlock::iterator P =<br>
- I == MBB.begin() ? MachineBasicBlock::iterator(nullptr)<br>
- : std::prev(I);<br>
-<br>
- // RS should process this instruction before we might scavenge at this<br>
- // location. This is because we might be replacing a virtual register<br>
- // defined by this instruction, and if so, registers killed by this<br>
- // instruction are available, and defined registers are not.<br>
- RS.forward(I);<br>
+/// Allocate a register for the virtual register \p VReg. The last use of<br>
+/// \p VReg is around the current position of the register scavenger \p RS.<br>
+/// \p ReserveAfter controls whether the scavenged register needs to be reserved<br>
+/// after the current instruction, otherwise it will only be reserved before the<br>
+/// current instruction.<br>
+static unsigned scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,<br>
+ unsigned VReg, bool ReserveAfter) {<br>
+ const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();<br>
+#ifndef NDEBUG<br>
+ // Verify that all definitions and uses are in the same basic block.<br>
+ const MachineBasicBlock *CommonMBB = nullptr;<br>
+ // Real definition for the reg, re-definitions are not considered.<br>
+ const MachineInstr *RealDef = nullptr;<br>
+ for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) {<br>
+ MachineBasicBlock *MBB = MO.getParent()->getParent();<br>
+ if (CommonMBB == nullptr)<br>
+ CommonMBB = MBB;<br>
+ assert(MBB == CommonMBB && "All defs+uses must be in the same basic block");<br>
+ if (MO.isDef()) {<br>
+ const MachineInstr &MI = *MO.getParent();<br>
+ if (!MI.readsRegister(VReg, &TRI)) {<br>
+ assert(!RealDef || RealDef == &MI &&<br>
+ "Can have at most one definition which is not a redefinition");<br>
+ RealDef = &MI;<br>
+ }<br>
+ }<br>
+ }<br>
+ assert(RealDef != nullptr && "Must have at least 1 Def");<br>
+#endif<br>
+<br>
+ // We should only have one definition of the register. However to accomodate<br>
+ // the requirements of two address code we also allow definitions in<br>
+ // subsequent instructions provided they also read the register. That way<br>
+ // we get a single contiguous lifetime.<br>
+ //<br>
+ // Definitions in MRI.def_begin() are unordered, search for the first.<br>
+ MachineRegisterInfo::def_iterator FirstDef =<br>
+ std::find_if(MRI.def_begin(VReg), MRI.def_end(),<br>
+ [VReg, &TRI](const MachineOperand &MO) {<br>
+ return !MO.getParent()->readsRegister(VReg, &TRI);<br>
+ });<br>
+ assert(FirstDef != MRI.def_end() &&<br>
+ "Must have one definition that does not redefine vreg");<br>
+ MachineInstr &DefMI = *FirstDef->getParent();<br>
+<br>
+ // The register scavenger will report a free register inserting an emergency<br>
+ // spill/reload if necessary.<br>
+ int SPAdj = 0;<br>
+ const TargetRegisterClass &RC = *MRI.getRegClass(VReg);<br>
+ unsigned SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),<br>
+ ReserveAfter, SPAdj);<br>
+ MRI.replaceRegWith(VReg, SReg);<br>
+ ++NumScavengedRegs;<br>
+ return SReg;<br>
+}<br>
<br>
- for (const MachineOperand &MO : MI.operands()) {<br>
+/// Allocate (scavenge) vregs inside a single basic block.<br>
+/// Returns true if the target spill callback created new vregs and a 2nd pass<br>
+/// is necessary.<br>
+static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI,<br>
+ RegScavenger &RS,<br>
+ MachineBasicBlock &MBB) {<br>
+ const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();<br>
+ RS.enterBasicBlockEnd(MBB);<br>
+<br>
+ unsigned InitialNumVirtRegs = MRI.getNumVirtRegs();<br>
+ bool NextInstructionReadsVReg = false;<br>
+ for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ) {<br>
+ --I;<br>
+ // Move RegScavenger to the position between *I and *std::next(I).<br>
+ RS.backward(I);<br>
+<br>
+ // Look for unassigned vregs in the uses of *std::next(I).<br>
+ if (NextInstructionReadsVReg) {<br>
+ MachineBasicBlock::iterator N = std::next(I);<br>
+ const MachineInstr &NMI = *N;<br>
+ for (const MachineOperand &MO : NMI.operands()) {<br>
if (!MO.isReg())<br>
continue;<br>
unsigned Reg = MO.getReg();<br>
- if (!TargetRegisterInfo::isVirtualRegister(Reg))<br>
+ // We only care about virtual registers and ignore virtual registers<br>
+ // created by the target callbacks in the process (those will be handled<br>
+ // in a scavenging round).<br>
+ if (!TargetRegisterInfo::isVirtualRegister(Reg) ||<br>
+ TargetRegisterInfo::virtReg2Index(Reg) >= InitialNumVirtRegs)<br>
continue;<br>
+ if (!MO.readsReg())<br>
+ continue;<br>
+<br>
+ unsigned SReg = scavengeVReg(MRI, RS, Reg, true);<br>
+ N->addRegisterKilled(SReg, &TRI, false);<br>
+ RS.setRegUsed(SReg);<br>
+ }<br>
+ }<br>
+<br>
+ // Look for unassigned vregs in the defs of *I.<br>
+ NextInstructionReadsVReg = false;<br>
+ const MachineInstr &MI = *I;<br>
+ for (const MachineOperand &MO : MI.operands()) {<br>
+ if (!MO.isReg())<br>
+ continue;<br>
+ unsigned Reg = MO.getReg();<br>
+ // Only vregs, no newly created vregs (see above).<br>
+ if (!TargetRegisterInfo::isVirtualRegister(Reg) ||<br>
+ TargetRegisterInfo::virtReg2Index(Reg) >= InitialNumVirtRegs)<br>
+ continue;<br>
+ // We have to look at all operands anyway so we can precalculate here<br>
+ // whether there is a reading operand. This allows use to skip the use<br>
+ // step in the next iteration if there was none.<br>
+ assert(!MO.isInternalRead() && "Cannot assign inside bundles");<br>
+ assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");<br>
+ if (MO.readsReg()) {<br>
+ NextInstructionReadsVReg = true;<br>
+ }<br>
+ if (MO.isDef()) {<br>
+ unsigned SReg = scavengeVReg(MRI, RS, Reg, false);<br>
+ I->addRegisterDead(SReg, &TRI, false);<br>
+ }<br>
+ }<br>
+ }<br>
+#ifndef NDEBUG<br>
+ for (const MachineOperand &MO : MBB.front().operands()) {<br>
+ if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))<br>
+ continue;<br>
+ assert(!MO.isInternalRead() && "Cannot assign inside bundles");<br>
+ assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");<br>
+ assert(!MO.readsReg() && "Vreg use in first instruction not allowed");<br>
+ }<br>
+#endif<br>
+<br>
+ return MRI.getNumVirtRegs() != InitialNumVirtRegs;<br>
+}<br>
+<br>
+void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {<br>
+ // FIXME: Iterating over the instruction stream is unnecessary. We can simply<br>
+ // iterate over the vreg use list, which at this point only contains machine<br>
+ // operands for which eliminateFrameIndex need a new scratch reg.<br>
+ MachineRegisterInfo &MRI = MF.getRegInfo();<br>
+ // Shortcut.<br>
+ if (MRI.getNumVirtRegs() == 0) {<br>
+ MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);<br>
+ return;<br>
+ }<br>
+<br>
+ // Run through the instructions and find any virtual registers.<br>
+ for (MachineBasicBlock &MBB : MF) {<br>
+ if (MBB.empty())<br>
+ continue;<br>
<br>
- // When we first encounter a new virtual register, it<br>
- // must be a definition.<br>
- assert(MO.isDef() && "frame index virtual missing def!");<br>
- // Scavenge a new scratch register<br>
- const TargetRegisterClass *RC = MRI.getRegClass(Reg);<br>
- unsigned ScratchReg = RS.scavengeRegister(RC, J, SPAdj);<br>
-<br>
- ++NumScavengedRegs;<br>
-<br>
- // Replace this reference to the virtual register with the<br>
- // scratch register.<br>
- assert(ScratchReg && "Missing scratch register!");<br>
- MRI.replaceRegWith(Reg, ScratchReg);<br>
-<br>
- // Because this instruction was processed by the RS before this<br>
- // register was allocated, make sure that the RS now records the<br>
- // register as being used.<br>
- RS.setRegUsed(ScratchReg);<br>
- }<br>
-<br>
- // If the scavenger needed to use one of its spill slots, the<br>
- // spill code will have been inserted in between I and J. This is a<br>
- // problem because we need the spill code before I: Move I to just<br>
- // prior to J.<br>
- if (I != std::prev(J)) {<br>
- MBB.splice(J, &MBB, I);<br>
-<br>
- // Before we move I, we need to prepare the RS to visit I again.<br>
- // Specifically, RS will assert if it sees uses of registers that<br>
- // it believes are undefined. Because we have already processed<br>
- // register kills in I, when it visits I again, it will believe that<br>
- // those registers are undefined. To avoid this situation, unprocess<br>
- // the instruction I.<br>
- assert(RS.getCurrentPosition() == I &&<br>
- "The register scavenger has an unexpected position");<br>
- I = P;<br>
- RS.unprocess(P);<br>
- } else<br>
- ++I;<br>
+ bool Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);<br>
+ if (Again) {<br>
+ DEBUG(dbgs() << "Warning: Required two scavenging passes for block "<br>
+ << MBB.getName() << '\n');<br>
+ Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);<br>
+ // The target required a 2nd run (because it created new vregs while<br>
+ // spilling). Refuse to do another pass to keep compiletime in check.<br>
+ if (Again)<br>
+ report_fatal_error("Incomplete scavenging after 2nd pass");<br>
}<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir Thu Jun 15 17:14:55 2017<br>
@@ -45,8 +45,42 @@ body: |<br>
%fp = COPY %xzr<br>
%lr = COPY %xzr<br>
ST1Fourv1d killed %d16_d17_d18_d19, %stack.0 :: (store 32 into %stack.0, align 8)<br>
-# CHECK: STRXui killed %[[SCAVREG:x[0-9]+|fp|lr]], %sp, [[SPOFFSET:[0-9]+]] :: (store 8 into %stack.1)<br>
-# CHECK-NEXT: %[[SCAVREG]] = ADDXri %sp, {{[0-9]+}}, 0<br>
-# CHECK-NEXT: ST1Fourv1d killed %d16_d17_d18_d19, killed %[[SCAVREG]] :: (store 32 into %stack.0, align 8)<br>
-# CHECK-NEXT: %[[SCAVREG]] = LDRXui %sp, [[SPOFFSET]] :: (load 8 from %stack.1)<br>
+ ; CHECK: STRXui killed %[[SCAVREG:x[0-9]+|fp|lr]], %sp, [[SPOFFSET:[0-9]+]] :: (store 8 into %stack.1)<br>
+ ; CHECK-NEXT: %[[SCAVREG]] = ADDXri %sp, {{[0-9]+}}, 0<br>
+ ; CHECK-NEXT: ST1Fourv1d killed %d16_d17_d18_d19, killed %[[SCAVREG]] :: (store 32 into %stack.0, align 8)<br>
+ ; CHECK-NEXT: %[[SCAVREG]] = LDRXui %sp, [[SPOFFSET]] :: (load 8 from %stack.1)<br>
+<br>
+ HINT 0, implicit %x0<br>
+ HINT 0, implicit %x1<br>
+ HINT 0, implicit %x2<br>
+ HINT 0, implicit %x3<br>
+ HINT 0, implicit %x4<br>
+ HINT 0, implicit %x5<br>
+ HINT 0, implicit %x6<br>
+ HINT 0, implicit %x7<br>
+ HINT 0, implicit %x8<br>
+ HINT 0, implicit %x9<br>
+ HINT 0, implicit %x10<br>
+ HINT 0, implicit %x11<br>
+ HINT 0, implicit %x12<br>
+ HINT 0, implicit %x13<br>
+ HINT 0, implicit %x14<br>
+ HINT 0, implicit %x15<br>
+ HINT 0, implicit %x16<br>
+ HINT 0, implicit %x17<br>
+ HINT 0, implicit %x18<br>
+ HINT 0, implicit %x19<br>
+ HINT 0, implicit %x20<br>
+ HINT 0, implicit %x21<br>
+ HINT 0, implicit %x22<br>
+ HINT 0, implicit %x23<br>
+ HINT 0, implicit %x24<br>
+ HINT 0, implicit %x25<br>
+ HINT 0, implicit %x26<br>
+ HINT 0, implicit %x27<br>
+ HINT 0, implicit %x28<br>
+ HINT 0, implicit %fp<br>
+ HINT 0, implicit %lr<br>
+<br>
+ RET_ReallyLR<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll Thu Jun 15 17:14:55 2017<br>
@@ -39,44 +39,49 @@ define amdgpu_kernel void @max_9_sgprs(i<br>
; features when the number of registers is frozen), this ends up using<br>
; more than expected.<br>
<br>
-; ALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs:<br>
-; TOSGPR: SGPRBlocks: 1<br>
-; TOSGPR: NumSGPRsForWavesPerEU: 16<br>
-<br>
-; TOSMEM: s_mov_b64 s[10:11], s[2:3]<br>
-; TOSMEM: s_mov_b64 s[8:9], s[0:1]<br>
-; TOSMEM: s_mov_b32 s7, s13<br>
-<br>
-; TOSMEM: SGPRBlocks: 1<br>
-; TOSMEM: NumSGPRsForWavesPerEU: 16<br>
-define amdgpu_kernel void @max_12_sgprs_14_input_sgprs(i32 addrspace(1)* %out1,<br>
- i32 addrspace(1)* %out2,<br>
- i32 addrspace(1)* %out3,<br>
- i32 addrspace(1)* %out4,<br>
- i32 %one, i32 %two, i32 %three, i32 %four) #2 {<br>
- %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()<br>
- %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()<br>
- %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()<br>
- %x.3 = call i64 @<a href="http://llvm.amdgcn.dispatch.id" rel="noreferrer" target="_blank">llvm.amdgcn.dispatch.id</a>()<br>
- %x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()<br>
- %x.5 = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr()<br>
- store volatile i32 0, i32* undef<br>
- br label %stores<br>
-<br>
-stores:<br>
- store volatile i32 %x.0, i32 addrspace(1)* undef<br>
- store volatile i32 %x.0, i32 addrspace(1)* undef<br>
- store volatile i32 %x.0, i32 addrspace(1)* undef<br>
- store volatile i64 %x.3, i64 addrspace(1)* undef<br>
- store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef<br>
- store volatile i8 addrspace(2)* %x.5, i8 addrspace(2)* addrspace(1)* undef<br>
-<br>
- store i32 %one, i32 addrspace(1)* %out1<br>
- store i32 %two, i32 addrspace(1)* %out2<br>
- store i32 %three, i32 addrspace(1)* %out3<br>
- store i32 %four, i32 addrspace(1)* %out4<br>
- ret void<br>
-}<br>
+; XALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs:<br>
+; XTOSGPR: SGPRBlocks: 1<br>
+; XTOSGPR: NumSGPRsForWavesPerEU: 16<br>
+<br>
+; XTOSMEM: s_mov_b64 s[10:11], s[2:3]<br>
+; XTOSMEM: s_mov_b64 s[8:9], s[0:1]<br>
+; XTOSMEM: s_mov_b32 s7, s13<br>
+<br>
+; XTOSMEM: SGPRBlocks: 1<br>
+; XTOSMEM: NumSGPRsForWavesPerEU: 16<br>
+;<br>
+; This test case is disabled: When calculating the spillslot addresses AMDGPU<br>
+; creates an extra vreg to save/restore m0 which in a point of maximum register<br>
+; pressure would trigger an endless loop; the compiler aborts earlier with<br>
+; "Incomplete scavenging after 2nd pass" in practice.<br>
+;define amdgpu_kernel void @max_12_sgprs_14_input_sgprs(i32 addrspace(1)* %out1,<br>
+; i32 addrspace(1)* %out2,<br>
+; i32 addrspace(1)* %out3,<br>
+; i32 addrspace(1)* %out4,<br>
+; i32 %one, i32 %two, i32 %three, i32 %four) #2 {<br>
+; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()<br>
+; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()<br>
+; %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()<br>
+; %x.3 = call i64 @<a href="http://llvm.amdgcn.dispatch.id" rel="noreferrer" target="_blank">llvm.amdgcn.dispatch.id</a>()<br>
+; %x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()<br>
+; %x.5 = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr()<br>
+; store volatile i32 0, i32* undef<br>
+; br label %stores<br>
+;<br>
+;stores:<br>
+; store volatile i32 %x.0, i32 addrspace(1)* undef<br>
+; store volatile i32 %x.0, i32 addrspace(1)* undef<br>
+; store volatile i32 %x.0, i32 addrspace(1)* undef<br>
+; store volatile i64 %x.3, i64 addrspace(1)* undef<br>
+; store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef<br>
+; store volatile i8 addrspace(2)* %x.5, i8 addrspace(2)* addrspace(1)* undef<br>
+;<br>
+; store i32 %one, i32 addrspace(1)* %out1<br>
+; store i32 %two, i32 addrspace(1)* %out2<br>
+; store i32 %three, i32 addrspace(1)* %out3<br>
+; store i32 %four, i32 addrspace(1)* %out4<br>
+; ret void<br>
+;}<br>
<br>
; The following test is commented out for now; <a href="http://llvm.org/PR31230" rel="noreferrer" target="_blank">http://llvm.org/PR31230</a><br>
; XALL-LABEL: max_12_sgprs_12_input_sgprs{{$}}<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll Thu Jun 15 17:14:55 2017<br>
@@ -12,8 +12,8 @@ declare void @llvm.dbg.declare(metadata,<br>
; CHECK: DebugProps:<br>
; CHECK: DebuggerABIVersion: [ 1, 0 ]<br>
; CHECK: ReservedNumVGPRs: 4<br>
-; GFX700: ReservedFirstVGPR: 11<br>
-; GFX800: ReservedFirstVGPR: 11<br>
+; GFX700: ReservedFirstVGPR: 8<br>
+; GFX800: ReservedFirstVGPR: 8<br>
; GFX9: ReservedFirstVGPR: 14<br>
; CHECK: PrivateSegmentBufferSGPR: 0<br>
; CHECK: WavefrontPrivateSegmentOffsetSGPR: 11<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll Thu Jun 15 17:14:55 2017<br>
@@ -22,9 +22,9 @@ define void @func_mov_fi_i32() #0 {<br>
<br>
; GCN-LABEL: {{^}}func_add_constant_to_fi_i32:<br>
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)<br>
-; GCN: s_sub_u32 s6, s5, s4<br>
-; GCN-NEXT: s_lshr_b32 s6, s6, 6<br>
-; GCN-NEXT: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, s6, 4<br>
+; GCN: s_sub_u32 vcc_hi, s5, s4<br>
+; GCN-NEXT: s_lshr_b32 vcc_hi, vcc_hi, 6<br>
+; GCN-NEXT: v_add_i32_e64 v0, {{s\[[0-9]+:[0-9]+\]|vcc}}, vcc_hi, 4<br>
; GCN-NEXT: v_add_i32_e32 v0, vcc, 4, v0<br>
; GCN-NOT: v_mov<br>
; GCN: ds_write_b32 v0, v0<br>
@@ -71,8 +71,8 @@ define void @func_load_private_arg_i32_p<br>
<br>
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr:<br>
; GCN: s_waitcnt<br>
-; GCN-NEXT: s_sub_u32 s6, s5, s4<br>
-; GCN-NEXT: v_lshr_b32_e64 v0, s6, 6<br>
+; GCN-NEXT: s_sub_u32 vcc_hi, s5, s4<br>
+; GCN-NEXT: v_lshr_b32_e64 v0, vcc_hi, 6<br>
; GCN-NEXT: v_add_i32_e32 v0, vcc, 4, v0<br>
; GCN-NOT: v_mov<br>
; GCN: ds_write_b32 v0, v0<br>
@@ -99,8 +99,8 @@ define void @void_func_byval_struct_i8_i<br>
}<br>
<br>
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr_nonentry_block:<br>
-; GCN: s_sub_u32 s8, s5, s4<br>
-; GCN: v_lshr_b32_e64 v1, s8, 6<br>
+; GCN: s_sub_u32 vcc_hi, s5, s4<br>
+; GCN: v_lshr_b32_e64 v1, vcc_hi, 6<br>
; GCN: s_and_saveexec_b64<br>
<br>
; GCN: v_add_i32_e32 v0, vcc, 4, v1<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/alloca-align.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/alloca-align.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/alloca-align.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/alloca-align.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/alloca-align.ll Thu Jun 15 17:14:55 2017<br>
@@ -12,7 +12,7 @@ declare void @bar(i32*, [20000 x i8]* by<br>
; And a base pointer getting used.<br>
; CHECK: mov r6, sp<br>
; Which is passed to the call<br>
-; CHECK: add [[REG:r[0-9]+]], r6, #19456<br>
+; CHECK: add [[REG:r[0-9]+|lr]], r6, #19456<br>
; CHECK: add r0, [[REG]], #536<br>
; CHECK: bl bar<br>
define void @foo([20000 x i8]* %addr) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll Thu Jun 15 17:14:55 2017<br>
@@ -10,10 +10,10 @@ define i8 @test_big_stack_frame() {<br>
; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}<br>
; CHECK-SUBW-ADDW: sub.w sp, sp, #65536<br>
; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}<br>
-; CHECK-SUBW-ADDW: add.w [[REG1:r[0-9]+]], sp, #255<br>
+; CHECK-SUBW-ADDW: add.w [[REG1:r[0-9]+|lr]], sp, #255<br>
; CHECK-SUBW-ADDW: add.w {{r[0-9]+}}, [[REG1]], #65280<br>
; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}<br>
-; CHECK-SUBW-ADDW: add.w lr, sp, #61440<br>
+; CHECK-SUBW-ADDW: add.w [[REGX:r[0-9]+|lr]], sp, #61440<br>
; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}<br>
; CHECK-SUBW-ADDW: add.w sp, sp, #65536<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir Thu Jun 15 17:14:55 2017<br>
@@ -3,10 +3,10 @@<br>
# This should trigger an emergency spill in the register scavenger because the<br>
# frame offset into the large argument is too large.<br>
# CHECK-LABEL: name: func0<br>
-# CHECK: t2STRi12 killed %r7, %sp, 0, 14, _ :: (store 4 into %stack.0)<br>
-# CHECK: %r7 = t2ADDri killed %sp, 4096, 14, _, _<br>
-# CHECK: %r11 = t2LDRi12 killed %r7, 36, 14, _ :: (load 4)<br>
-# CHECK: %r7 = t2LDRi12 %sp, 0, 14, _ :: (load 4 from %stack.0)<br>
+# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, _ :: (store 4 into %stack.0)<br>
+# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, _, _<br>
+# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, _ :: (load 4)<br>
+# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, _ :: (load 4 from %stack.0)<br>
name: func0<br>
tracksRegLiveness: true<br>
fixedStack:<br>
@@ -23,6 +23,7 @@ body: |<br>
%r4 = IMPLICIT_DEF<br>
%r5 = IMPLICIT_DEF<br>
%r6 = IMPLICIT_DEF<br>
+ %r7 = IMPLICIT_DEF<br>
%r8 = IMPLICIT_DEF<br>
%r9 = IMPLICIT_DEF<br>
%r10 = IMPLICIT_DEF<br>
@@ -30,7 +31,7 @@ body: |<br>
%r12 = IMPLICIT_DEF<br>
%lr = IMPLICIT_DEF<br>
<br>
- %r11 = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4)<br>
+ %sp = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4)<br>
<br>
KILL %r0<br>
KILL %r1<br>
@@ -39,6 +40,7 @@ body: |<br>
KILL %r4<br>
KILL %r5<br>
KILL %r6<br>
+ KILL %r7<br>
KILL %r8<br>
KILL %r9<br>
KILL %r10<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll Thu Jun 15 17:14:55 2017<br>
@@ -1,34 +1,62 @@<br>
-; Check that register scavenging spill slot is close to $fp.<br>
; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s<br>
+; Check that register scavenging spill slot is close to $fp.<br>
+target triple="mipsel--"<br>
<br>
-; CHECK: sw ${{.*}}, 8($sp)<br>
-; CHECK: lw ${{.*}}, 8($sp)<br>
+@var = external global i32<br>
+@ptrvar = external global i8*<br>
<br>
-define i32 @main(i32 signext %argc, i8** %argv) #0 {<br>
-entry:<br>
- %retval = alloca i32, align 4<br>
- %argc.addr = alloca i32, align 4<br>
- %argv.addr = alloca i8**, align 4<br>
- %v0 = alloca <16 x i8>, align 16<br>
- %.compoundliteral = alloca <16 x i8>, align 16<br>
- %v1 = alloca <16 x i8>, align 16<br>
- %.compoundliteral1 = alloca <16 x i8>, align 16<br>
- %unused_variable = alloca [16384 x i32], align 4<br>
- %result = alloca <16 x i8>, align 16<br>
- store i32 0, i32* %retval<br>
- store i32 %argc, i32* %argc.addr, align 4<br>
- store i8** %argv, i8*** %argv.addr, align 4<br>
- store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral<br>
- %0 = load <16 x i8>, <16 x i8>* %.compoundliteral<br>
- store <16 x i8> %0, <16 x i8>* %v0, align 16<br>
- store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1<br>
- %1 = load <16 x i8>, <16 x i8>* %.compoundliteral1<br>
- store <16 x i8> %1, <16 x i8>* %v1, align 16<br>
- %2 = load <16 x i8>, <16 x i8>* %v0, align 16<br>
- %3 = load <16 x i8>, <16 x i8>* %v1, align 16<br>
- %mul = mul <16 x i8> %2, %3<br>
- store <16 x i8> %mul, <16 x i8>* %result, align 16<br>
- ret i32 0<br>
-}<br>
+; CHECK-LABEL: func:<br>
+define void @func() {<br>
+ %space = alloca i32, align 4<br>
+ %stackspace = alloca[16384 x i32], align 4<br>
+<br>
+ ; ensure stackspace is not optimized out<br>
+ %stackspace_casted = bitcast [16384 x i32]* %stackspace to i8*<br>
+ store volatile i8* %stackspace_casted, i8** @ptrvar<br>
<br>
-attributes #0 = { noinline "no-frame-pointer-elim"="true" }<br>
+ ; Load values to increase register pressure.<br>
+ %v0 = load volatile i32, i32* @var<br>
+ %v1 = load volatile i32, i32* @var<br>
+ %v2 = load volatile i32, i32* @var<br>
+ %v3 = load volatile i32, i32* @var<br>
+ %v4 = load volatile i32, i32* @var<br>
+ %v5 = load volatile i32, i32* @var<br>
+ %v6 = load volatile i32, i32* @var<br>
+ %v7 = load volatile i32, i32* @var<br>
+ %v8 = load volatile i32, i32* @var<br>
+ %v9 = load volatile i32, i32* @var<br>
+ %v10 = load volatile i32, i32* @var<br>
+ %v11 = load volatile i32, i32* @var<br>
+ %v12 = load volatile i32, i32* @var<br>
+ %v13 = load volatile i32, i32* @var<br>
+ %v14 = load volatile i32, i32* @var<br>
+ %v15 = load volatile i32, i32* @var<br>
+ %v16 = load volatile i32, i32* @var<br>
+<br>
+ ; Computing a stack-relative values needs an additional register.<br>
+ ; We should get an emergency spill/reload for this.<br>
+ ; CHECK: sw ${{.*}}, 0($sp)<br>
+ ; CHECK: lw ${{.*}}, 0($sp)<br>
+ store volatile i32 %v0, i32* %space<br>
+<br>
+ ; store values so they are used.<br>
+ store volatile i32 %v0, i32* @var<br>
+ store volatile i32 %v1, i32* @var<br>
+ store volatile i32 %v2, i32* @var<br>
+ store volatile i32 %v3, i32* @var<br>
+ store volatile i32 %v4, i32* @var<br>
+ store volatile i32 %v5, i32* @var<br>
+ store volatile i32 %v6, i32* @var<br>
+ store volatile i32 %v7, i32* @var<br>
+ store volatile i32 %v8, i32* @var<br>
+ store volatile i32 %v9, i32* @var<br>
+ store volatile i32 %v10, i32* @var<br>
+ store volatile i32 %v11, i32* @var<br>
+ store volatile i32 %v12, i32* @var<br>
+ store volatile i32 %v13, i32* @var<br>
+ store volatile i32 %v14, i32* @var<br>
+ store volatile i32 %v15, i32* @var<br>
+ store volatile i32 %v16, i32* @var<br>
+<br>
+ ret void<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll (original)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll Thu Jun 15 17:14:55 2017<br>
@@ -25,8 +25,8 @@ entry:<br>
<br>
; CHECK-DAG: li [[REG1:[0-9]+]], -128<br>
; CHECK-DAG: neg [[REG2:[0-9]+]],<br>
-; CHECK: and [[REG1]], [[REG2]], [[REG1]]<br>
-; CHECK: stdux {{[0-9]+}}, 1, [[REG1]]<br>
+; CHECK: and [[REG3:[0-9]+]], [[REG2]], [[REG1]]<br>
+; CHECK: stdux {{[0-9]+}}, 1, [[REG3]]<br>
<br>
; CHECK: blr<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerPC/scavenging.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/scavenging.mir?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/scavenging.mir?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/scavenging.mir (original)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/scavenging.mir Thu Jun 15 17:14:55 2017<br>
@@ -6,7 +6,7 @@ tracksRegLiveness: true<br>
body: |<br>
bb.0:<br>
; CHECK: [[REG0:%r[0-9]+]] = LI 42<br>
- ; CHECK-NEXT: NOP implicit [[REG0]]<br>
+ ; CHECK-NEXT: NOP implicit killed [[REG0]]<br>
%0 : gprc = LI 42<br>
NOP implicit %0<br>
<br>
@@ -14,7 +14,7 @@ body: |<br>
; CHECK-NEXT: NOP<br>
; CHECK-NEXT: NOP implicit [[REG1]]<br>
; CHECK-NEXT: NOP<br>
- ; CHECK-NEXT: NOP implicit [[REG1]]<br>
+ ; CHECK-NEXT: NOP implicit killed [[REG1]]<br>
%1 : gprc = LI 42<br>
NOP<br>
NOP implicit %1<br>
@@ -48,8 +48,8 @@ body: |<br>
; CHECK-NOT: %x30 = LI 42<br>
; CHECK: [[REG3:%r[0-9]+]] = LI 42<br>
; CHECK-NEXT: %x5 = IMPLICIT_DEF<br>
- ; CHECK-NEXT: NOP implicit [[REG2]]<br>
- ; CHECK-NEXT: NOP implicit [[REG3]]<br>
+ ; CHECK-NEXT: NOP implicit killed [[REG2]]<br>
+ ; CHECK-NEXT: NOP implicit killed [[REG3]]<br>
%3 : gprc = LI 42<br>
%x5 = IMPLICIT_DEF<br>
NOP implicit %2<br>
@@ -110,7 +110,7 @@ body: |<br>
<br>
; CHECK: STD killed [[SPILLEDREG:%x[0-9]+]]<br>
; CHECK: [[SPILLEDREG]] = LI8 42<br>
- ; CHECK: NOP implicit [[SPILLEDREG]]<br>
+ ; CHECK: NOP implicit killed [[SPILLEDREG]]<br>
; CHECK: [[SPILLEDREG]] = LD<br>
%0 : g8rc = LI8 42<br>
NOP implicit %0<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb/large-stack.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/large-stack.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/large-stack.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Thumb/large-stack.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb/large-stack.ll Thu Jun 15 17:14:55 2017<br>
@@ -69,10 +69,10 @@ define i32 @test3() {<br>
; CHECK-LABEL: test3:<br>
; CHECK: ldr [[TEMP:r[0-7]]],<br>
; CHECK: add sp, [[TEMP]]<br>
-; CHECK: ldr [[TEMP]],<br>
-; CHECK: add [[TEMP]], sp<br>
-; CHECK: ldr [[TEMP:r[0-7]]],<br>
-; CHECK: add sp, [[TEMP]]<br>
+; CHECK: ldr [[TEMP2:r[0-7]]],<br>
+; CHECK: add [[TEMP2]], sp<br>
+; CHECK: ldr [[TEMP3:r[0-7]]],<br>
+; CHECK: add sp, [[TEMP3]]<br>
%retval = alloca i32, align 4<br>
%tmp = alloca i32, align 4<br>
%a = alloca [805306369 x i8], align 16<br>
@@ -85,8 +85,8 @@ define i32 @test3_nofpelim() "no-frame-p<br>
; CHECK-LABEL: test3_nofpelim:<br>
; CHECK: ldr [[TEMP:r[0-7]]],<br>
; CHECK: add sp, [[TEMP]]<br>
-; CHECK: ldr [[TEMP]],<br>
-; CHECK: add [[TEMP]], sp<br>
+; CHECK: ldr [[TEMP2:r[0-7]]],<br>
+; CHECK: add [[TEMP2]], sp<br>
; CHECK: subs r4, r7,<br>
; CHECK: mov sp, r4<br>
%retval = alloca i32, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/scavenger.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/scavenger.mir?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/scavenger.mir?rev=305516&r1=305515&r2=305516&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/scavenger.mir (original)<br>
+++ llvm/trunk/test/CodeGen/X86/scavenger.mir Thu Jun 15 17:14:55 2017<br>
@@ -5,6 +5,8 @@ name: func0<br>
tracksRegLiveness: true<br>
body: |<br>
bb.0:<br>
+ ; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42<br>
+ ; CHECK: %ebp = COPY killed [[REG0]]<br>
%0 : gr32 = MOV32ri 42<br>
%ebp = COPY %0<br>
...<br>
@@ -16,7 +18,7 @@ body: |<br>
bb.0:<br>
; CHECK-NOT: %eax = MOV32ri 42<br>
; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42<br>
- ; CHECK: %ebp = COPY [[REG0]]<br>
+ ; CHECK: %ebp = COPY killed [[REG0]]<br>
%eax = MOV32ri 13<br>
%0 : gr32 = MOV32ri 42<br>
%ebp = COPY %0<br>
@@ -30,25 +32,18 @@ body: |<br>
<br>
NOOP implicit %ebp<br>
<br>
- ; CHECK: NOOP implicit [[REG2]]<br>
- ; CHECK: NOOP implicit [[REG1]]<br>
+ ; CHECK: NOOP implicit killed [[REG2]]<br>
+ ; CHECK: NOOP implicit killed [[REG1]]<br>
NOOP implicit %2<br>
NOOP implicit %1<br>
RETQ %eax<br>
...<br>
---<br>
-# Defs without uses are currently broken<br>
-#name: func3<br>
-#tracksRegLiveness: true<br>
-#body: |<br>
-# bb.0:<br>
-# dead %0 : gr32 = MOV32ri 42<br>
-...<br>
----<br>
-# Uses without defs are currently broken (and honestly not that useful).<br>
-#name: func3<br>
-#tracksRegLiveness: true<br>
-#body: |<br>
-# bb.0:<br>
-# NOOP undef implicit %0 : gr32<br>
+# CHECK-LABEL: name: func3<br>
+name: func3<br>
+tracksRegLiveness: true<br>
+body: |<br>
+ bb.0:<br>
+ ; CHECK dead {{%e[a-z]+}} = MOV32ri 42<br>
+ dead %0 : gr32 = MOV32ri 42<br>
...<br>
<br>
<br>
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</blockquote></div>