<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><div class="">Thanks for the reproducer! Fixed in r305625.</div><div class=""><br class=""></div><div><blockquote type="cite" class=""><div class="">On Jun 16, 2017, at 5:58 PM, Eric Christopher <<a href="mailto:echristo@gmail.com" class="">echristo@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Sent offline due to size :\<div class=""><br class=""></div><div class="">-eric</div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Fri, Jun 16, 2017 at 10:59 AM Eric Christopher <<a href="mailto:echristo@gmail.com" class="">echristo@gmail.com</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr" class="">Yep. Will do :)</div><div dir="ltr" class=""><div class=""><br class=""></div><div class="">-eric</div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Fri, Jun 16, 2017 at 10:50 AM Matthias Braun <<a href="mailto:matze@braunis.de" target="_blank" class="">matze@braunis.de</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word" class=""><div class="">Sure, I reverted in r305566 but will definitely need a reproducer to investigate what exactly went wrong.</div></div><div style="word-wrap:break-word" class=""><div class=""><br class=""></div><div class="">- Matthias</div></div><div style="word-wrap:break-word" class=""><br class=""><div class=""><blockquote type="cite" class=""><div class="">On Jun 16, 2017, at 10:14 AM, Eric Christopher <<a href="mailto:echristo@gmail.com" target="_blank" class="">echristo@gmail.com</a>> wrote:</div><br class="m_-4104718330410612871m_2659329558805563094Apple-interchange-newline"><div class=""><div dir="ltr" class="">Hi Matthias,<div class=""><br class=""></div><div class="">Working on getting you something, but I did find this:</div><div class=""><br class=""></div><div class=""><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif" class="">fatal error: error in backend: Error while trying to spill X0 from class G8RC: Cannot scavenge register without an emergency spill slot!</span><br style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif" class=""></div><div class=""><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif" class=""><br class=""></span></div><div class=""><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif" class="">on a testcase. Guess we can try to revert for now and I'll work on a testcase?</span></div><div class=""><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif" class=""><br class=""></span></div><div class=""><span style="color:rgb(34,34,34);font-family:Arial,Helvetica,sans-serif" class="">-eric</span></div></div><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Thu, Jun 15, 2017 at 3:15 PM Matthias Braun via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: matze<br class="">
Date: Thu Jun 15 17:14:55 2017<br class="">
New Revision: 305516<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=305516&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=305516&view=rev</a><br class="">
Log:<br class="">
RegScavenging: Add scavengeRegisterBackwards()<br class="">
<br class="">
Re-apply r276044/r279124. Trying to reproduce or disprove the ppc64<br class="">
problems reported in the stage2 build last time, which I cannot<br class="">
reproduce right now.<br class="">
<br class="">
This is a variant of scavengeRegister() that works for<br class="">
enterBasicBlockEnd()/backward(). The benefit of the backward mode is<br class="">
that it is not affected by incomplete kill flags.<br class="">
<br class="">
This patch also changes<br class="">
PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register<br class="">
scavenger in backwards mode.<br class="">
<br class="">
Differential Revision: <a href="http://reviews.llvm.org/D21885" rel="noreferrer" target="_blank" class="">http://reviews.llvm.org/D21885</a><br class="">
<br class="">
Modified:<br class="">
llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h<br class="">
llvm/trunk/lib/CodeGen/RegisterScavenging.cpp<br class="">
llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir<br class="">
llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll<br class="">
llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll<br class="">
llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll<br class="">
llvm/trunk/test/CodeGen/ARM/alloca-align.ll<br class="">
llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll<br class="">
llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir<br class="">
llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll<br class="">
llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll<br class="">
llvm/trunk/test/CodeGen/PowerPC/scavenging.mir<br class="">
llvm/trunk/test/CodeGen/Thumb/large-stack.ll<br class="">
llvm/trunk/test/CodeGen/X86/scavenger.mir<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original)<br class="">
+++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Thu Jun 15 17:14:55 2017<br class="">
@@ -156,12 +156,24 @@ public:<br class="">
/// available and do the appropriate bookkeeping. SPAdj is the stack<br class="">
/// adjustment due to call frame, it's passed along to eliminateFrameIndex().<br class="">
/// Returns the scavenged register.<br class="">
+ /// This is deprecated as it depends on the quality of the kill flags being<br class="">
+ /// present; Use scavengeRegisterBackwards() instead!<br class="">
unsigned scavengeRegister(const TargetRegisterClass *RegClass,<br class="">
MachineBasicBlock::iterator I, int SPAdj);<br class="">
unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {<br class="">
return scavengeRegister(RegClass, MBBI, SPAdj);<br class="">
}<br class="">
<br class="">
+ /// Make a register of the specific register class available from the current<br class="">
+ /// position backwards to the place before \p To. If \p RestoreAfter is true<br class="">
+ /// this includes the instruction following the current position.<br class="">
+ /// SPAdj is the stack adjustment due to call frame, it's passed along to<br class="">
+ /// eliminateFrameIndex().<br class="">
+ /// Returns the scavenged register.<br class="">
+ unsigned scavengeRegisterBackwards(const TargetRegisterClass &RC,<br class="">
+ MachineBasicBlock::iterator To,<br class="">
+ bool RestoreAfter, int SPAdj);<br class="">
+<br class="">
/// Tell the scavenger a register is used.<br class="">
void setRegUsed(unsigned Reg, LaneBitmask LaneMask = LaneBitmask::getAll());<br class="">
<br class="">
@@ -202,6 +214,12 @@ private:<br class="">
<br class="">
/// Mark live-in registers of basic block as used.<br class="">
void setLiveInsUsed(const MachineBasicBlock &MBB);<br class="">
+<br class="">
+ /// Spill a register after position \p After and reload it before position<br class="">
+ /// \p UseMI.<br class="">
+ ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,<br class="">
+ MachineBasicBlock::iterator After,<br class="">
+ MachineBasicBlock::iterator &UseMI);<br class="">
};<br class="">
<br class="">
/// Replaces all frame index virtual registers with physical registers. Uses the<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Thu Jun 15 17:14:55 2017<br class="">
@@ -35,6 +35,7 @@<br class="">
#include "llvm/Target/TargetInstrInfo.h"<br class="">
#include "llvm/Target/TargetRegisterInfo.h"<br class="">
#include "llvm/Target/TargetSubtargetInfo.h"<br class="">
+#include <algorithm><br class="">
#include <cassert><br class="">
#include <iterator><br class="">
#include <limits><br class="">
@@ -260,6 +261,14 @@ void RegScavenger::backward() {<br class="">
const MachineInstr &MI = *MBBI;<br class="">
LiveUnits.stepBackward(MI);<br class="">
<br class="">
+ // Expire scavenge spill frameindex uses.<br class="">
+ for (ScavengedInfo &I : Scavenged) {<br class="">
+ if (I.Restore == &MI) {<br class="">
+ I.Reg = 0;<br class="">
+ I.Restore = nullptr;<br class="">
+ }<br class="">
+ }<br class="">
+<br class="">
if (MBBI == MBB->begin()) {<br class="">
MBBI = MachineBasicBlock::iterator(nullptr);<br class="">
Tracking = false;<br class="">
@@ -356,6 +365,76 @@ unsigned RegScavenger::findSurvivorReg(M<br class="">
return Survivor;<br class="">
}<br class="">
<br class="">
+/// Given the bitvector \p Available of free register units at position<br class="">
+/// \p From. Search backwards to find a register that is part of \p<br class="">
+/// Candidates and not used/clobbered until the point \p To. If there is<br class="">
+/// multiple candidates continue searching and pick the one that is not used/<br class="">
+/// clobbered for the longest time.<br class="">
+/// Returns the register and the earliest position we know it to be free or<br class="">
+/// the position MBB.end() if no register is available.<br class="">
+static std::pair<unsigned, MachineBasicBlock::iterator><br class="">
+findSurvivorBackwards(const TargetRegisterInfo &TRI,<br class="">
+ MachineBasicBlock::iterator From, MachineBasicBlock::iterator To,<br class="">
+ BitVector &Available, BitVector &Candidates) {<br class="">
+ bool FoundTo = false;<br class="">
+ unsigned Survivor = 0;<br class="">
+ MachineBasicBlock::iterator Pos;<br class="">
+ MachineBasicBlock &MBB = *From->getParent();<br class="">
+ unsigned InstrLimit = 25;<br class="">
+ unsigned InstrCountDown = InstrLimit;<br class="">
+ for (MachineBasicBlock::iterator I = From;; --I) {<br class="">
+ const MachineInstr &MI = *I;<br class="">
+<br class="">
+ // Remove any candidates touched by instruction.<br class="">
+ bool FoundVReg = false;<br class="">
+ for (const MachineOperand &MO : MI.operands()) {<br class="">
+ if (MO.isRegMask()) {<br class="">
+ Candidates.clearBitsNotInMask(MO.getRegMask());<br class="">
+ continue;<br class="">
+ }<br class="">
+ if (!MO.isReg() || MO.isUndef() || MO.isDebug())<br class="">
+ continue;<br class="">
+ unsigned Reg = MO.getReg();<br class="">
+ if (TargetRegisterInfo::isVirtualRegister(Reg)) {<br class="">
+ FoundVReg = true;<br class="">
+ } else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {<br class="">
+ for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)<br class="">
+ Candidates.reset(*AI);<br class="">
+ }<br class="">
+ }<br class="">
+<br class="">
+ if (I == To) {<br class="">
+ // If one of the available registers survived this long take it.<br class="">
+ Available &= Candidates;<br class="">
+ int Reg = Available.find_first();<br class="">
+ if (Reg != -1)<br class="">
+ return std::make_pair(Reg, MBB.end());<br class="">
+ // Otherwise we will continue up to InstrLimit instructions to find<br class="">
+ // the register which is not defined/used for the longest time.<br class="">
+ FoundTo = true;<br class="">
+ Pos = To;<br class="">
+ }<br class="">
+ if (FoundTo) {<br class="">
+ if (Survivor == 0 || !Candidates.test(Survivor)) {<br class="">
+ int Reg = Candidates.find_first();<br class="">
+ if (Reg == -1)<br class="">
+ break;<br class="">
+ Survivor = Reg;<br class="">
+ }<br class="">
+ if (--InstrCountDown == 0 || I == MBB.begin())<br class="">
+ break;<br class="">
+ if (FoundVReg) {<br class="">
+ // Keep searching when we find a vreg since the spilled register will<br class="">
+ // be usefull for this other vreg as well later.<br class="">
+ InstrCountDown = InstrLimit;<br class="">
+ Pos = I;<br class="">
+ }<br class="">
+ }<br class="">
+ }<br class="">
+<br class="">
+ return std::make_pair(Survivor, Pos);<br class="">
+}<br class="">
+<br class="">
static unsigned getFrameIndexOperandNum(MachineInstr &MI) {<br class="">
unsigned i = 0;<br class="">
while (!MI.getOperand(i).isFI()) {<br class="">
@@ -365,44 +444,16 @@ static unsigned getFrameIndexOperandNum(<br class="">
return i;<br class="">
}<br class="">
<br class="">
-unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,<br class="">
- MachineBasicBlock::iterator I,<br class="">
- int SPAdj) {<br class="">
- MachineInstr &MI = *I;<br class="">
- const MachineFunction &MF = *MI.getParent()->getParent();<br class="">
- // Consider all allocatable registers in the register class initially<br class="">
- BitVector Candidates = TRI->getAllocatableSet(MF, RC);<br class="">
-<br class="">
- // Exclude all the registers being used by the instruction.<br class="">
- for (const MachineOperand &MO : MI.operands()) {<br class="">
- if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&<br class="">
- !TargetRegisterInfo::isVirtualRegister(MO.getReg()))<br class="">
- for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)<br class="">
- Candidates.reset(*AI);<br class="">
- }<br class="">
-<br class="">
- // Try to find a register that's unused if there is one, as then we won't<br class="">
- // have to spill.<br class="">
- BitVector Available = getRegsAvailable(RC);<br class="">
- Available &= Candidates;<br class="">
- if (Available.any())<br class="">
- Candidates = Available;<br class="">
-<br class="">
- // Find the register whose use is furthest away.<br class="">
- MachineBasicBlock::iterator UseMI;<br class="">
- unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);<br class="">
-<br class="">
- // If we found an unused register there is no reason to spill it.<br class="">
- if (!isRegUsed(SReg)) {<br class="">
- DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");<br class="">
- return SReg;<br class="">
- }<br class="">
-<br class="">
+RegScavenger::ScavengedInfo &<br class="">
+RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,<br class="">
+ MachineBasicBlock::iterator Before,<br class="">
+ MachineBasicBlock::iterator &UseMI) {<br class="">
// Find an available scavenging slot with size and alignment matching<br class="">
// the requirements of the class RC.<br class="">
+ const MachineFunction &MF = *Before->getParent()->getParent();<br class="">
const MachineFrameInfo &MFI = MF.getFrameInfo();<br class="">
- unsigned NeedSize = TRI->getSpillSize(*RC);<br class="">
- unsigned NeedAlign = TRI->getSpillAlignment(*RC);<br class="">
+ unsigned NeedSize = TRI->getSpillSize(RC);<br class="">
+ unsigned NeedAlign = TRI->getSpillAlignment(RC);<br class="">
<br class="">
unsigned SI = Scavenged.size(), Diff = std::numeric_limits<unsigned>::max();<br class="">
int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();<br class="">
@@ -437,39 +488,72 @@ unsigned RegScavenger::scavengeRegister(<br class="">
}<br class="">
<br class="">
// Avoid infinite regress<br class="">
- Scavenged[SI].Reg = SReg;<br class="">
+ Scavenged[SI].Reg = Reg;<br class="">
<br class="">
// If the target knows how to save/restore the register, let it do so;<br class="">
// otherwise, use the emergency stack spill slot.<br class="">
- if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {<br class="">
- // Spill the scavenged register before I.<br class="">
+ if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {<br class="">
+ // Spill the scavenged register before \p Before.<br class="">
int FI = Scavenged[SI].FrameIndex;<br class="">
if (FI < FIB || FI >= FIE) {<br class="">
std::string Msg = std::string("Error while trying to spill ") +<br class="">
- TRI->getName(SReg) + " from class " + TRI->getRegClassName(RC) +<br class="">
+ TRI->getName(Reg) + " from class " + TRI->getRegClassName(&RC) +<br class="">
": Cannot scavenge register without an emergency spill slot!";<br class="">
report_fatal_error(Msg.c_str());<br class="">
}<br class="">
- TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,<br class="">
- RC, TRI);<br class="">
- MachineBasicBlock::iterator II = std::prev(I);<br class="">
+ TII->storeRegToStackSlot(*MBB, Before, Reg, true, Scavenged[SI].FrameIndex,<br class="">
+ &RC, TRI);<br class="">
+ MachineBasicBlock::iterator II = std::prev(Before);<br class="">
<br class="">
unsigned FIOperandNum = getFrameIndexOperandNum(*II);<br class="">
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);<br class="">
<br class="">
// Restore the scavenged register before its use (or first terminator).<br class="">
- TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,<br class="">
- RC, TRI);<br class="">
+ TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,<br class="">
+ &RC, TRI);<br class="">
II = std::prev(UseMI);<br class="">
<br class="">
FIOperandNum = getFrameIndexOperandNum(*II);<br class="">
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);<br class="">
}<br class="">
+ return Scavenged[SI];<br class="">
+}<br class="">
+<br class="">
+unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,<br class="">
+ MachineBasicBlock::iterator I,<br class="">
+ int SPAdj) {<br class="">
+ MachineInstr &MI = *I;<br class="">
+ const MachineFunction &MF = *MI.getParent()->getParent();<br class="">
+ // Consider all allocatable registers in the register class initially<br class="">
+ BitVector Candidates = TRI->getAllocatableSet(MF, RC);<br class="">
+<br class="">
+ // Exclude all the registers being used by the instruction.<br class="">
+ for (const MachineOperand &MO : MI.operands()) {<br class="">
+ if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&<br class="">
+ !TargetRegisterInfo::isVirtualRegister(MO.getReg()))<br class="">
+ for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)<br class="">
+ Candidates.reset(*AI);<br class="">
+ }<br class="">
+<br class="">
+ // Try to find a register that's unused if there is one, as then we won't<br class="">
+ // have to spill.<br class="">
+ BitVector Available = getRegsAvailable(RC);<br class="">
+ Available &= Candidates;<br class="">
+ if (Available.any())<br class="">
+ Candidates = Available;<br class="">
+<br class="">
+ // Find the register whose use is furthest away.<br class="">
+ MachineBasicBlock::iterator UseMI;<br class="">
+ unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);<br class="">
<br class="">
- Scavenged[SI].Restore = &*std::prev(UseMI);<br class="">
+ // If we found an unused register there is no reason to spill it.<br class="">
+ if (!isRegUsed(SReg)) {<br class="">
+ DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n");<br class="">
+ return SReg;<br class="">
+ }<br class="">
<br class="">
- // Doing this here leads to infinite regress.<br class="">
- // Scavenged[SI].Reg = SReg;<br class="">
+ ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);<br class="">
+ Scavenged.Restore = &*std::prev(UseMI);<br class="">
<br class="">
DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<<br class="">
"\n");<br class="">
@@ -477,85 +561,200 @@ unsigned RegScavenger::scavengeRegister(<br class="">
return SReg;<br class="">
}<br class="">
<br class="">
-void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {<br class="">
- // FIXME: Iterating over the instruction stream is unnecessary. We can simply<br class="">
- // iterate over the vreg use list, which at this point only contains machine<br class="">
- // operands for which eliminateFrameIndex need a new scratch reg.<br class="">
+unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,<br class="">
+ MachineBasicBlock::iterator To,<br class="">
+ bool RestoreAfter, int SPAdj) {<br class="">
+ const MachineBasicBlock &MBB = *To->getParent();<br class="">
+ const MachineFunction &MF = *MBB.getParent();<br class="">
+ // Consider all allocatable registers in the register class initially<br class="">
+ BitVector Candidates = TRI->getAllocatableSet(MF, &RC);<br class="">
<br class="">
- // Run through the instructions and find any virtual registers.<br class="">
- MachineRegisterInfo &MRI = MF.getRegInfo();<br class="">
- for (MachineBasicBlock &MBB : MF) {<br class="">
- RS.enterBasicBlock(MBB);<br class="">
+ // Try to find a register that's unused if there is one, as then we won't<br class="">
+ // have to spill.<br class="">
+ BitVector Available = getRegsAvailable(&RC);<br class="">
<br class="">
- int SPAdj = 0;<br class="">
+ // Find the register whose use is furthest away.<br class="">
+ MachineBasicBlock::iterator UseMI;<br class="">
+ std::pair<unsigned, MachineBasicBlock::iterator> P =<br class="">
+ findSurvivorBackwards(*TRI, MBBI, To, Available, Candidates);<br class="">
+ unsigned Reg = P.first;<br class="">
+ MachineBasicBlock::iterator SpillBefore = P.second;<br class="">
+ assert(Reg != 0 && "No register left to scavenge!");<br class="">
+ // Found an available register?<br class="">
+ if (SpillBefore != MBB.end()) {<br class="">
+ MachineBasicBlock::iterator ReloadAfter =<br class="">
+ RestoreAfter ? std::next(MBBI) : MBBI;<br class="">
+ MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);<br class="">
+ DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');<br class="">
+ ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);<br class="">
+ Scavenged.Restore = &*std::prev(SpillBefore);<br class="">
+ LiveUnits.removeReg(Reg);<br class="">
+ DEBUG(dbgs() << "Scavenged register with spill: " << PrintReg(Reg, TRI)<br class="">
+ << " until " << *SpillBefore);<br class="">
+ } else {<br class="">
+ DEBUG(dbgs() << "Scavenged free register: " << PrintReg(Reg, TRI) << '\n');<br class="">
+ }<br class="">
+ return Reg;<br class="">
+}<br class="">
<br class="">
- // The instruction stream may change in the loop, so check MBB.end()<br class="">
- // directly.<br class="">
- for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {<br class="">
- // We might end up here again with a NULL iterator if we scavenged a<br class="">
- // register for which we inserted spill code for definition by what was<br class="">
- // originally the first instruction in MBB.<br class="">
- if (I == MachineBasicBlock::iterator(nullptr))<br class="">
- I = MBB.begin();<br class="">
-<br class="">
- const MachineInstr &MI = *I;<br class="">
- MachineBasicBlock::iterator J = std::next(I);<br class="">
- MachineBasicBlock::iterator P =<br class="">
- I == MBB.begin() ? MachineBasicBlock::iterator(nullptr)<br class="">
- : std::prev(I);<br class="">
-<br class="">
- // RS should process this instruction before we might scavenge at this<br class="">
- // location. This is because we might be replacing a virtual register<br class="">
- // defined by this instruction, and if so, registers killed by this<br class="">
- // instruction are available, and defined registers are not.<br class="">
- RS.forward(I);<br class="">
+/// Allocate a register for the virtual register \p VReg. The last use of<br class="">
+/// \p VReg is around the current position of the register scavenger \p RS.<br class="">
+/// \p ReserveAfter controls whether the scavenged register needs to be reserved<br class="">
+/// after the current instruction, otherwise it will only be reserved before the<br class="">
+/// current instruction.<br class="">
+static unsigned scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,<br class="">
+ unsigned VReg, bool ReserveAfter) {<br class="">
+ const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();<br class="">
+#ifndef NDEBUG<br class="">
+ // Verify that all definitions and uses are in the same basic block.<br class="">
+ const MachineBasicBlock *CommonMBB = nullptr;<br class="">
+ // Real definition for the reg, re-definitions are not considered.<br class="">
+ const MachineInstr *RealDef = nullptr;<br class="">
+ for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) {<br class="">
+ MachineBasicBlock *MBB = MO.getParent()->getParent();<br class="">
+ if (CommonMBB == nullptr)<br class="">
+ CommonMBB = MBB;<br class="">
+ assert(MBB == CommonMBB && "All defs+uses must be in the same basic block");<br class="">
+ if (MO.isDef()) {<br class="">
+ const MachineInstr &MI = *MO.getParent();<br class="">
+ if (!MI.readsRegister(VReg, &TRI)) {<br class="">
+ assert(!RealDef || RealDef == &MI &&<br class="">
+ "Can have at most one definition which is not a redefinition");<br class="">
+ RealDef = &MI;<br class="">
+ }<br class="">
+ }<br class="">
+ }<br class="">
+ assert(RealDef != nullptr && "Must have at least 1 Def");<br class="">
+#endif<br class="">
+<br class="">
+ // We should only have one definition of the register. However to accomodate<br class="">
+ // the requirements of two address code we also allow definitions in<br class="">
+ // subsequent instructions provided they also read the register. That way<br class="">
+ // we get a single contiguous lifetime.<br class="">
+ //<br class="">
+ // Definitions in MRI.def_begin() are unordered, search for the first.<br class="">
+ MachineRegisterInfo::def_iterator FirstDef =<br class="">
+ std::find_if(MRI.def_begin(VReg), MRI.def_end(),<br class="">
+ [VReg, &TRI](const MachineOperand &MO) {<br class="">
+ return !MO.getParent()->readsRegister(VReg, &TRI);<br class="">
+ });<br class="">
+ assert(FirstDef != MRI.def_end() &&<br class="">
+ "Must have one definition that does not redefine vreg");<br class="">
+ MachineInstr &DefMI = *FirstDef->getParent();<br class="">
+<br class="">
+ // The register scavenger will report a free register inserting an emergency<br class="">
+ // spill/reload if necessary.<br class="">
+ int SPAdj = 0;<br class="">
+ const TargetRegisterClass &RC = *MRI.getRegClass(VReg);<br class="">
+ unsigned SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),<br class="">
+ ReserveAfter, SPAdj);<br class="">
+ MRI.replaceRegWith(VReg, SReg);<br class="">
+ ++NumScavengedRegs;<br class="">
+ return SReg;<br class="">
+}<br class="">
<br class="">
- for (const MachineOperand &MO : MI.operands()) {<br class="">
+/// Allocate (scavenge) vregs inside a single basic block.<br class="">
+/// Returns true if the target spill callback created new vregs and a 2nd pass<br class="">
+/// is necessary.<br class="">
+static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI,<br class="">
+ RegScavenger &RS,<br class="">
+ MachineBasicBlock &MBB) {<br class="">
+ const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();<br class="">
+ RS.enterBasicBlockEnd(MBB);<br class="">
+<br class="">
+ unsigned InitialNumVirtRegs = MRI.getNumVirtRegs();<br class="">
+ bool NextInstructionReadsVReg = false;<br class="">
+ for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ) {<br class="">
+ --I;<br class="">
+ // Move RegScavenger to the position between *I and *std::next(I).<br class="">
+ RS.backward(I);<br class="">
+<br class="">
+ // Look for unassigned vregs in the uses of *std::next(I).<br class="">
+ if (NextInstructionReadsVReg) {<br class="">
+ MachineBasicBlock::iterator N = std::next(I);<br class="">
+ const MachineInstr &NMI = *N;<br class="">
+ for (const MachineOperand &MO : NMI.operands()) {<br class="">
if (!MO.isReg())<br class="">
continue;<br class="">
unsigned Reg = MO.getReg();<br class="">
- if (!TargetRegisterInfo::isVirtualRegister(Reg))<br class="">
+ // We only care about virtual registers and ignore virtual registers<br class="">
+ // created by the target callbacks in the process (those will be handled<br class="">
+ // in a scavenging round).<br class="">
+ if (!TargetRegisterInfo::isVirtualRegister(Reg) ||<br class="">
+ TargetRegisterInfo::virtReg2Index(Reg) >= InitialNumVirtRegs)<br class="">
continue;<br class="">
+ if (!MO.readsReg())<br class="">
+ continue;<br class="">
+<br class="">
+ unsigned SReg = scavengeVReg(MRI, RS, Reg, true);<br class="">
+ N->addRegisterKilled(SReg, &TRI, false);<br class="">
+ RS.setRegUsed(SReg);<br class="">
+ }<br class="">
+ }<br class="">
+<br class="">
+ // Look for unassigned vregs in the defs of *I.<br class="">
+ NextInstructionReadsVReg = false;<br class="">
+ const MachineInstr &MI = *I;<br class="">
+ for (const MachineOperand &MO : MI.operands()) {<br class="">
+ if (!MO.isReg())<br class="">
+ continue;<br class="">
+ unsigned Reg = MO.getReg();<br class="">
+ // Only vregs, no newly created vregs (see above).<br class="">
+ if (!TargetRegisterInfo::isVirtualRegister(Reg) ||<br class="">
+ TargetRegisterInfo::virtReg2Index(Reg) >= InitialNumVirtRegs)<br class="">
+ continue;<br class="">
+ // We have to look at all operands anyway so we can precalculate here<br class="">
+ // whether there is a reading operand. This allows use to skip the use<br class="">
+ // step in the next iteration if there was none.<br class="">
+ assert(!MO.isInternalRead() && "Cannot assign inside bundles");<br class="">
+ assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");<br class="">
+ if (MO.readsReg()) {<br class="">
+ NextInstructionReadsVReg = true;<br class="">
+ }<br class="">
+ if (MO.isDef()) {<br class="">
+ unsigned SReg = scavengeVReg(MRI, RS, Reg, false);<br class="">
+ I->addRegisterDead(SReg, &TRI, false);<br class="">
+ }<br class="">
+ }<br class="">
+ }<br class="">
+#ifndef NDEBUG<br class="">
+ for (const MachineOperand &MO : MBB.front().operands()) {<br class="">
+ if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))<br class="">
+ continue;<br class="">
+ assert(!MO.isInternalRead() && "Cannot assign inside bundles");<br class="">
+ assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");<br class="">
+ assert(!MO.readsReg() && "Vreg use in first instruction not allowed");<br class="">
+ }<br class="">
+#endif<br class="">
+<br class="">
+ return MRI.getNumVirtRegs() != InitialNumVirtRegs;<br class="">
+}<br class="">
+<br class="">
+void llvm::scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS) {<br class="">
+ // FIXME: Iterating over the instruction stream is unnecessary. We can simply<br class="">
+ // iterate over the vreg use list, which at this point only contains machine<br class="">
+ // operands for which eliminateFrameIndex need a new scratch reg.<br class="">
+ MachineRegisterInfo &MRI = MF.getRegInfo();<br class="">
+ // Shortcut.<br class="">
+ if (MRI.getNumVirtRegs() == 0) {<br class="">
+ MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);<br class="">
+ return;<br class="">
+ }<br class="">
+<br class="">
+ // Run through the instructions and find any virtual registers.<br class="">
+ for (MachineBasicBlock &MBB : MF) {<br class="">
+ if (MBB.empty())<br class="">
+ continue;<br class="">
<br class="">
- // When we first encounter a new virtual register, it<br class="">
- // must be a definition.<br class="">
- assert(MO.isDef() && "frame index virtual missing def!");<br class="">
- // Scavenge a new scratch register<br class="">
- const TargetRegisterClass *RC = MRI.getRegClass(Reg);<br class="">
- unsigned ScratchReg = RS.scavengeRegister(RC, J, SPAdj);<br class="">
-<br class="">
- ++NumScavengedRegs;<br class="">
-<br class="">
- // Replace this reference to the virtual register with the<br class="">
- // scratch register.<br class="">
- assert(ScratchReg && "Missing scratch register!");<br class="">
- MRI.replaceRegWith(Reg, ScratchReg);<br class="">
-<br class="">
- // Because this instruction was processed by the RS before this<br class="">
- // register was allocated, make sure that the RS now records the<br class="">
- // register as being used.<br class="">
- RS.setRegUsed(ScratchReg);<br class="">
- }<br class="">
-<br class="">
- // If the scavenger needed to use one of its spill slots, the<br class="">
- // spill code will have been inserted in between I and J. This is a<br class="">
- // problem because we need the spill code before I: Move I to just<br class="">
- // prior to J.<br class="">
- if (I != std::prev(J)) {<br class="">
- MBB.splice(J, &MBB, I);<br class="">
-<br class="">
- // Before we move I, we need to prepare the RS to visit I again.<br class="">
- // Specifically, RS will assert if it sees uses of registers that<br class="">
- // it believes are undefined. Because we have already processed<br class="">
- // register kills in I, when it visits I again, it will believe that<br class="">
- // those registers are undefined. To avoid this situation, unprocess<br class="">
- // the instruction I.<br class="">
- assert(RS.getCurrentPosition() == I &&<br class="">
- "The register scavenger has an unexpected position");<br class="">
- I = P;<br class="">
- RS.unprocess(P);<br class="">
- } else<br class="">
- ++I;<br class="">
+ bool Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);<br class="">
+ if (Again) {<br class="">
+ DEBUG(dbgs() << "Warning: Required two scavenging passes for block "<br class="">
+ << MBB.getName() << '\n');<br class="">
+ Again = scavengeFrameVirtualRegsInBlock(MRI, RS, MBB);<br class="">
+ // The target required a 2nd run (because it created new vregs while<br class="">
+ // spilling). Refuse to do another pass to keep compiletime in check.<br class="">
+ if (Again)<br class="">
+ report_fatal_error("Incomplete scavenging after 2nd pass");<br class="">
}<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/AArch64/reg-scavenge-frame.mir Thu Jun 15 17:14:55 2017<br class="">
@@ -45,8 +45,42 @@ body: |<br class="">
%fp = COPY %xzr<br class="">
%lr = COPY %xzr<br class="">
ST1Fourv1d killed %d16_d17_d18_d19, %stack.0 :: (store 32 into %stack.0, align 8)<br class="">
-# CHECK: STRXui killed %[[SCAVREG:x[0-9]+|fp|lr]], %sp, [[SPOFFSET:[0-9]+]] :: (store 8 into %stack.1)<br class="">
-# CHECK-NEXT: %[[SCAVREG]] = ADDXri %sp, {{[0-9]+}}, 0<br class="">
-# CHECK-NEXT: ST1Fourv1d killed %d16_d17_d18_d19, killed %[[SCAVREG]] :: (store 32 into %stack.0, align 8)<br class="">
-# CHECK-NEXT: %[[SCAVREG]] = LDRXui %sp, [[SPOFFSET]] :: (load 8 from %stack.1)<br class="">
+ ; CHECK: STRXui killed %[[SCAVREG:x[0-9]+|fp|lr]], %sp, [[SPOFFSET:[0-9]+]] :: (store 8 into %stack.1)<br class="">
+ ; CHECK-NEXT: %[[SCAVREG]] = ADDXri %sp, {{[0-9]+}}, 0<br class="">
+ ; CHECK-NEXT: ST1Fourv1d killed %d16_d17_d18_d19, killed %[[SCAVREG]] :: (store 32 into %stack.0, align 8)<br class="">
+ ; CHECK-NEXT: %[[SCAVREG]] = LDRXui %sp, [[SPOFFSET]] :: (load 8 from %stack.1)<br class="">
+<br class="">
+ HINT 0, implicit %x0<br class="">
+ HINT 0, implicit %x1<br class="">
+ HINT 0, implicit %x2<br class="">
+ HINT 0, implicit %x3<br class="">
+ HINT 0, implicit %x4<br class="">
+ HINT 0, implicit %x5<br class="">
+ HINT 0, implicit %x6<br class="">
+ HINT 0, implicit %x7<br class="">
+ HINT 0, implicit %x8<br class="">
+ HINT 0, implicit %x9<br class="">
+ HINT 0, implicit %x10<br class="">
+ HINT 0, implicit %x11<br class="">
+ HINT 0, implicit %x12<br class="">
+ HINT 0, implicit %x13<br class="">
+ HINT 0, implicit %x14<br class="">
+ HINT 0, implicit %x15<br class="">
+ HINT 0, implicit %x16<br class="">
+ HINT 0, implicit %x17<br class="">
+ HINT 0, implicit %x18<br class="">
+ HINT 0, implicit %x19<br class="">
+ HINT 0, implicit %x20<br class="">
+ HINT 0, implicit %x21<br class="">
+ HINT 0, implicit %x22<br class="">
+ HINT 0, implicit %x23<br class="">
+ HINT 0, implicit %x24<br class="">
+ HINT 0, implicit %x25<br class="">
+ HINT 0, implicit %x26<br class="">
+ HINT 0, implicit %x27<br class="">
+ HINT 0, implicit %x28<br class="">
+ HINT 0, implicit %fp<br class="">
+ HINT 0, implicit %lr<br class="">
+<br class="">
+ RET_ReallyLR<br class="">
...<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll Thu Jun 15 17:14:55 2017<br class="">
@@ -39,44 +39,49 @@ define amdgpu_kernel void @max_9_sgprs(i<br class="">
; features when the number of registers is frozen), this ends up using<br class="">
; more than expected.<br class="">
<br class="">
-; ALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs:<br class="">
-; TOSGPR: SGPRBlocks: 1<br class="">
-; TOSGPR: NumSGPRsForWavesPerEU: 16<br class="">
-<br class="">
-; TOSMEM: s_mov_b64 s[10:11], s[2:3]<br class="">
-; TOSMEM: s_mov_b64 s[8:9], s[0:1]<br class="">
-; TOSMEM: s_mov_b32 s7, s13<br class="">
-<br class="">
-; TOSMEM: SGPRBlocks: 1<br class="">
-; TOSMEM: NumSGPRsForWavesPerEU: 16<br class="">
-define amdgpu_kernel void @max_12_sgprs_14_input_sgprs(i32 addrspace(1)* %out1,<br class="">
- i32 addrspace(1)* %out2,<br class="">
- i32 addrspace(1)* %out3,<br class="">
- i32 addrspace(1)* %out4,<br class="">
- i32 %one, i32 %two, i32 %three, i32 %four) #2 {<br class="">
- %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()<br class="">
- %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()<br class="">
- %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()<br class="">
- %x.3 = call i64 @<a href="http://llvm.amdgcn.dispatch.id/" rel="noreferrer" target="_blank" class="">llvm.amdgcn.dispatch.id</a>()<br class="">
- %x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()<br class="">
- %x.5 = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr()<br class="">
- store volatile i32 0, i32* undef<br class="">
- br label %stores<br class="">
-<br class="">
-stores:<br class="">
- store volatile i32 %x.0, i32 addrspace(1)* undef<br class="">
- store volatile i32 %x.0, i32 addrspace(1)* undef<br class="">
- store volatile i32 %x.0, i32 addrspace(1)* undef<br class="">
- store volatile i64 %x.3, i64 addrspace(1)* undef<br class="">
- store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef<br class="">
- store volatile i8 addrspace(2)* %x.5, i8 addrspace(2)* addrspace(1)* undef<br class="">
-<br class="">
- store i32 %one, i32 addrspace(1)* %out1<br class="">
- store i32 %two, i32 addrspace(1)* %out2<br class="">
- store i32 %three, i32 addrspace(1)* %out3<br class="">
- store i32 %four, i32 addrspace(1)* %out4<br class="">
- ret void<br class="">
-}<br class="">
+; XALL-LABEL: {{^}}max_12_sgprs_14_input_sgprs:<br class="">
+; XTOSGPR: SGPRBlocks: 1<br class="">
+; XTOSGPR: NumSGPRsForWavesPerEU: 16<br class="">
+<br class="">
+; XTOSMEM: s_mov_b64 s[10:11], s[2:3]<br class="">
+; XTOSMEM: s_mov_b64 s[8:9], s[0:1]<br class="">
+; XTOSMEM: s_mov_b32 s7, s13<br class="">
+<br class="">
+; XTOSMEM: SGPRBlocks: 1<br class="">
+; XTOSMEM: NumSGPRsForWavesPerEU: 16<br class="">
+;<br class="">
+; This test case is disabled: When calculating the spillslot addresses AMDGPU<br class="">
+; creates an extra vreg to save/restore m0 which in a point of maximum register<br class="">
+; pressure would trigger an endless loop; the compiler aborts earlier with<br class="">
+; "Incomplete scavenging after 2nd pass" in practice.<br class="">
+;define amdgpu_kernel void @max_12_sgprs_14_input_sgprs(i32 addrspace(1)* %out1,<br class="">
+; i32 addrspace(1)* %out2,<br class="">
+; i32 addrspace(1)* %out3,<br class="">
+; i32 addrspace(1)* %out4,<br class="">
+; i32 %one, i32 %two, i32 %three, i32 %four) #2 {<br class="">
+; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()<br class="">
+; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()<br class="">
+; %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()<br class="">
+; %x.3 = call i64 @<a href="http://llvm.amdgcn.dispatch.id/" rel="noreferrer" target="_blank" class="">llvm.amdgcn.dispatch.id</a>()<br class="">
+; %x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()<br class="">
+; %x.5 = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr()<br class="">
+; store volatile i32 0, i32* undef<br class="">
+; br label %stores<br class="">
+;<br class="">
+;stores:<br class="">
+; store volatile i32 %x.0, i32 addrspace(1)* undef<br class="">
+; store volatile i32 %x.0, i32 addrspace(1)* undef<br class="">
+; store volatile i32 %x.0, i32 addrspace(1)* undef<br class="">
+; store volatile i64 %x.3, i64 addrspace(1)* undef<br class="">
+; store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef<br class="">
+; store volatile i8 addrspace(2)* %x.5, i8 addrspace(2)* addrspace(1)* undef<br class="">
+;<br class="">
+; store i32 %one, i32 addrspace(1)* %out1<br class="">
+; store i32 %two, i32 addrspace(1)* %out2<br class="">
+; store i32 %three, i32 addrspace(1)* %out3<br class="">
+; store i32 %four, i32 addrspace(1)* %out4<br class="">
+; ret void<br class="">
+;}<br class="">
<br class="">
; The following test is commented out for now; <a href="http://llvm.org/PR31230" rel="noreferrer" target="_blank" class="">http://llvm.org/PR31230</a><br class="">
; XALL-LABEL: max_12_sgprs_12_input_sgprs{{$}}<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll Thu Jun 15 17:14:55 2017<br class="">
@@ -12,8 +12,8 @@ declare void @llvm.dbg.declare(metadata,<br class="">
; CHECK: DebugProps:<br class="">
; CHECK: DebuggerABIVersion: [ 1, 0 ]<br class="">
; CHECK: ReservedNumVGPRs: 4<br class="">
-; GFX700: ReservedFirstVGPR: 11<br class="">
-; GFX800: ReservedFirstVGPR: 11<br class="">
+; GFX700: ReservedFirstVGPR: 8<br class="">
+; GFX800: ReservedFirstVGPR: 8<br class="">
; GFX9: ReservedFirstVGPR: 14<br class="">
; CHECK: PrivateSegmentBufferSGPR: 0<br class="">
; CHECK: WavefrontPrivateSegmentOffsetSGPR: 11<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll Thu Jun 15 17:14:55 2017<br class="">
@@ -22,9 +22,9 @@ define void @func_mov_fi_i32() #0 {<br class="">
<br class="">
; GCN-LABEL: {{^}}func_add_constant_to_fi_i32:<br class="">
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)<br class="">
-; GCN: s_sub_u32 s6, s5, s4<br class="">
-; GCN-NEXT: s_lshr_b32 s6, s6, 6<br class="">
-; GCN-NEXT: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, s6, 4<br class="">
+; GCN: s_sub_u32 vcc_hi, s5, s4<br class="">
+; GCN-NEXT: s_lshr_b32 vcc_hi, vcc_hi, 6<br class="">
+; GCN-NEXT: v_add_i32_e64 v0, {{s\[[0-9]+:[0-9]+\]|vcc}}, vcc_hi, 4<br class="">
; GCN-NEXT: v_add_i32_e32 v0, vcc, 4, v0<br class="">
; GCN-NOT: v_mov<br class="">
; GCN: ds_write_b32 v0, v0<br class="">
@@ -71,8 +71,8 @@ define void @func_load_private_arg_i32_p<br class="">
<br class="">
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr:<br class="">
; GCN: s_waitcnt<br class="">
-; GCN-NEXT: s_sub_u32 s6, s5, s4<br class="">
-; GCN-NEXT: v_lshr_b32_e64 v0, s6, 6<br class="">
+; GCN-NEXT: s_sub_u32 vcc_hi, s5, s4<br class="">
+; GCN-NEXT: v_lshr_b32_e64 v0, vcc_hi, 6<br class="">
; GCN-NEXT: v_add_i32_e32 v0, vcc, 4, v0<br class="">
; GCN-NOT: v_mov<br class="">
; GCN: ds_write_b32 v0, v0<br class="">
@@ -99,8 +99,8 @@ define void @void_func_byval_struct_i8_i<br class="">
}<br class="">
<br class="">
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr_nonentry_block:<br class="">
-; GCN: s_sub_u32 s8, s5, s4<br class="">
-; GCN: v_lshr_b32_e64 v1, s8, 6<br class="">
+; GCN: s_sub_u32 vcc_hi, s5, s4<br class="">
+; GCN: v_lshr_b32_e64 v1, vcc_hi, 6<br class="">
; GCN: s_and_saveexec_b64<br class="">
<br class="">
; GCN: v_add_i32_e32 v0, vcc, 4, v1<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/ARM/alloca-align.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/alloca-align.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/alloca-align.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/ARM/alloca-align.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/alloca-align.ll Thu Jun 15 17:14:55 2017<br class="">
@@ -12,7 +12,7 @@ declare void @bar(i32*, [20000 x i8]* by<br class="">
; And a base pointer getting used.<br class="">
; CHECK: mov r6, sp<br class="">
; Which is passed to the call<br class="">
-; CHECK: add [[REG:r[0-9]+]], r6, #19456<br class="">
+; CHECK: add [[REG:r[0-9]+|lr]], r6, #19456<br class="">
; CHECK: add r0, [[REG]], #536<br class="">
; CHECK: bl bar<br class="">
define void @foo([20000 x i8]* %addr) {<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/execute-only-big-stack-frame.ll Thu Jun 15 17:14:55 2017<br class="">
@@ -10,10 +10,10 @@ define i8 @test_big_stack_frame() {<br class="">
; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}<br class="">
; CHECK-SUBW-ADDW: sub.w sp, sp, #65536<br class="">
; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}<br class="">
-; CHECK-SUBW-ADDW: add.w [[REG1:r[0-9]+]], sp, #255<br class="">
+; CHECK-SUBW-ADDW: add.w [[REG1:r[0-9]+|lr]], sp, #255<br class="">
; CHECK-SUBW-ADDW: add.w {{r[0-9]+}}, [[REG1]], #65280<br class="">
; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}<br class="">
-; CHECK-SUBW-ADDW: add.w lr, sp, #61440<br class="">
+; CHECK-SUBW-ADDW: add.w [[REGX:r[0-9]+|lr]], sp, #61440<br class="">
; CHECK-SUBW-ADDW-NOT: ldr {{r[0-9]+}}, .{{.*}}<br class="">
; CHECK-SUBW-ADDW: add.w sp, sp, #65536<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/fpoffset_overflow.mir Thu Jun 15 17:14:55 2017<br class="">
@@ -3,10 +3,10 @@<br class="">
# This should trigger an emergency spill in the register scavenger because the<br class="">
# frame offset into the large argument is too large.<br class="">
# CHECK-LABEL: name: func0<br class="">
-# CHECK: t2STRi12 killed %r7, %sp, 0, 14, _ :: (store 4 into %stack.0)<br class="">
-# CHECK: %r7 = t2ADDri killed %sp, 4096, 14, _, _<br class="">
-# CHECK: %r11 = t2LDRi12 killed %r7, 36, 14, _ :: (load 4)<br class="">
-# CHECK: %r7 = t2LDRi12 %sp, 0, 14, _ :: (load 4 from %stack.0)<br class="">
+# CHECK: t2STRi12 killed [[SPILLED:%r[0-9]+]], %sp, 0, 14, _ :: (store 4 into %stack.0)<br class="">
+# CHECK: [[SPILLED]] = t2ADDri killed %sp, 4096, 14, _, _<br class="">
+# CHECK: %sp = t2LDRi12 killed [[SPILLED]], 40, 14, _ :: (load 4)<br class="">
+# CHECK: [[SPILLED]] = t2LDRi12 %sp, 0, 14, _ :: (load 4 from %stack.0)<br class="">
name: func0<br class="">
tracksRegLiveness: true<br class="">
fixedStack:<br class="">
@@ -23,6 +23,7 @@ body: |<br class="">
%r4 = IMPLICIT_DEF<br class="">
%r5 = IMPLICIT_DEF<br class="">
%r6 = IMPLICIT_DEF<br class="">
+ %r7 = IMPLICIT_DEF<br class="">
%r8 = IMPLICIT_DEF<br class="">
%r9 = IMPLICIT_DEF<br class="">
%r10 = IMPLICIT_DEF<br class="">
@@ -30,7 +31,7 @@ body: |<br class="">
%r12 = IMPLICIT_DEF<br class="">
%lr = IMPLICIT_DEF<br class="">
<br class="">
- %r11 = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4)<br class="">
+ %sp = t2LDRi12 %fixed-stack.0, 0, 14, _ :: (load 4)<br class="">
<br class="">
KILL %r0<br class="">
KILL %r1<br class="">
@@ -39,6 +40,7 @@ body: |<br class="">
KILL %r4<br class="">
KILL %r5<br class="">
KILL %r6<br class="">
+ KILL %r7<br class="">
KILL %r8<br class="">
KILL %r9<br class="">
KILL %r10<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll Thu Jun 15 17:14:55 2017<br class="">
@@ -1,34 +1,62 @@<br class="">
-; Check that register scavenging spill slot is close to $fp.<br class="">
; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s<br class="">
+; Check that register scavenging spill slot is close to $fp.<br class="">
+target triple="mipsel--"<br class="">
<br class="">
-; CHECK: sw ${{.*}}, 8($sp)<br class="">
-; CHECK: lw ${{.*}}, 8($sp)<br class="">
+@var = external global i32<br class="">
+@ptrvar = external global i8*<br class="">
<br class="">
-define i32 @main(i32 signext %argc, i8** %argv) #0 {<br class="">
-entry:<br class="">
- %retval = alloca i32, align 4<br class="">
- %argc.addr = alloca i32, align 4<br class="">
- %argv.addr = alloca i8**, align 4<br class="">
- %v0 = alloca <16 x i8>, align 16<br class="">
- %.compoundliteral = alloca <16 x i8>, align 16<br class="">
- %v1 = alloca <16 x i8>, align 16<br class="">
- %.compoundliteral1 = alloca <16 x i8>, align 16<br class="">
- %unused_variable = alloca [16384 x i32], align 4<br class="">
- %result = alloca <16 x i8>, align 16<br class="">
- store i32 0, i32* %retval<br class="">
- store i32 %argc, i32* %argc.addr, align 4<br class="">
- store i8** %argv, i8*** %argv.addr, align 4<br class="">
- store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral<br class="">
- %0 = load <16 x i8>, <16 x i8>* %.compoundliteral<br class="">
- store <16 x i8> %0, <16 x i8>* %v0, align 16<br class="">
- store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1<br class="">
- %1 = load <16 x i8>, <16 x i8>* %.compoundliteral1<br class="">
- store <16 x i8> %1, <16 x i8>* %v1, align 16<br class="">
- %2 = load <16 x i8>, <16 x i8>* %v0, align 16<br class="">
- %3 = load <16 x i8>, <16 x i8>* %v1, align 16<br class="">
- %mul = mul <16 x i8> %2, %3<br class="">
- store <16 x i8> %mul, <16 x i8>* %result, align 16<br class="">
- ret i32 0<br class="">
-}<br class="">
+; CHECK-LABEL: func:<br class="">
+define void @func() {<br class="">
+ %space = alloca i32, align 4<br class="">
+ %stackspace = alloca[16384 x i32], align 4<br class="">
+<br class="">
+ ; ensure stackspace is not optimized out<br class="">
+ %stackspace_casted = bitcast [16384 x i32]* %stackspace to i8*<br class="">
+ store volatile i8* %stackspace_casted, i8** @ptrvar<br class="">
<br class="">
-attributes #0 = { noinline "no-frame-pointer-elim"="true" }<br class="">
+ ; Load values to increase register pressure.<br class="">
+ %v0 = load volatile i32, i32* @var<br class="">
+ %v1 = load volatile i32, i32* @var<br class="">
+ %v2 = load volatile i32, i32* @var<br class="">
+ %v3 = load volatile i32, i32* @var<br class="">
+ %v4 = load volatile i32, i32* @var<br class="">
+ %v5 = load volatile i32, i32* @var<br class="">
+ %v6 = load volatile i32, i32* @var<br class="">
+ %v7 = load volatile i32, i32* @var<br class="">
+ %v8 = load volatile i32, i32* @var<br class="">
+ %v9 = load volatile i32, i32* @var<br class="">
+ %v10 = load volatile i32, i32* @var<br class="">
+ %v11 = load volatile i32, i32* @var<br class="">
+ %v12 = load volatile i32, i32* @var<br class="">
+ %v13 = load volatile i32, i32* @var<br class="">
+ %v14 = load volatile i32, i32* @var<br class="">
+ %v15 = load volatile i32, i32* @var<br class="">
+ %v16 = load volatile i32, i32* @var<br class="">
+<br class="">
+ ; Computing a stack-relative values needs an additional register.<br class="">
+ ; We should get an emergency spill/reload for this.<br class="">
+ ; CHECK: sw ${{.*}}, 0($sp)<br class="">
+ ; CHECK: lw ${{.*}}, 0($sp)<br class="">
+ store volatile i32 %v0, i32* %space<br class="">
+<br class="">
+ ; store values so they are used.<br class="">
+ store volatile i32 %v0, i32* @var<br class="">
+ store volatile i32 %v1, i32* @var<br class="">
+ store volatile i32 %v2, i32* @var<br class="">
+ store volatile i32 %v3, i32* @var<br class="">
+ store volatile i32 %v4, i32* @var<br class="">
+ store volatile i32 %v5, i32* @var<br class="">
+ store volatile i32 %v6, i32* @var<br class="">
+ store volatile i32 %v7, i32* @var<br class="">
+ store volatile i32 %v8, i32* @var<br class="">
+ store volatile i32 %v9, i32* @var<br class="">
+ store volatile i32 %v10, i32* @var<br class="">
+ store volatile i32 %v11, i32* @var<br class="">
+ store volatile i32 %v12, i32* @var<br class="">
+ store volatile i32 %v13, i32* @var<br class="">
+ store volatile i32 %v14, i32* @var<br class="">
+ store volatile i32 %v15, i32* @var<br class="">
+ store volatile i32 %v16, i32* @var<br class="">
+<br class="">
+ ret void<br class="">
+}<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/dyn-alloca-aligned.ll Thu Jun 15 17:14:55 2017<br class="">
@@ -25,8 +25,8 @@ entry:<br class="">
<br class="">
; CHECK-DAG: li [[REG1:[0-9]+]], -128<br class="">
; CHECK-DAG: neg [[REG2:[0-9]+]],<br class="">
-; CHECK: and [[REG1]], [[REG2]], [[REG1]]<br class="">
-; CHECK: stdux {{[0-9]+}}, 1, [[REG1]]<br class="">
+; CHECK: and [[REG3:[0-9]+]], [[REG2]], [[REG1]]<br class="">
+; CHECK: stdux {{[0-9]+}}, 1, [[REG3]]<br class="">
<br class="">
; CHECK: blr<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/PowerPC/scavenging.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/scavenging.mir?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/scavenging.mir?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/PowerPC/scavenging.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/PowerPC/scavenging.mir Thu Jun 15 17:14:55 2017<br class="">
@@ -6,7 +6,7 @@ tracksRegLiveness: true<br class="">
body: |<br class="">
bb.0:<br class="">
; CHECK: [[REG0:%r[0-9]+]] = LI 42<br class="">
- ; CHECK-NEXT: NOP implicit [[REG0]]<br class="">
+ ; CHECK-NEXT: NOP implicit killed [[REG0]]<br class="">
%0 : gprc = LI 42<br class="">
NOP implicit %0<br class="">
<br class="">
@@ -14,7 +14,7 @@ body: |<br class="">
; CHECK-NEXT: NOP<br class="">
; CHECK-NEXT: NOP implicit [[REG1]]<br class="">
; CHECK-NEXT: NOP<br class="">
- ; CHECK-NEXT: NOP implicit [[REG1]]<br class="">
+ ; CHECK-NEXT: NOP implicit killed [[REG1]]<br class="">
%1 : gprc = LI 42<br class="">
NOP<br class="">
NOP implicit %1<br class="">
@@ -48,8 +48,8 @@ body: |<br class="">
; CHECK-NOT: %x30 = LI 42<br class="">
; CHECK: [[REG3:%r[0-9]+]] = LI 42<br class="">
; CHECK-NEXT: %x5 = IMPLICIT_DEF<br class="">
- ; CHECK-NEXT: NOP implicit [[REG2]]<br class="">
- ; CHECK-NEXT: NOP implicit [[REG3]]<br class="">
+ ; CHECK-NEXT: NOP implicit killed [[REG2]]<br class="">
+ ; CHECK-NEXT: NOP implicit killed [[REG3]]<br class="">
%3 : gprc = LI 42<br class="">
%x5 = IMPLICIT_DEF<br class="">
NOP implicit %2<br class="">
@@ -110,7 +110,7 @@ body: |<br class="">
<br class="">
; CHECK: STD killed [[SPILLEDREG:%x[0-9]+]]<br class="">
; CHECK: [[SPILLEDREG]] = LI8 42<br class="">
- ; CHECK: NOP implicit [[SPILLEDREG]]<br class="">
+ ; CHECK: NOP implicit killed [[SPILLEDREG]]<br class="">
; CHECK: [[SPILLEDREG]] = LD<br class="">
%0 : g8rc = LI8 42<br class="">
NOP implicit %0<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/Thumb/large-stack.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/large-stack.ll?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/large-stack.ll?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/Thumb/large-stack.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/Thumb/large-stack.ll Thu Jun 15 17:14:55 2017<br class="">
@@ -69,10 +69,10 @@ define i32 @test3() {<br class="">
; CHECK-LABEL: test3:<br class="">
; CHECK: ldr [[TEMP:r[0-7]]],<br class="">
; CHECK: add sp, [[TEMP]]<br class="">
-; CHECK: ldr [[TEMP]],<br class="">
-; CHECK: add [[TEMP]], sp<br class="">
-; CHECK: ldr [[TEMP:r[0-7]]],<br class="">
-; CHECK: add sp, [[TEMP]]<br class="">
+; CHECK: ldr [[TEMP2:r[0-7]]],<br class="">
+; CHECK: add [[TEMP2]], sp<br class="">
+; CHECK: ldr [[TEMP3:r[0-7]]],<br class="">
+; CHECK: add sp, [[TEMP3]]<br class="">
%retval = alloca i32, align 4<br class="">
%tmp = alloca i32, align 4<br class="">
%a = alloca [805306369 x i8], align 16<br class="">
@@ -85,8 +85,8 @@ define i32 @test3_nofpelim() "no-frame-p<br class="">
; CHECK-LABEL: test3_nofpelim:<br class="">
; CHECK: ldr [[TEMP:r[0-7]]],<br class="">
; CHECK: add sp, [[TEMP]]<br class="">
-; CHECK: ldr [[TEMP]],<br class="">
-; CHECK: add [[TEMP]], sp<br class="">
+; CHECK: ldr [[TEMP2:r[0-7]]],<br class="">
+; CHECK: add [[TEMP2]], sp<br class="">
; CHECK: subs r4, r7,<br class="">
; CHECK: mov sp, r4<br class="">
%retval = alloca i32, align 4<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/scavenger.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/scavenger.mir?rev=305516&r1=305515&r2=305516&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/scavenger.mir?rev=305516&r1=305515&r2=305516&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/scavenger.mir (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/scavenger.mir Thu Jun 15 17:14:55 2017<br class="">
@@ -5,6 +5,8 @@ name: func0<br class="">
tracksRegLiveness: true<br class="">
body: |<br class="">
bb.0:<br class="">
+ ; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42<br class="">
+ ; CHECK: %ebp = COPY killed [[REG0]]<br class="">
%0 : gr32 = MOV32ri 42<br class="">
%ebp = COPY %0<br class="">
...<br class="">
@@ -16,7 +18,7 @@ body: |<br class="">
bb.0:<br class="">
; CHECK-NOT: %eax = MOV32ri 42<br class="">
; CHECK: [[REG0:%e[a-z]+]] = MOV32ri 42<br class="">
- ; CHECK: %ebp = COPY [[REG0]]<br class="">
+ ; CHECK: %ebp = COPY killed [[REG0]]<br class="">
%eax = MOV32ri 13<br class="">
%0 : gr32 = MOV32ri 42<br class="">
%ebp = COPY %0<br class="">
@@ -30,25 +32,18 @@ body: |<br class="">
<br class="">
NOOP implicit %ebp<br class="">
<br class="">
- ; CHECK: NOOP implicit [[REG2]]<br class="">
- ; CHECK: NOOP implicit [[REG1]]<br class="">
+ ; CHECK: NOOP implicit killed [[REG2]]<br class="">
+ ; CHECK: NOOP implicit killed [[REG1]]<br class="">
NOOP implicit %2<br class="">
NOOP implicit %1<br class="">
RETQ %eax<br class="">
...<br class="">
---<br class="">
-# Defs without uses are currently broken<br class="">
-#name: func3<br class="">
-#tracksRegLiveness: true<br class="">
-#body: |<br class="">
-# bb.0:<br class="">
-# dead %0 : gr32 = MOV32ri 42<br class="">
-...<br class="">
----<br class="">
-# Uses without defs are currently broken (and honestly not that useful).<br class="">
-#name: func3<br class="">
-#tracksRegLiveness: true<br class="">
-#body: |<br class="">
-# bb.0:<br class="">
-# NOOP undef implicit %0 : gr32<br class="">
+# CHECK-LABEL: name: func3<br class="">
+name: func3<br class="">
+tracksRegLiveness: true<br class="">
+body: |<br class="">
+ bb.0:<br class="">
+ ; CHECK dead {{%e[a-z]+}} = MOV32ri 42<br class="">
+ dead %0 : gr32 = MOV32ri 42<br class="">
...<br class="">
<br class="">
<br class="">
_______________________________________________<br class="">
llvm-commits mailing list<br class="">
<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a><br class="">
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