<div dir="ltr">Any reason we can't use the VT variable being passed into the function?</div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Thu, Jun 15, 2017 at 7:52 AM, Simon Pilgrim via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br>
Date: Thu Jun 15 09:52:30 2017<br>
New Revision: 305472<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=305472&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=305472&view=rev</a><br>
Log:<br>
[X86][AVX2] Fix issue in lowerV8I16GeneralSingleInputVe<wbr>ctorShuffle that was assuming v8i16 vectors<br>
<br>
We can use this with v16i16/v32i16 as well.<br>
<br>
Found during fuzz testing.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-256-v16.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=305472&r1=305471&r2=305472&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86ISelLowering.cpp?rev=<wbr>305472&r1=305471&r2=305472&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp Thu Jun 15 09:52:30 2017<br>
@@ -10889,9 +10889,10 @@ static SDValue lowerV8I16GeneralSingleIn<br>
"We need to be changing the number of flipped inputs!");<br>
int PSHUFHalfMask[] = {0, 1, 2, 3};<br>
std::swap(PSHUFHalfMask[<wbr>FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);<br>
- V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,<br>
- MVT::v8i16, V,<br>
- getV4X86ShuffleImm8ForMask(<wbr>PSHUFHalfMask, DL, DAG));<br>
+ V = DAG.getNode(<br>
+ FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,<br>
+ MVT::getVectorVT(MVT::i16, V.getValueSizeInBits() / 16), V,<br>
+ getV4X86ShuffleImm8ForMask(<wbr>PSHUFHalfMask, DL, DAG));<br>
<br>
for (int &M : Mask)<br>
if (M >= 0 && M == FixIdx)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-256-v16.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-256-v16.ll?rev=305472&r1=305471&r2=305472&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/vector-shuffle-<wbr>256-v16.ll?rev=305472&r1=<wbr>305471&r2=305472&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-256-v16.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-256-v16.ll Thu Jun 15 09:52:30 2017<br>
@@ -1559,6 +1559,24 @@ define <16 x i16> @shuffle_v16i16_17_18_<br>
ret <16 x i16> %shuffle<br>
}<br>
<br>
+define <16 x i16> @shuffle_v16i16_06_07_01_02_<wbr>07_00_04_05_14_15_09_10_15_08_<wbr>12_13(<16 x i16> %a) {<br>
+; AVX1-LABEL: shuffle_v16i16_06_07_01_02_07_<wbr>00_04_05_14_15_09_10_15_08_12_<wbr>13:<br>
+; AVX1: # BB#0:<br>
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1<br>
+; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [12,13,14,15,2,3,4,5,14,15,0,<wbr>1,8,9,10,11]<br>
+; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1<br>
+; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0<br>
+; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
+; AVX1-NEXT: retq<br>
+;<br>
+; AVX2OR512VL-LABEL: shuffle_v16i16_06_07_01_02_07_<wbr>00_04_05_14_15_09_10_15_08_12_<wbr>13:<br>
+; AVX2OR512VL: # BB#0:<br>
+; AVX2OR512VL-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[12,13,14,15,2,3,4,5,14,<wbr>15,0,1,8,9,10,11,28,29,30,31,<wbr>18,19,20,21,30,31,16,17,24,25,<wbr>26,27]<br>
+; AVX2OR512VL-NEXT: retq<br>
+ %1 = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 6, i32 7, i32 1, i32 2, i32 7, i32 0, i32 4, i32 5, i32 14, i32 15, i32 9, i32 10, i32 15, i32 8, i32 12, i32 13><br>
+ ret <16 x i16> %1<br>
+}<br>
+<br>
;<br>
; Shuffle to logical bit shifts<br>
;<br>
<br>
<br>
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</blockquote></div><br></div>