<div dir="ltr">This or related patch breaks ubsan bots. <div>Please fix ASAP.</div><div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/5691/steps/check-llvm%20ubsan/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/5691/steps/check-llvm%20ubsan/logs/stdio</a><br><div><pre style="font-family:"Courier New",courier,monotype,monospace;color:rgb(0,0,0);font-size:medium"><span class="gmail-stdout">/mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp:273:15: runtime error: left shift of negative value -2
#0 0x15bfbf5 in InRange(long, unsigned short, int, int) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp:273:15
#1 0x15bf529 in ImmInRange(llvm::MachineInstr*, (anonymous namespace)::ReduceEntry const&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp:286:8
#2 0x15beddd in (anonymous namespace)::MicroMipsSizeReduce::ReduceADDIUToADDIUR1SP(llvm::MachineInstr*, (anonymous namespace)::ReduceEntry const&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp:347:8
#3 0x15c027a in (anonymous namespace)::MicroMipsSizeReduce::Re</span><span class="gmail-stdout">duceMI(llvm::ilist_iterator<llvm::ilist_detail::node_options<llvm::MachineInstr, true, true, void>, false, false> const&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp:315:9
</span><span class="gmail-stdout"> #4 0x15c0134 in (anonymous namespace)::MicroMipsSizeReduce::ReduceMBB(llvm::MachineBasicBlock&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp:414:17
#5 0x15bffe6 in (anonymous namespace)::MicroMipsSizeReduce::runOnMachineFunction(llvm::MachineFunction&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp:470:17
#6 0x2318d4e in llvm::MachineFunctionPass::runOnFunction(llvm::Function&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/CodeGen/MachineFunctionPass.cpp:62:13
#7 0x2814c20 in llvm::FPPassManager::runOnFunction(llvm::Function&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/IR/LegacyPassManager.cpp:1519:27
#8 0x2814f86 in llvm::FPPassManager::runOnModule(llvm::Module&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/IR/LegacyPassManager.cpp:1540:16
#9 0x281582e in (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/IR/LegacyPassManager.cpp:1596:27
#10 0x28152f1 in llvm::legacy::PassManagerImpl::run(llvm::Module&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/IR/LegacyPassManager.cpp:1699:44
#11 0xa1513a in compileModule(char**, llvm::LLVMContext&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/tools/llc/llc.cpp:609:8
#12 0xa139da in main /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/tools/llc/llc.cpp:350:22
#13 0x7f7f34f6b82f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x2082f)
#14 0x9ec2a8 in _start (/mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm_build_ubsan/bin/llc+0x9ec2a8)</span></pre></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jun 15, 2017 at 2:14 AM, Zoran Jovanovic via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: zjovanovic<br>
Date: Thu Jun 15 04:14:33 2017<br>
New Revision: 305455<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=305455&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=305455&view=rev</a><br>
Log:<br>
[mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP<br>
Author: milena.vujosevic.janicic<br>
Reviewers: sdardis<br>
The patch extends size reduction pass for MicroMIPS.<br>
The following instructions are examined and transformed, if possible:<br>
ADDIU instruction is transformed into 16-bit instruction ADDIUSP<br>
ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP<br>
Differential Revision: <a href="https://reviews.llvm.org/D33887" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D33887</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/Mips/<wbr>micromips-sizereduction/<wbr>micromips-addiur1sp-addiusp.ll<br>
Modified:<br>
llvm/trunk/lib/Target/Mips/<wbr>MicroMipsSizeReduction.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/<wbr>MicroMipsSizeReduction.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsSizeReduction.cpp?rev=305455&r1=305454&r2=305455&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>Mips/MicroMipsSizeReduction.<wbr>cpp?rev=305455&r1=305454&r2=<wbr>305455&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/<wbr>MicroMipsSizeReduction.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/<wbr>MicroMipsSizeReduction.cpp Thu Jun 15 04:14:33 2017<br>
@@ -32,6 +32,8 @@ namespace {<br>
enum OperandTransfer {<br>
OT_NA, ///< Not applicable<br>
OT_OperandsAll, ///< Transfer all operands<br>
+ OT_Operands02, ///< Transfer operands 0 and 2<br>
+ OT_Operand2, ///< Transfer just operand 2<br>
};<br>
<br>
/// Reduction type<br>
@@ -143,14 +145,24 @@ private:<br>
// returns true on success.<br>
static bool ReduceSXtoSX16(MachineInstr *MI, const ReduceEntry &Entry);<br>
<br>
- // Attempts to reduce arithmetic instructions, returns true on success<br>
+ // Attempts to reduce arithmetic instructions, returns true on success.<br>
static bool ReduceArithmeticInstructions(<wbr>MachineInstr *MI,<br>
const ReduceEntry &Entry);<br>
<br>
- // Changes opcode of an instruction<br>
+ // Attempts to reduce ADDIU into ADDIUSP instruction,<br>
+ // returns true on success.<br>
+ static bool ReduceADDIUToADDIUSP(<wbr>MachineInstr *MI,<br>
+ const ReduceEntry &Entry);<br>
+<br>
+ // Attempts to reduce ADDIU into ADDIUR1SP instruction,<br>
+ // returns true on success.<br>
+ static bool ReduceADDIUToADDIUR1SP(<wbr>MachineInstr *MI,<br>
+ const ReduceEntry &Entry);<br>
+<br>
+ // Changes opcode of an instruction.<br>
static bool ReplaceInstruction(<wbr>MachineInstr *MI, const ReduceEntry &Entry);<br>
<br>
- // Table with transformation rules for each instruction<br>
+ // Table with transformation rules for each instruction.<br>
static llvm::SmallVector<ReduceEntry, 16> ReduceTable;<br>
};<br>
<br>
@@ -158,12 +170,20 @@ char MicroMipsSizeReduce::ID = 0;<br>
const MipsInstrInfo *MicroMipsSizeReduce::MipsII;<br>
<br>
// This table must be sorted by WideOpc as a main criterion and<br>
-// ReduceType as a sub-criterion (when wide opcodes are the same)<br>
+// ReduceType as a sub-criterion (when wide opcodes are the same).<br>
llvm::SmallVector<ReduceEntry, 16> MicroMipsSizeReduce::<wbr>ReduceTable = {<br>
<br>
// ReduceType, OpCodes, ReduceFunction,<br>
// OpInfo(TransferOperands),<br>
// ImmField(Shift, LBound, HBound, ImmFieldPosition)<br>
+ {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),<br>
+ ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},<br>
+ {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM),<br>
+ ReduceADDIUToADDIUSP, OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},<br>
+ {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),<br>
+ ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},<br>
+ {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),<br>
+ ReduceADDIUToADDIUSP, OpInfo(OT_Operand2), ImmField(0, 0, 0, 2)},<br>
{RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),<br>
ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),<br>
ImmField(0, 0, 0, -1)},<br>
@@ -174,6 +194,8 @@ llvm::SmallVector<ReduceEntry, 16> Micro<br>
OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},<br>
{RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,<br>
OpInfo(OT_OperandsAll), ImmField(0, -1, 15, 2)},<br>
+ {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),<br>
+ ReduceADDIUToADDIUR1SP, OpInfo(OT_Operands02), ImmField(2, 0, 64, 2)},<br>
{RT_OneInstr, OpCodes(Mips::LHu, Mips::LHU16_MM), ReduceLXUtoLXU16,<br>
OpInfo(OT_OperandsAll), ImmField(1, 0, 16, 2)},<br>
{RT_OneInstr, OpCodes(Mips::LHu_MM, Mips::LHU16_MM), ReduceLXUtoLXU16,<br>
@@ -203,7 +225,7 @@ llvm::SmallVector<ReduceEntry, 16> Micro<br>
};<br>
}<br>
<br>
-// Returns true if the machine operand MO is register SP<br>
+// Returns true if the machine operand MO is register SP.<br>
static bool IsSP(const MachineOperand &MO) {<br>
if (MO.isReg() && ((MO.getReg() == Mips::SP)))<br>
return true;<br>
@@ -225,7 +247,7 @@ static bool isMMSourceRegister(const Mac<br>
}<br>
<br>
// Returns true if the operand Op is an immediate value<br>
-// and writes the immediate value into variable Imm<br>
+// and writes the immediate value into variable Imm.<br>
static bool GetImm(MachineInstr *MI, unsigned Op, int64_t &Imm) {<br>
<br>
if (!MI->getOperand(Op).isImm())<br>
@@ -234,8 +256,17 @@ static bool GetImm(MachineInstr *MI, uns<br>
return true;<br>
}<br>
<br>
+// Returns true if the value is a valid immediate for ADDIUSP.<br>
+static bool AddiuspImmValue(int64_t Value) {<br>
+ int64_t Value2 = Value >> 2;<br>
+ if (Value == (Value2 << 2) &&<br>
+ ((Value2 >= 2 && Value2 <= 257) || (Value2 >= -258 && Value2 <= -3)))<br>
+ return true;<br>
+ return false;<br>
+}<br>
+<br>
// Returns true if the variable Value has the number of least-significant zero<br>
-// bits equal to Shift and if the shifted value is between the bounds<br>
+// bits equal to Shift and if the shifted value is between the bounds.<br>
static bool InRange(int64_t Value, unsigned short Shift, int LBound,<br>
int HBound) {<br>
int64_t Value2 = Value >> Shift;<br>
@@ -244,7 +275,7 @@ static bool InRange(int64_t Value, unsig<br>
return false;<br>
}<br>
<br>
-// Returns true if immediate operand is in range<br>
+// Returns true if immediate operand is in range.<br>
static bool ImmInRange(MachineInstr *MI, const ReduceEntry &Entry) {<br>
<br>
int64_t offset;<br>
@@ -310,6 +341,34 @@ bool MicroMipsSizeReduce::<wbr>ReduceArithmet<br>
return ReplaceInstruction(MI, Entry);<br>
}<br>
<br>
+bool MicroMipsSizeReduce::<wbr>ReduceADDIUToADDIUR1SP(<wbr>MachineInstr *MI,<br>
+ const ReduceEntry &Entry) {<br>
+<br>
+ if (!ImmInRange(MI, Entry))<br>
+ return false;<br>
+<br>
+ if (!isMMThreeBitGPRegister(MI-><wbr>getOperand(0)) || !IsSP(MI->getOperand(1)))<br>
+ return false;<br>
+<br>
+ return ReplaceInstruction(MI, Entry);<br>
+}<br>
+<br>
+bool MicroMipsSizeReduce::<wbr>ReduceADDIUToADDIUSP(<wbr>MachineInstr *MI,<br>
+ const ReduceEntry &Entry) {<br>
+<br>
+ int64_t ImmValue;<br>
+ if (!GetImm(MI, Entry.ImmField(), ImmValue))<br>
+ return false;<br>
+<br>
+ if (!AddiuspImmValue(ImmValue))<br>
+ return false;<br>
+<br>
+ if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))<br>
+ return false;<br>
+<br>
+ return ReplaceInstruction(MI, Entry);<br>
+}<br>
+<br>
bool MicroMipsSizeReduce::<wbr>ReduceLXUtoLXU16(MachineInstr *MI,<br>
const ReduceEntry &Entry) {<br>
<br>
@@ -361,10 +420,36 @@ bool MicroMipsSizeReduce::<wbr>ReduceMBB(Mach<br>
bool MicroMipsSizeReduce::<wbr>ReplaceInstruction(<wbr>MachineInstr *MI,<br>
const ReduceEntry &Entry) {<br>
<br>
- MI->setDesc(MipsII->get(Entry.<wbr>NarrowOpc()));<br>
- DEBUG(dbgs() << "Converted into 16-bit: " << *MI);<br>
- ++NumReduced;<br>
- return true;<br>
+ enum OperandTransfer OpTransfer = Entry.TransferOperands();<br>
+ if (OpTransfer == OT_OperandsAll) {<br>
+ DEBUG(dbgs() << "Converted 32-bit: " << *MI);<br>
+ MI->setDesc(MipsII->get(Entry.<wbr>NarrowOpc()));<br>
+ DEBUG(dbgs() << " to 16-bit: " << *MI);<br>
+ ++NumReduced;<br>
+ return true;<br>
+ } else {<br>
+ MachineBasicBlock &MBB = *MI->getParent();<br>
+ const MCInstrDesc &NewMCID = MipsII->get(Entry.NarrowOpc())<wbr>;<br>
+ DebugLoc dl = MI->getDebugLoc();<br>
+ MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);<br>
+<br>
+ if (OpTransfer == OT_Operand2)<br>
+ MIB.add(MI->getOperand(2));<br>
+ else if (OpTransfer == OT_Operands02) {<br>
+ MIB.add(MI->getOperand(0));<br>
+ MIB.add(MI->getOperand(2));<br>
+ }<br>
+<br>
+ // Transfer MI flags.<br>
+ MIB.setMIFlags(MI->getFlags())<wbr>;<br>
+<br>
+ DEBUG(dbgs() << "Converted 32-bit: " << *MI<br>
+ << " to 16-bit: " << *MIB);<br>
+ MBB.erase_instr(MI);<br>
+ ++NumReduced;<br>
+ return true;<br>
+ }<br>
+ return false;<br>
}<br>
<br>
bool MicroMipsSizeReduce::<wbr>runOnMachineFunction(<wbr>MachineFunction &MF) {<br>
<br>
Added: llvm/trunk/test/CodeGen/Mips/<wbr>micromips-sizereduction/<wbr>micromips-addiur1sp-addiusp.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-sizereduction/micromips-addiur1sp-addiusp.ll?rev=305455&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/micromips-<wbr>sizereduction/micromips-<wbr>addiur1sp-addiusp.ll?rev=<wbr>305455&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>micromips-sizereduction/<wbr>micromips-addiur1sp-addiusp.ll (added)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>micromips-sizereduction/<wbr>micromips-addiur1sp-addiusp.ll Thu Jun 15 04:14:33 2017<br>
@@ -0,0 +1,17 @@<br>
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s<br>
+<br>
+define i32 @f1() {<br>
+entry:<br>
+; CHECK-LABEL: f1:<br>
+; CHECK: addiusp<br>
+; CHECK: addiur1sp<br>
+; CHECK: addiusp<br>
+ %a = alloca [10 x i32], align 4<br>
+ %index = getelementptr inbounds [10 x i32], [10 x i32]* %a, i32 0, i32 0<br>
+ call void @init(i32* %index)<br>
+ %0 = load i32, i32* %index, align 4<br>
+ ret i32 %0<br>
+}<br>
+<br>
+declare void @init(i32*)<br>
+<br>
<br>
<br>
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</blockquote></div><br></div>