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On 2017-06-08 19:46, Friedman, Eli wrote:<br>
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cite="mid:eb2e2caf-452e-e29f-afb8-6228d1d29a87@codeaurora.org">
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<div class="moz-cite-prefix">On 6/8/2017 4:23 AM, Jonas Paulsson
via llvm-commits wrote:<br>
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cite="mid:cb082534-f8fc-ed6e-daa9-d816e365f795@linux.vnet.ibm.com">
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<p>Hi,</p>
<p>SystemZ has some failing tests relating to llvm.trap (with
EXPENSIVE_CHECKS). See <a class="moz-txt-link-freetext"
href="https://bugs.llvm.org/show_bug.cgi?id=33047"
moz-do-not-send="true">https://bugs.llvm.org/show_bug.cgi?id=33047</a>.</p>
<p>One of the problems is that this function<br>
</p>
<pre wrap="">*** IR Dump After Module Verifier ***
define i32 @f0() {
entry:
tail call void @llvm.trap()
ret i32 0
}
never reaches the ret, but still SystemZTargetLowering::LowerReturn() is called. This results in
BB#0: derived from LLVM BB %entry
Trap
%vreg0<def> = LHI 0; GR32Bit:%vreg0
%R2L<def> = COPY %vreg0; GR32Bit:%vreg0
Return %R2L<imp-use>
, and this fails since Trap is a terminator (<tt><font size="2">non-terminator after terminator instruction).
It seems that the call to LowerReturn() should never have been made, since it is unreachable.
</font></tt></pre>
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<br>
Other targets solve this problem by not marking their "TRAP"
instruction as a terminator. That seems much simpler than
special-casing trap instrinsics in SelectionDAGBuilder.<br>
<br>
-Eli<br>
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<br>
As explained on <a class="moz-txt-link-freetext" href="https://bugs.llvm.org/show_bug.cgi?id=33047">https://bugs.llvm.org/show_bug.cgi?id=33047</a>, without
the terminator flag *another test case* fails:<br>
<br>
# After Instruction Selection
<pre class="bz_comment_text" id="comment_text_1"># Machine code for function f1: IsSSA, TracksLiveness
Function Live Ins: %R2D in %vreg0
BB#0: derived from LLVM BB %entry
Live Ins: %R2D
%vreg0<def> = COPY %R2D; GR64Bit:%vreg0
%vreg1<def> = COPY %vreg0:subreg_l32; GR32Bit:%vreg1 GR64Bit:%vreg0
CHI %vreg1<kill>, 15, %CC<imp-def>; GR32Bit:%vreg1
BRC 14, 4, <BB#2>, %CC<imp-use>
J <BB#1>
Successors according to CFG: BB#1(0x00000800 / 0x80000000 = 0.00%) BB#2(0x7ffff800 / 0x80000000 = 100.00%)
BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
Trap
BB#2: derived from LLVM BB %if.end
Predecessors according to CFG: BB#0
%vreg2<def> = LHI 0; GR32Bit:%vreg2
%R2L<def> = COPY %vreg2; GR32Bit:%vreg2
Return %R2L<imp-use>
# End machine code for function f1.
*** Bad machine code: MBB exits via unconditional fall-through but ends with a barrier instruction! ***
- function: f1
- basic block: BB#1 if.then (0x4ee2298)
LLVM ERROR: Found 1 machine code errors.
This fails when Trap is a barrier but not a terminator.
Actually, all tests pass if I remove the barrier flag as well as the terminator flag (and the proposed patch). The only flag then is hasCtrlDep=1, which seems to translate to the
unmodeled side effects flag. Would this be correct?
I btw see that ARM actually has
let isBarrier = 1, isTerminator = 1 in
def TRAP
...
/Jonas
</pre>
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