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Hi Uli,<br>
<br>
<div class="moz-cite-prefix">On 2017-06-09 12:07, Ulrich Weigand
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:OFC7B650A4.B56D1060-ONC125813A.00378A18-C125813A.0037A3BE@notes.na.collabserv.com">
<p><tt><font size="2">Hi Jonas,</font></tt><br>
<br>
<tt><font size="2">> I btw see that ARM actually has<br>
> <br>
> let isBarrier = 1, isTerminator = 1 in<br>
> def TRAP<br>
</font></tt><br>
<tt><font size="2">just as a side comment -- can you try running
the SystemZ</font></tt><br>
<tt><font size="2">tests on ARM and see what happens there? Do
we get the</font></tt><br>
<tt><font size="2">same errors?</font></tt><br>
<br>
<tt><font size="2">Bye,</font></tt><br>
<tt><font size="2">Ulrich</font></tt><br>
<br>
</p>
</blockquote>
<br>
I see that the SystemZ/trap-01.ll test indeed fails the same way on
ARM (with isMachineVerifierClean() changed to return true):<br>
<br>
; Check unconditional traps<br>
define i32 @f0() {<br>
; CHECK-LABEL: f0:<br>
; CHECK-LABEL: .Ltmp0<br>
; CHECK: j .Ltmp0+2<br>
entry:<br>
tail call void @llvm.trap()<br>
ret i32 0<br>
}<br>
<br>
-> <br>
<br>
# After Instruction Selection<br>
# Machine code for function f0: IsSSA, TracksLiveness<br>
<br>
BB#0: derived from LLVM BB %entry<br>
TRAP<br>
%vreg0<def> = MOVi 0, pred:14, pred:%noreg, opt:%noreg;
GPR:%vreg0<br>
%R0<def> = COPY %vreg0; GPR:%vreg0<br>
MOVPCLR pred:14, pred:%noreg, %R0<imp-use><br>
<br>
# End machine code for function f0.<br>
<br>
*** Bad machine code: Non-terminator instruction after the first
terminator ***<br>
- function: f0<br>
- basic block: BB#0 entry (0x4eadbc8)<br>
- instruction: %vreg0<def> = MOVi<br>
First terminator was: TRAP<br>
...<br>
<br>
Interestingly enough, a similar test in ARM/trap.ll looks like:<br>
<br>
define void @t() nounwind {<br>
entry:<br>
call void @llvm.trap()<br>
unreachable<br>
}<br>
<br>
, which of course passes also on SystemZ with or without the barrier
and terminator flag.<br>
<br>
So it is then a question if we need to test ret after trap...<br>
<br>
/Jonas<br>
<br>
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