<div dir="ltr">Hi Mark,<div><br></div><div>I suspect that your change has caused msan and ubsan failures.</div><div><div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/1507/steps/check-llvm%20msan/logs/stdio" target="_blank">http://lab.llvm.org:8011/<wbr>builders/sanitizer-x86_64-<wbr>linux-bootstrap/builds/1507/<wbr>steps/check-llvm%20msan/logs/<wbr>stdio</a></div></div><div><div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/1507/steps/check-llvm%20ubsan/logs/stdio" target="_blank">http://lab.llvm.org:8011/<wbr>builders/sanitizer-x86_64-<wbr>linux-bootstrap/builds/1507/<wbr>steps/check-llvm%20ubsan/logs/<wbr>stdio</a></div></div><div>Can you please take a look?</div><div><br></div><div>Thanks,</div><div>Peter</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jun 2, 2017 at 7:19 AM, Mark Searles via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: msearles<br>
Date: Fri Jun 2 09:19:25 2017<br>
New Revision: 304551<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=304551&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=304551&view=rev</a><br>
Log:<br>
[AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.<br>
<br>
-enable-si-insert-waitcnts=1 becomes the default<br>
-enable-si-insert-waitcnts=0 to use old pass<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D33730" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D33730</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>AMDGPUTargetMachine.cpp<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/basic-branch.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/branch-condition-and.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/branch-relaxation.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/control-flow-<wbr>fastregalloc.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/indirect-addressing-si.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/infinite-loop.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.buffer.<wbr>store.format.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.buffer.<wbr>store.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.ds.swizzle.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.image.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>inv.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>inv.vol.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>wb.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>wb.vol.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.waitcnt.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/multi-divergent-exit-<wbr>region.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/ret_jump.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/si-lower-control-flow-<wbr>unreachable-block.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/smrd-vccz-bug.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/spill-m0.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/valu-i1.ll<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>AMDGPUTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/AMDGPUTargetMachine.<wbr>cpp?rev=304551&r1=304550&r2=<wbr>304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>AMDGPUTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>AMDGPUTargetMachine.cpp Fri Jun 2 09:19:25 2017<br>
@@ -116,7 +116,7 @@ static cl::opt<bool> EnableAMDGPUAliasAn<br>
static cl::opt<bool> EnableSIInsertWaitcntsPass(<br>
"enable-si-insert-waitcnts",<br>
cl::desc("Use new waitcnt insertion pass"),<br>
- cl::init(false));<br>
+ cl::init(true));<br>
<br>
// Option to run late CFG structurizer<br>
static cl::opt<bool> LateCFGStructurize(<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/basic-branch.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/basic-branch.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/basic-branch.<wbr>ll?rev=304551&r1=304550&r2=<wbr>304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/basic-branch.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/basic-branch.ll Fri Jun 2 09:19:25 2017<br>
@@ -34,8 +34,6 @@ end:<br>
; GCN: s_cbranch_vccnz [[END:BB[0-9]+_[0-9]+]]<br>
<br>
; GCN: buffer_store_dword<br>
-; GCNOPT-NEXT: s_waitcnt vmcnt(0) expcnt(0)<br>
-; TODO: This waitcnt can be eliminated<br>
<br>
; GCN: {{^}}[[END]]:<br>
; GCN: s_endpgm<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/branch-condition-and.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/branch-condition-and.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/branch-<wbr>condition-and.ll?rev=304551&<wbr>r1=304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/branch-condition-and.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/branch-condition-and.ll Fri Jun 2 09:19:25 2017<br>
@@ -19,9 +19,8 @@<br>
<br>
; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %bb4<br>
; GCN: ds_write_b32<br>
-; GCN: s_waitcnt<br>
<br>
-; GCN-NEXT: [[BB5]]<br>
+; GCN: [[BB5]]<br>
; GCN: s_or_b64 exec, exec<br>
; GCN-NEXT: s_endpgm<br>
; GCN-NEXT: .Lfunc_end<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/branch-relaxation.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/branch-relaxation.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/branch-<wbr>relaxation.ll?rev=304551&r1=<wbr>304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/branch-relaxation.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/branch-relaxation.ll Fri Jun 2 09:19:25 2017<br>
@@ -223,7 +223,6 @@ bb3:<br>
; GCN-NEXT: [[BB2]]: ; %bb2<br>
; GCN: v_mov_b32_e32 [[BB2_K:v[0-9]+]], 17<br>
; GCN: buffer_store_dword [[BB2_K]]<br>
-; GCN: s_waitcnt vmcnt(0)<br>
<br>
; GCN-NEXT: [[LONG_JUMP1:BB[0-9]+_[0-9]+]]<wbr>: ; %bb2<br>
; GCN-NEXT: s_getpc_b64 vcc<br>
@@ -393,7 +392,6 @@ bb3:<br>
<br>
; GCN-NEXT: ; BB#2: ; %if_uniform<br>
; GCN: buffer_store_dword<br>
-; GCN: s_waitcnt vmcnt(0)<br>
<br>
; GCN-NEXT: [[ENDIF]]: ; %endif<br>
; GCN-NEXT: s_or_b64 exec, exec, [[MASK]]<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/control-flow-<wbr>fastregalloc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/control-flow-<wbr>fastregalloc.ll?rev=304551&r1=<wbr>304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/control-flow-<wbr>fastregalloc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/control-flow-<wbr>fastregalloc.ll Fri Jun 2 09:19:25 2017<br>
@@ -37,22 +37,21 @@<br>
<br>
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[<wbr>ANDEXEC_HI]]{{\]}}<br>
<br>
-; GCN: s_waitcnt vmcnt(0) expcnt(0)<br>
; GCN: mask branch [[ENDIF:BB[0-9]+_[0-9]+]]<br>
<br>
; GCN: {{^}}BB{{[0-9]+}}_1: ; %if<br>
; GCN: s_mov_b32 m0, -1<br>
; GCN: ds_read_b32 [[LOAD1:v[0-9]+]]<br>
+; GCN: s_waitcnt lgkmcnt(0)<br>
; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], s7 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload<br>
-; GCN: s_waitcnt vmcnt(0)<br>
<br>
; Spill val register<br>
; GCN: v_add_i32_e32 [[VAL:v[0-9]+]], vcc, [[LOAD1]], [[RELOAD_LOAD0]]<br>
; GCN: buffer_store_dword [[VAL]], off, s[0:3], s7 offset:[[VAL_OFFSET:[0-9]+]] ; 4-byte Folded Spill<br>
-; GCN: s_waitcnt vmcnt(0)<br>
<br>
; VMEM: [[ENDIF]]:<br>
; Reload and restore exec mask<br>
+; VGPR: s_waitcnt lgkmcnt(0)<br>
; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+<wbr>]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]<br>
; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+<wbr>]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]<br>
<br>
@@ -119,7 +118,6 @@ endif:<br>
<br>
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[<wbr>ANDEXEC_HI]]{{\]}}<br>
<br>
-; GCN: s_waitcnt vmcnt(0) expcnt(0)<br>
; GCN-NEXT: ; mask branch [[END:BB[0-9]+_[0-9]+]]<br>
; GCN-NEXT: s_cbranch_execz [[END]]<br>
<br>
@@ -130,7 +128,6 @@ endif:<br>
; GCN: v_cmp_ne_u32_e32 vcc,<br>
; GCN: s_and_b64 vcc, exec, vcc<br>
; GCN: buffer_store_dword [[VAL_LOOP]], off, s[0:3], s7 offset:[[VAL_SUB_OFFSET:[0-9]+<wbr>]] ; 4-byte Folded Spill<br>
-; GCN: s_waitcnt vmcnt(0) expcnt(0)<br>
; GCN-NEXT: s_cbranch_vccnz [[LOOP]]<br>
<br>
<br>
@@ -197,7 +194,6 @@ end:<br>
; VMEM: buffer_store_dword v[[V_SAVEEXEC_HI]], off, s[0:3], s7 offset:[[SAVEEXEC_HI_OFFSET:[<wbr>0-9]+]] ; 4-byte Folded Spill<br>
<br>
; GCN: s_mov_b64 exec, [[CMP0]]<br>
-; GCN: s_waitcnt vmcnt(0) expcnt(0)<br>
<br>
; FIXME: It makes no sense to put this skip here<br>
; GCN-NEXT: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]]<br>
@@ -235,7 +231,6 @@ end:<br>
<br>
; GCN: buffer_store_dword [[FLOW_VAL]], off, s[0:3], s7 offset:[[RESULT_OFFSET:[0-9]+]<wbr>] ; 4-byte Folded Spill<br>
; GCN: s_xor_b64 exec, exec, s{{\[}}[[FLOW_S_RELOAD_<wbr>SAVEEXEC_LO]]:[[FLOW_S_RELOAD_<wbr>SAVEEXEC_HI]]{{\]}}<br>
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)<br>
; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9]+_[0-9]+]]<br>
; GCN-NEXT: s_cbranch_execz [[ENDIF]]<br>
<br>
@@ -245,14 +240,12 @@ end:<br>
; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], s7 offset:4 ; 4-byte Folded Reload<br>
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]]<br>
; GCN: buffer_store_dword [[ADD]], off, s[0:3], s7 offset:[[RESULT_OFFSET]] ; 4-byte Folded Spill<br>
-; GCN: s_waitcnt vmcnt(0) expcnt(0)<br>
; GCN-NEXT: s_branch [[ENDIF:BB[0-9]+_[0-9]+]]<br>
<br>
; GCN: [[ELSE]]: ; %else<br>
; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], s7 offset:4 ; 4-byte Folded Reload<br>
; GCN: v_subrev_i32_e32 [[SUB:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]]<br>
; GCN: buffer_store_dword [[ADD]], off, s[0:3], s7 offset:[[FLOW_RESULT_OFFSET:[<wbr>0-9]+]] ; 4-byte Folded Spill<br>
-; GCN: s_waitcnt vmcnt(0) expcnt(0)<br>
; GCN-NEXT: s_branch [[FLOW]]<br>
<br>
; GCN: [[ENDIF]]:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/indirect-addressing-si.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/indirect-addressing-si.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/indirect-<wbr>addressing-si.ll?rev=304551&<wbr>r1=304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/indirect-addressing-si.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/indirect-addressing-si.<wbr>ll Fri Jun 2 09:19:25 2017<br>
@@ -120,8 +120,7 @@ entry:<br>
; FIXME: The waitcnt for the argument load can go after the loop<br>
; IDXMODE: s_set_gpr_idx_on 0, src0<br>
; GCN: s_mov_b64 s{{\[[0-9]+:[0-9]+\]}}, exec<br>
-; GCN: s_waitcnt lgkmcnt(0)<br>
-<br>
+; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]:<br>
; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v{{[0-9]+}}<br>
<br>
; MOVREL: s_add_i32 m0, [[READLANE]], 0xfffffe0<br>
@@ -250,8 +249,6 @@ entry:<br>
; GCN-DAG: v_mov_b32_e32 [[VEC_ELT3:v[0-9]+]], 4{{$}}<br>
<br>
; GCN: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]<wbr>], exec<br>
-; GCN: s_waitcnt lgkmcnt(0)<br>
-<br>
; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]:<br>
; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]]<br>
<br>
@@ -290,7 +287,6 @@ entry:<br>
; IDXMODE: s_set_gpr_idx_on 0, dst<br>
<br>
; GCN: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]<wbr>], exec<br>
-; GCN: s_waitcnt lgkmcnt(0)<br>
<br>
; The offset depends on the register that holds the first element of the vector.<br>
; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]]<br>
@@ -330,9 +326,9 @@ entry:<br>
; IDXMODE: s_set_gpr_idx_on 0, src0<br>
<br>
; GCN: s_mov_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec<br>
-; GCN: s_waitcnt vmcnt(0)<br>
<br>
; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]:<br>
+; GCN-NEXT: s_waitcnt vmcnt(0)<br>
; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]<br>
; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]<br>
<br>
@@ -411,6 +407,7 @@ bb2:<br>
; IDXMODE: s_set_gpr_idx_on 0, dst<br>
<br>
; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]:<br>
+; GCN-NEXT: s_waitcnt vmcnt(0)<br>
; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]<br>
; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/infinite-loop.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/infinite-loop.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/infinite-loop.<wbr>ll?rev=304551&r1=304550&r2=<wbr>304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/infinite-loop.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/infinite-loop.ll Fri Jun 2 09:19:25 2017<br>
@@ -4,8 +4,8 @@<br>
; SI-LABEL: {{^}}infinite_loop:<br>
; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x3e7<br>
; SI: BB0_1:<br>
+; SI: s_waitcnt lgkmcnt(0)<br>
; SI: buffer_store_dword [[REG]]<br>
-; SI: s_waitcnt vmcnt(0) expcnt(0)<br>
; SI: s_branch BB0_1<br>
define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) {<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.buffer.<wbr>store.format.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.<wbr>buffer.store.format.ll?rev=<wbr>304551&r1=304550&r2=304551&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.buffer.<wbr>store.format.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.buffer.<wbr>store.format.ll Fri Jun 2 09:19:25 2017<br>
@@ -58,7 +58,7 @@ main_body:<br>
;<br>
;CHECK-LABEL: {{^}}buffer_store_wait:<br>
;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen<br>
-;CHECK: s_waitcnt vmcnt(0) expcnt(0)<br>
+;CHECK: s_waitcnt expcnt(0)<br>
;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen<br>
;CHECK: s_waitcnt vmcnt(0)<br>
;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.buffer.<wbr>store.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.<wbr>buffer.store.ll?rev=304551&r1=<wbr>304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.buffer.<wbr>store.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.buffer.<wbr>store.ll Fri Jun 2 09:19:25 2017<br>
@@ -58,7 +58,7 @@ main_body:<br>
;<br>
;CHECK-LABEL: {{^}}buffer_store_wait:<br>
;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen<br>
-;CHECK: s_waitcnt vmcnt(0) expcnt(0)<br>
+;CHECK: s_waitcnt expcnt(0)<br>
;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen<br>
;CHECK: s_waitcnt vmcnt(0)<br>
;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.ds.swizzle.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.ds.<wbr>swizzle.ll?rev=304551&r1=<wbr>304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.ds.swizzle.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.ds.swizzle.<wbr>ll Fri Jun 2 09:19:25 2017<br>
@@ -5,7 +5,6 @@ declare i32 @llvm.amdgcn.ds.swizzle(i32,<br>
<br>
; FUNC-LABEL: {{^}}ds_swizzle:<br>
; CHECK: ds_swizzle_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:swizzle(BITMASK_PERM,"<wbr>00p11")<br>
-; CHECK: s_waitcnt lgkmcnt<br>
define amdgpu_kernel void @ds_swizzle(i32 addrspace(1)* %out, i32 %src) nounwind {<br>
%swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0<br>
store i32 %swizzle, i32 addrspace(1)* %out, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.image.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.<wbr>image.ll?rev=304551&r1=304550&<wbr>r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.image.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.image.ll Fri Jun 2 09:19:25 2017<br>
@@ -130,7 +130,7 @@ main_body:<br>
;<br>
; GCN-LABEL: {{^}}image_store_wait:<br>
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm<br>
-; GCN: s_waitcnt vmcnt(0) expcnt(0)<br>
+; GCN: s_waitcnt expcnt(0)<br>
; GCN: image_load v[0:3], v4, s[8:15] dmask:0xf unorm<br>
; GCN: s_waitcnt vmcnt(0)<br>
; GCN: image_store v[0:3], v4, s[16:23] dmask:0xf unorm<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>inv.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.s.<wbr>dcache.inv.ll?rev=304551&r1=<wbr>304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>inv.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>inv.ll Fri Jun 2 09:19:25 2017<br>
@@ -20,7 +20,7 @@ define amdgpu_kernel void @test_s_dcache<br>
; GCN: s_waitcnt lgkmcnt(0) ; encoding<br>
define amdgpu_kernel void @test_s_dcache_inv_insert_<wbr>wait() #0 {<br>
call void @llvm.amdgcn.s.dcache.inv()<br>
- call void @llvm.amdgcn.s.waitcnt(i32 0)<br>
+ call void @llvm.amdgcn.s.waitcnt(i32 127)<br>
br label %end<br>
<br>
end:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>inv.vol.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.s.<wbr>dcache.inv.vol.ll?rev=304551&<wbr>r1=304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>inv.vol.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>inv.vol.ll Fri Jun 2 09:19:25 2017<br>
@@ -20,7 +20,7 @@ define amdgpu_kernel void @test_s_dcache<br>
; GCN: s_waitcnt lgkmcnt(0) ; encoding<br>
define amdgpu_kernel void @test_s_dcache_inv_vol_insert_<wbr>wait() #0 {<br>
call void @llvm.amdgcn.s.dcache.inv.vol(<wbr>)<br>
- call void @llvm.amdgcn.s.waitcnt(i32 0)<br>
+ call void @llvm.amdgcn.s.waitcnt(i32 127)<br>
br label %end<br>
<br>
end:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>wb.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.s.<wbr>dcache.wb.ll?rev=304551&r1=<wbr>304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>wb.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>wb.ll Fri Jun 2 09:19:25 2017<br>
@@ -18,7 +18,7 @@ define amdgpu_kernel void @test_s_dcache<br>
; VI: s_waitcnt lgkmcnt(0) ; encoding<br>
define amdgpu_kernel void @test_s_dcache_wb_insert_wait(<wbr>) #0 {<br>
call void @llvm.amdgcn.s.dcache.wb()<br>
- call void @llvm.amdgcn.s.waitcnt(i32 0)<br>
+ call void @llvm.amdgcn.s.waitcnt(i32 127)<br>
br label %end<br>
<br>
end:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>wb.vol.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.s.<wbr>dcache.wb.vol.ll?rev=304551&<wbr>r1=304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>wb.vol.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.dcache.<wbr>wb.vol.ll Fri Jun 2 09:19:25 2017<br>
@@ -18,7 +18,7 @@ define amdgpu_kernel void @test_s_dcache<br>
; VI: s_waitcnt lgkmcnt(0) ; encoding<br>
define amdgpu_kernel void @test_s_dcache_wb_vol_insert_<wbr>wait() #0 {<br>
call void @llvm.amdgcn.s.dcache.wb.vol()<br>
- call void @llvm.amdgcn.s.waitcnt(i32 0)<br>
+ call void @llvm.amdgcn.s.waitcnt(i32 127)<br>
br label %end<br>
<br>
end:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.waitcnt.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/llvm.amdgcn.s.<wbr>waitcnt.ll?rev=304551&r1=<wbr>304550&r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.waitcnt.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/llvm.amdgcn.s.waitcnt.<wbr>ll Fri Jun 2 09:19:25 2017<br>
@@ -18,8 +18,8 @@ define amdgpu_ps void @test1(<8 x i32> i<br>
;<br>
; CHECK-LABEL: {{^}}test2:<br>
; CHECK: image_load<br>
-; CHECK-NOT: s_waitcnt vmcnt(0){{$}}<br>
-; CHECK: s_waitcnt<br>
+; CHECK-NEXT: s_waitcnt<br>
+; CHECK: s_waitcnt vmcnt(0){{$}}<br>
; CHECK-NEXT: image_store<br>
define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, i32 %c) {<br>
%t = call <4 x float> @llvm.amdgcn.image.load.v4f32.<wbr>i32.v8i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/multi-divergent-exit-<wbr>region.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/multi-<wbr>divergent-exit-region.ll?rev=<wbr>304551&r1=304550&r2=304551&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/multi-divergent-exit-<wbr>region.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/multi-divergent-exit-<wbr>region.ll Fri Jun 2 09:19:25 2017<br>
@@ -362,6 +362,7 @@ exit1:<br>
<br>
; GCN: {{^BB[0-9]+_[0-9]+}}: ; %UnifiedReturnBlock<br>
; GCN-NEXT: s_or_b64 exec, exec<br>
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)<br>
; GCN-NEXT: ; return<br>
<br>
define amdgpu_ps float @uniform_branch_to_multi_<wbr>divergent_region_exit_ret_ret_<wbr>return_value(i32 inreg %sgpr, i32 %vgpr) #0 {<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/ret_jump.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ret_jump.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/ret_jump.ll?<wbr>rev=304551&r1=304550&r2=<wbr>304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/ret_jump.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/ret_jump.ll Fri Jun 2 09:19:25 2017<br>
@@ -65,7 +65,6 @@ <a href="http://ret.bb" rel="noreferrer" target="_blank">ret.bb</a>:<br>
<br>
; GCN-NEXT: ; %<a href="http://unreachable.bb" rel="noreferrer" target="_blank">unreachable.bb</a><br>
; GCN: ds_write_b32<br>
-; GCN: s_waitcnt<br>
; GCN: ; divergent unreachable<br>
<br>
; GCN: ; %<a href="http://ret.bb" rel="noreferrer" target="_blank">ret.bb</a><br>
@@ -73,6 +72,7 @@ <a href="http://ret.bb" rel="noreferrer" target="_blank">ret.bb</a>:<br>
<br>
; GCN: ; %UnifiedReturnBlock<br>
; GCN-NEXT: s_or_b64 exec, exec<br>
+; GCN-NEXT: s_waitcnt<br>
; GCN-NEXT: ; return<br>
; GCN-NEXT: .Lfunc_end<br>
define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @uniform_br_nontrivial_ret_<wbr>divergent_br_nontrivial_<wbr>unreachable([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <8 x i32>] addrspace(2)* byval %arg2, i32 addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 inreg %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/si-lower-control-flow-<wbr>unreachable-block.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/si-lower-<wbr>control-flow-unreachable-<wbr>block.ll?rev=304551&r1=304550&<wbr>r2=304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/si-lower-control-flow-<wbr>unreachable-block.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/si-lower-control-flow-<wbr>unreachable-block.ll Fri Jun 2 09:19:25 2017<br>
@@ -9,7 +9,6 @@<br>
; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %unreachable<br>
; GCN: ds_write_b32<br>
; GCN: ; divergent unreachable<br>
-; GCN: s_waitcnt<br>
<br>
; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock<br>
; GCN-NEXT: s_or_b64 exec, exec<br>
@@ -38,7 +37,6 @@ ret:<br>
; GCN-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %unreachable<br>
; GCN: ds_write_b32<br>
; GCN: ; divergent unreachable<br>
-; GCN: s_waitcnt<br>
<br>
; GCN: [[RETURN]]:<br>
; GCN-NEXT: s_or_b64 exec, exec<br>
@@ -66,7 +64,6 @@ unreachable:<br>
<br>
; GCN: [[UNREACHABLE]]:<br>
; GCN: ds_write_b32<br>
-; GCN: s_waitcnt<br>
define amdgpu_kernel void @uniform_lower_control_flow_<wbr>unreachable_terminator(i32 %arg0) #0 {<br>
bb:<br>
%tmp63 = icmp eq i32 %arg0, 32<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/smrd-vccz-bug.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/smrd-vccz-bug.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/smrd-vccz-bug.<wbr>ll?rev=304551&r1=304550&r2=<wbr>304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/smrd-vccz-bug.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/smrd-vccz-bug.ll Fri Jun 2 09:19:25 2017<br>
@@ -5,7 +5,7 @@<br>
; GCN-FUNC: {{^}}vccz_workaround:<br>
; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x0<br>
; GCN: v_cmp_neq_f32_e64 vcc, s{{[0-9]+}}, 0{{$}}<br>
-; GCN: s_waitcnt lgkmcnt(0)<br>
+; VCCZ-BUG: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)<br>
; VCCZ-BUG: s_mov_b64 vcc, vcc<br>
; NOVCCZ-BUG-NOT: s_mov_b64 vcc, vcc<br>
; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]]<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/spill-m0.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-m0.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/spill-m0.ll?<wbr>rev=304551&r1=304550&r2=<wbr>304551&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/spill-m0.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/spill-m0.ll Fri Jun 2 09:19:25 2017<br>
@@ -18,13 +18,11 @@<br>
; TOVMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0<br>
; TOVMEM-DAG: v_mov_b32_e32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]]<br>
; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4 ; 4-byte Folded Spill<br>
-; TOVMEM: s_waitcnt vmcnt(0)<br>
<br>
; TOSMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0<br>
; TOSMEM: s_add_u32 m0, s3, 0x100{{$}}<br>
; TOSMEM-NOT: [[M0_COPY]]<br>
; TOSMEM: s_buffer_store_dword [[M0_COPY]], s{{\[}}[[LO]]:[[HI]]], m0 ; 4-byte Folded Spill<br>
-; TOSMEM: s_waitcnt lgkmcnt(0)<br>
<br>
; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]]<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/valu-i1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/valu-i1.ll?rev=304551&r1=304550&r2=304551&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/valu-i1.ll?rev=<wbr>304551&r1=304550&r2=304551&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/valu-i1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/valu-i1.ll Fri Jun 2 09:19:25 2017<br>
@@ -11,7 +11,6 @@ declare i32 @llvm.amdgcn.workitem.id.x()<br>
; SI: v_cmp_lt_i32_e32 vcc, 0,<br>
; SI-NEXT: s_and_saveexec_b64 [[SAVE1:s\[[0-9]+:[0-9]+\]]], vcc<br>
; SI-NEXT: s_xor_b64 [[SAVE2:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE1]]<br>
-; SI-NEXT: s_waitcnt lgkmcnt(0)<br>
; SI-NEXT: ; mask branch [[FLOW_BB:BB[0-9]+_[0-9]+]]<br>
; SI-NEXT: s_cbranch_execz [[FLOW_BB]]<br>
<br>
@@ -72,7 +71,6 @@ end:<br>
<br>
; SI-NEXT: BB{{[0-9]+_[0-9]+}}:<br>
; SI: buffer_store_dword<br>
-; SI-NEXT: s_waitcnt<br>
<br>
; SI-NEXT: {{^}}[[EXIT]]:<br>
; SI: s_or_b64 exec, exec, [[BR_SREG]]<br>
@@ -101,7 +99,6 @@ exit:<br>
<br>
; SI-NEXT: BB{{[0-9]+_[0-9]+}}:<br>
; SI: buffer_store_dword<br>
-; SI-NEXT: s_waitcnt<br>
<br>
; SI-NEXT: {{^}}[[EXIT]]:<br>
; SI: s_or_b64 exec, exec, [[BR_SREG]]<br>
@@ -132,7 +129,6 @@ exit:<br>
<br>
; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %exit<br>
; SI: ds_write_b32<br>
-; SI: s_waitcnt<br>
<br>
; SI-NEXT: {{^}}[[FLOW]]:<br>
; SI-NEXT: s_or_saveexec_b64<br>
@@ -140,8 +136,8 @@ exit:<br>
; SI-NEXT: ; mask branch [[UNIFIED_RETURN:BB[0-9]+_[0-<wbr>9]+]]<br>
<br>
; SI-NEXT: {{^BB[0-9]+_[0-9]+}}: ; %then<br>
-; SI: buffer_store_dword<br>
-; SI-NEXT: s_waitcnt<br>
+; SI: s_waitcnt<br>
+; SI-NEXT: buffer_store_dword<br>
<br>
; SI-NEXT: {{^}}[[UNIFIED_RETURN]]: ; %UnifiedReturnBlock<br>
; SI: s_or_b64 exec, exec<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature" data-smartmail="gmail_signature"><div dir="ltr">-- <div>Peter</div></div></div>
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