<div dir="ltr">Do you have the segfault link? I commited a fix for the one I saw earlier. Would like to see if it continued after that fix.</div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Sun, May 28, 2017 at 6:48 PM, Zachary Turner via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: zturner<br>
Date: Sun May 28 20:48:53 2017<br>
New Revision: 304121<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=304121&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=304121&view=rev</a><br>
Log:<br>
Revert "[X86] Adding new LLVM TableGen backend that generates the X86 backend memory folding tables."<br>
<br>
This reverts commit 28cb1003507f287726f43c771024a1<wbr>dc102c45fe as well<br>
as all subsequent followups. llvm-tblgen currently segfaults with<br>
this change, and it seems it has been broken on the bots all<br>
day with no fixes in preparation. See, for example:<br>
<br>
<a href="http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/" rel="noreferrer" target="_blank">http://lab.llvm.org:8011/<wbr>builders/clang-x86-windows-<wbr>msvc2015/</a><br>
<br>
Removed:<br>
  llvm/trunk/utils/TableGen/<wbr>X86FoldTablesEmitter.cpp<br>
Modified:<br>
  llvm/trunk/lib/Target/X86/<wbr>CMakeLists.txt<br>
  llvm/trunk/lib/Target/X86/<wbr>X86InstrInfo.cpp<br>
  llvm/trunk/test/CodeGen/X86/<wbr>sse42-intrinsics-fast-isel.ll<br>
  llvm/trunk/test/CodeGen/X86/<wbr>stack-folding-fp-avx1.ll<br>
  llvm/trunk/test/CodeGen/X86/<wbr>vector-sqrt.ll<br>
  llvm/trunk/utils/TableGen/<wbr>CMakeLists.txt<br>
  llvm/trunk/utils/TableGen/<wbr>TableGen.cpp<br>
  llvm/trunk/utils/TableGen/<wbr>TableGenBackends.h<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=304121&r1=304120&r2=304121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/CMakeLists.txt?rev=304121&<wbr>r1=304120&r2=304121&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>CMakeLists.txt Sun May 28 20:48:53 2017<br>
@@ -11,7 +11,6 @@ tablegen(LLVM X86GenFastISel.inc -gen-fa<br>
 tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)<br>
 tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)<br>
 tablegen(LLVM X86GenEVEX2VEXTables.inc -gen-x86-EVEX2VEX-tables)<br>
-tablegen(LLVM X86GenFoldTables.inc -gen-x86-fold-tables)<br>
 if(LLVM_BUILD_GLOBAL_ISEL)<br>
  tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)<br>
  tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=304121&r1=304120&r2=304121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86InstrInfo.cpp?rev=<wbr>304121&r1=304120&r2=304121&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86InstrInfo.cpp Sun May 28 20:48:53 2017<br>
@@ -121,8 +121,172 @@ X86InstrInfo::X86InstrInfo(<wbr>X86Subtarget<br>
            (STI.is64Bit() ? X86::RETQ : X86::RETL)),<br>
    Subtarget(STI), RI(STI.getTargetTriple()) {<br>
<br>
-// Generated memory folding tables.<br>
-#include "X86GenFoldTables.inc"<br>
+Â static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {<br>
+  { X86::ADC32ri,   X86::ADC32mi,  0 },<br>
+  { X86::ADC32ri8,  X86::ADC32mi8,  0 },<br>
+  { X86::ADC32rr,   X86::ADC32mr,  0 },<br>
+  { X86::ADC64ri32,  X86::ADC64mi32, 0 },<br>
+  { X86::ADC64ri8,  X86::ADC64mi8,  0 },<br>
+  { X86::ADC64rr,   X86::ADC64mr,  0 },<br>
+  { X86::ADD16ri,   X86::ADD16mi,  0 },<br>
+  { X86::ADD16ri8,  X86::ADD16mi8,  0 },<br>
+  { X86::ADD16ri_DB, X86::ADD16mi,  TB_NO_REVERSE },<br>
+  { X86::ADD16ri8_DB, X86::ADD16mi8,  TB_NO_REVERSE },<br>
+  { X86::ADD16rr,   X86::ADD16mr,  0 },<br>
+  { X86::ADD16rr_DB, X86::ADD16mr,  TB_NO_REVERSE },<br>
+  { X86::ADD32ri,   X86::ADD32mi,  0 },<br>
+  { X86::ADD32ri8,  X86::ADD32mi8,  0 },<br>
+  { X86::ADD32ri_DB, X86::ADD32mi,  TB_NO_REVERSE },<br>
+  { X86::ADD32ri8_DB, X86::ADD32mi8,  TB_NO_REVERSE },<br>
+  { X86::ADD32rr,   X86::ADD32mr,  0 },<br>
+  { X86::ADD32rr_DB, X86::ADD32mr,  TB_NO_REVERSE },<br>
+  { X86::ADD64ri32,  X86::ADD64mi32, 0 },<br>
+  { X86::ADD64ri8,  X86::ADD64mi8,  0 },<br>
+  { X86::ADD64ri32_DB,X86::<wbr>ADD64mi32, TB_NO_REVERSE },<br>
+  { X86::ADD64ri8_DB, X86::ADD64mi8,  TB_NO_REVERSE },<br>
+  { X86::ADD64rr,   X86::ADD64mr,  0 },<br>
+  { X86::ADD64rr_DB, X86::ADD64mr,  TB_NO_REVERSE },<br>
+  { X86::ADD8ri,   X86::ADD8mi,   0 },<br>
+  { X86::ADD8rr,   X86::ADD8mr,   0 },<br>
+  { X86::AND16ri,   X86::AND16mi,  0 },<br>
+  { X86::AND16ri8,  X86::AND16mi8,  0 },<br>
+  { X86::AND16rr,   X86::AND16mr,  0 },<br>
+  { X86::AND32ri,   X86::AND32mi,  0 },<br>
+  { X86::AND32ri8,  X86::AND32mi8,  0 },<br>
+  { X86::AND32rr,   X86::AND32mr,  0 },<br>
+  { X86::AND64ri32,  X86::AND64mi32, 0 },<br>
+  { X86::AND64ri8,  X86::AND64mi8,  0 },<br>
+  { X86::AND64rr,   X86::AND64mr,  0 },<br>
+  { X86::AND8ri,   X86::AND8mi,   0 },<br>
+  { X86::AND8rr,   X86::AND8mr,   0 },<br>
+  { X86::DEC16r,   X86::DEC16m,   0 },<br>
+  { X86::DEC32r,   X86::DEC32m,   0 },<br>
+  { X86::DEC64r,   X86::DEC64m,   0 },<br>
+  { X86::DEC8r,    X86::DEC8m,   0 },<br>
+  { X86::INC16r,   X86::INC16m,   0 },<br>
+  { X86::INC32r,   X86::INC32m,   0 },<br>
+  { X86::INC64r,   X86::INC64m,   0 },<br>
+  { X86::INC8r,    X86::INC8m,   0 },<br>
+  { X86::NEG16r,   X86::NEG16m,   0 },<br>
+  { X86::NEG32r,   X86::NEG32m,   0 },<br>
+  { X86::NEG64r,   X86::NEG64m,   0 },<br>
+  { X86::NEG8r,    X86::NEG8m,   0 },<br>
+  { X86::NOT16r,   X86::NOT16m,   0 },<br>
+  { X86::NOT32r,   X86::NOT32m,   0 },<br>
+  { X86::NOT64r,   X86::NOT64m,   0 },<br>
+  { X86::NOT8r,    X86::NOT8m,   0 },<br>
+  { X86::OR16ri,   X86::OR16mi,   0 },<br>
+  { X86::OR16ri8,   X86::OR16mi8,  0 },<br>
+  { X86::OR16rr,   X86::OR16mr,   0 },<br>
+  { X86::OR32ri,   X86::OR32mi,   0 },<br>
+  { X86::OR32ri8,   X86::OR32mi8,  0 },<br>
+  { X86::OR32rr,   X86::OR32mr,   0 },<br>
+  { X86::OR64ri32,  X86::OR64mi32,  0 },<br>
+  { X86::OR64ri8,   X86::OR64mi8,  0 },<br>
+  { X86::OR64rr,   X86::OR64mr,   0 },<br>
+  { X86::OR8ri,    X86::OR8mi,   0 },<br>
+  { X86::OR8rr,    X86::OR8mr,   0 },<br>
+  { X86::ROL16r1,   X86::ROL16m1,  0 },<br>
+  { X86::ROL16rCL,  X86::ROL16mCL,  0 },<br>
+  { X86::ROL16ri,   X86::ROL16mi,  0 },<br>
+  { X86::ROL32r1,   X86::ROL32m1,  0 },<br>
+  { X86::ROL32rCL,  X86::ROL32mCL,  0 },<br>
+  { X86::ROL32ri,   X86::ROL32mi,  0 },<br>
+  { X86::ROL64r1,   X86::ROL64m1,  0 },<br>
+  { X86::ROL64rCL,  X86::ROL64mCL,  0 },<br>
+  { X86::ROL64ri,   X86::ROL64mi,  0 },<br>
+  { X86::ROL8r1,   X86::ROL8m1,   0 },<br>
+  { X86::ROL8rCL,   X86::ROL8mCL,  0 },<br>
+  { X86::ROL8ri,   X86::ROL8mi,   0 },<br>
+  { X86::ROR16r1,   X86::ROR16m1,  0 },<br>
+  { X86::ROR16rCL,  X86::ROR16mCL,  0 },<br>
+  { X86::ROR16ri,   X86::ROR16mi,  0 },<br>
+  { X86::ROR32r1,   X86::ROR32m1,  0 },<br>
+  { X86::ROR32rCL,  X86::ROR32mCL,  0 },<br>
+  { X86::ROR32ri,   X86::ROR32mi,  0 },<br>
+  { X86::ROR64r1,   X86::ROR64m1,  0 },<br>
+  { X86::ROR64rCL,  X86::ROR64mCL,  0 },<br>
+  { X86::ROR64ri,   X86::ROR64mi,  0 },<br>
+  { X86::ROR8r1,   X86::ROR8m1,   0 },<br>
+  { X86::ROR8rCL,   X86::ROR8mCL,  0 },<br>
+  { X86::ROR8ri,   X86::ROR8mi,   0 },<br>
+  { X86::SAR16r1,   X86::SAR16m1,  0 },<br>
+  { X86::SAR16rCL,  X86::SAR16mCL,  0 },<br>
+  { X86::SAR16ri,   X86::SAR16mi,  0 },<br>
+  { X86::SAR32r1,   X86::SAR32m1,  0 },<br>
+  { X86::SAR32rCL,  X86::SAR32mCL,  0 },<br>
+  { X86::SAR32ri,   X86::SAR32mi,  0 },<br>
+  { X86::SAR64r1,   X86::SAR64m1,  0 },<br>
+  { X86::SAR64rCL,  X86::SAR64mCL,  0 },<br>
+  { X86::SAR64ri,   X86::SAR64mi,  0 },<br>
+  { X86::SAR8r1,   X86::SAR8m1,   0 },<br>
+  { X86::SAR8rCL,   X86::SAR8mCL,  0 },<br>
+  { X86::SAR8ri,   X86::SAR8mi,   0 },<br>
+  { X86::SBB32ri,   X86::SBB32mi,  0 },<br>
+  { X86::SBB32ri8,  X86::SBB32mi8,  0 },<br>
+  { X86::SBB32rr,   X86::SBB32mr,  0 },<br>
+  { X86::SBB64ri32,  X86::SBB64mi32, 0 },<br>
+  { X86::SBB64ri8,  X86::SBB64mi8,  0 },<br>
+  { X86::SBB64rr,   X86::SBB64mr,  0 },<br>
+  { X86::SHL16r1,   X86::SHL16m1,  0 },<br>
+  { X86::SHL16rCL,  X86::SHL16mCL,  0 },<br>
+  { X86::SHL16ri,   X86::SHL16mi,  0 },<br>
+  { X86::SHL32r1,   X86::SHL32m1,  0 },<br>
+  { X86::SHL32rCL,  X86::SHL32mCL,  0 },<br>
+  { X86::SHL32ri,   X86::SHL32mi,  0 },<br>
+  { X86::SHL64r1,   X86::SHL64m1,  0 },<br>
+  { X86::SHL64rCL,  X86::SHL64mCL,  0 },<br>
+  { X86::SHL64ri,   X86::SHL64mi,  0 },<br>
+  { X86::SHL8r1,   X86::SHL8m1,   0 },<br>
+  { X86::SHL8rCL,   X86::SHL8mCL,  0 },<br>
+  { X86::SHL8ri,   X86::SHL8mi,   0 },<br>
+  { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },<br>
+  { X86::SHLD16rri8, X86::SHLD16mri8, 0 },<br>
+  { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },<br>
+  { X86::SHLD32rri8, X86::SHLD32mri8, 0 },<br>
+  { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },<br>
+  { X86::SHLD64rri8, X86::SHLD64mri8, 0 },<br>
+  { X86::SHR16r1,   X86::SHR16m1,  0 },<br>
+  { X86::SHR16rCL,  X86::SHR16mCL,  0 },<br>
+  { X86::SHR16ri,   X86::SHR16mi,  0 },<br>
+  { X86::SHR32r1,   X86::SHR32m1,  0 },<br>
+  { X86::SHR32rCL,  X86::SHR32mCL,  0 },<br>
+  { X86::SHR32ri,   X86::SHR32mi,  0 },<br>
+  { X86::SHR64r1,   X86::SHR64m1,  0 },<br>
+  { X86::SHR64rCL,  X86::SHR64mCL,  0 },<br>
+  { X86::SHR64ri,   X86::SHR64mi,  0 },<br>
+  { X86::SHR8r1,   X86::SHR8m1,   0 },<br>
+  { X86::SHR8rCL,   X86::SHR8mCL,  0 },<br>
+  { X86::SHR8ri,   X86::SHR8mi,   0 },<br>
+  { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },<br>
+  { X86::SHRD16rri8, X86::SHRD16mri8, 0 },<br>
+  { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },<br>
+  { X86::SHRD32rri8, X86::SHRD32mri8, 0 },<br>
+  { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },<br>
+  { X86::SHRD64rri8, X86::SHRD64mri8, 0 },<br>
+  { X86::SUB16ri,   X86::SUB16mi,  0 },<br>
+  { X86::SUB16ri8,  X86::SUB16mi8,  0 },<br>
+  { X86::SUB16rr,   X86::SUB16mr,  0 },<br>
+  { X86::SUB32ri,   X86::SUB32mi,  0 },<br>
+  { X86::SUB32ri8,  X86::SUB32mi8,  0 },<br>
+  { X86::SUB32rr,   X86::SUB32mr,  0 },<br>
+  { X86::SUB64ri32,  X86::SUB64mi32, 0 },<br>
+  { X86::SUB64ri8,  X86::SUB64mi8,  0 },<br>
+  { X86::SUB64rr,   X86::SUB64mr,  0 },<br>
+  { X86::SUB8ri,   X86::SUB8mi,   0 },<br>
+  { X86::SUB8rr,   X86::SUB8mr,   0 },<br>
+  { X86::XOR16ri,   X86::XOR16mi,  0 },<br>
+  { X86::XOR16ri8,  X86::XOR16mi8,  0 },<br>
+  { X86::XOR16rr,   X86::XOR16mr,  0 },<br>
+  { X86::XOR32ri,   X86::XOR32mi,  0 },<br>
+  { X86::XOR32ri8,  X86::XOR32mi8,  0 },<br>
+  { X86::XOR32rr,   X86::XOR32mr,  0 },<br>
+  { X86::XOR64ri32,  X86::XOR64mi32, 0 },<br>
+  { X86::XOR64ri8,  X86::XOR64mi8,  0 },<br>
+  { X86::XOR64rr,   X86::XOR64mr,  0 },<br>
+  { X86::XOR8ri,   X86::XOR8mi,   0 },<br>
+  { X86::XOR8rr,   X86::XOR8mr,   0 }<br>
+Â };<br>
<br>
  for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {<br>
   AddTableEntry(<wbr>RegOp2MemOpTable2Addr, MemOp2RegOpTable,<br>
@@ -131,11 +295,746 @@ X86InstrInfo::X86InstrInfo(<wbr>X86Subtarget<br>
          Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);<br>
  }<br>
<br>
+Â static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {<br>
+  { X86::BT16ri8,   X86::BT16mi8,    TB_FOLDED_LOAD },<br>
+  { X86::BT32ri8,   X86::BT32mi8,    TB_FOLDED_LOAD },<br>
+  { X86::BT64ri8,   X86::BT64mi8,    TB_FOLDED_LOAD },<br>
+  { X86::CALL32r,   X86::CALL32m,    TB_FOLDED_LOAD },<br>
+  { X86::CALL64r,   X86::CALL64m,    TB_FOLDED_LOAD },<br>
+  { X86::CMP16ri,   X86::CMP16mi,    TB_FOLDED_LOAD },<br>
+  { X86::CMP16ri8,  X86::CMP16mi8,   TB_FOLDED_LOAD },<br>
+  { X86::CMP16rr,   X86::CMP16mr,    TB_FOLDED_LOAD },<br>
+  { X86::CMP32ri,   X86::CMP32mi,    TB_FOLDED_LOAD },<br>
+  { X86::CMP32ri8,  X86::CMP32mi8,   TB_FOLDED_LOAD },<br>
+  { X86::CMP32rr,   X86::CMP32mr,    TB_FOLDED_LOAD },<br>
+  { X86::CMP64ri32,  X86::CMP64mi32,   TB_FOLDED_LOAD },<br>
+  { X86::CMP64ri8,  X86::CMP64mi8,   TB_FOLDED_LOAD },<br>
+  { X86::CMP64rr,   X86::CMP64mr,    TB_FOLDED_LOAD },<br>
+  { X86::CMP8ri,   X86::CMP8mi,    TB_FOLDED_LOAD },<br>
+  { X86::CMP8rr,   X86::CMP8mr,    TB_FOLDED_LOAD },<br>
+  { X86::DIV16r,   X86::DIV16m,    TB_FOLDED_LOAD },<br>
+  { X86::DIV32r,   X86::DIV32m,    TB_FOLDED_LOAD },<br>
+  { X86::DIV64r,   X86::DIV64m,    TB_FOLDED_LOAD },<br>
+  { X86::DIV8r,    X86::DIV8m,     TB_FOLDED_LOAD },<br>
+  { X86::EXTRACTPSrr, X86::EXTRACTPSmr,  TB_FOLDED_STORE },<br>
+  { X86::IDIV16r,   X86::IDIV16m,    TB_FOLDED_LOAD },<br>
+  { X86::IDIV32r,   X86::IDIV32m,    TB_FOLDED_LOAD },<br>
+  { X86::IDIV64r,   X86::IDIV64m,    TB_FOLDED_LOAD },<br>
+  { X86::IDIV8r,   X86::IDIV8m,    TB_FOLDED_LOAD },<br>
+  { X86::IMUL16r,   X86::IMUL16m,    TB_FOLDED_LOAD },<br>
+  { X86::IMUL32r,   X86::IMUL32m,    TB_FOLDED_LOAD },<br>
+  { X86::IMUL64r,   X86::IMUL64m,    TB_FOLDED_LOAD },<br>
+  { X86::IMUL8r,   X86::IMUL8m,    TB_FOLDED_LOAD },<br>
+  { X86::JMP32r,   X86::JMP32m,    TB_FOLDED_LOAD },<br>
+  { X86::JMP64r,   X86::JMP64m,    TB_FOLDED_LOAD },<br>
+  { X86::MOV16ri,   X86::MOV16mi,    TB_FOLDED_STORE },<br>
+  { X86::MOV16rr,   X86::MOV16mr,    TB_FOLDED_STORE },<br>
+  { X86::MOV32ri,   X86::MOV32mi,    TB_FOLDED_STORE },<br>
+  { X86::MOV32rr,   X86::MOV32mr,    TB_FOLDED_STORE },<br>
+  { X86::MOV64ri32,  X86::MOV64mi32,   TB_FOLDED_STORE },<br>
+  { X86::MOV64rr,   X86::MOV64mr,    TB_FOLDED_STORE },<br>
+  { X86::MOV8ri,   X86::MOV8mi,    TB_FOLDED_STORE },<br>
+  { X86::MOV8rr,   X86::MOV8mr,    TB_FOLDED_STORE },<br>
+Â Â { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },<br>
+  { X86::MOVAPDrr,  X86::MOVAPDmr,   TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::MOVAPSrr,  X86::MOVAPSmr,   TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::MOVDQArr,  X86::MOVDQAmr,   TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::MOVDQUrr,  X86::MOVDQUmr,   TB_FOLDED_STORE },<br>
+  { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,  TB_FOLDED_STORE },<br>
+  { X86::MOVPQIto64rr,X86::<wbr>MOVPQI2QImr,  TB_FOLDED_STORE },<br>
+  { X86::MOVSDto64rr, X86::MOVSDto64mr,  TB_FOLDED_STORE },<br>
+  { X86::MOVSS2DIrr, X86::MOVSS2DImr,  TB_FOLDED_STORE },<br>
+  { X86::MOVUPDrr,  X86::MOVUPDmr,   TB_FOLDED_STORE },<br>
+  { X86::MOVUPSrr,  X86::MOVUPSmr,   TB_FOLDED_STORE },<br>
+  { X86::MUL16r,   X86::MUL16m,    TB_FOLDED_LOAD },<br>
+  { X86::MUL32r,   X86::MUL32m,    TB_FOLDED_LOAD },<br>
+  { X86::MUL64r,   X86::MUL64m,    TB_FOLDED_LOAD },<br>
+  { X86::MUL8r,    X86::MUL8m,     TB_FOLDED_LOAD },<br>
+  { X86::PEXTRDrr,  X86::PEXTRDmr,   TB_FOLDED_STORE },<br>
+  { X86::PEXTRQrr,  X86::PEXTRQmr,   TB_FOLDED_STORE },<br>
+  { X86::PUSH16r,   X86::PUSH16rmm,   TB_FOLDED_LOAD },<br>
+  { X86::PUSH32r,   X86::PUSH32rmm,   TB_FOLDED_LOAD },<br>
+  { X86::PUSH64r,   X86::PUSH64rmm,   TB_FOLDED_LOAD },<br>
+  { X86::SETAEr,   X86::SETAEm,    TB_FOLDED_STORE },<br>
+  { X86::SETAr,    X86::SETAm,     TB_FOLDED_STORE },<br>
+  { X86::SETBEr,   X86::SETBEm,    TB_FOLDED_STORE },<br>
+  { X86::SETBr,    X86::SETBm,     TB_FOLDED_STORE },<br>
+  { X86::SETEr,    X86::SETEm,     TB_FOLDED_STORE },<br>
+  { X86::SETGEr,   X86::SETGEm,    TB_FOLDED_STORE },<br>
+  { X86::SETGr,    X86::SETGm,     TB_FOLDED_STORE },<br>
+  { X86::SETLEr,   X86::SETLEm,    TB_FOLDED_STORE },<br>
+  { X86::SETLr,    X86::SETLm,     TB_FOLDED_STORE },<br>
+  { X86::SETNEr,   X86::SETNEm,    TB_FOLDED_STORE },<br>
+  { X86::SETNOr,   X86::SETNOm,    TB_FOLDED_STORE },<br>
+  { X86::SETNPr,   X86::SETNPm,    TB_FOLDED_STORE },<br>
+  { X86::SETNSr,   X86::SETNSm,    TB_FOLDED_STORE },<br>
+  { X86::SETOr,    X86::SETOm,     TB_FOLDED_STORE },<br>
+  { X86::SETPr,    X86::SETPm,     TB_FOLDED_STORE },<br>
+  { X86::SETSr,    X86::SETSm,     TB_FOLDED_STORE },<br>
+  { X86::TAILJMPr,  X86::TAILJMPm,   TB_FOLDED_LOAD },<br>
+  { X86::TAILJMPr64, X86::TAILJMPm64,  TB_FOLDED_LOAD },<br>
+Â Â { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },<br>
+  { X86::TEST16ri,  X86::TEST16mi,   TB_FOLDED_LOAD },<br>
+  { X86::TEST32ri,  X86::TEST32mi,   TB_FOLDED_LOAD },<br>
+  { X86::TEST64ri32, X86::TEST64mi32,  TB_FOLDED_LOAD },<br>
+  { X86::TEST8ri,   X86::TEST8mi,    TB_FOLDED_LOAD },<br>
+<br>
+Â Â // AVX 128-bit versions of foldable instructions<br>
+  { X86::VEXTRACTPSrr,X86::<wbr>VEXTRACTPSmr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::VMOVAPDrr,  X86::VMOVAPDmr,   TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::VMOVAPSrr,  X86::VMOVAPSmr,   TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::VMOVDQArr,  X86::VMOVDQAmr,   TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::VMOVDQUrr,  X86::VMOVDQUmr,   TB_FOLDED_STORE },<br>
+  { X86::VMOVPDI2DIrr,X86::<wbr>VMOVPDI2DImr, TB_FOLDED_STORE },<br>
+Â Â { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_<wbr>STORE },<br>
+  { X86::VMOVSDto64rr,X86::<wbr>VMOVSDto64mr, TB_FOLDED_STORE },<br>
+  { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVUPDrr,  X86::VMOVUPDmr,   TB_FOLDED_STORE },<br>
+  { X86::VMOVUPSrr,  X86::VMOVUPSmr,   TB_FOLDED_STORE },<br>
+  { X86::VPEXTRDrr,  X86::VPEXTRDmr,   TB_FOLDED_STORE },<br>
+  { X86::VPEXTRQrr,  X86::VPEXTRQmr,   TB_FOLDED_STORE },<br>
+<br>
+Â Â // AVX 256-bit foldable instructions<br>
+Â Â { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::VMOVAPDYrr, X86::VMOVAPDYmr,  TB_FOLDED_STORE | TB_ALIGN_32 },<br>
+  { X86::VMOVAPSYrr, X86::VMOVAPSYmr,  TB_FOLDED_STORE | TB_ALIGN_32 },<br>
+  { X86::VMOVDQAYrr, X86::VMOVDQAYmr,  TB_FOLDED_STORE | TB_ALIGN_32 },<br>
+  { X86::VMOVDQUYrr, X86::VMOVDQUYmr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVUPDYrr, X86::VMOVUPDYmr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVUPSYrr, X86::VMOVUPSYmr,  TB_FOLDED_STORE },<br>
+<br>
+Â Â // AVX-512 foldable instructions<br>
+Â Â { X86::VEXTRACTF32x4Zrr,X86::<wbr>VEXTRACTF32x4Zmr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTF32x8Zrr,X86::<wbr>VEXTRACTF32x8Zmr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTF64x2Zrr,X86::<wbr>VEXTRACTF64x2Zmr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTF64x4Zrr,X86::<wbr>VEXTRACTF64x4Zmr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTI32x4Zrr,X86::<wbr>VEXTRACTI32x4Zmr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTI32x8Zrr,X86::<wbr>VEXTRACTI32x8Zmr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTI64x2Zrr,X86::<wbr>VEXTRACTI64x2Zmr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTI64x4Zrr,X86::<wbr>VEXTRACTI64x4Zmr, TB_FOLDED_STORE },<br>
+  { X86::VEXTRACTPSZrr,  X86::VEXTRACTPSZmr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVAPDZrr,   X86::VMOVAPDZmr,  TB_FOLDED_STORE | TB_ALIGN_64 },<br>
+  { X86::VMOVAPSZrr,   X86::VMOVAPSZmr,  TB_FOLDED_STORE | TB_ALIGN_64 },<br>
+  { X86::VMOVDQA32Zrr,  X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },<br>
+  { X86::VMOVDQA64Zrr,  X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },<br>
+  { X86::VMOVDQU8Zrr,   X86::VMOVDQU8Zmr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU16Zrr,  X86::VMOVDQU16Zmr, TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU32Zrr,  X86::VMOVDQU32Zmr, TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU64Zrr,  X86::VMOVDQU64Zmr, TB_FOLDED_STORE },<br>
+  { X86::VMOVPDI2DIZrr,  X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },<br>
+  { X86::VMOVPQIto64Zrr, X86::VMOVPQI2QIZmr, TB_FOLDED_STORE },<br>
+  { X86::VMOVSDto64Zrr,  X86::VMOVSDto64Zmr, TB_FOLDED_STORE },<br>
+  { X86::VMOVSS2DIZrr,  X86::VMOVSS2DIZmr, TB_FOLDED_STORE },<br>
+  { X86::VMOVUPDZrr,   X86::VMOVUPDZmr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVUPSZrr,   X86::VMOVUPSZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPEXTRDZrr,   X86::VPEXTRDZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPEXTRQZrr,   X86::VPEXTRQZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVDBZrr,   X86::VPMOVDBZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVDWZrr,   X86::VPMOVDWZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVQDZrr,   X86::VPMOVQDZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVQWZrr,   X86::VPMOVQWZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVWBZrr,   X86::VPMOVWBZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVSDBZrr,   X86::VPMOVSDBZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVSDWZrr,   X86::VPMOVSDWZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVSQDZrr,   X86::VPMOVSQDZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVSQWZrr,   X86::VPMOVSQWZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVSWBZrr,   X86::VPMOVSWBZmr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVUSDBZrr,  X86::VPMOVUSDBZmr, TB_FOLDED_STORE },<br>
+  { X86::VPMOVUSDWZrr,  X86::VPMOVUSDWZmr, TB_FOLDED_STORE },<br>
+  { X86::VPMOVUSQDZrr,  X86::VPMOVUSQDZmr, TB_FOLDED_STORE },<br>
+  { X86::VPMOVUSQWZrr,  X86::VPMOVUSQWZmr, TB_FOLDED_STORE },<br>
+  { X86::VPMOVUSWBZrr,  X86::VPMOVUSWBZmr, TB_FOLDED_STORE },<br>
+<br>
+Â Â // AVX-512 foldable instructions (256-bit versions)<br>
+Â Â { X86::VEXTRACTF32x4Z256rr,X86::<wbr>VEXTRACTF32x4Z256mr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTF64x2Z256rr,X86::<wbr>VEXTRACTF64x2Z256mr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTI32x4Z256rr,X86::<wbr>VEXTRACTI32x4Z256mr, TB_FOLDED_STORE },<br>
+Â Â { X86::VEXTRACTI64x2Z256rr,X86::<wbr>VEXTRACTI64x2Z256mr, TB_FOLDED_STORE },<br>
+  { X86::VMOVAPDZ256rr,   X86::VMOVAPDZ256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },<br>
+  { X86::VMOVAPSZ256rr,   X86::VMOVAPSZ256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },<br>
+  { X86::VMOVDQA32Z256rr,  X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },<br>
+  { X86::VMOVDQA64Z256rr,  X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },<br>
+  { X86::VMOVUPDZ256rr,   X86::VMOVUPDZ256mr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVUPSZ256rr,   X86::VMOVUPSZ256mr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU8Z256rr,   X86::VMOVDQU8Z256mr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU16Z256rr,  X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU32Z256rr,  X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU64Z256rr,  X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },<br>
+  { X86::VPMOVDWZ256rr,   X86::VPMOVDWZ256mr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVQDZ256rr,   X86::VPMOVQDZ256mr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVWBZ256rr,   X86::VPMOVWBZ256mr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVSDWZ256rr,   X86::VPMOVSDWZ256mr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVSQDZ256rr,   X86::VPMOVSQDZ256mr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVSWBZ256rr,   X86::VPMOVSWBZ256mr,  TB_FOLDED_STORE },<br>
+  { X86::VPMOVUSDWZ256rr,  X86::VPMOVUSDWZ256mr, TB_FOLDED_STORE },<br>
+  { X86::VPMOVUSQDZ256rr,  X86::VPMOVUSQDZ256mr, TB_FOLDED_STORE },<br>
+  { X86::VPMOVUSWBZ256rr,  X86::VPMOVUSWBZ256mr, TB_FOLDED_STORE },<br>
+<br>
+Â Â // AVX-512 foldable instructions (128-bit versions)<br>
+  { X86::VMOVAPDZ128rr,   X86::VMOVAPDZ128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::VMOVAPSZ128rr,   X86::VMOVAPSZ128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::VMOVDQA32Z128rr,  X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::VMOVDQA64Z128rr,  X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },<br>
+  { X86::VMOVUPDZ128rr,   X86::VMOVUPDZ128mr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVUPSZ128rr,   X86::VMOVUPSZ128mr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU8Z128rr,   X86::VMOVDQU8Z128mr,  TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU16Z128rr,  X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU32Z128rr,  X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },<br>
+  { X86::VMOVDQU64Z128rr,  X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },<br>
+<br>
+Â Â // F16C foldable instructions<br>
+  { X86::VCVTPS2PHrr,    X86::VCVTPS2PHmr,   TB_FOLDED_STORE },<br>
+  { X86::VCVTPS2PHYrr,    X86::VCVTPS2PHYmr,   TB_FOLDED_STORE }<br>
+Â };<br>
+<br>
  for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {<br>
   AddTableEntry(<wbr>RegOp2MemOpTable0, MemOp2RegOpTable,<br>
          Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);<br>
  }<br>
<br>
+Â static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {<br>
+  { X86::BSF16rr,     X86::BSF16rm,       0 },<br>
+  { X86::BSF32rr,     X86::BSF32rm,       0 },<br>
+  { X86::BSF64rr,     X86::BSF64rm,       0 },<br>
+  { X86::BSR16rr,     X86::BSR16rm,       0 },<br>
+  { X86::BSR32rr,     X86::BSR32rm,       0 },<br>
+  { X86::BSR64rr,     X86::BSR64rm,       0 },<br>
+  { X86::CMP16rr,     X86::CMP16rm,       0 },<br>
+  { X86::CMP32rr,     X86::CMP32rm,       0 },<br>
+  { X86::CMP64rr,     X86::CMP64rm,       0 },<br>
+  { X86::CMP8rr,     X86::CMP8rm,       0 },<br>
+  { X86::CVTSD2SSrr,   X86::CVTSD2SSrm,     0 },<br>
+  { X86::CVTSI2SD64rr,  X86::CVTSI2SD64rm,    0 },<br>
+  { X86::CVTSI2SDrr,   X86::CVTSI2SDrm,     0 },<br>
+  { X86::CVTSI2SS64rr,  X86::CVTSI2SS64rm,    0 },<br>
+  { X86::CVTSI2SSrr,   X86::CVTSI2SSrm,     0 },<br>
+  { X86::CVTSS2SDrr,   X86::CVTSS2SDrm,     0 },<br>
+  { X86::CVTTSD2SI64rr,  X86::CVTTSD2SI64rm,    0 },<br>
+  { X86::CVTTSD2SIrr,   X86::CVTTSD2SIrm,     0 },<br>
+  { X86::CVTTSS2SI64rr,  X86::CVTTSS2SI64rm,    0 },<br>
+  { X86::CVTTSS2SIrr,   X86::CVTTSS2SIrm,     0 },<br>
+  { X86::IMUL16rri,    X86::IMUL16rmi,      0 },<br>
+  { X86::IMUL16rri8,   X86::IMUL16rmi8,     0 },<br>
+  { X86::IMUL32rri,    X86::IMUL32rmi,      0 },<br>
+  { X86::IMUL32rri8,   X86::IMUL32rmi8,     0 },<br>
+  { X86::IMUL64rri32,   X86::IMUL64rmi32,     0 },<br>
+  { X86::IMUL64rri8,   X86::IMUL64rmi8,     0 },<br>
+  { X86::Int_COMISDrr,  X86::Int_COMISDrm,    TB_NO_REVERSE },<br>
+  { X86::Int_COMISSrr,  X86::Int_COMISSrm,    TB_NO_REVERSE },<br>
+  { X86::CVTSD2SI64rr,  X86::CVTSD2SI64rm,    TB_NO_REVERSE },<br>
+  { X86::CVTSD2SIrr,   X86::CVTSD2SIrm,     TB_NO_REVERSE },<br>
+  { X86::CVTSS2SI64rr,  X86::CVTSS2SI64rm,    TB_NO_REVERSE },<br>
+  { X86::CVTSS2SIrr,   X86::CVTSS2SIrm,     TB_NO_REVERSE },<br>
+  { X86::CVTDQ2PDrr,   X86::CVTDQ2PDrm,     TB_NO_REVERSE },<br>
+  { X86::CVTDQ2PSrr,   X86::CVTDQ2PSrm,     TB_ALIGN_16 },<br>
+  { X86::CVTPD2DQrr,   X86::CVTPD2DQrm,     TB_ALIGN_16 },<br>
+  { X86::CVTPD2PSrr,   X86::CVTPD2PSrm,     TB_ALIGN_16 },<br>
+  { X86::CVTPS2DQrr,   X86::CVTPS2DQrm,     TB_ALIGN_16 },<br>
+  { X86::CVTPS2PDrr,   X86::CVTPS2PDrm,     TB_NO_REVERSE },<br>
+  { X86::CVTTPD2DQrr,   X86::CVTTPD2DQrm,     TB_ALIGN_16 },<br>
+  { X86::CVTTPS2DQrr,   X86::CVTTPS2DQrm,     TB_ALIGN_16 },<br>
+  { X86::Int_CVTTSD2SI64rr,X86::<wbr>Int_CVTTSD2SI64rm, TB_NO_REVERSE },<br>
+  { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,   TB_NO_REVERSE },<br>
+  { X86::Int_CVTTSS2SI64rr,X86::<wbr>Int_CVTTSS2SI64rm, TB_NO_REVERSE },<br>
+  { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,   TB_NO_REVERSE },<br>
+  { X86::Int_UCOMISDrr,  X86::Int_UCOMISDrm,    TB_NO_REVERSE },<br>
+  { X86::Int_UCOMISSrr,  X86::Int_UCOMISSrm,    TB_NO_REVERSE },<br>
+  { X86::MOV16rr,     X86::MOV16rm,       0 },<br>
+  { X86::MOV32rr,     X86::MOV32rm,       0 },<br>
+  { X86::MOV64rr,     X86::MOV64rm,       0 },<br>
+  { X86::MOV64toPQIrr,  X86::MOVQI2PQIrm,     0 },<br>
+  { X86::MOV64toSDrr,   X86::MOV64toSDrm,     0 },<br>
+  { X86::MOV8rr,     X86::MOV8rm,       0 },<br>
+  { X86::MOVAPDrr,    X86::MOVAPDrm,      TB_ALIGN_16 },<br>
+  { X86::MOVAPSrr,    X86::MOVAPSrm,      TB_ALIGN_16 },<br>
+  { X86::MOVDDUPrr,    X86::MOVDDUPrm,      TB_NO_REVERSE },<br>
+  { X86::MOVDI2PDIrr,   X86::MOVDI2PDIrm,     0 },<br>
+  { X86::MOVDI2SSrr,   X86::MOVDI2SSrm,     0 },<br>
+  { X86::MOVDQArr,    X86::MOVDQArm,      TB_ALIGN_16 },<br>
+  { X86::MOVDQUrr,    X86::MOVDQUrm,      0 },<br>
+  { X86::MOVSHDUPrr,   X86::MOVSHDUPrm,     TB_ALIGN_16 },<br>
+  { X86::MOVSLDUPrr,   X86::MOVSLDUPrm,     TB_ALIGN_16 },<br>
+  { X86::MOVSX16rr8,   X86::MOVSX16rm8,     0 },<br>
+  { X86::MOVSX32rr16,   X86::MOVSX32rm16,     0 },<br>
+  { X86::MOVSX32rr8,   X86::MOVSX32rm8,     0 },<br>
+  { X86::MOVSX64rr16,   X86::MOVSX64rm16,     0 },<br>
+  { X86::MOVSX64rr32,   X86::MOVSX64rm32,     0 },<br>
+  { X86::MOVSX64rr8,   X86::MOVSX64rm8,     0 },<br>
+  { X86::MOVUPDrr,    X86::MOVUPDrm,      0 },<br>
+  { X86::MOVUPSrr,    X86::MOVUPSrm,      0 },<br>
+  { X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm,     TB_NO_REVERSE },<br>
+  { X86::MOVZX16rr8,   X86::MOVZX16rm8,     0 },<br>
+  { X86::MOVZX32rr16,   X86::MOVZX32rm16,     0 },<br>
+  { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,  0 },<br>
+  { X86::MOVZX32rr8,   X86::MOVZX32rm8,     0 },<br>
+  { X86::PABSBrr,     X86::PABSBrm,       TB_ALIGN_16 },<br>
+  { X86::PABSDrr,     X86::PABSDrm,       TB_ALIGN_16 },<br>
+  { X86::PABSWrr,     X86::PABSWrm,       TB_ALIGN_16 },<br>
+  { X86::PCMPESTRIrr,   X86::PCMPESTRIrm,     TB_ALIGN_16 },<br>
+  { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm,   TB_ALIGN_16 },<br>
+  { X86::PCMPISTRIrr,   X86::PCMPISTRIrm,     TB_ALIGN_16 },<br>
+  { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm,   TB_ALIGN_16 },<br>
+  { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,   TB_ALIGN_16 },<br>
+  { X86::PMOVSXBDrr,   X86::PMOVSXBDrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVSXBQrr,   X86::PMOVSXBQrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVSXBWrr,   X86::PMOVSXBWrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVSXDQrr,   X86::PMOVSXDQrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVSXWDrr,   X86::PMOVSXWDrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVSXWQrr,   X86::PMOVSXWQrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVZXBDrr,   X86::PMOVZXBDrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVZXBQrr,   X86::PMOVZXBQrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVZXBWrr,   X86::PMOVZXBWrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVZXDQrr,   X86::PMOVZXDQrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVZXWDrr,   X86::PMOVZXWDrm,     TB_NO_REVERSE },<br>
+  { X86::PMOVZXWQrr,   X86::PMOVZXWQrm,     TB_NO_REVERSE },<br>
+  { X86::PSHUFDri,    X86::PSHUFDmi,      TB_ALIGN_16 },<br>
+  { X86::PSHUFHWri,    X86::PSHUFHWmi,      TB_ALIGN_16 },<br>
+  { X86::PSHUFLWri,    X86::PSHUFLWmi,      TB_ALIGN_16 },<br>
+  { X86::PTESTrr,     X86::PTESTrm,       TB_ALIGN_16 },<br>
+  { X86::RCPPSr,     X86::RCPPSm,       TB_ALIGN_16 },<br>
+  { X86::RCPSSr,     X86::RCPSSm,       0 },<br>
+  { X86::RCPSSr_Int,   X86::RCPSSm_Int,     TB_NO_REVERSE },<br>
+  { X86::ROUNDPDr,    X86::ROUNDPDm,      TB_ALIGN_16 },<br>
+  { X86::ROUNDPSr,    X86::ROUNDPSm,      TB_ALIGN_16 },<br>
+  { X86::ROUNDSDr,    X86::ROUNDSDm,      0 },<br>
+  { X86::ROUNDSSr,    X86::ROUNDSSm,      0 },<br>
+  { X86::RSQRTPSr,    X86::RSQRTPSm,      TB_ALIGN_16 },<br>
+  { X86::RSQRTSSr,    X86::RSQRTSSm,      0 },<br>
+  { X86::RSQRTSSr_Int,  X86::RSQRTSSm_Int,    TB_NO_REVERSE },<br>
+  { X86::SQRTPDr,     X86::SQRTPDm,       TB_ALIGN_16 },<br>
+  { X86::SQRTPSr,     X86::SQRTPSm,       TB_ALIGN_16 },<br>
+  { X86::SQRTSDr,     X86::SQRTSDm,       0 },<br>
+  { X86::SQRTSDr_Int,   X86::SQRTSDm_Int,     TB_NO_REVERSE },<br>
+  { X86::SQRTSSr,     X86::SQRTSSm,       0 },<br>
+  { X86::SQRTSSr_Int,   X86::SQRTSSm_Int,     TB_NO_REVERSE },<br>
+  { X86::TEST16rr,    X86::TEST16rm,      0 },<br>
+  { X86::TEST32rr,    X86::TEST32rm,      0 },<br>
+  { X86::TEST64rr,    X86::TEST64rm,      0 },<br>
+  { X86::TEST8rr,     X86::TEST8rm,       0 },<br>
+Â Â // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0<br>
+  { X86::UCOMISDrr,    X86::UCOMISDrm,      0 },<br>
+  { X86::UCOMISSrr,    X86::UCOMISSrm,      0 },<br>
+<br>
+Â Â // MMX version of foldable instructions<br>
+  { X86::MMX_CVTPD2PIirr,  X86::MMX_CVTPD2PIirm,  0 },<br>
+  { X86::MMX_CVTPI2PDirr,  X86::MMX_CVTPI2PDirm,  0 },<br>
+  { X86::MMX_CVTPS2PIirr,  X86::MMX_CVTPS2PIirm,  0 },<br>
+  { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },<br>
+  { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },<br>
+  { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm,   0 },<br>
+  { X86::MMX_PABSBrr64,   X86::MMX_PABSBrm64,   0 },<br>
+  { X86::MMX_PABSDrr64,   X86::MMX_PABSDrm64,   0 },<br>
+  { X86::MMX_PABSWrr64,   X86::MMX_PABSWrm64,   0 },<br>
+  { X86::MMX_PSHUFWri,   X86::MMX_PSHUFWmi,   0 },<br>
+<br>
+Â Â // 3DNow! version of foldable instructions<br>
+  { X86::PF2IDrr,     X86::PF2IDrm,       0 },<br>
+  { X86::PF2IWrr,     X86::PF2IWrm,       0 },<br>
+  { X86::PFRCPrr,     X86::PFRCPrm,       0 },<br>
+  { X86::PFRSQRTrr,    X86::PFRSQRTrm,      0 },<br>
+  { X86::PI2FDrr,     X86::PI2FDrm,       0 },<br>
+  { X86::PI2FWrr,     X86::PI2FWrm,       0 },<br>
+  { X86::PSWAPDrr,    X86::PSWAPDrm,      0 },<br>
+<br>
+Â Â // AVX 128-bit versions of foldable instructions<br>
+  { X86::Int_VCOMISDrr,  X86::Int_VCOMISDrm,    TB_NO_REVERSE },<br>
+  { X86::Int_VCOMISSrr,  X86::Int_VCOMISSrm,    TB_NO_REVERSE },<br>
+  { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm,   TB_NO_REVERSE },<br>
+  { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm,   TB_NO_REVERSE },<br>
+  { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm,   0 },<br>
+Â Â { X86::Int_VCVTTSD2SI64rr,X86::<wbr>Int_VCVTTSD2SI64rm,TB_NO_<wbr>REVERSE },<br>
+  { X86::VCVTTSD2SIrr,  X86::VCVTTSD2SIrm,    0 },<br>
+  { X86::Int_VCVTTSD2SIrr,X86::<wbr>Int_VCVTTSD2SIrm,  TB_NO_REVERSE },<br>
+  { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm,   0 },<br>
+Â Â { X86::Int_VCVTTSS2SI64rr,X86::<wbr>Int_VCVTTSS2SI64rm,TB_NO_<wbr>REVERSE },<br>
+  { X86::VCVTTSS2SIrr,  X86::VCVTTSS2SIrm,    0 },<br>
+  { X86::Int_VCVTTSS2SIrr,X86::<wbr>Int_VCVTTSS2SIrm,  TB_NO_REVERSE },<br>
+  { X86::VCVTSD2SI64rr,  X86::VCVTSD2SI64rm,    TB_NO_REVERSE },<br>
+  { X86::VCVTSD2SIrr,   X86::VCVTSD2SIrm,     TB_NO_REVERSE },<br>
+  { X86::VCVTSS2SI64rr,  X86::VCVTSS2SI64rm,    TB_NO_REVERSE },<br>
+  { X86::VCVTSS2SIrr,   X86::VCVTSS2SIrm,     TB_NO_REVERSE },<br>
+  { X86::VCVTDQ2PDrr,   X86::VCVTDQ2PDrm,     TB_NO_REVERSE },<br>
+  { X86::VCVTDQ2PSrr,   X86::VCVTDQ2PSrm,     0 },<br>
+  { X86::VCVTPD2DQrr,   X86::VCVTPD2DQrm,     0 },<br>
+  { X86::VCVTPD2PSrr,   X86::VCVTPD2PSrm,     0 },<br>
+  { X86::VCVTPS2DQrr,   X86::VCVTPS2DQrm,     0 },<br>
+  { X86::VCVTPS2PDrr,   X86::VCVTPS2PDrm,     TB_NO_REVERSE },<br>
+  { X86::VCVTTPD2DQrr,  X86::VCVTTPD2DQrm,    0 },<br>
+  { X86::VCVTTPS2DQrr,  X86::VCVTTPS2DQrm,    0 },<br>
+  { X86::VMOV64toPQIrr,  X86::VMOVQI2PQIrm,    0 },<br>
+  { X86::VMOV64toSDrr,  X86::VMOV64toSDrm,    0 },<br>
+  { X86::VMOVAPDrr,    X86::VMOVAPDrm,      TB_ALIGN_16 },<br>
+  { X86::VMOVAPSrr,    X86::VMOVAPSrm,      TB_ALIGN_16 },<br>
+  { X86::VMOVDDUPrr,   X86::VMOVDDUPrm,     TB_NO_REVERSE },<br>
+  { X86::VMOVDI2PDIrr,  X86::VMOVDI2PDIrm,    0 },<br>
+  { X86::VMOVDI2SSrr,   X86::VMOVDI2SSrm,     0 },<br>
+  { X86::VMOVDQArr,    X86::VMOVDQArm,      TB_ALIGN_16 },<br>
+  { X86::VMOVDQUrr,    X86::VMOVDQUrm,      0 },<br>
+  { X86::VMOVSLDUPrr,   X86::VMOVSLDUPrm,     0 },<br>
+  { X86::VMOVSHDUPrr,   X86::VMOVSHDUPrm,     0 },<br>
+  { X86::VMOVUPDrr,    X86::VMOVUPDrm,      0 },<br>
+  { X86::VMOVUPSrr,    X86::VMOVUPSrm,      0 },<br>
+  { X86::VMOVZPQILo2PQIrr,X86::<wbr>VMOVQI2PQIrm,    TB_NO_REVERSE },<br>
+  { X86::VPABSBrr,    X86::VPABSBrm,      0 },<br>
+  { X86::VPABSDrr,    X86::VPABSDrm,      0 },<br>
+  { X86::VPABSWrr,    X86::VPABSWrm,      0 },<br>
+  { X86::VPCMPESTRIrr,  X86::VPCMPESTRIrm,    0 },<br>
+  { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,   0 },<br>
+  { X86::VPCMPISTRIrr,  X86::VPCMPISTRIrm,    0 },<br>
+  { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,   0 },<br>
+  { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,  0 },<br>
+  { X86::VPERMILPDri,   X86::VPERMILPDmi,     0 },<br>
+  { X86::VPERMILPSri,   X86::VPERMILPSmi,     0 },<br>
+  { X86::VPMOVSXBDrr,   X86::VPMOVSXBDrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBQrr,   X86::VPMOVSXBQrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWrr,   X86::VPMOVSXBWrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVSXDQrr,   X86::VPMOVSXDQrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVSXWDrr,   X86::VPMOVSXWDrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVSXWQrr,   X86::VPMOVSXWQrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBDrr,   X86::VPMOVZXBDrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBQrr,   X86::VPMOVZXBQrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWrr,   X86::VPMOVZXBWrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVZXDQrr,   X86::VPMOVZXDQrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVZXWDrr,   X86::VPMOVZXWDrm,     TB_NO_REVERSE },<br>
+  { X86::VPMOVZXWQrr,   X86::VPMOVZXWQrm,     TB_NO_REVERSE },<br>
+  { X86::VPSHUFDri,    X86::VPSHUFDmi,      0 },<br>
+  { X86::VPSHUFHWri,   X86::VPSHUFHWmi,     0 },<br>
+  { X86::VPSHUFLWri,   X86::VPSHUFLWmi,     0 },<br>
+  { X86::VPTESTrr,    X86::VPTESTrm,      0 },<br>
+  { X86::VRCPPSr,     X86::VRCPPSm,       0 },<br>
+  { X86::VROUNDPDr,    X86::VROUNDPDm,      0 },<br>
+  { X86::VROUNDPSr,    X86::VROUNDPSm,      0 },<br>
+  { X86::VRSQRTPSr,    X86::VRSQRTPSm,      0 },<br>
+  { X86::VSQRTPDr,    X86::VSQRTPDm,      0 },<br>
+  { X86::VSQRTPSr,    X86::VSQRTPSm,      0 },<br>
+  { X86::VTESTPDrr,    X86::VTESTPDrm,      0 },<br>
+  { X86::VTESTPSrr,    X86::VTESTPSrm,      0 },<br>
+  { X86::VUCOMISDrr,   X86::VUCOMISDrm,     0 },<br>
+  { X86::VUCOMISSrr,   X86::VUCOMISSrm,     0 },<br>
+<br>
+Â Â // AVX 256-bit foldable instructions<br>
+  { X86::VCVTDQ2PDYrr,  X86::VCVTDQ2PDYrm,    TB_NO_REVERSE },<br>
+  { X86::VCVTDQ2PSYrr,  X86::VCVTDQ2PSYrm,    0 },<br>
+  { X86::VCVTPD2DQYrr,  X86::VCVTPD2DQYrm,    0 },<br>
+  { X86::VCVTPD2PSYrr,  X86::VCVTPD2PSYrm,    0 },<br>
+  { X86::VCVTPS2DQYrr,  X86::VCVTPS2DQYrm,    0 },<br>
+  { X86::VCVTPS2PDYrr,  X86::VCVTPS2PDYrm,    TB_NO_REVERSE },<br>
+  { X86::VCVTTPD2DQYrr,  X86::VCVTTPD2DQYrm,    0 },<br>
+  { X86::VCVTTPS2DQYrr,  X86::VCVTTPS2DQYrm,    0 },<br>
+  { X86::VMOVAPDYrr,   X86::VMOVAPDYrm,     TB_ALIGN_32 },<br>
+  { X86::VMOVAPSYrr,   X86::VMOVAPSYrm,     TB_ALIGN_32 },<br>
+  { X86::VMOVDDUPYrr,   X86::VMOVDDUPYrm,     0 },<br>
+  { X86::VMOVDQAYrr,   X86::VMOVDQAYrm,     TB_ALIGN_32 },<br>
+  { X86::VMOVDQUYrr,   X86::VMOVDQUYrm,     0 },<br>
+  { X86::VMOVSLDUPYrr,  X86::VMOVSLDUPYrm,    0 },<br>
+  { X86::VMOVSHDUPYrr,  X86::VMOVSHDUPYrm,    0 },<br>
+  { X86::VMOVUPDYrr,   X86::VMOVUPDYrm,     0 },<br>
+  { X86::VMOVUPSYrr,   X86::VMOVUPSYrm,     0 },<br>
+  { X86::VPERMILPDYri,  X86::VPERMILPDYmi,    0 },<br>
+  { X86::VPERMILPSYri,  X86::VPERMILPSYmi,    0 },<br>
+  { X86::VPTESTYrr,    X86::VPTESTYrm,      0 },<br>
+  { X86::VRCPPSYr,    X86::VRCPPSYm,      0 },<br>
+  { X86::VROUNDYPDr,   X86::VROUNDYPDm,     0 },<br>
+  { X86::VROUNDYPSr,   X86::VROUNDYPSm,     0 },<br>
+  { X86::VRSQRTPSYr,   X86::VRSQRTPSYm,     0 },<br>
+  { X86::VSQRTPDYr,    X86::VSQRTPDYm,      0 },<br>
+  { X86::VSQRTPSYr,    X86::VSQRTPSYm,      0 },<br>
+  { X86::VTESTPDYrr,   X86::VTESTPDYrm,     0 },<br>
+  { X86::VTESTPSYrr,   X86::VTESTPSYrm,     0 },<br>
+<br>
+Â Â // AVX2 foldable instructions<br>
+<br>
+Â Â // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the<br>
+Â Â // VBROADCASTS{SD}rm memory instructions were available from AVX1.<br>
+Â Â // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction<br>
+Â Â // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions<br>
+Â Â // so they don't need an equivalent limitation.<br>
+  { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm,   TB_NO_REVERSE },<br>
+  { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,   TB_NO_REVERSE },<br>
+  { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,   TB_NO_REVERSE },<br>
+  { X86::VPABSBYrr,    X86::VPABSBYrm,      0 },<br>
+  { X86::VPABSDYrr,    X86::VPABSDYrm,      0 },<br>
+  { X86::VPABSWYrr,    X86::VPABSWYrm,      0 },<br>
+  { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm,   TB_NO_REVERSE },<br>
+  { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,   TB_NO_REVERSE },<br>
+  { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm,   TB_NO_REVERSE },<br>
+  { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,   TB_NO_REVERSE },<br>
+  { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm,   TB_NO_REVERSE },<br>
+  { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,   TB_NO_REVERSE },<br>
+  { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm,   TB_NO_REVERSE },<br>
+  { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,   TB_NO_REVERSE },<br>
+  { X86::VPERMPDYri,   X86::VPERMPDYmi,     0 },<br>
+  { X86::VPERMQYri,    X86::VPERMQYmi,      0 },<br>
+  { X86::VPMOVSXBDYrr,  X86::VPMOVSXBDYrm,    TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBQYrr,  X86::VPMOVSXBQYrm,    TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWYrr,  X86::VPMOVSXBWYrm,    0 },<br>
+  { X86::VPMOVSXDQYrr,  X86::VPMOVSXDQYrm,    0 },<br>
+  { X86::VPMOVSXWDYrr,  X86::VPMOVSXWDYrm,    0 },<br>
+  { X86::VPMOVSXWQYrr,  X86::VPMOVSXWQYrm,    TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBDYrr,  X86::VPMOVZXBDYrm,    TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBQYrr,  X86::VPMOVZXBQYrm,    TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWYrr,  X86::VPMOVZXBWYrm,    0 },<br>
+  { X86::VPMOVZXDQYrr,  X86::VPMOVZXDQYrm,    0 },<br>
+  { X86::VPMOVZXWDYrr,  X86::VPMOVZXWDYrm,    0 },<br>
+  { X86::VPMOVZXWQYrr,  X86::VPMOVZXWQYrm,    TB_NO_REVERSE },<br>
+  { X86::VPSHUFDYri,   X86::VPSHUFDYmi,     0 },<br>
+  { X86::VPSHUFHWYri,   X86::VPSHUFHWYmi,     0 },<br>
+  { X86::VPSHUFLWYri,   X86::VPSHUFLWYmi,     0 },<br>
+<br>
+Â Â // XOP foldable instructions<br>
+  { X86::VFRCZPDrr,     X86::VFRCZPDrm,    0 },<br>
+  { X86::VFRCZPDrrY,     X86::VFRCZPDrmY,    0 },<br>
+  { X86::VFRCZPSrr,     X86::VFRCZPSrm,    0 },<br>
+  { X86::VFRCZPSrrY,     X86::VFRCZPSrmY,    0 },<br>
+  { X86::VFRCZSDrr,     X86::VFRCZSDrm,    0 },<br>
+  { X86::VFRCZSSrr,     X86::VFRCZSSrm,    0 },<br>
+  { X86::VPHADDBDrr,     X86::VPHADDBDrm,    0 },<br>
+  { X86::VPHADDBQrr,     X86::VPHADDBQrm,    0 },<br>
+  { X86::VPHADDBWrr,     X86::VPHADDBWrm,    0 },<br>
+  { X86::VPHADDDQrr,     X86::VPHADDDQrm,    0 },<br>
+  { X86::VPHADDWDrr,     X86::VPHADDWDrm,    0 },<br>
+  { X86::VPHADDWQrr,     X86::VPHADDWQrm,    0 },<br>
+  { X86::VPHADDUBDrr,    X86::VPHADDUBDrm,   0 },<br>
+  { X86::VPHADDUBQrr,    X86::VPHADDUBQrm,   0 },<br>
+  { X86::VPHADDUBWrr,    X86::VPHADDUBWrm,   0 },<br>
+  { X86::VPHADDUDQrr,    X86::VPHADDUDQrm,   0 },<br>
+  { X86::VPHADDUWDrr,    X86::VPHADDUWDrm,   0 },<br>
+  { X86::VPHADDUWQrr,    X86::VPHADDUWQrm,   0 },<br>
+  { X86::VPHSUBBWrr,     X86::VPHSUBBWrm,    0 },<br>
+  { X86::VPHSUBDQrr,     X86::VPHSUBDQrm,    0 },<br>
+  { X86::VPHSUBWDrr,     X86::VPHSUBWDrm,    0 },<br>
+  { X86::VPROTBri,      X86::VPROTBmi,     0 },<br>
+  { X86::VPROTBrr,      X86::VPROTBmr,     0 },<br>
+  { X86::VPROTDri,      X86::VPROTDmi,     0 },<br>
+  { X86::VPROTDrr,      X86::VPROTDmr,     0 },<br>
+  { X86::VPROTQri,      X86::VPROTQmi,     0 },<br>
+  { X86::VPROTQrr,      X86::VPROTQmr,     0 },<br>
+  { X86::VPROTWri,      X86::VPROTWmi,     0 },<br>
+  { X86::VPROTWrr,      X86::VPROTWmr,     0 },<br>
+  { X86::VPSHABrr,      X86::VPSHABmr,     0 },<br>
+  { X86::VPSHADrr,      X86::VPSHADmr,     0 },<br>
+  { X86::VPSHAQrr,      X86::VPSHAQmr,     0 },<br>
+  { X86::VPSHAWrr,      X86::VPSHAWmr,     0 },<br>
+  { X86::VPSHLBrr,      X86::VPSHLBmr,     0 },<br>
+  { X86::VPSHLDrr,      X86::VPSHLDmr,     0 },<br>
+  { X86::VPSHLQrr,      X86::VPSHLQmr,     0 },<br>
+  { X86::VPSHLWrr,      X86::VPSHLWmr,     0 },<br>
+<br>
+Â Â // LWP foldable instructions<br>
+  { X86::LWPINS32rri,    X86::LWPINS32rmi,   0 },<br>
+  { X86::LWPINS64rri,    X86::LWPINS64rmi,   0 },<br>
+  { X86::LWPVAL32rri,    X86::LWPVAL32rmi,   0 },<br>
+  { X86::LWPVAL64rri,    X86::LWPVAL64rmi,   0 },<br>
+<br>
+Â Â // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions<br>
+  { X86::BEXTR32rr,    X86::BEXTR32rm,      0 },<br>
+  { X86::BEXTR64rr,    X86::BEXTR64rm,      0 },<br>
+  { X86::BEXTRI32ri,   X86::BEXTRI32mi,     0 },<br>
+  { X86::BEXTRI64ri,   X86::BEXTRI64mi,     0 },<br>
+  { X86::BLCFILL32rr,   X86::BLCFILL32rm,     0 },<br>
+  { X86::BLCFILL64rr,   X86::BLCFILL64rm,     0 },<br>
+  { X86::BLCI32rr,    X86::BLCI32rm,      0 },<br>
+  { X86::BLCI64rr,    X86::BLCI64rm,      0 },<br>
+  { X86::BLCIC32rr,    X86::BLCIC32rm,      0 },<br>
+  { X86::BLCIC64rr,    X86::BLCIC64rm,      0 },<br>
+  { X86::BLCMSK32rr,   X86::BLCMSK32rm,     0 },<br>
+  { X86::BLCMSK64rr,   X86::BLCMSK64rm,     0 },<br>
+  { X86::BLCS32rr,    X86::BLCS32rm,      0 },<br>
+  { X86::BLCS64rr,    X86::BLCS64rm,      0 },<br>
+  { X86::BLSFILL32rr,   X86::BLSFILL32rm,     0 },<br>
+  { X86::BLSFILL64rr,   X86::BLSFILL64rm,     0 },<br>
+  { X86::BLSI32rr,    X86::BLSI32rm,      0 },<br>
+  { X86::BLSI64rr,    X86::BLSI64rm,      0 },<br>
+  { X86::BLSIC32rr,    X86::BLSIC32rm,      0 },<br>
+  { X86::BLSIC64rr,    X86::BLSIC64rm,      0 },<br>
+  { X86::BLSMSK32rr,   X86::BLSMSK32rm,     0 },<br>
+  { X86::BLSMSK64rr,   X86::BLSMSK64rm,     0 },<br>
+  { X86::BLSR32rr,    X86::BLSR32rm,      0 },<br>
+  { X86::BLSR64rr,    X86::BLSR64rm,      0 },<br>
+  { X86::BZHI32rr,    X86::BZHI32rm,      0 },<br>
+  { X86::BZHI64rr,    X86::BZHI64rm,      0 },<br>
+  { X86::LZCNT16rr,    X86::LZCNT16rm,      0 },<br>
+  { X86::LZCNT32rr,    X86::LZCNT32rm,      0 },<br>
+  { X86::LZCNT64rr,    X86::LZCNT64rm,      0 },<br>
+  { X86::POPCNT16rr,   X86::POPCNT16rm,     0 },<br>
+  { X86::POPCNT32rr,   X86::POPCNT32rm,     0 },<br>
+  { X86::POPCNT64rr,   X86::POPCNT64rm,     0 },<br>
+  { X86::RORX32ri,    X86::RORX32mi,      0 },<br>
+  { X86::RORX64ri,    X86::RORX64mi,      0 },<br>
+  { X86::SARX32rr,    X86::SARX32rm,      0 },<br>
+  { X86::SARX64rr,    X86::SARX64rm,      0 },<br>
+  { X86::SHRX32rr,    X86::SHRX32rm,      0 },<br>
+  { X86::SHRX64rr,    X86::SHRX64rm,      0 },<br>
+  { X86::SHLX32rr,    X86::SHLX32rm,      0 },<br>
+  { X86::SHLX64rr,    X86::SHLX64rm,      0 },<br>
+  { X86::T1MSKC32rr,   X86::T1MSKC32rm,     0 },<br>
+  { X86::T1MSKC64rr,   X86::T1MSKC64rm,     0 },<br>
+  { X86::TZCNT16rr,    X86::TZCNT16rm,      0 },<br>
+  { X86::TZCNT32rr,    X86::TZCNT32rm,      0 },<br>
+  { X86::TZCNT64rr,    X86::TZCNT64rm,      0 },<br>
+  { X86::TZMSK32rr,    X86::TZMSK32rm,      0 },<br>
+  { X86::TZMSK64rr,    X86::TZMSK64rm,      0 },<br>
+<br>
+Â Â // AVX-512 foldable instructions<br>
+  { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,   TB_NO_REVERSE },<br>
+  { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,   TB_NO_REVERSE },<br>
+  { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,   0 },<br>
+  { X86::VMOV64toSDZrr,  X86::VMOV64toSDZrm,   0 },<br>
+  { X86::VMOVDI2PDIZrr,  X86::VMOVDI2PDIZrm,   0 },<br>
+  { X86::VMOVDI2SSZrr,   X86::VMOVDI2SSZrm,    0 },<br>
+  { X86::VMOVAPDZrr,    X86::VMOVAPDZrm,     TB_ALIGN_64 },<br>
+  { X86::VMOVAPSZrr,    X86::VMOVAPSZrm,     TB_ALIGN_64 },<br>
+  { X86::VMOVDQA32Zrr,   X86::VMOVDQA32Zrm,    TB_ALIGN_64 },<br>
+  { X86::VMOVDQA64Zrr,   X86::VMOVDQA64Zrm,    TB_ALIGN_64 },<br>
+  { X86::VMOVDQU8Zrr,   X86::VMOVDQU8Zrm,    0 },<br>
+  { X86::VMOVDQU16Zrr,   X86::VMOVDQU16Zrm,    0 },<br>
+  { X86::VMOVDQU32Zrr,   X86::VMOVDQU32Zrm,    0 },<br>
+  { X86::VMOVDQU64Zrr,   X86::VMOVDQU64Zrm,    0 },<br>
+  { X86::VMOVUPDZrr,    X86::VMOVUPDZrm,     0 },<br>
+  { X86::VMOVUPSZrr,    X86::VMOVUPSZrm,     0 },<br>
+  { X86::VMOVZPQILo2PQIZrr,X86::<wbr>VMOVQI2PQIZrm,   TB_NO_REVERSE },<br>
+  { X86::VPABSBZrr,    X86::VPABSBZrm,     0 },<br>
+  { X86::VPABSDZrr,    X86::VPABSDZrm,     0 },<br>
+  { X86::VPABSQZrr,    X86::VPABSQZrm,     0 },<br>
+  { X86::VPABSWZrr,    X86::VPABSWZrm,     0 },<br>
+  { X86::VPERMILPDZri,   X86::VPERMILPDZmi,    0 },<br>
+  { X86::VPERMILPSZri,   X86::VPERMILPSZmi,    0 },<br>
+  { X86::VPERMPDZri,    X86::VPERMPDZmi,     0 },<br>
+  { X86::VPERMQZri,    X86::VPERMQZmi,     0 },<br>
+  { X86::VPMOVSXBDZrr,   X86::VPMOVSXBDZrm,    0 },<br>
+  { X86::VPMOVSXBQZrr,   X86::VPMOVSXBQZrm,    TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWZrr,   X86::VPMOVSXBWZrm,    0 },<br>
+  { X86::VPMOVSXDQZrr,   X86::VPMOVSXDQZrm,    0 },<br>
+  { X86::VPMOVSXWDZrr,   X86::VPMOVSXWDZrm,    0 },<br>
+  { X86::VPMOVSXWQZrr,   X86::VPMOVSXWQZrm,    0 },<br>
+  { X86::VPMOVZXBDZrr,   X86::VPMOVZXBDZrm,    0 },<br>
+  { X86::VPMOVZXBQZrr,   X86::VPMOVZXBQZrm,    TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWZrr,   X86::VPMOVZXBWZrm,    0 },<br>
+  { X86::VPMOVZXDQZrr,   X86::VPMOVZXDQZrm,    0 },<br>
+  { X86::VPMOVZXWDZrr,   X86::VPMOVZXWDZrm,    0 },<br>
+  { X86::VPMOVZXWQZrr,   X86::VPMOVZXWQZrm,    0 },<br>
+  { X86::VPOPCNTDZrr,   X86::VPOPCNTDZrm,    0 },<br>
+  { X86::VPOPCNTQZrr,   X86::VPOPCNTQZrm,    0 },<br>
+  { X86::VPSHUFDZri,    X86::VPSHUFDZmi,     0 },<br>
+  { X86::VPSHUFHWZri,   X86::VPSHUFHWZmi,    0 },<br>
+  { X86::VPSHUFLWZri,   X86::VPSHUFLWZmi,    0 },<br>
+  { X86::VPSLLDQZ512rr,  X86::VPSLLDQZ512rm,   0 },<br>
+  { X86::VPSLLDZri,    X86::VPSLLDZmi,     0 },<br>
+  { X86::VPSLLQZri,    X86::VPSLLQZmi,     0 },<br>
+  { X86::VPSLLWZri,    X86::VPSLLWZmi,     0 },<br>
+  { X86::VPSRADZri,    X86::VPSRADZmi,     0 },<br>
+  { X86::VPSRAQZri,    X86::VPSRAQZmi,     0 },<br>
+  { X86::VPSRAWZri,    X86::VPSRAWZmi,     0 },<br>
+  { X86::VPSRLDQZ512rr,  X86::VPSRLDQZ512rm,   0 },<br>
+  { X86::VPSRLDZri,    X86::VPSRLDZmi,     0 },<br>
+  { X86::VPSRLQZri,    X86::VPSRLQZmi,     0 },<br>
+  { X86::VPSRLWZri,    X86::VPSRLWZmi,     0 },<br>
+<br>
+Â Â // AVX-512 foldable instructions (256-bit versions)<br>
+  { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,  TB_NO_REVERSE },<br>
+  { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,  TB_NO_REVERSE },<br>
+  { X86::VMOVAPDZ256rr,    X86::VMOVAPDZ256rm,    TB_ALIGN_32 },<br>
+  { X86::VMOVAPSZ256rr,    X86::VMOVAPSZ256rm,    TB_ALIGN_32 },<br>
+  { X86::VMOVDQA32Z256rr,   X86::VMOVDQA32Z256rm,   TB_ALIGN_32 },<br>
+  { X86::VMOVDQA64Z256rr,   X86::VMOVDQA64Z256rm,   TB_ALIGN_32 },<br>
+  { X86::VMOVDQU8Z256rr,    X86::VMOVDQU8Z256rm,    0 },<br>
+  { X86::VMOVDQU16Z256rr,   X86::VMOVDQU16Z256rm,   0 },<br>
+  { X86::VMOVDQU32Z256rr,   X86::VMOVDQU32Z256rm,   0 },<br>
+  { X86::VMOVDQU64Z256rr,   X86::VMOVDQU64Z256rm,   0 },<br>
+  { X86::VMOVUPDZ256rr,    X86::VMOVUPDZ256rm,    0 },<br>
+  { X86::VMOVUPSZ256rr,    X86::VMOVUPSZ256rm,    0 },<br>
+  { X86::VPABSBZ256rr,     X86::VPABSBZ256rm,     0 },<br>
+  { X86::VPABSDZ256rr,     X86::VPABSDZ256rm,     0 },<br>
+  { X86::VPABSQZ256rr,     X86::VPABSQZ256rm,     0 },<br>
+  { X86::VPABSWZ256rr,     X86::VPABSWZ256rm,     0 },<br>
+  { X86::VPERMILPDZ256ri,   X86::VPERMILPDZ256mi,   0 },<br>
+  { X86::VPERMILPSZ256ri,   X86::VPERMILPSZ256mi,   0 },<br>
+  { X86::VPERMPDZ256ri,    X86::VPERMPDZ256mi,    0 },<br>
+  { X86::VPERMQZ256ri,     X86::VPERMQZ256mi,     0 },<br>
+  { X86::VPMOVSXBDZ256rr,   X86::VPMOVSXBDZ256rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBQZ256rr,   X86::VPMOVSXBQZ256rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWZ256rr,   X86::VPMOVSXBWZ256rm,   0 },<br>
+  { X86::VPMOVSXDQZ256rr,   X86::VPMOVSXDQZ256rm,   0 },<br>
+  { X86::VPMOVSXWDZ256rr,   X86::VPMOVSXWDZ256rm,   0 },<br>
+  { X86::VPMOVSXWQZ256rr,   X86::VPMOVSXWQZ256rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBDZ256rr,   X86::VPMOVZXBDZ256rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBQZ256rr,   X86::VPMOVZXBQZ256rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWZ256rr,   X86::VPMOVZXBWZ256rm,   0 },<br>
+  { X86::VPMOVZXDQZ256rr,   X86::VPMOVZXDQZ256rm,   0 },<br>
+  { X86::VPMOVZXWDZ256rr,   X86::VPMOVZXWDZ256rm,   0 },<br>
+  { X86::VPMOVZXWQZ256rr,   X86::VPMOVZXWQZ256rm,   TB_NO_REVERSE },<br>
+  { X86::VPSHUFDZ256ri,    X86::VPSHUFDZ256mi,    0 },<br>
+  { X86::VPSHUFHWZ256ri,    X86::VPSHUFHWZ256mi,    0 },<br>
+  { X86::VPSHUFLWZ256ri,    X86::VPSHUFLWZ256mi,    0 },<br>
+  { X86::VPSLLDQZ256rr,    X86::VPSLLDQZ256rm,    0 },<br>
+  { X86::VPSLLDZ256ri,     X86::VPSLLDZ256mi,     0 },<br>
+  { X86::VPSLLQZ256ri,     X86::VPSLLQZ256mi,     0 },<br>
+  { X86::VPSLLWZ256ri,     X86::VPSLLWZ256mi,     0 },<br>
+  { X86::VPSRADZ256ri,     X86::VPSRADZ256mi,     0 },<br>
+  { X86::VPSRAQZ256ri,     X86::VPSRAQZ256mi,     0 },<br>
+  { X86::VPSRAWZ256ri,     X86::VPSRAWZ256mi,     0 },<br>
+  { X86::VPSRLDQZ256rr,    X86::VPSRLDQZ256rm,    0 },<br>
+  { X86::VPSRLDZ256ri,     X86::VPSRLDZ256mi,     0 },<br>
+  { X86::VPSRLQZ256ri,     X86::VPSRLQZ256mi,     0 },<br>
+  { X86::VPSRLWZ256ri,     X86::VPSRLWZ256mi,     0 },<br>
+<br>
+Â Â // AVX-512 foldable instructions (128-bit versions)<br>
+  { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,  TB_NO_REVERSE },<br>
+  { X86::VMOVAPDZ128rr,    X86::VMOVAPDZ128rm,    TB_ALIGN_16 },<br>
+  { X86::VMOVAPSZ128rr,    X86::VMOVAPSZ128rm,    TB_ALIGN_16 },<br>
+  { X86::VMOVDQA32Z128rr,   X86::VMOVDQA32Z128rm,   TB_ALIGN_16 },<br>
+  { X86::VMOVDQA64Z128rr,   X86::VMOVDQA64Z128rm,   TB_ALIGN_16 },<br>
+  { X86::VMOVDQU8Z128rr,    X86::VMOVDQU8Z128rm,    0 },<br>
+  { X86::VMOVDQU16Z128rr,   X86::VMOVDQU16Z128rm,   0 },<br>
+  { X86::VMOVDQU32Z128rr,   X86::VMOVDQU32Z128rm,   0 },<br>
+  { X86::VMOVDQU64Z128rr,   X86::VMOVDQU64Z128rm,   0 },<br>
+  { X86::VMOVUPDZ128rr,    X86::VMOVUPDZ128rm,    0 },<br>
+  { X86::VMOVUPSZ128rr,    X86::VMOVUPSZ128rm,    0 },<br>
+  { X86::VPABSBZ128rr,     X86::VPABSBZ128rm,     0 },<br>
+  { X86::VPABSDZ128rr,     X86::VPABSDZ128rm,     0 },<br>
+  { X86::VPABSQZ128rr,     X86::VPABSQZ128rm,     0 },<br>
+  { X86::VPABSWZ128rr,     X86::VPABSWZ128rm,     0 },<br>
+  { X86::VPERMILPDZ128ri,   X86::VPERMILPDZ128mi,   0 },<br>
+  { X86::VPERMILPSZ128ri,   X86::VPERMILPSZ128mi,   0 },<br>
+  { X86::VPMOVSXBDZ128rr,   X86::VPMOVSXBDZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBQZ128rr,   X86::VPMOVSXBQZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWZ128rr,   X86::VPMOVSXBWZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXDQZ128rr,   X86::VPMOVSXDQZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXWDZ128rr,   X86::VPMOVSXWDZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXWQZ128rr,   X86::VPMOVSXWQZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBDZ128rr,   X86::VPMOVZXBDZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBQZ128rr,   X86::VPMOVZXBQZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWZ128rr,   X86::VPMOVZXBWZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXDQZ128rr,   X86::VPMOVZXDQZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXWDZ128rr,   X86::VPMOVZXWDZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXWQZ128rr,   X86::VPMOVZXWQZ128rm,   TB_NO_REVERSE },<br>
+  { X86::VPSHUFDZ128ri,    X86::VPSHUFDZ128mi,    0 },<br>
+  { X86::VPSHUFHWZ128ri,    X86::VPSHUFHWZ128mi,    0 },<br>
+  { X86::VPSHUFLWZ128ri,    X86::VPSHUFLWZ128mi,    0 },<br>
+  { X86::VPSLLDQZ128rr,    X86::VPSLLDQZ128rm,    0 },<br>
+  { X86::VPSLLDZ128ri,     X86::VPSLLDZ128mi,     0 },<br>
+  { X86::VPSLLQZ128ri,     X86::VPSLLQZ128mi,     0 },<br>
+  { X86::VPSLLWZ128ri,     X86::VPSLLWZ128mi,     0 },<br>
+  { X86::VPSRADZ128ri,     X86::VPSRADZ128mi,     0 },<br>
+  { X86::VPSRAQZ128ri,     X86::VPSRAQZ128mi,     0 },<br>
+  { X86::VPSRAWZ128ri,     X86::VPSRAWZ128mi,     0 },<br>
+  { X86::VPSRLDQZ128rr,    X86::VPSRLDQZ128rm,    0 },<br>
+  { X86::VPSRLDZ128ri,     X86::VPSRLDZ128mi,     0 },<br>
+  { X86::VPSRLQZ128ri,     X86::VPSRLQZ128mi,     0 },<br>
+  { X86::VPSRLWZ128ri,     X86::VPSRLWZ128mi,     0 },<br>
+<br>
+Â Â // F16C foldable instructions<br>
+  { X86::VCVTPH2PSrr,    X86::VCVTPH2PSrm,      0 },<br>
+  { X86::VCVTPH2PSYrr,    X86::VCVTPH2PSYrm,      0 },<br>
+<br>
+Â Â // AES foldable instructions<br>
+  { X86::AESIMCrr,       X86::AESIMCrm,       TB_ALIGN_16 },<br>
+  { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },<br>
+  { X86::VAESIMCrr,       X86::VAESIMCrm,       0 },<br>
+Â Â { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }<br>
+Â };<br>
+<br>
  for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {<br>
   AddTableEntry(<wbr>RegOp2MemOpTable1, MemOp2RegOpTable,<br>
          Entry.RegOp, Entry.MemOp,<br>
@@ -143,6 +1042,1396 @@ X86InstrInfo::X86InstrInfo(<wbr>X86Subtarget<br>
          Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);<br>
  }<br>
<br>
+Â static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {<br>
+  { X86::ADC32rr,     X86::ADC32rm,    0 },<br>
+  { X86::ADC64rr,     X86::ADC64rm,    0 },<br>
+  { X86::ADD16rr,     X86::ADD16rm,    0 },<br>
+  { X86::ADD16rr_DB,   X86::ADD16rm,    TB_NO_REVERSE },<br>
+  { X86::ADD32rr,     X86::ADD32rm,    0 },<br>
+  { X86::ADD32rr_DB,   X86::ADD32rm,    TB_NO_REVERSE },<br>
+  { X86::ADD64rr,     X86::ADD64rm,    0 },<br>
+  { X86::ADD64rr_DB,   X86::ADD64rm,    TB_NO_REVERSE },<br>
+  { X86::ADD8rr,     X86::ADD8rm,    0 },<br>
+  { X86::ADDPDrr,     X86::ADDPDrm,    TB_ALIGN_16 },<br>
+  { X86::ADDPSrr,     X86::ADDPSrm,    TB_ALIGN_16 },<br>
+  { X86::ADDSDrr,     X86::ADDSDrm,    0 },<br>
+  { X86::ADDSDrr_Int,   X86::ADDSDrm_Int,  TB_NO_REVERSE },<br>
+  { X86::ADDSSrr,     X86::ADDSSrm,    0 },<br>
+  { X86::ADDSSrr_Int,   X86::ADDSSrm_Int,  TB_NO_REVERSE },<br>
+  { X86::ADDSUBPDrr,   X86::ADDSUBPDrm,  TB_ALIGN_16 },<br>
+  { X86::ADDSUBPSrr,   X86::ADDSUBPSrm,  TB_ALIGN_16 },<br>
+  { X86::AND16rr,     X86::AND16rm,    0 },<br>
+  { X86::AND32rr,     X86::AND32rm,    0 },<br>
+  { X86::AND64rr,     X86::AND64rm,    0 },<br>
+  { X86::AND8rr,     X86::AND8rm,    0 },<br>
+  { X86::ANDNPDrr,    X86::ANDNPDrm,   TB_ALIGN_16 },<br>
+  { X86::ANDNPSrr,    X86::ANDNPSrm,   TB_ALIGN_16 },<br>
+  { X86::ANDPDrr,     X86::ANDPDrm,    TB_ALIGN_16 },<br>
+  { X86::ANDPSrr,     X86::ANDPSrm,    TB_ALIGN_16 },<br>
+  { X86::BLENDPDrri,   X86::BLENDPDrmi,  TB_ALIGN_16 },<br>
+  { X86::BLENDPSrri,   X86::BLENDPSrmi,  TB_ALIGN_16 },<br>
+  { X86::BLENDVPDrr0,   X86::BLENDVPDrm0,  TB_ALIGN_16 },<br>
+  { X86::BLENDVPSrr0,   X86::BLENDVPSrm0,  TB_ALIGN_16 },<br>
+  { X86::CMOVA16rr,    X86::CMOVA16rm,   0 },<br>
+  { X86::CMOVA32rr,    X86::CMOVA32rm,   0 },<br>
+  { X86::CMOVA64rr,    X86::CMOVA64rm,   0 },<br>
+  { X86::CMOVAE16rr,   X86::CMOVAE16rm,  0 },<br>
+  { X86::CMOVAE32rr,   X86::CMOVAE32rm,  0 },<br>
+  { X86::CMOVAE64rr,   X86::CMOVAE64rm,  0 },<br>
+  { X86::CMOVB16rr,    X86::CMOVB16rm,   0 },<br>
+  { X86::CMOVB32rr,    X86::CMOVB32rm,   0 },<br>
+  { X86::CMOVB64rr,    X86::CMOVB64rm,   0 },<br>
+  { X86::CMOVBE16rr,   X86::CMOVBE16rm,  0 },<br>
+  { X86::CMOVBE32rr,   X86::CMOVBE32rm,  0 },<br>
+  { X86::CMOVBE64rr,   X86::CMOVBE64rm,  0 },<br>
+  { X86::CMOVE16rr,    X86::CMOVE16rm,   0 },<br>
+  { X86::CMOVE32rr,    X86::CMOVE32rm,   0 },<br>
+  { X86::CMOVE64rr,    X86::CMOVE64rm,   0 },<br>
+  { X86::CMOVG16rr,    X86::CMOVG16rm,   0 },<br>
+  { X86::CMOVG32rr,    X86::CMOVG32rm,   0 },<br>
+  { X86::CMOVG64rr,    X86::CMOVG64rm,   0 },<br>
+  { X86::CMOVGE16rr,   X86::CMOVGE16rm,  0 },<br>
+  { X86::CMOVGE32rr,   X86::CMOVGE32rm,  0 },<br>
+  { X86::CMOVGE64rr,   X86::CMOVGE64rm,  0 },<br>
+  { X86::CMOVL16rr,    X86::CMOVL16rm,   0 },<br>
+  { X86::CMOVL32rr,    X86::CMOVL32rm,   0 },<br>
+  { X86::CMOVL64rr,    X86::CMOVL64rm,   0 },<br>
+  { X86::CMOVLE16rr,   X86::CMOVLE16rm,  0 },<br>
+  { X86::CMOVLE32rr,   X86::CMOVLE32rm,  0 },<br>
+  { X86::CMOVLE64rr,   X86::CMOVLE64rm,  0 },<br>
+  { X86::CMOVNE16rr,   X86::CMOVNE16rm,  0 },<br>
+  { X86::CMOVNE32rr,   X86::CMOVNE32rm,  0 },<br>
+  { X86::CMOVNE64rr,   X86::CMOVNE64rm,  0 },<br>
+  { X86::CMOVNO16rr,   X86::CMOVNO16rm,  0 },<br>
+  { X86::CMOVNO32rr,   X86::CMOVNO32rm,  0 },<br>
+  { X86::CMOVNO64rr,   X86::CMOVNO64rm,  0 },<br>
+  { X86::CMOVNP16rr,   X86::CMOVNP16rm,  0 },<br>
+  { X86::CMOVNP32rr,   X86::CMOVNP32rm,  0 },<br>
+  { X86::CMOVNP64rr,   X86::CMOVNP64rm,  0 },<br>
+  { X86::CMOVNS16rr,   X86::CMOVNS16rm,  0 },<br>
+  { X86::CMOVNS32rr,   X86::CMOVNS32rm,  0 },<br>
+  { X86::CMOVNS64rr,   X86::CMOVNS64rm,  0 },<br>
+  { X86::CMOVO16rr,    X86::CMOVO16rm,   0 },<br>
+  { X86::CMOVO32rr,    X86::CMOVO32rm,   0 },<br>
+  { X86::CMOVO64rr,    X86::CMOVO64rm,   0 },<br>
+  { X86::CMOVP16rr,    X86::CMOVP16rm,   0 },<br>
+  { X86::CMOVP32rr,    X86::CMOVP32rm,   0 },<br>
+  { X86::CMOVP64rr,    X86::CMOVP64rm,   0 },<br>
+  { X86::CMOVS16rr,    X86::CMOVS16rm,   0 },<br>
+  { X86::CMOVS32rr,    X86::CMOVS32rm,   0 },<br>
+  { X86::CMOVS64rr,    X86::CMOVS64rm,   0 },<br>
+  { X86::CMPPDrri,    X86::CMPPDrmi,   TB_ALIGN_16 },<br>
+  { X86::CMPPSrri,    X86::CMPPSrmi,   TB_ALIGN_16 },<br>
+  { X86::CMPSDrr,     X86::CMPSDrm,    0 },<br>
+  { X86::CMPSSrr,     X86::CMPSSrm,    0 },<br>
+  { X86::CRC32r32r32,   X86::CRC32r32m32,  0 },<br>
+  { X86::CRC32r64r64,   X86::CRC32r64m64,  0 },<br>
+  { X86::DIVPDrr,     X86::DIVPDrm,    TB_ALIGN_16 },<br>
+  { X86::DIVPSrr,     X86::DIVPSrm,    TB_ALIGN_16 },<br>
+  { X86::DIVSDrr,     X86::DIVSDrm,    0 },<br>
+  { X86::DIVSDrr_Int,   X86::DIVSDrm_Int,  TB_NO_REVERSE },<br>
+  { X86::DIVSSrr,     X86::DIVSSrm,    0 },<br>
+  { X86::DIVSSrr_Int,   X86::DIVSSrm_Int,  TB_NO_REVERSE },<br>
+  { X86::DPPDrri,     X86::DPPDrmi,    TB_ALIGN_16 },<br>
+  { X86::DPPSrri,     X86::DPPSrmi,    TB_ALIGN_16 },<br>
+  { X86::HADDPDrr,    X86::HADDPDrm,   TB_ALIGN_16 },<br>
+  { X86::HADDPSrr,    X86::HADDPSrm,   TB_ALIGN_16 },<br>
+  { X86::HSUBPDrr,    X86::HSUBPDrm,   TB_ALIGN_16 },<br>
+  { X86::HSUBPSrr,    X86::HSUBPSrm,   TB_ALIGN_16 },<br>
+  { X86::IMUL16rr,    X86::IMUL16rm,   0 },<br>
+  { X86::IMUL32rr,    X86::IMUL32rm,   0 },<br>
+  { X86::IMUL64rr,    X86::IMUL64rm,   0 },<br>
+  { X86::Int_CMPSDrr,   X86::Int_CMPSDrm,  TB_NO_REVERSE },<br>
+  { X86::Int_CMPSSrr,   X86::Int_CMPSSrm,  TB_NO_REVERSE },<br>
+  { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm,   TB_NO_REVERSE },<br>
+  { X86::Int_CVTSI2SD64rr,X86::<wbr>Int_CVTSI2SD64rm,  0 },<br>
+  { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm,   0 },<br>
+  { X86::Int_CVTSI2SS64rr,X86::<wbr>Int_CVTSI2SS64rm,  0 },<br>
+  { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm,   0 },<br>
+  { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm,   TB_NO_REVERSE },<br>
+  { X86::MAXPDrr,     X86::MAXPDrm,    TB_ALIGN_16 },<br>
+  { X86::MAXCPDrr,    X86::MAXCPDrm,   TB_ALIGN_16 },<br>
+  { X86::MAXPSrr,     X86::MAXPSrm,    TB_ALIGN_16 },<br>
+  { X86::MAXCPSrr,    X86::MAXCPSrm,   TB_ALIGN_16 },<br>
+  { X86::MAXSDrr,     X86::MAXSDrm,    0 },<br>
+  { X86::MAXCSDrr,    X86::MAXCSDrm,   0 },<br>
+  { X86::MAXSDrr_Int,   X86::MAXSDrm_Int,  TB_NO_REVERSE },<br>
+  { X86::MAXSSrr,     X86::MAXSSrm,    0 },<br>
+  { X86::MAXCSSrr,    X86::MAXCSSrm,   0 },<br>
+  { X86::MAXSSrr_Int,   X86::MAXSSrm_Int,  TB_NO_REVERSE },<br>
+  { X86::MINPDrr,     X86::MINPDrm,    TB_ALIGN_16 },<br>
+  { X86::MINCPDrr,    X86::MINCPDrm,   TB_ALIGN_16 },<br>
+  { X86::MINPSrr,     X86::MINPSrm,    TB_ALIGN_16 },<br>
+  { X86::MINCPSrr,    X86::MINCPSrm,   TB_ALIGN_16 },<br>
+  { X86::MINSDrr,     X86::MINSDrm,    0 },<br>
+  { X86::MINCSDrr,    X86::MINCSDrm,   0 },<br>
+  { X86::MINSDrr_Int,   X86::MINSDrm_Int,  TB_NO_REVERSE },<br>
+  { X86::MINSSrr,     X86::MINSSrm,    0 },<br>
+  { X86::MINCSSrr,    X86::MINCSSrm,   0 },<br>
+  { X86::MINSSrr_Int,   X86::MINSSrm_Int,  TB_NO_REVERSE },<br>
+  { X86::MOVLHPSrr,    X86::MOVHPSrm,   TB_NO_REVERSE },<br>
+  { X86::MPSADBWrri,   X86::MPSADBWrmi,  TB_ALIGN_16 },<br>
+  { X86::MULPDrr,     X86::MULPDrm,    TB_ALIGN_16 },<br>
+  { X86::MULPSrr,     X86::MULPSrm,    TB_ALIGN_16 },<br>
+  { X86::MULSDrr,     X86::MULSDrm,    0 },<br>
+  { X86::MULSDrr_Int,   X86::MULSDrm_Int,  TB_NO_REVERSE },<br>
+  { X86::MULSSrr,     X86::MULSSrm,    0 },<br>
+  { X86::MULSSrr_Int,   X86::MULSSrm_Int,  TB_NO_REVERSE },<br>
+  { X86::OR16rr,     X86::OR16rm,    0 },<br>
+  { X86::OR32rr,     X86::OR32rm,    0 },<br>
+  { X86::OR64rr,     X86::OR64rm,    0 },<br>
+  { X86::OR8rr,      X86::OR8rm,     0 },<br>
+  { X86::ORPDrr,     X86::ORPDrm,    TB_ALIGN_16 },<br>
+  { X86::ORPSrr,     X86::ORPSrm,    TB_ALIGN_16 },<br>
+  { X86::PACKSSDWrr,   X86::PACKSSDWrm,  TB_ALIGN_16 },<br>
+  { X86::PACKSSWBrr,   X86::PACKSSWBrm,  TB_ALIGN_16 },<br>
+  { X86::PACKUSDWrr,   X86::PACKUSDWrm,  TB_ALIGN_16 },<br>
+  { X86::PACKUSWBrr,   X86::PACKUSWBrm,  TB_ALIGN_16 },<br>
+  { X86::PADDBrr,     X86::PADDBrm,    TB_ALIGN_16 },<br>
+  { X86::PADDDrr,     X86::PADDDrm,    TB_ALIGN_16 },<br>
+  { X86::PADDQrr,     X86::PADDQrm,    TB_ALIGN_16 },<br>
+  { X86::PADDSBrr,    X86::PADDSBrm,   TB_ALIGN_16 },<br>
+  { X86::PADDSWrr,    X86::PADDSWrm,   TB_ALIGN_16 },<br>
+  { X86::PADDUSBrr,    X86::PADDUSBrm,   TB_ALIGN_16 },<br>
+  { X86::PADDUSWrr,    X86::PADDUSWrm,   TB_ALIGN_16 },<br>
+  { X86::PADDWrr,     X86::PADDWrm,    TB_ALIGN_16 },<br>
+  { X86::PALIGNRrri,   X86::PALIGNRrmi,  TB_ALIGN_16 },<br>
+  { X86::PANDNrr,     X86::PANDNrm,    TB_ALIGN_16 },<br>
+  { X86::PANDrr,     X86::PANDrm,    TB_ALIGN_16 },<br>
+  { X86::PAVGBrr,     X86::PAVGBrm,    TB_ALIGN_16 },<br>
+  { X86::PAVGWrr,     X86::PAVGWrm,    TB_ALIGN_16 },<br>
+  { X86::PBLENDVBrr0,   X86::PBLENDVBrm0,  TB_ALIGN_16 },<br>
+  { X86::PBLENDWrri,   X86::PBLENDWrmi,  TB_ALIGN_16 },<br>
+  { X86::PCLMULQDQrr,   X86::PCLMULQDQrm,  TB_ALIGN_16 },<br>
+  { X86::PCMPEQBrr,    X86::PCMPEQBrm,   TB_ALIGN_16 },<br>
+  { X86::PCMPEQDrr,    X86::PCMPEQDrm,   TB_ALIGN_16 },<br>
+  { X86::PCMPEQQrr,    X86::PCMPEQQrm,   TB_ALIGN_16 },<br>
+  { X86::PCMPEQWrr,    X86::PCMPEQWrm,   TB_ALIGN_16 },<br>
+  { X86::PCMPGTBrr,    X86::PCMPGTBrm,   TB_ALIGN_16 },<br>
+  { X86::PCMPGTDrr,    X86::PCMPGTDrm,   TB_ALIGN_16 },<br>
+  { X86::PCMPGTQrr,    X86::PCMPGTQrm,   TB_ALIGN_16 },<br>
+  { X86::PCMPGTWrr,    X86::PCMPGTWrm,   TB_ALIGN_16 },<br>
+  { X86::PHADDDrr,    X86::PHADDDrm,   TB_ALIGN_16 },<br>
+  { X86::PHADDWrr,    X86::PHADDWrm,   TB_ALIGN_16 },<br>
+  { X86::PHADDSWrr128,  X86::PHADDSWrm128, TB_ALIGN_16 },<br>
+  { X86::PHSUBDrr,    X86::PHSUBDrm,   TB_ALIGN_16 },<br>
+  { X86::PHSUBSWrr128,  X86::PHSUBSWrm128, TB_ALIGN_16 },<br>
+  { X86::PHSUBWrr,    X86::PHSUBWrm,   TB_ALIGN_16 },<br>
+  { X86::PINSRBrr,    X86::PINSRBrm,   0 },<br>
+  { X86::PINSRDrr,    X86::PINSRDrm,   0 },<br>
+  { X86::PINSRQrr,    X86::PINSRQrm,   0 },<br>
+  { X86::PINSRWrri,    X86::PINSRWrmi,   0 },<br>
+  { X86::PMADDUBSWrr,   X86::PMADDUBSWrm,  TB_ALIGN_16 },<br>
+  { X86::PMADDWDrr,    X86::PMADDWDrm,   TB_ALIGN_16 },<br>
+  { X86::PMAXSBrr,    X86::PMAXSBrm,   TB_ALIGN_16 },<br>
+  { X86::PMAXSDrr,    X86::PMAXSDrm,   TB_ALIGN_16 },<br>
+  { X86::PMAXSWrr,    X86::PMAXSWrm,   TB_ALIGN_16 },<br>
+  { X86::PMAXUBrr,    X86::PMAXUBrm,   TB_ALIGN_16 },<br>
+  { X86::PMAXUDrr,    X86::PMAXUDrm,   TB_ALIGN_16 },<br>
+  { X86::PMAXUWrr,    X86::PMAXUWrm,   TB_ALIGN_16 },<br>
+  { X86::PMINSBrr,    X86::PMINSBrm,   TB_ALIGN_16 },<br>
+  { X86::PMINSDrr,    X86::PMINSDrm,   TB_ALIGN_16 },<br>
+  { X86::PMINSWrr,    X86::PMINSWrm,   TB_ALIGN_16 },<br>
+  { X86::PMINUBrr,    X86::PMINUBrm,   TB_ALIGN_16 },<br>
+  { X86::PMINUDrr,    X86::PMINUDrm,   TB_ALIGN_16 },<br>
+  { X86::PMINUWrr,    X86::PMINUWrm,   TB_ALIGN_16 },<br>
+  { X86::PMULDQrr,    X86::PMULDQrm,   TB_ALIGN_16 },<br>
+  { X86::PMULHRSWrr,   X86::PMULHRSWrm,  TB_ALIGN_16 },<br>
+  { X86::PMULHUWrr,    X86::PMULHUWrm,   TB_ALIGN_16 },<br>
+  { X86::PMULHWrr,    X86::PMULHWrm,   TB_ALIGN_16 },<br>
+  { X86::PMULLDrr,    X86::PMULLDrm,   TB_ALIGN_16 },<br>
+  { X86::PMULLWrr,    X86::PMULLWrm,   TB_ALIGN_16 },<br>
+  { X86::PMULUDQrr,    X86::PMULUDQrm,   TB_ALIGN_16 },<br>
+  { X86::PORrr,      X86::PORrm,     TB_ALIGN_16 },<br>
+  { X86::PSADBWrr,    X86::PSADBWrm,   TB_ALIGN_16 },<br>
+  { X86::PSHUFBrr,    X86::PSHUFBrm,   TB_ALIGN_16 },<br>
+  { X86::PSIGNBrr128,   X86::PSIGNBrm128,  TB_ALIGN_16 },<br>
+  { X86::PSIGNWrr128,   X86::PSIGNWrm128,  TB_ALIGN_16 },<br>
+  { X86::PSIGNDrr128,   X86::PSIGNDrm128,  TB_ALIGN_16 },<br>
+  { X86::PSLLDrr,     X86::PSLLDrm,    TB_ALIGN_16 },<br>
+  { X86::PSLLQrr,     X86::PSLLQrm,    TB_ALIGN_16 },<br>
+  { X86::PSLLWrr,     X86::PSLLWrm,    TB_ALIGN_16 },<br>
+  { X86::PSRADrr,     X86::PSRADrm,    TB_ALIGN_16 },<br>
+  { X86::PSRAWrr,     X86::PSRAWrm,    TB_ALIGN_16 },<br>
+  { X86::PSRLDrr,     X86::PSRLDrm,    TB_ALIGN_16 },<br>
+  { X86::PSRLQrr,     X86::PSRLQrm,    TB_ALIGN_16 },<br>
+  { X86::PSRLWrr,     X86::PSRLWrm,    TB_ALIGN_16 },<br>
+  { X86::PSUBBrr,     X86::PSUBBrm,    TB_ALIGN_16 },<br>
+  { X86::PSUBDrr,     X86::PSUBDrm,    TB_ALIGN_16 },<br>
+  { X86::PSUBQrr,     X86::PSUBQrm,    TB_ALIGN_16 },<br>
+  { X86::PSUBSBrr,    X86::PSUBSBrm,   TB_ALIGN_16 },<br>
+  { X86::PSUBSWrr,    X86::PSUBSWrm,   TB_ALIGN_16 },<br>
+  { X86::PSUBUSBrr,    X86::PSUBUSBrm,   TB_ALIGN_16 },<br>
+  { X86::PSUBUSWrr,    X86::PSUBUSWrm,   TB_ALIGN_16 },<br>
+  { X86::PSUBWrr,     X86::PSUBWrm,    TB_ALIGN_16 },<br>
+  { X86::PUNPCKHBWrr,   X86::PUNPCKHBWrm,  TB_ALIGN_16 },<br>
+  { X86::PUNPCKHDQrr,   X86::PUNPCKHDQrm,  TB_ALIGN_16 },<br>
+  { X86::PUNPCKHQDQrr,  X86::PUNPCKHQDQrm, TB_ALIGN_16 },<br>
+  { X86::PUNPCKHWDrr,   X86::PUNPCKHWDrm,  TB_ALIGN_16 },<br>
+  { X86::PUNPCKLBWrr,   X86::PUNPCKLBWrm,  TB_ALIGN_16 },<br>
+  { X86::PUNPCKLDQrr,   X86::PUNPCKLDQrm,  TB_ALIGN_16 },<br>
+  { X86::PUNPCKLQDQrr,  X86::PUNPCKLQDQrm, TB_ALIGN_16 },<br>
+  { X86::PUNPCKLWDrr,   X86::PUNPCKLWDrm,  TB_ALIGN_16 },<br>
+  { X86::PXORrr,     X86::PXORrm,    TB_ALIGN_16 },<br>
+  { X86::ROUNDSDr_Int,  X86::ROUNDSDm_Int, TB_NO_REVERSE },<br>
+  { X86::ROUNDSSr_Int,  X86::ROUNDSSm_Int, TB_NO_REVERSE },<br>
+  { X86::SBB32rr,     X86::SBB32rm,    0 },<br>
+  { X86::SBB64rr,     X86::SBB64rm,    0 },<br>
+  { X86::SHUFPDrri,    X86::SHUFPDrmi,   TB_ALIGN_16 },<br>
+  { X86::SHUFPSrri,    X86::SHUFPSrmi,   TB_ALIGN_16 },<br>
+  { X86::SUB16rr,     X86::SUB16rm,    0 },<br>
+  { X86::SUB32rr,     X86::SUB32rm,    0 },<br>
+  { X86::SUB64rr,     X86::SUB64rm,    0 },<br>
+  { X86::SUB8rr,     X86::SUB8rm,    0 },<br>
+  { X86::SUBPDrr,     X86::SUBPDrm,    TB_ALIGN_16 },<br>
+  { X86::SUBPSrr,     X86::SUBPSrm,    TB_ALIGN_16 },<br>
+  { X86::SUBSDrr,     X86::SUBSDrm,    0 },<br>
+  { X86::SUBSDrr_Int,   X86::SUBSDrm_Int,  TB_NO_REVERSE },<br>
+  { X86::SUBSSrr,     X86::SUBSSrm,    0 },<br>
+  { X86::SUBSSrr_Int,   X86::SUBSSrm_Int,  TB_NO_REVERSE },<br>
+Â Â // FIXME: TEST*rr -> swapped operand of TEST*mr.<br>
+  { X86::UNPCKHPDrr,   X86::UNPCKHPDrm,  TB_ALIGN_16 },<br>
+  { X86::UNPCKHPSrr,   X86::UNPCKHPSrm,  TB_ALIGN_16 },<br>
+  { X86::UNPCKLPDrr,   X86::UNPCKLPDrm,  TB_ALIGN_16 },<br>
+  { X86::UNPCKLPSrr,   X86::UNPCKLPSrm,  TB_ALIGN_16 },<br>
+  { X86::XOR16rr,     X86::XOR16rm,    0 },<br>
+  { X86::XOR32rr,     X86::XOR32rm,    0 },<br>
+  { X86::XOR64rr,     X86::XOR64rm,    0 },<br>
+  { X86::XOR8rr,     X86::XOR8rm,    0 },<br>
+  { X86::XORPDrr,     X86::XORPDrm,    TB_ALIGN_16 },<br>
+  { X86::XORPSrr,     X86::XORPSrm,    TB_ALIGN_16 },<br>
+<br>
+Â Â // MMX version of foldable instructions<br>
+  { X86::MMX_CVTPI2PSirr,  X86::MMX_CVTPI2PSirm,  0 },<br>
+  { X86::MMX_PACKSSDWirr,  X86::MMX_PACKSSDWirm,  0 },<br>
+  { X86::MMX_PACKSSWBirr,  X86::MMX_PACKSSWBirm,  0 },<br>
+  { X86::MMX_PACKUSWBirr,  X86::MMX_PACKUSWBirm,  0 },<br>
+  { X86::MMX_PADDBirr,   X86::MMX_PADDBirm,   0 },<br>
+  { X86::MMX_PADDDirr,   X86::MMX_PADDDirm,   0 },<br>
+  { X86::MMX_PADDQirr,   X86::MMX_PADDQirm,   0 },<br>
+  { X86::MMX_PADDSBirr,   X86::MMX_PADDSBirm,   0 },<br>
+  { X86::MMX_PADDSWirr,   X86::MMX_PADDSWirm,   0 },<br>
+  { X86::MMX_PADDUSBirr,  X86::MMX_PADDUSBirm,  0 },<br>
+  { X86::MMX_PADDUSWirr,  X86::MMX_PADDUSWirm,  0 },<br>
+  { X86::MMX_PADDWirr,   X86::MMX_PADDWirm,   0 },<br>
+  { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },<br>
+  { X86::MMX_PANDNirr,   X86::MMX_PANDNirm,   0 },<br>
+  { X86::MMX_PANDirr,    X86::MMX_PANDirm,    0 },<br>
+  { X86::MMX_PAVGBirr,   X86::MMX_PAVGBirm,   0 },<br>
+  { X86::MMX_PAVGWirr,   X86::MMX_PAVGWirm,   0 },<br>
+  { X86::MMX_PCMPEQBirr,  X86::MMX_PCMPEQBirm,  0 },<br>
+  { X86::MMX_PCMPEQDirr,  X86::MMX_PCMPEQDirm,  0 },<br>
+  { X86::MMX_PCMPEQWirr,  X86::MMX_PCMPEQWirm,  0 },<br>
+  { X86::MMX_PCMPGTBirr,  X86::MMX_PCMPGTBirm,  0 },<br>
+  { X86::MMX_PCMPGTDirr,  X86::MMX_PCMPGTDirm,  0 },<br>
+  { X86::MMX_PCMPGTWirr,  X86::MMX_PCMPGTWirm,  0 },<br>
+  { X86::MMX_PHADDSWrr64,  X86::MMX_PHADDSWrm64,  0 },<br>
+  { X86::MMX_PHADDWrr64,  X86::MMX_PHADDWrm64,  0 },<br>
+  { X86::MMX_PHADDrr64,   X86::MMX_PHADDrm64,   0 },<br>
+  { X86::MMX_PHSUBDrr64,  X86::MMX_PHSUBDrm64,  0 },<br>
+  { X86::MMX_PHSUBSWrr64,  X86::MMX_PHSUBSWrm64,  0 },<br>
+  { X86::MMX_PHSUBWrr64,  X86::MMX_PHSUBWrm64,  0 },<br>
+  { X86::MMX_PINSRWirri,  X86::MMX_PINSRWirmi,  0 },<br>
+Â Â { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },<br>
+  { X86::MMX_PMADDWDirr,  X86::MMX_PMADDWDirm,  0 },<br>
+  { X86::MMX_PMAXSWirr,   X86::MMX_PMAXSWirm,   0 },<br>
+  { X86::MMX_PMAXUBirr,   X86::MMX_PMAXUBirm,   0 },<br>
+  { X86::MMX_PMINSWirr,   X86::MMX_PMINSWirm,   0 },<br>
+  { X86::MMX_PMINUBirr,   X86::MMX_PMINUBirm,   0 },<br>
+  { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },<br>
+  { X86::MMX_PMULHUWirr,  X86::MMX_PMULHUWirm,  0 },<br>
+  { X86::MMX_PMULHWirr,   X86::MMX_PMULHWirm,   0 },<br>
+  { X86::MMX_PMULLWirr,   X86::MMX_PMULLWirm,   0 },<br>
+  { X86::MMX_PMULUDQirr,  X86::MMX_PMULUDQirm,  0 },<br>
+  { X86::MMX_PORirr,    X86::MMX_PORirm,    0 },<br>
+  { X86::MMX_PSADBWirr,   X86::MMX_PSADBWirm,   0 },<br>
+  { X86::MMX_PSHUFBrr64,  X86::MMX_PSHUFBrm64,  0 },<br>
+  { X86::MMX_PSIGNBrr64,  X86::MMX_PSIGNBrm64,  0 },<br>
+  { X86::MMX_PSIGNDrr64,  X86::MMX_PSIGNDrm64,  0 },<br>
+  { X86::MMX_PSIGNWrr64,  X86::MMX_PSIGNWrm64,  0 },<br>
+  { X86::MMX_PSLLDrr,    X86::MMX_PSLLDrm,    0 },<br>
+  { X86::MMX_PSLLQrr,    X86::MMX_PSLLQrm,    0 },<br>
+  { X86::MMX_PSLLWrr,    X86::MMX_PSLLWrm,    0 },<br>
+  { X86::MMX_PSRADrr,    X86::MMX_PSRADrm,    0 },<br>
+  { X86::MMX_PSRAWrr,    X86::MMX_PSRAWrm,    0 },<br>
+  { X86::MMX_PSRLDrr,    X86::MMX_PSRLDrm,    0 },<br>
+  { X86::MMX_PSRLQrr,    X86::MMX_PSRLQrm,    0 },<br>
+  { X86::MMX_PSRLWrr,    X86::MMX_PSRLWrm,    0 },<br>
+  { X86::MMX_PSUBBirr,   X86::MMX_PSUBBirm,   0 },<br>
+  { X86::MMX_PSUBDirr,   X86::MMX_PSUBDirm,   0 },<br>
+  { X86::MMX_PSUBQirr,   X86::MMX_PSUBQirm,   0 },<br>
+  { X86::MMX_PSUBSBirr,   X86::MMX_PSUBSBirm,   0 },<br>
+  { X86::MMX_PSUBSWirr,   X86::MMX_PSUBSWirm,   0 },<br>
+  { X86::MMX_PSUBUSBirr,  X86::MMX_PSUBUSBirm,  0 },<br>
+  { X86::MMX_PSUBUSWirr,  X86::MMX_PSUBUSWirm,  0 },<br>
+  { X86::MMX_PSUBWirr,   X86::MMX_PSUBWirm,   0 },<br>
+  { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },<br>
+  { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },<br>
+  { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },<br>
+  { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },<br>
+  { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },<br>
+  { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },<br>
+  { X86::MMX_PXORirr,    X86::MMX_PXORirm,    0 },<br>
+<br>
+Â Â // 3DNow! version of foldable instructions<br>
+  { X86::PAVGUSBrr,     X86::PAVGUSBrm,     0 },<br>
+  { X86::PFACCrr,      X86::PFACCrm,      0 },<br>
+  { X86::PFADDrr,      X86::PFADDrm,      0 },<br>
+  { X86::PFCMPEQrr,     X86::PFCMPEQrm,     0 },<br>
+  { X86::PFCMPGErr,     X86::PFCMPGErm,     0 },<br>
+  { X86::PFCMPGTrr,     X86::PFCMPGTrm,     0 },<br>
+  { X86::PFMAXrr,      X86::PFMAXrm,      0 },<br>
+  { X86::PFMINrr,      X86::PFMINrm,      0 },<br>
+  { X86::PFMULrr,      X86::PFMULrm,      0 },<br>
+  { X86::PFNACCrr,     X86::PFNACCrm,     0 },<br>
+  { X86::PFPNACCrr,     X86::PFPNACCrm,     0 },<br>
+  { X86::PFRCPIT1rr,    X86::PFRCPIT1rm,    0 },<br>
+  { X86::PFRCPIT2rr,    X86::PFRCPIT2rm,    0 },<br>
+  { X86::PFRSQIT1rr,    X86::PFRSQIT1rm,    0 },<br>
+  { X86::PFSUBrr,      X86::PFSUBrm,      0 },<br>
+  { X86::PFSUBRrr,     X86::PFSUBRrm,     0 },<br>
+  { X86::PMULHRWrr,     X86::PMULHRWrm,     0 },<br>
+<br>
+Â Â // AVX 128-bit versions of foldable instructions<br>
+  { X86::VCVTSI2SD64rr,   X86::VCVTSI2SD64rm,   0 },<br>
+  { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },<br>
+  { X86::VCVTSI2SDrr,    X86::VCVTSI2SDrm,    0 },<br>
+  { X86::Int_VCVTSI2SDrr,  X86::Int_VCVTSI2SDrm,  0 },<br>
+  { X86::VCVTSI2SS64rr,   X86::VCVTSI2SS64rm,   0 },<br>
+  { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },<br>
+  { X86::VCVTSI2SSrr,    X86::VCVTSI2SSrm,    0 },<br>
+  { X86::Int_VCVTSI2SSrr,  X86::Int_VCVTSI2SSrm,  0 },<br>
+  { X86::VADDPDrr,     X86::VADDPDrm,      0 },<br>
+  { X86::VADDPSrr,     X86::VADDPSrm,      0 },<br>
+  { X86::VADDSDrr,     X86::VADDSDrm,      0 },<br>
+  { X86::VADDSDrr_Int,   X86::VADDSDrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VADDSSrr,     X86::VADDSSrm,      0 },<br>
+  { X86::VADDSSrr_Int,   X86::VADDSSrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VADDSUBPDrr,    X86::VADDSUBPDrm,    0 },<br>
+  { X86::VADDSUBPSrr,    X86::VADDSUBPSrm,    0 },<br>
+  { X86::VANDNPDrr,     X86::VANDNPDrm,     0 },<br>
+  { X86::VANDNPSrr,     X86::VANDNPSrm,     0 },<br>
+  { X86::VANDPDrr,     X86::VANDPDrm,      0 },<br>
+  { X86::VANDPSrr,     X86::VANDPSrm,      0 },<br>
+  { X86::VBLENDPDrri,    X86::VBLENDPDrmi,    0 },<br>
+  { X86::VBLENDPSrri,    X86::VBLENDPSrmi,    0 },<br>
+  { X86::VBLENDVPDrr,    X86::VBLENDVPDrm,    0 },<br>
+  { X86::VBLENDVPSrr,    X86::VBLENDVPSrm,    0 },<br>
+  { X86::VCMPPDrri,     X86::VCMPPDrmi,     0 },<br>
+  { X86::VCMPPSrri,     X86::VCMPPSrmi,     0 },<br>
+  { X86::VCMPSDrr,     X86::VCMPSDrm,      0 },<br>
+  { X86::VCMPSSrr,     X86::VCMPSSrm,      0 },<br>
+  { X86::VDIVPDrr,     X86::VDIVPDrm,      0 },<br>
+  { X86::VDIVPSrr,     X86::VDIVPSrm,      0 },<br>
+  { X86::VDIVSDrr,     X86::VDIVSDrm,      0 },<br>
+  { X86::VDIVSDrr_Int,   X86::VDIVSDrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VDIVSSrr,     X86::VDIVSSrm,      0 },<br>
+  { X86::VDIVSSrr_Int,   X86::VDIVSSrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VDPPDrri,     X86::VDPPDrmi,      0 },<br>
+  { X86::VDPPSrri,     X86::VDPPSrmi,      0 },<br>
+  { X86::VHADDPDrr,     X86::VHADDPDrm,     0 },<br>
+  { X86::VHADDPSrr,     X86::VHADDPSrm,     0 },<br>
+  { X86::VHSUBPDrr,     X86::VHSUBPDrm,     0 },<br>
+  { X86::VHSUBPSrr,     X86::VHSUBPSrm,     0 },<br>
+  { X86::Int_VCMPSDrr,   X86::Int_VCMPSDrm,    TB_NO_REVERSE },<br>
+  { X86::Int_VCMPSSrr,   X86::Int_VCMPSSrm,    TB_NO_REVERSE },<br>
+  { X86::VMAXCPDrr,     X86::VMAXCPDrm,     0 },<br>
+  { X86::VMAXCPSrr,     X86::VMAXCPSrm,     0 },<br>
+  { X86::VMAXCSDrr,     X86::VMAXCSDrm,     0 },<br>
+  { X86::VMAXCSSrr,     X86::VMAXCSSrm,     0 },<br>
+  { X86::VMAXPDrr,     X86::VMAXPDrm,      0 },<br>
+  { X86::VMAXPSrr,     X86::VMAXPSrm,      0 },<br>
+  { X86::VMAXSDrr,     X86::VMAXSDrm,      0 },<br>
+  { X86::VMAXSDrr_Int,   X86::VMAXSDrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMAXSSrr,     X86::VMAXSSrm,      0 },<br>
+  { X86::VMAXSSrr_Int,   X86::VMAXSSrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMINCPDrr,     X86::VMINCPDrm,     0 },<br>
+  { X86::VMINCPSrr,     X86::VMINCPSrm,     0 },<br>
+  { X86::VMINCSDrr,     X86::VMINCSDrm,     0 },<br>
+  { X86::VMINCSSrr,     X86::VMINCSSrm,     0 },<br>
+  { X86::VMINPDrr,     X86::VMINPDrm,      0 },<br>
+  { X86::VMINPSrr,     X86::VMINPSrm,      0 },<br>
+  { X86::VMINSDrr,     X86::VMINSDrm,      0 },<br>
+  { X86::VMINSDrr_Int,   X86::VMINSDrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMINSSrr,     X86::VMINSSrm,      0 },<br>
+  { X86::VMINSSrr_Int,   X86::VMINSSrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMOVLHPSrr,    X86::VMOVHPSrm,     TB_NO_REVERSE },<br>
+  { X86::VMPSADBWrri,    X86::VMPSADBWrmi,    0 },<br>
+  { X86::VMULPDrr,     X86::VMULPDrm,      0 },<br>
+  { X86::VMULPSrr,     X86::VMULPSrm,      0 },<br>
+  { X86::VMULSDrr,     X86::VMULSDrm,      0 },<br>
+  { X86::VMULSDrr_Int,   X86::VMULSDrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMULSSrr,     X86::VMULSSrm,      0 },<br>
+  { X86::VMULSSrr_Int,   X86::VMULSSrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VORPDrr,      X86::VORPDrm,      0 },<br>
+  { X86::VORPSrr,      X86::VORPSrm,      0 },<br>
+  { X86::VPACKSSDWrr,    X86::VPACKSSDWrm,    0 },<br>
+  { X86::VPACKSSWBrr,    X86::VPACKSSWBrm,    0 },<br>
+  { X86::VPACKUSDWrr,    X86::VPACKUSDWrm,    0 },<br>
+  { X86::VPACKUSWBrr,    X86::VPACKUSWBrm,    0 },<br>
+  { X86::VPADDBrr,     X86::VPADDBrm,      0 },<br>
+  { X86::VPADDDrr,     X86::VPADDDrm,      0 },<br>
+  { X86::VPADDQrr,     X86::VPADDQrm,      0 },<br>
+  { X86::VPADDSBrr,     X86::VPADDSBrm,     0 },<br>
+  { X86::VPADDSWrr,     X86::VPADDSWrm,     0 },<br>
+  { X86::VPADDUSBrr,    X86::VPADDUSBrm,     0 },<br>
+  { X86::VPADDUSWrr,    X86::VPADDUSWrm,     0 },<br>
+  { X86::VPADDWrr,     X86::VPADDWrm,      0 },<br>
+  { X86::VPALIGNRrri,    X86::VPALIGNRrmi,    0 },<br>
+  { X86::VPANDNrr,     X86::VPANDNrm,      0 },<br>
+  { X86::VPANDrr,      X86::VPANDrm,      0 },<br>
+  { X86::VPAVGBrr,     X86::VPAVGBrm,      0 },<br>
+  { X86::VPAVGWrr,     X86::VPAVGWrm,      0 },<br>
+  { X86::VPBLENDVBrr,    X86::VPBLENDVBrm,    0 },<br>
+  { X86::VPBLENDWrri,    X86::VPBLENDWrmi,    0 },<br>
+  { X86::VPCLMULQDQrr,   X86::VPCLMULQDQrm,    0 },<br>
+  { X86::VPCMPEQBrr,    X86::VPCMPEQBrm,     0 },<br>
+  { X86::VPCMPEQDrr,    X86::VPCMPEQDrm,     0 },<br>
+  { X86::VPCMPEQQrr,    X86::VPCMPEQQrm,     0 },<br>
+  { X86::VPCMPEQWrr,    X86::VPCMPEQWrm,     0 },<br>
+  { X86::VPCMPGTBrr,    X86::VPCMPGTBrm,     0 },<br>
+  { X86::VPCMPGTDrr,    X86::VPCMPGTDrm,     0 },<br>
+  { X86::VPCMPGTQrr,    X86::VPCMPGTQrm,     0 },<br>
+  { X86::VPCMPGTWrr,    X86::VPCMPGTWrm,     0 },<br>
+  { X86::VPHADDDrr,     X86::VPHADDDrm,     0 },<br>
+  { X86::VPHADDSWrr128,   X86::VPHADDSWrm128,   0 },<br>
+  { X86::VPHADDWrr,     X86::VPHADDWrm,     0 },<br>
+  { X86::VPHSUBDrr,     X86::VPHSUBDrm,     0 },<br>
+  { X86::VPHSUBSWrr128,   X86::VPHSUBSWrm128,   0 },<br>
+  { X86::VPHSUBWrr,     X86::VPHSUBWrm,     0 },<br>
+  { X86::VPERMILPDrr,    X86::VPERMILPDrm,    0 },<br>
+  { X86::VPERMILPSrr,    X86::VPERMILPSrm,    0 },<br>
+  { X86::VPINSRBrr,     X86::VPINSRBrm,     0 },<br>
+  { X86::VPINSRDrr,     X86::VPINSRDrm,     0 },<br>
+  { X86::VPINSRQrr,     X86::VPINSRQrm,     0 },<br>
+  { X86::VPINSRWrri,    X86::VPINSRWrmi,     0 },<br>
+  { X86::VPMADDUBSWrr,   X86::VPMADDUBSWrm,    0 },<br>
+  { X86::VPMADDWDrr,    X86::VPMADDWDrm,     0 },<br>
+  { X86::VPMAXSBrr,     X86::VPMAXSBrm,     0 },<br>
+  { X86::VPMAXSDrr,     X86::VPMAXSDrm,     0 },<br>
+  { X86::VPMAXSWrr,     X86::VPMAXSWrm,     0 },<br>
+  { X86::VPMAXUBrr,     X86::VPMAXUBrm,     0 },<br>
+  { X86::VPMAXUDrr,     X86::VPMAXUDrm,     0 },<br>
+  { X86::VPMAXUWrr,     X86::VPMAXUWrm,     0 },<br>
+  { X86::VPMINSBrr,     X86::VPMINSBrm,     0 },<br>
+  { X86::VPMINSDrr,     X86::VPMINSDrm,     0 },<br>
+  { X86::VPMINSWrr,     X86::VPMINSWrm,     0 },<br>
+  { X86::VPMINUBrr,     X86::VPMINUBrm,     0 },<br>
+  { X86::VPMINUDrr,     X86::VPMINUDrm,     0 },<br>
+  { X86::VPMINUWrr,     X86::VPMINUWrm,     0 },<br>
+  { X86::VPMULDQrr,     X86::VPMULDQrm,     0 },<br>
+  { X86::VPMULHRSWrr,    X86::VPMULHRSWrm,    0 },<br>
+  { X86::VPMULHUWrr,    X86::VPMULHUWrm,     0 },<br>
+  { X86::VPMULHWrr,     X86::VPMULHWrm,     0 },<br>
+  { X86::VPMULLDrr,     X86::VPMULLDrm,     0 },<br>
+  { X86::VPMULLWrr,     X86::VPMULLWrm,     0 },<br>
+  { X86::VPMULUDQrr,    X86::VPMULUDQrm,     0 },<br>
+  { X86::VPORrr,      X86::VPORrm,       0 },<br>
+  { X86::VPSADBWrr,     X86::VPSADBWrm,     0 },<br>
+  { X86::VPSHUFBrr,     X86::VPSHUFBrm,     0 },<br>
+  { X86::VPSIGNBrr128,   X86::VPSIGNBrm128,    0 },<br>
+  { X86::VPSIGNWrr128,   X86::VPSIGNWrm128,    0 },<br>
+  { X86::VPSIGNDrr128,   X86::VPSIGNDrm128,    0 },<br>
+  { X86::VPSLLDrr,     X86::VPSLLDrm,      0 },<br>
+  { X86::VPSLLQrr,     X86::VPSLLQrm,      0 },<br>
+  { X86::VPSLLWrr,     X86::VPSLLWrm,      0 },<br>
+  { X86::VPSRADrr,     X86::VPSRADrm,      0 },<br>
+  { X86::VPSRAWrr,     X86::VPSRAWrm,      0 },<br>
+  { X86::VPSRLDrr,     X86::VPSRLDrm,      0 },<br>
+  { X86::VPSRLQrr,     X86::VPSRLQrm,      0 },<br>
+  { X86::VPSRLWrr,     X86::VPSRLWrm,      0 },<br>
+  { X86::VPSUBBrr,     X86::VPSUBBrm,      0 },<br>
+  { X86::VPSUBDrr,     X86::VPSUBDrm,      0 },<br>
+  { X86::VPSUBQrr,     X86::VPSUBQrm,      0 },<br>
+  { X86::VPSUBSBrr,     X86::VPSUBSBrm,     0 },<br>
+  { X86::VPSUBSWrr,     X86::VPSUBSWrm,     0 },<br>
+  { X86::VPSUBUSBrr,    X86::VPSUBUSBrm,     0 },<br>
+  { X86::VPSUBUSWrr,    X86::VPSUBUSWrm,     0 },<br>
+  { X86::VPSUBWrr,     X86::VPSUBWrm,      0 },<br>
+  { X86::VPUNPCKHBWrr,   X86::VPUNPCKHBWrm,    0 },<br>
+  { X86::VPUNPCKHDQrr,   X86::VPUNPCKHDQrm,    0 },<br>
+  { X86::VPUNPCKHQDQrr,   X86::VPUNPCKHQDQrm,   0 },<br>
+  { X86::VPUNPCKHWDrr,   X86::VPUNPCKHWDrm,    0 },<br>
+  { X86::VPUNPCKLBWrr,   X86::VPUNPCKLBWrm,    0 },<br>
+  { X86::VPUNPCKLDQrr,   X86::VPUNPCKLDQrm,    0 },<br>
+  { X86::VPUNPCKLQDQrr,   X86::VPUNPCKLQDQrm,   0 },<br>
+  { X86::VPUNPCKLWDrr,   X86::VPUNPCKLWDrm,    0 },<br>
+  { X86::VPXORrr,      X86::VPXORrm,      0 },<br>
+  { X86::VRCPSSr,      X86::VRCPSSm,      0 },<br>
+  { X86::VRCPSSr_Int,    X86::VRCPSSm_Int,    TB_NO_REVERSE },<br>
+  { X86::VRSQRTSSr,     X86::VRSQRTSSm,     0 },<br>
+  { X86::VRSQRTSSr_Int,   X86::VRSQRTSSm_Int,   TB_NO_REVERSE },<br>
+  { X86::VROUNDSDr,     X86::VROUNDSDm,     0 },<br>
+  { X86::VROUNDSDr_Int,   X86::VROUNDSDm_Int,   TB_NO_REVERSE },<br>
+  { X86::VROUNDSSr,     X86::VROUNDSSm,     0 },<br>
+  { X86::VROUNDSSr_Int,   X86::VROUNDSSm_Int,   TB_NO_REVERSE },<br>
+  { X86::VSHUFPDrri,    X86::VSHUFPDrmi,     0 },<br>
+  { X86::VSHUFPSrri,    X86::VSHUFPSrmi,     0 },<br>
+  { X86::VSQRTSDr,     X86::VSQRTSDm,      0 },<br>
+  { X86::VSQRTSDr_Int,   X86::VSQRTSDm_Int,    TB_NO_REVERSE },<br>
+  { X86::VSQRTSSr,     X86::VSQRTSSm,      0 },<br>
+  { X86::VSQRTSSr_Int,   X86::VSQRTSSm_Int,    TB_NO_REVERSE },<br>
+  { X86::VSUBPDrr,     X86::VSUBPDrm,      0 },<br>
+  { X86::VSUBPSrr,     X86::VSUBPSrm,      0 },<br>
+  { X86::VSUBSDrr,     X86::VSUBSDrm,      0 },<br>
+  { X86::VSUBSDrr_Int,   X86::VSUBSDrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VSUBSSrr,     X86::VSUBSSrm,      0 },<br>
+  { X86::VSUBSSrr_Int,   X86::VSUBSSrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VUNPCKHPDrr,    X86::VUNPCKHPDrm,    0 },<br>
+  { X86::VUNPCKHPSrr,    X86::VUNPCKHPSrm,    0 },<br>
+  { X86::VUNPCKLPDrr,    X86::VUNPCKLPDrm,    0 },<br>
+  { X86::VUNPCKLPSrr,    X86::VUNPCKLPSrm,    0 },<br>
+  { X86::VXORPDrr,     X86::VXORPDrm,      0 },<br>
+  { X86::VXORPSrr,     X86::VXORPSrm,      0 },<br>
+<br>
+Â Â // AVX 256-bit foldable instructions<br>
+  { X86::VADDPDYrr,     X86::VADDPDYrm,     0 },<br>
+  { X86::VADDPSYrr,     X86::VADDPSYrm,     0 },<br>
+  { X86::VADDSUBPDYrr,   X86::VADDSUBPDYrm,    0 },<br>
+  { X86::VADDSUBPSYrr,   X86::VADDSUBPSYrm,    0 },<br>
+  { X86::VANDNPDYrr,    X86::VANDNPDYrm,     0 },<br>
+  { X86::VANDNPSYrr,    X86::VANDNPSYrm,     0 },<br>
+  { X86::VANDPDYrr,     X86::VANDPDYrm,     0 },<br>
+  { X86::VANDPSYrr,     X86::VANDPSYrm,     0 },<br>
+  { X86::VBLENDPDYrri,   X86::VBLENDPDYrmi,    0 },<br>
+  { X86::VBLENDPSYrri,   X86::VBLENDPSYrmi,    0 },<br>
+  { X86::VBLENDVPDYrr,   X86::VBLENDVPDYrm,    0 },<br>
+  { X86::VBLENDVPSYrr,   X86::VBLENDVPSYrm,    0 },<br>
+  { X86::VCMPPDYrri,    X86::VCMPPDYrmi,     0 },<br>
+  { X86::VCMPPSYrri,    X86::VCMPPSYrmi,     0 },<br>
+  { X86::VDIVPDYrr,     X86::VDIVPDYrm,     0 },<br>
+  { X86::VDIVPSYrr,     X86::VDIVPSYrm,     0 },<br>
+  { X86::VDPPSYrri,     X86::VDPPSYrmi,     0 },<br>
+  { X86::VHADDPDYrr,    X86::VHADDPDYrm,     0 },<br>
+  { X86::VHADDPSYrr,    X86::VHADDPSYrm,     0 },<br>
+  { X86::VHSUBPDYrr,    X86::VHSUBPDYrm,     0 },<br>
+  { X86::VHSUBPSYrr,    X86::VHSUBPSYrm,     0 },<br>
+  { X86::VINSERTF128rr,   X86::VINSERTF128rm,   0 },<br>
+  { X86::VMAXCPDYrr,    X86::VMAXCPDYrm,     0 },<br>
+  { X86::VMAXCPSYrr,    X86::VMAXCPSYrm,     0 },<br>
+  { X86::VMAXPDYrr,     X86::VMAXPDYrm,     0 },<br>
+  { X86::VMAXPSYrr,     X86::VMAXPSYrm,     0 },<br>
+  { X86::VMINCPDYrr,    X86::VMINCPDYrm,     0 },<br>
+  { X86::VMINCPSYrr,    X86::VMINCPSYrm,     0 },<br>
+  { X86::VMINPDYrr,     X86::VMINPDYrm,     0 },<br>
+  { X86::VMINPSYrr,     X86::VMINPSYrm,     0 },<br>
+  { X86::VMULPDYrr,     X86::VMULPDYrm,     0 },<br>
+  { X86::VMULPSYrr,     X86::VMULPSYrm,     0 },<br>
+  { X86::VORPDYrr,     X86::VORPDYrm,      0 },<br>
+  { X86::VORPSYrr,     X86::VORPSYrm,      0 },<br>
+  { X86::VPERM2F128rr,   X86::VPERM2F128rm,    0 },<br>
+  { X86::VPERMILPDYrr,   X86::VPERMILPDYrm,    0 },<br>
+  { X86::VPERMILPSYrr,   X86::VPERMILPSYrm,    0 },<br>
+  { X86::VSHUFPDYrri,    X86::VSHUFPDYrmi,    0 },<br>
+  { X86::VSHUFPSYrri,    X86::VSHUFPSYrmi,    0 },<br>
+  { X86::VSUBPDYrr,     X86::VSUBPDYrm,     0 },<br>
+  { X86::VSUBPSYrr,     X86::VSUBPSYrm,     0 },<br>
+  { X86::VUNPCKHPDYrr,   X86::VUNPCKHPDYrm,    0 },<br>
+  { X86::VUNPCKHPSYrr,   X86::VUNPCKHPSYrm,    0 },<br>
+  { X86::VUNPCKLPDYrr,   X86::VUNPCKLPDYrm,    0 },<br>
+  { X86::VUNPCKLPSYrr,   X86::VUNPCKLPSYrm,    0 },<br>
+  { X86::VXORPDYrr,     X86::VXORPDYrm,     0 },<br>
+  { X86::VXORPSYrr,     X86::VXORPSYrm,     0 },<br>
+<br>
+Â Â // AVX2 foldable instructions<br>
+  { X86::VINSERTI128rr,   X86::VINSERTI128rm,   0 },<br>
+  { X86::VPACKSSDWYrr,   X86::VPACKSSDWYrm,    0 },<br>
+  { X86::VPACKSSWBYrr,   X86::VPACKSSWBYrm,    0 },<br>
+  { X86::VPACKUSDWYrr,   X86::VPACKUSDWYrm,    0 },<br>
+  { X86::VPACKUSWBYrr,   X86::VPACKUSWBYrm,    0 },<br>
+  { X86::VPADDBYrr,     X86::VPADDBYrm,     0 },<br>
+  { X86::VPADDDYrr,     X86::VPADDDYrm,     0 },<br>
+  { X86::VPADDQYrr,     X86::VPADDQYrm,     0 },<br>
+  { X86::VPADDSBYrr,    X86::VPADDSBYrm,     0 },<br>
+  { X86::VPADDSWYrr,    X86::VPADDSWYrm,     0 },<br>
+  { X86::VPADDUSBYrr,    X86::VPADDUSBYrm,    0 },<br>
+  { X86::VPADDUSWYrr,    X86::VPADDUSWYrm,    0 },<br>
+  { X86::VPADDWYrr,     X86::VPADDWYrm,     0 },<br>
+  { X86::VPALIGNRYrri,   X86::VPALIGNRYrmi,    0 },<br>
+  { X86::VPANDNYrr,     X86::VPANDNYrm,     0 },<br>
+  { X86::VPANDYrr,     X86::VPANDYrm,      0 },<br>
+  { X86::VPAVGBYrr,     X86::VPAVGBYrm,     0 },<br>
+  { X86::VPAVGWYrr,     X86::VPAVGWYrm,     0 },<br>
+  { X86::VPBLENDDrri,    X86::VPBLENDDrmi,    0 },<br>
+  { X86::VPBLENDDYrri,   X86::VPBLENDDYrmi,    0 },<br>
+  { X86::VPBLENDVBYrr,   X86::VPBLENDVBYrm,    0 },<br>
+  { X86::VPBLENDWYrri,   X86::VPBLENDWYrmi,    0 },<br>
+  { X86::VPCMPEQBYrr,    X86::VPCMPEQBYrm,    0 },<br>
+  { X86::VPCMPEQDYrr,    X86::VPCMPEQDYrm,    0 },<br>
+  { X86::VPCMPEQQYrr,    X86::VPCMPEQQYrm,    0 },<br>
+  { X86::VPCMPEQWYrr,    X86::VPCMPEQWYrm,    0 },<br>
+  { X86::VPCMPGTBYrr,    X86::VPCMPGTBYrm,    0 },<br>
+  { X86::VPCMPGTDYrr,    X86::VPCMPGTDYrm,    0 },<br>
+  { X86::VPCMPGTQYrr,    X86::VPCMPGTQYrm,    0 },<br>
+  { X86::VPCMPGTWYrr,    X86::VPCMPGTWYrm,    0 },<br>
+  { X86::VPERM2I128rr,   X86::VPERM2I128rm,    0 },<br>
+  { X86::VPERMDYrr,     X86::VPERMDYrm,     0 },<br>
+  { X86::VPERMPSYrr,    X86::VPERMPSYrm,     0 },<br>
+  { X86::VPHADDDYrr,    X86::VPHADDDYrm,     0 },<br>
+  { X86::VPHADDSWrr256,   X86::VPHADDSWrm256,   0 },<br>
+  { X86::VPHADDWYrr,    X86::VPHADDWYrm,     0 },<br>
+  { X86::VPHSUBDYrr,    X86::VPHSUBDYrm,     0 },<br>
+  { X86::VPHSUBSWrr256,   X86::VPHSUBSWrm256,   0 },<br>
+  { X86::VPHSUBWYrr,    X86::VPHSUBWYrm,     0 },<br>
+  { X86::VPMADDUBSWYrr,   X86::VPMADDUBSWYrm,   0 },<br>
+  { X86::VPMADDWDYrr,    X86::VPMADDWDYrm,    0 },<br>
+  { X86::VPMAXSBYrr,    X86::VPMAXSBYrm,     0 },<br>
+  { X86::VPMAXSDYrr,    X86::VPMAXSDYrm,     0 },<br>
+  { X86::VPMAXSWYrr,    X86::VPMAXSWYrm,     0 },<br>
+  { X86::VPMAXUBYrr,    X86::VPMAXUBYrm,     0 },<br>
+  { X86::VPMAXUDYrr,    X86::VPMAXUDYrm,     0 },<br>
+  { X86::VPMAXUWYrr,    X86::VPMAXUWYrm,     0 },<br>
+  { X86::VPMINSBYrr,    X86::VPMINSBYrm,     0 },<br>
+  { X86::VPMINSDYrr,    X86::VPMINSDYrm,     0 },<br>
+  { X86::VPMINSWYrr,    X86::VPMINSWYrm,     0 },<br>
+  { X86::VPMINUBYrr,    X86::VPMINUBYrm,     0 },<br>
+  { X86::VPMINUDYrr,    X86::VPMINUDYrm,     0 },<br>
+  { X86::VPMINUWYrr,    X86::VPMINUWYrm,     0 },<br>
+  { X86::VMPSADBWYrri,   X86::VMPSADBWYrmi,    0 },<br>
+  { X86::VPMULDQYrr,    X86::VPMULDQYrm,     0 },<br>
+  { X86::VPMULHRSWYrr,   X86::VPMULHRSWYrm,    0 },<br>
+  { X86::VPMULHUWYrr,    X86::VPMULHUWYrm,    0 },<br>
+  { X86::VPMULHWYrr,    X86::VPMULHWYrm,     0 },<br>
+  { X86::VPMULLDYrr,    X86::VPMULLDYrm,     0 },<br>
+  { X86::VPMULLWYrr,    X86::VPMULLWYrm,     0 },<br>
+  { X86::VPMULUDQYrr,    X86::VPMULUDQYrm,    0 },<br>
+  { X86::VPORYrr,      X86::VPORYrm,      0 },<br>
+  { X86::VPSADBWYrr,    X86::VPSADBWYrm,     0 },<br>
+  { X86::VPSHUFBYrr,    X86::VPSHUFBYrm,     0 },<br>
+  { X86::VPSIGNBYrr256,   X86::VPSIGNBYrm256,   0 },<br>
+  { X86::VPSIGNWYrr256,   X86::VPSIGNWYrm256,   0 },<br>
+  { X86::VPSIGNDYrr256,   X86::VPSIGNDYrm256,   0 },<br>
+  { X86::VPSLLDYrr,     X86::VPSLLDYrm,     0 },<br>
+  { X86::VPSLLQYrr,     X86::VPSLLQYrm,     0 },<br>
+  { X86::VPSLLWYrr,     X86::VPSLLWYrm,     0 },<br>
+  { X86::VPSLLVDrr,     X86::VPSLLVDrm,     0 },<br>
+  { X86::VPSLLVDYrr,    X86::VPSLLVDYrm,     0 },<br>
+  { X86::VPSLLVQrr,     X86::VPSLLVQrm,     0 },<br>
+  { X86::VPSLLVQYrr,    X86::VPSLLVQYrm,     0 },<br>
+  { X86::VPSRADYrr,     X86::VPSRADYrm,     0 },<br>
+  { X86::VPSRAWYrr,     X86::VPSRAWYrm,     0 },<br>
+  { X86::VPSRAVDrr,     X86::VPSRAVDrm,     0 },<br>
+  { X86::VPSRAVDYrr,    X86::VPSRAVDYrm,     0 },<br>
+  { X86::VPSRLDYrr,     X86::VPSRLDYrm,     0 },<br>
+  { X86::VPSRLQYrr,     X86::VPSRLQYrm,     0 },<br>
+  { X86::VPSRLWYrr,     X86::VPSRLWYrm,     0 },<br>
+  { X86::VPSRLVDrr,     X86::VPSRLVDrm,     0 },<br>
+  { X86::VPSRLVDYrr,    X86::VPSRLVDYrm,     0 },<br>
+  { X86::VPSRLVQrr,     X86::VPSRLVQrm,     0 },<br>
+  { X86::VPSRLVQYrr,    X86::VPSRLVQYrm,     0 },<br>
+  { X86::VPSUBBYrr,     X86::VPSUBBYrm,     0 },<br>
+  { X86::VPSUBDYrr,     X86::VPSUBDYrm,     0 },<br>
+  { X86::VPSUBQYrr,     X86::VPSUBQYrm,     0 },<br>
+  { X86::VPSUBSBYrr,    X86::VPSUBSBYrm,     0 },<br>
+  { X86::VPSUBSWYrr,    X86::VPSUBSWYrm,     0 },<br>
+  { X86::VPSUBUSBYrr,    X86::VPSUBUSBYrm,    0 },<br>
+  { X86::VPSUBUSWYrr,    X86::VPSUBUSWYrm,    0 },<br>
+  { X86::VPSUBWYrr,     X86::VPSUBWYrm,     0 },<br>
+  { X86::VPUNPCKHBWYrr,   X86::VPUNPCKHBWYrm,   0 },<br>
+  { X86::VPUNPCKHDQYrr,   X86::VPUNPCKHDQYrm,   0 },<br>
+  { X86::VPUNPCKHQDQYrr,  X86::VPUNPCKHQDQYrm,   0 },<br>
+  { X86::VPUNPCKHWDYrr,   X86::VPUNPCKHWDYrm,   0 },<br>
+  { X86::VPUNPCKLBWYrr,   X86::VPUNPCKLBWYrm,   0 },<br>
+  { X86::VPUNPCKLDQYrr,   X86::VPUNPCKLDQYrm,   0 },<br>
+  { X86::VPUNPCKLQDQYrr,  X86::VPUNPCKLQDQYrm,   0 },<br>
+  { X86::VPUNPCKLWDYrr,   X86::VPUNPCKLWDYrm,   0 },<br>
+  { X86::VPXORYrr,     X86::VPXORYrm,      0 },<br>
+<br>
+Â Â // FMA4 foldable patterns<br>
+  { X86::VFMADDSS4rr,    X86::VFMADDSS4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFMADDSS4rr_Int,  X86::VFMADDSS4mr_Int,  TB_NO_REVERSE },<br>
+  { X86::VFMADDSD4rr,    X86::VFMADDSD4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFMADDSD4rr_Int,  X86::VFMADDSD4mr_Int,  TB_NO_REVERSE },<br>
+  { X86::VFMADDPS4rr,    X86::VFMADDPS4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFMADDPD4rr,    X86::VFMADDPD4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFMADDPS4Yrr,   X86::VFMADDPS4Ymr,    TB_ALIGN_NONE },<br>
+  { X86::VFMADDPD4Yrr,   X86::VFMADDPD4Ymr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMADDSS4rr,   X86::VFNMADDSS4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMADDSS4rr_Int, X86::VFNMADDSS4mr_Int,  TB_NO_REVERSE },<br>
+  { X86::VFNMADDSD4rr,   X86::VFNMADDSD4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMADDSD4rr_Int, X86::VFNMADDSD4mr_Int,  TB_NO_REVERSE },<br>
+  { X86::VFNMADDPS4rr,   X86::VFNMADDPS4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMADDPD4rr,   X86::VFNMADDPD4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMADDPS4Yrr,   X86::VFNMADDPS4Ymr,   TB_ALIGN_NONE },<br>
+  { X86::VFNMADDPD4Yrr,   X86::VFNMADDPD4Ymr,   TB_ALIGN_NONE },<br>
+  { X86::VFMSUBSS4rr,    X86::VFMSUBSS4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFMSUBSS4rr_Int,  X86::VFMSUBSS4mr_Int,  TB_NO_REVERSE },<br>
+  { X86::VFMSUBSD4rr,    X86::VFMSUBSD4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFMSUBSD4rr_Int,  X86::VFMSUBSD4mr_Int,  TB_NO_REVERSE },<br>
+  { X86::VFMSUBPS4rr,    X86::VFMSUBPS4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFMSUBPD4rr,    X86::VFMSUBPD4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFMSUBPS4Yrr,   X86::VFMSUBPS4Ymr,    TB_ALIGN_NONE },<br>
+  { X86::VFMSUBPD4Yrr,   X86::VFMSUBPD4Ymr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBSS4rr,   X86::VFNMSUBSS4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBSS4rr_Int, X86::VFNMSUBSS4mr_Int,  TB_NO_REVERSE },<br>
+  { X86::VFNMSUBSD4rr,   X86::VFNMSUBSD4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBSD4rr_Int, X86::VFNMSUBSD4mr_Int,  TB_NO_REVERSE },<br>
+  { X86::VFNMSUBPS4rr,   X86::VFNMSUBPS4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBPD4rr,   X86::VFNMSUBPD4mr,    TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBPS4Yrr,   X86::VFNMSUBPS4Ymr,   TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBPD4Yrr,   X86::VFNMSUBPD4Ymr,   TB_ALIGN_NONE },<br>
+  { X86::VFMADDSUBPS4rr,  X86::VFMADDSUBPS4mr,   TB_ALIGN_NONE },<br>
+  { X86::VFMADDSUBPD4rr,  X86::VFMADDSUBPD4mr,   TB_ALIGN_NONE },<br>
+  { X86::VFMADDSUBPS4Yrr,  X86::VFMADDSUBPS4Ymr,  TB_ALIGN_NONE },<br>
+  { X86::VFMADDSUBPD4Yrr,  X86::VFMADDSUBPD4Ymr,  TB_ALIGN_NONE },<br>
+  { X86::VFMSUBADDPS4rr,  X86::VFMSUBADDPS4mr,   TB_ALIGN_NONE },<br>
+  { X86::VFMSUBADDPD4rr,  X86::VFMSUBADDPD4mr,   TB_ALIGN_NONE },<br>
+  { X86::VFMSUBADDPS4Yrr,  X86::VFMSUBADDPS4Ymr,  TB_ALIGN_NONE },<br>
+  { X86::VFMSUBADDPD4Yrr,  X86::VFMSUBADDPD4Ymr,  TB_ALIGN_NONE },<br>
+<br>
+Â Â // XOP foldable instructions<br>
+  { X86::VPCMOVrrr,     X86::VPCMOVrmr,      0 },<br>
+  { X86::VPCMOVYrrr,    X86::VPCMOVYrmr,     0 },<br>
+  { X86::VPCOMBri,     X86::VPCOMBmi,      0 },<br>
+  { X86::VPCOMDri,     X86::VPCOMDmi,      0 },<br>
+  { X86::VPCOMQri,     X86::VPCOMQmi,      0 },<br>
+  { X86::VPCOMWri,     X86::VPCOMWmi,      0 },<br>
+  { X86::VPCOMUBri,     X86::VPCOMUBmi,      0 },<br>
+  { X86::VPCOMUDri,     X86::VPCOMUDmi,      0 },<br>
+  { X86::VPCOMUQri,     X86::VPCOMUQmi,      0 },<br>
+  { X86::VPCOMUWri,     X86::VPCOMUWmi,      0 },<br>
+  { X86::VPERMIL2PDrr,   X86::VPERMIL2PDmr,    0 },<br>
+  { X86::VPERMIL2PDYrr,   X86::VPERMIL2PDYmr,    0 },<br>
+  { X86::VPERMIL2PSrr,   X86::VPERMIL2PSmr,    0 },<br>
+  { X86::VPERMIL2PSYrr,   X86::VPERMIL2PSYmr,    0 },<br>
+  { X86::VPMACSDDrr,    X86::VPMACSDDrm,     0 },<br>
+  { X86::VPMACSDQHrr,    X86::VPMACSDQHrm,     0 },<br>
+  { X86::VPMACSDQLrr,    X86::VPMACSDQLrm,     0 },<br>
+  { X86::VPMACSSDDrr,    X86::VPMACSSDDrm,     0 },<br>
+  { X86::VPMACSSDQHrr,   X86::VPMACSSDQHrm,    0 },<br>
+  { X86::VPMACSSDQLrr,   X86::VPMACSSDQLrm,    0 },<br>
+  { X86::VPMACSSWDrr,    X86::VPMACSSWDrm,     0 },<br>
+  { X86::VPMACSSWWrr,    X86::VPMACSSWWrm,     0 },<br>
+  { X86::VPMACSWDrr,    X86::VPMACSWDrm,     0 },<br>
+  { X86::VPMACSWWrr,    X86::VPMACSWWrm,     0 },<br>
+  { X86::VPMADCSSWDrr,   X86::VPMADCSSWDrm,    0 },<br>
+  { X86::VPMADCSWDrr,    X86::VPMADCSWDrm,     0 },<br>
+  { X86::VPPERMrrr,     X86::VPPERMrmr,      0 },<br>
+  { X86::VPROTBrr,     X86::VPROTBrm,      0 },<br>
+  { X86::VPROTDrr,     X86::VPROTDrm,      0 },<br>
+  { X86::VPROTQrr,     X86::VPROTQrm,      0 },<br>
+  { X86::VPROTWrr,     X86::VPROTWrm,      0 },<br>
+  { X86::VPSHABrr,     X86::VPSHABrm,      0 },<br>
+  { X86::VPSHADrr,     X86::VPSHADrm,      0 },<br>
+  { X86::VPSHAQrr,     X86::VPSHAQrm,      0 },<br>
+  { X86::VPSHAWrr,     X86::VPSHAWrm,      0 },<br>
+  { X86::VPSHLBrr,     X86::VPSHLBrm,      0 },<br>
+  { X86::VPSHLDrr,     X86::VPSHLDrm,      0 },<br>
+  { X86::VPSHLQrr,     X86::VPSHLQrm,      0 },<br>
+  { X86::VPSHLWrr,     X86::VPSHLWrm,      0 },<br>
+<br>
+Â Â // BMI/BMI2 foldable instructions<br>
+  { X86::ANDN32rr,     X86::ANDN32rm,      0 },<br>
+  { X86::ANDN64rr,     X86::ANDN64rm,      0 },<br>
+  { X86::MULX32rr,     X86::MULX32rm,      0 },<br>
+  { X86::MULX64rr,     X86::MULX64rm,      0 },<br>
+  { X86::PDEP32rr,     X86::PDEP32rm,      0 },<br>
+  { X86::PDEP64rr,     X86::PDEP64rm,      0 },<br>
+  { X86::PEXT32rr,     X86::PEXT32rm,      0 },<br>
+  { X86::PEXT64rr,     X86::PEXT64rm,      0 },<br>
+<br>
+Â Â // ADX foldable instructions<br>
+  { X86::ADCX32rr,     X86::ADCX32rm,      0 },<br>
+  { X86::ADCX64rr,     X86::ADCX64rm,      0 },<br>
+  { X86::ADOX32rr,     X86::ADOX32rm,      0 },<br>
+  { X86::ADOX64rr,     X86::ADOX64rm,      0 },<br>
+<br>
+Â Â // AVX-512 foldable instructions<br>
+  { X86::VADDPDZrr,     X86::VADDPDZrm,      0 },<br>
+  { X86::VADDPSZrr,     X86::VADDPSZrm,      0 },<br>
+  { X86::VADDSDZrr,     X86::VADDSDZrm,      0 },<br>
+  { X86::VADDSDZrr_Int,   X86::VADDSDZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VADDSSZrr,     X86::VADDSSZrm,      0 },<br>
+  { X86::VADDSSZrr_Int,   X86::VADDSSZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VALIGNDZrri,    X86::VALIGNDZrmi,     0 },<br>
+  { X86::VALIGNQZrri,    X86::VALIGNQZrmi,     0 },<br>
+  { X86::VANDNPDZrr,    X86::VANDNPDZrm,     0 },<br>
+  { X86::VANDNPSZrr,    X86::VANDNPSZrm,     0 },<br>
+  { X86::VANDPDZrr,     X86::VANDPDZrm,      0 },<br>
+  { X86::VANDPSZrr,     X86::VANDPSZrm,      0 },<br>
+  { X86::VCMPPDZrri,    X86::VCMPPDZrmi,     0 },<br>
+  { X86::VCMPPSZrri,    X86::VCMPPSZrmi,     0 },<br>
+  { X86::VCMPSDZrr,     X86::VCMPSDZrm,      0 },<br>
+  { X86::VCMPSDZrr_Int,   X86::VCMPSDZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VCMPSSZrr,     X86::VCMPSSZrm,      0 },<br>
+  { X86::VCMPSSZrr_Int,   X86::VCMPSSZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VDIVPDZrr,     X86::VDIVPDZrm,      0 },<br>
+  { X86::VDIVPSZrr,     X86::VDIVPSZrm,      0 },<br>
+  { X86::VDIVSDZrr,     X86::VDIVSDZrm,      0 },<br>
+  { X86::VDIVSDZrr_Int,   X86::VDIVSDZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VDIVSSZrr,     X86::VDIVSSZrm,      0 },<br>
+  { X86::VDIVSSZrr_Int,   X86::VDIVSSZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VINSERTF32x4Zrr,  X86::VINSERTF32x4Zrm,   0 },<br>
+  { X86::VINSERTF32x8Zrr,  X86::VINSERTF32x8Zrm,   0 },<br>
+  { X86::VINSERTF64x2Zrr,  X86::VINSERTF64x2Zrm,   0 },<br>
+  { X86::VINSERTF64x4Zrr,  X86::VINSERTF64x4Zrm,   0 },<br>
+  { X86::VINSERTI32x4Zrr,  X86::VINSERTI32x4Zrm,   0 },<br>
+  { X86::VINSERTI32x8Zrr,  X86::VINSERTI32x8Zrm,   0 },<br>
+  { X86::VINSERTI64x2Zrr,  X86::VINSERTI64x2Zrm,   0 },<br>
+  { X86::VINSERTI64x4Zrr,  X86::VINSERTI64x4Zrm,   0 },<br>
+  { X86::VMAXCPDZrr,    X86::VMAXCPDZrm,     0 },<br>
+  { X86::VMAXCPSZrr,    X86::VMAXCPSZrm,     0 },<br>
+  { X86::VMAXCSDZrr,    X86::VMAXCSDZrm,     0 },<br>
+  { X86::VMAXCSSZrr,    X86::VMAXCSSZrm,     0 },<br>
+  { X86::VMAXPDZrr,     X86::VMAXPDZrm,      0 },<br>
+  { X86::VMAXPSZrr,     X86::VMAXPSZrm,      0 },<br>
+  { X86::VMAXSDZrr,     X86::VMAXSDZrm,      0 },<br>
+  { X86::VMAXSDZrr_Int,   X86::VMAXSDZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMAXSSZrr,     X86::VMAXSSZrm,      0 },<br>
+  { X86::VMAXSSZrr_Int,   X86::VMAXSSZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMINCPDZrr,    X86::VMINCPDZrm,     0 },<br>
+  { X86::VMINCPSZrr,    X86::VMINCPSZrm,     0 },<br>
+  { X86::VMINCSDZrr,    X86::VMINCSDZrm,     0 },<br>
+  { X86::VMINCSSZrr,    X86::VMINCSSZrm,     0 },<br>
+  { X86::VMINPDZrr,     X86::VMINPDZrm,      0 },<br>
+  { X86::VMINPSZrr,     X86::VMINPSZrm,      0 },<br>
+  { X86::VMINSDZrr,     X86::VMINSDZrm,      0 },<br>
+  { X86::VMINSDZrr_Int,   X86::VMINSDZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMINSSZrr,     X86::VMINSSZrm,      0 },<br>
+  { X86::VMINSSZrr_Int,   X86::VMINSSZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMOVLHPSZrr,    X86::VMOVHPSZ128rm,    TB_NO_REVERSE },<br>
+  { X86::VMULPDZrr,     X86::VMULPDZrm,      0 },<br>
+  { X86::VMULPSZrr,     X86::VMULPSZrm,      0 },<br>
+  { X86::VMULSDZrr,     X86::VMULSDZrm,      0 },<br>
+  { X86::VMULSDZrr_Int,   X86::VMULSDZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VMULSSZrr,     X86::VMULSSZrm,      0 },<br>
+  { X86::VMULSSZrr_Int,   X86::VMULSSZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VORPDZrr,     X86::VORPDZrm,      0 },<br>
+  { X86::VORPSZrr,     X86::VORPSZrm,      0 },<br>
+  { X86::VPACKSSDWZrr,   X86::VPACKSSDWZrm,    0 },<br>
+  { X86::VPACKSSWBZrr,   X86::VPACKSSWBZrm,    0 },<br>
+  { X86::VPACKUSDWZrr,   X86::VPACKUSDWZrm,    0 },<br>
+  { X86::VPACKUSWBZrr,   X86::VPACKUSWBZrm,    0 },<br>
+  { X86::VPADDBZrr,     X86::VPADDBZrm,      0 },<br>
+  { X86::VPADDDZrr,     X86::VPADDDZrm,      0 },<br>
+  { X86::VPADDQZrr,     X86::VPADDQZrm,      0 },<br>
+  { X86::VPADDSBZrr,    X86::VPADDSBZrm,     0 },<br>
+  { X86::VPADDSWZrr,    X86::VPADDSWZrm,     0 },<br>
+  { X86::VPADDUSBZrr,    X86::VPADDUSBZrm,     0 },<br>
+  { X86::VPADDUSWZrr,    X86::VPADDUSWZrm,     0 },<br>
+  { X86::VPADDWZrr,     X86::VPADDWZrm,      0 },<br>
+  { X86::VPALIGNRZrri,   X86::VPALIGNRZrmi,    0 },<br>
+  { X86::VPANDDZrr,     X86::VPANDDZrm,      0 },<br>
+  { X86::VPANDNDZrr,    X86::VPANDNDZrm,     0 },<br>
+  { X86::VPANDNQZrr,    X86::VPANDNQZrm,     0 },<br>
+  { X86::VPANDQZrr,     X86::VPANDQZrm,      0 },<br>
+  { X86::VPAVGBZrr,     X86::VPAVGBZrm,      0 },<br>
+  { X86::VPAVGWZrr,     X86::VPAVGWZrm,      0 },<br>
+  { X86::VPCMPBZrri,    X86::VPCMPBZrmi,     0 },<br>
+  { X86::VPCMPDZrri,    X86::VPCMPDZrmi,     0 },<br>
+  { X86::VPCMPEQBZrr,    X86::VPCMPEQBZrm,     0 },<br>
+  { X86::VPCMPEQDZrr,    X86::VPCMPEQDZrm,     0 },<br>
+  { X86::VPCMPEQQZrr,    X86::VPCMPEQQZrm,     0 },<br>
+  { X86::VPCMPEQWZrr,    X86::VPCMPEQWZrm,     0 },<br>
+  { X86::VPCMPGTBZrr,    X86::VPCMPGTBZrm,     0 },<br>
+  { X86::VPCMPGTDZrr,    X86::VPCMPGTDZrm,     0 },<br>
+  { X86::VPCMPGTQZrr,    X86::VPCMPGTQZrm,     0 },<br>
+  { X86::VPCMPGTWZrr,    X86::VPCMPGTWZrm,     0 },<br>
+  { X86::VPCMPQZrri,    X86::VPCMPQZrmi,     0 },<br>
+  { X86::VPCMPUBZrri,    X86::VPCMPUBZrmi,     0 },<br>
+  { X86::VPCMPUDZrri,    X86::VPCMPUDZrmi,     0 },<br>
+  { X86::VPCMPUQZrri,    X86::VPCMPUQZrmi,     0 },<br>
+  { X86::VPCMPUWZrri,    X86::VPCMPUWZrmi,     0 },<br>
+  { X86::VPCMPWZrri,    X86::VPCMPWZrmi,     0 },<br>
+  { X86::VPERMBZrr,     X86::VPERMBZrm,      0 },<br>
+  { X86::VPERMDZrr,     X86::VPERMDZrm,      0 },<br>
+  { X86::VPERMILPDZrr,   X86::VPERMILPDZrm,    0 },<br>
+  { X86::VPERMILPSZrr,   X86::VPERMILPSZrm,    0 },<br>
+  { X86::VPERMPDZrr,    X86::VPERMPDZrm,     0 },<br>
+  { X86::VPERMPSZrr,    X86::VPERMPSZrm,     0 },<br>
+  { X86::VPERMQZrr,     X86::VPERMQZrm,      0 },<br>
+  { X86::VPERMWZrr,     X86::VPERMWZrm,      0 },<br>
+  { X86::VPINSRBZrr,    X86::VPINSRBZrm,     0 },<br>
+  { X86::VPINSRDZrr,    X86::VPINSRDZrm,     0 },<br>
+  { X86::VPINSRQZrr,    X86::VPINSRQZrm,     0 },<br>
+  { X86::VPINSRWZrr,    X86::VPINSRWZrm,     0 },<br>
+  { X86::VPMADDUBSWZrr,   X86::VPMADDUBSWZrm,    0 },<br>
+  { X86::VPMADDWDZrr,    X86::VPMADDWDZrm,     0 },<br>
+  { X86::VPMAXSBZrr,    X86::VPMAXSBZrm,     0 },<br>
+  { X86::VPMAXSDZrr,    X86::VPMAXSDZrm,     0 },<br>
+  { X86::VPMAXSQZrr,    X86::VPMAXSQZrm,     0 },<br>
+  { X86::VPMAXSWZrr,    X86::VPMAXSWZrm,     0 },<br>
+  { X86::VPMAXUBZrr,    X86::VPMAXUBZrm,     0 },<br>
+  { X86::VPMAXUDZrr,    X86::VPMAXUDZrm,     0 },<br>
+  { X86::VPMAXUQZrr,    X86::VPMAXUQZrm,     0 },<br>
+  { X86::VPMAXUWZrr,    X86::VPMAXUWZrm,     0 },<br>
+  { X86::VPMINSBZrr,    X86::VPMINSBZrm,     0 },<br>
+  { X86::VPMINSDZrr,    X86::VPMINSDZrm,     0 },<br>
+  { X86::VPMINSQZrr,    X86::VPMINSQZrm,     0 },<br>
+  { X86::VPMINSWZrr,    X86::VPMINSWZrm,     0 },<br>
+  { X86::VPMINUBZrr,    X86::VPMINUBZrm,     0 },<br>
+  { X86::VPMINUDZrr,    X86::VPMINUDZrm,     0 },<br>
+  { X86::VPMINUQZrr,    X86::VPMINUQZrm,     0 },<br>
+  { X86::VPMINUWZrr,    X86::VPMINUWZrm,     0 },<br>
+  { X86::VPMULDQZrr,    X86::VPMULDQZrm,     0 },<br>
+  { X86::VPMULLDZrr,    X86::VPMULLDZrm,     0 },<br>
+  { X86::VPMULLQZrr,    X86::VPMULLQZrm,     0 },<br>
+  { X86::VPMULLWZrr,    X86::VPMULLWZrm,     0 },<br>
+  { X86::VPMULUDQZrr,    X86::VPMULUDQZrm,     0 },<br>
+  { X86::VPORDZrr,     X86::VPORDZrm,      0 },<br>
+  { X86::VPORQZrr,     X86::VPORQZrm,      0 },<br>
+  { X86::VPSADBWZ512rr,   X86::VPSADBWZ512rm,    0 },<br>
+  { X86::VPSHUFBZrr,    X86::VPSHUFBZrm,     0 },<br>
+  { X86::VPSLLDZrr,     X86::VPSLLDZrm,      0 },<br>
+  { X86::VPSLLQZrr,     X86::VPSLLQZrm,      0 },<br>
+  { X86::VPSLLVDZrr,    X86::VPSLLVDZrm,     0 },<br>
+  { X86::VPSLLVQZrr,    X86::VPSLLVQZrm,     0 },<br>
+  { X86::VPSLLVWZrr,    X86::VPSLLVWZrm,     0 },<br>
+  { X86::VPSLLWZrr,     X86::VPSLLWZrm,      0 },<br>
+  { X86::VPSRADZrr,     X86::VPSRADZrm,      0 },<br>
+  { X86::VPSRAQZrr,     X86::VPSRAQZrm,      0 },<br>
+  { X86::VPSRAVDZrr,    X86::VPSRAVDZrm,     0 },<br>
+  { X86::VPSRAVQZrr,    X86::VPSRAVQZrm,     0 },<br>
+  { X86::VPSRAVWZrr,    X86::VPSRAVWZrm,     0 },<br>
+  { X86::VPSRAWZrr,     X86::VPSRAWZrm,      0 },<br>
+  { X86::VPSRLDZrr,     X86::VPSRLDZrm,      0 },<br>
+  { X86::VPSRLQZrr,     X86::VPSRLQZrm,      0 },<br>
+  { X86::VPSRLVDZrr,    X86::VPSRLVDZrm,     0 },<br>
+  { X86::VPSRLVQZrr,    X86::VPSRLVQZrm,     0 },<br>
+  { X86::VPSRLVWZrr,    X86::VPSRLVWZrm,     0 },<br>
+  { X86::VPSRLWZrr,     X86::VPSRLWZrm,      0 },<br>
+  { X86::VPSUBBZrr,     X86::VPSUBBZrm,      0 },<br>
+  { X86::VPSUBDZrr,     X86::VPSUBDZrm,      0 },<br>
+  { X86::VPSUBQZrr,     X86::VPSUBQZrm,      0 },<br>
+  { X86::VPSUBSBZrr,    X86::VPSUBSBZrm,     0 },<br>
+  { X86::VPSUBSWZrr,    X86::VPSUBSWZrm,     0 },<br>
+  { X86::VPSUBUSBZrr,    X86::VPSUBUSBZrm,     0 },<br>
+  { X86::VPSUBUSWZrr,    X86::VPSUBUSWZrm,     0 },<br>
+  { X86::VPSUBWZrr,     X86::VPSUBWZrm,      0 },<br>
+  { X86::VPUNPCKHBWZrr,   X86::VPUNPCKHBWZrm,    0 },<br>
+  { X86::VPUNPCKHDQZrr,   X86::VPUNPCKHDQZrm,    0 },<br>
+  { X86::VPUNPCKHQDQZrr,  X86::VPUNPCKHQDQZrm,   0 },<br>
+  { X86::VPUNPCKHWDZrr,   X86::VPUNPCKHWDZrm,    0 },<br>
+  { X86::VPUNPCKLBWZrr,   X86::VPUNPCKLBWZrm,    0 },<br>
+  { X86::VPUNPCKLDQZrr,   X86::VPUNPCKLDQZrm,    0 },<br>
+  { X86::VPUNPCKLQDQZrr,  X86::VPUNPCKLQDQZrm,   0 },<br>
+  { X86::VPUNPCKLWDZrr,   X86::VPUNPCKLWDZrm,    0 },<br>
+  { X86::VPXORDZrr,     X86::VPXORDZrm,      0 },<br>
+  { X86::VPXORQZrr,     X86::VPXORQZrm,      0 },<br>
+  { X86::VSHUFPDZrri,    X86::VSHUFPDZrmi,     0 },<br>
+  { X86::VSHUFPSZrri,    X86::VSHUFPSZrmi,     0 },<br>
+  { X86::VSUBPDZrr,     X86::VSUBPDZrm,      0 },<br>
+  { X86::VSUBPSZrr,     X86::VSUBPSZrm,      0 },<br>
+  { X86::VSUBSDZrr,     X86::VSUBSDZrm,      0 },<br>
+  { X86::VSUBSDZrr_Int,   X86::VSUBSDZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VSUBSSZrr,     X86::VSUBSSZrm,      0 },<br>
+  { X86::VSUBSSZrr_Int,   X86::VSUBSSZrm_Int,    TB_NO_REVERSE },<br>
+  { X86::VUNPCKHPDZrr,   X86::VUNPCKHPDZrm,    0 },<br>
+  { X86::VUNPCKHPSZrr,   X86::VUNPCKHPSZrm,    0 },<br>
+  { X86::VUNPCKLPDZrr,   X86::VUNPCKLPDZrm,    0 },<br>
+  { X86::VUNPCKLPSZrr,   X86::VUNPCKLPSZrm,    0 },<br>
+  { X86::VXORPDZrr,     X86::VXORPDZrm,      0 },<br>
+  { X86::VXORPSZrr,     X86::VXORPSZrm,      0 },<br>
+<br>
+Â Â // AVX-512{F,VL} foldable instructions<br>
+  { X86::VADDPDZ128rr,   X86::VADDPDZ128rm,    0 },<br>
+  { X86::VADDPDZ256rr,   X86::VADDPDZ256rm,    0 },<br>
+  { X86::VADDPSZ128rr,   X86::VADDPSZ128rm,    0 },<br>
+  { X86::VADDPSZ256rr,   X86::VADDPSZ256rm,    0 },<br>
+  { X86::VALIGNDZ128rri,  X86::VALIGNDZ128rmi,   0 },<br>
+  { X86::VALIGNDZ256rri,  X86::VALIGNDZ256rmi,   0 },<br>
+  { X86::VALIGNQZ128rri,  X86::VALIGNQZ128rmi,   0 },<br>
+  { X86::VALIGNQZ256rri,  X86::VALIGNQZ256rmi,   0 },<br>
+  { X86::VANDNPDZ128rr,   X86::VANDNPDZ128rm,    0 },<br>
+  { X86::VANDNPDZ256rr,   X86::VANDNPDZ256rm,    0 },<br>
+  { X86::VANDNPSZ128rr,   X86::VANDNPSZ128rm,    0 },<br>
+  { X86::VANDNPSZ256rr,   X86::VANDNPSZ256rm,    0 },<br>
+  { X86::VANDPDZ128rr,   X86::VANDPDZ128rm,    0 },<br>
+  { X86::VANDPDZ256rr,   X86::VANDPDZ256rm,    0 },<br>
+  { X86::VANDPSZ128rr,   X86::VANDPSZ128rm,    0 },<br>
+  { X86::VANDPSZ256rr,   X86::VANDPSZ256rm,    0 },<br>
+  { X86::VCMPPDZ128rri,   X86::VCMPPDZ128rmi,    0 },<br>
+  { X86::VCMPPDZ256rri,   X86::VCMPPDZ256rmi,    0 },<br>
+  { X86::VCMPPSZ128rri,   X86::VCMPPSZ128rmi,    0 },<br>
+  { X86::VCMPPSZ256rri,   X86::VCMPPSZ256rmi,    0 },<br>
+  { X86::VDIVPDZ128rr,   X86::VDIVPDZ128rm,    0 },<br>
+  { X86::VDIVPDZ256rr,   X86::VDIVPDZ256rm,    0 },<br>
+  { X86::VDIVPSZ128rr,   X86::VDIVPSZ128rm,    0 },<br>
+  { X86::VDIVPSZ256rr,   X86::VDIVPSZ256rm,    0 },<br>
+  { X86::VINSERTF32x4Z256rr,X86::<wbr>VINSERTF32x4Z256rm, 0 },<br>
+  { X86::VINSERTF64x2Z256rr,X86::<wbr>VINSERTF64x2Z256rm, 0 },<br>
+  { X86::VINSERTI32x4Z256rr,X86::<wbr>VINSERTI32x4Z256rm, 0 },<br>
+  { X86::VINSERTI64x2Z256rr,X86::<wbr>VINSERTI64x2Z256rm, 0 },<br>
+  { X86::VMAXCPDZ128rr,   X86::VMAXCPDZ128rm,    0 },<br>
+  { X86::VMAXCPDZ256rr,   X86::VMAXCPDZ256rm,    0 },<br>
+  { X86::VMAXCPSZ128rr,   X86::VMAXCPSZ128rm,    0 },<br>
+  { X86::VMAXCPSZ256rr,   X86::VMAXCPSZ256rm,    0 },<br>
+  { X86::VMAXPDZ128rr,   X86::VMAXPDZ128rm,    0 },<br>
+  { X86::VMAXPDZ256rr,   X86::VMAXPDZ256rm,    0 },<br>
+  { X86::VMAXPSZ128rr,   X86::VMAXPSZ128rm,    0 },<br>
+  { X86::VMAXPSZ256rr,   X86::VMAXPSZ256rm,    0 },<br>
+  { X86::VMINCPDZ128rr,   X86::VMINCPDZ128rm,    0 },<br>
+  { X86::VMINCPDZ256rr,   X86::VMINCPDZ256rm,    0 },<br>
+  { X86::VMINCPSZ128rr,   X86::VMINCPSZ128rm,    0 },<br>
+  { X86::VMINCPSZ256rr,   X86::VMINCPSZ256rm,    0 },<br>
+  { X86::VMINPDZ128rr,   X86::VMINPDZ128rm,    0 },<br>
+  { X86::VMINPDZ256rr,   X86::VMINPDZ256rm,    0 },<br>
+  { X86::VMINPSZ128rr,   X86::VMINPSZ128rm,    0 },<br>
+  { X86::VMINPSZ256rr,   X86::VMINPSZ256rm,    0 },<br>
+  { X86::VMULPDZ128rr,   X86::VMULPDZ128rm,    0 },<br>
+  { X86::VMULPDZ256rr,   X86::VMULPDZ256rm,    0 },<br>
+  { X86::VMULPSZ128rr,   X86::VMULPSZ128rm,    0 },<br>
+  { X86::VMULPSZ256rr,   X86::VMULPSZ256rm,    0 },<br>
+  { X86::VORPDZ128rr,    X86::VORPDZ128rm,     0 },<br>
+  { X86::VORPDZ256rr,    X86::VORPDZ256rm,     0 },<br>
+  { X86::VORPSZ128rr,    X86::VORPSZ128rm,     0 },<br>
+  { X86::VORPSZ256rr,    X86::VORPSZ256rm,     0 },<br>
+  { X86::VPACKSSDWZ256rr,  X86::VPACKSSDWZ256rm,   0 },<br>
+  { X86::VPACKSSDWZ128rr,  X86::VPACKSSDWZ128rm,   0 },<br>
+  { X86::VPACKSSWBZ256rr,  X86::VPACKSSWBZ256rm,   0 },<br>
+  { X86::VPACKSSWBZ128rr,  X86::VPACKSSWBZ128rm,   0 },<br>
+  { X86::VPACKUSDWZ256rr,  X86::VPACKUSDWZ256rm,   0 },<br>
+  { X86::VPACKUSDWZ128rr,  X86::VPACKUSDWZ128rm,   0 },<br>
+  { X86::VPACKUSWBZ256rr,  X86::VPACKUSWBZ256rm,   0 },<br>
+  { X86::VPACKUSWBZ128rr,  X86::VPACKUSWBZ128rm,   0 },<br>
+  { X86::VPADDBZ128rr,   X86::VPADDBZ128rm,    0 },<br>
+  { X86::VPADDBZ256rr,   X86::VPADDBZ256rm,    0 },<br>
+  { X86::VPADDDZ128rr,   X86::VPADDDZ128rm,    0 },<br>
+  { X86::VPADDDZ256rr,   X86::VPADDDZ256rm,    0 },<br>
+  { X86::VPADDQZ128rr,   X86::VPADDQZ128rm,    0 },<br>
+  { X86::VPADDQZ256rr,   X86::VPADDQZ256rm,    0 },<br>
+  { X86::VPADDSBZ128rr,   X86::VPADDSBZ128rm,    0 },<br>
+  { X86::VPADDSBZ256rr,   X86::VPADDSBZ256rm,    0 },<br>
+  { X86::VPADDSWZ128rr,   X86::VPADDSWZ128rm,    0 },<br>
+  { X86::VPADDSWZ256rr,   X86::VPADDSWZ256rm,    0 },<br>
+  { X86::VPADDUSBZ128rr,  X86::VPADDUSBZ128rm,   0 },<br>
+  { X86::VPADDUSBZ256rr,  X86::VPADDUSBZ256rm,   0 },<br>
+  { X86::VPADDUSWZ128rr,  X86::VPADDUSWZ128rm,   0 },<br>
+  { X86::VPADDUSWZ256rr,  X86::VPADDUSWZ256rm,   0 },<br>
+  { X86::VPADDWZ128rr,   X86::VPADDWZ128rm,    0 },<br>
+  { X86::VPADDWZ256rr,   X86::VPADDWZ256rm,    0 },<br>
+  { X86::VPALIGNRZ128rri,  X86::VPALIGNRZ128rmi,   0 },<br>
+  { X86::VPALIGNRZ256rri,  X86::VPALIGNRZ256rmi,   0 },<br>
+  { X86::VPANDDZ128rr,   X86::VPANDDZ128rm,    0 },<br>
+  { X86::VPANDDZ256rr,   X86::VPANDDZ256rm,    0 },<br>
+  { X86::VPANDNDZ128rr,   X86::VPANDNDZ128rm,    0 },<br>
+  { X86::VPANDNDZ256rr,   X86::VPANDNDZ256rm,    0 },<br>
+  { X86::VPANDNQZ128rr,   X86::VPANDNQZ128rm,    0 },<br>
+  { X86::VPANDNQZ256rr,   X86::VPANDNQZ256rm,    0 },<br>
+  { X86::VPANDQZ128rr,   X86::VPANDQZ128rm,    0 },<br>
+  { X86::VPANDQZ256rr,   X86::VPANDQZ256rm,    0 },<br>
+  { X86::VPAVGBZ128rr,   X86::VPAVGBZ128rm,    0 },<br>
+  { X86::VPAVGBZ256rr,   X86::VPAVGBZ256rm,    0 },<br>
+  { X86::VPAVGWZ128rr,   X86::VPAVGWZ128rm,    0 },<br>
+  { X86::VPAVGWZ256rr,   X86::VPAVGWZ256rm,    0 },<br>
+  { X86::VPCMPBZ128rri,   X86::VPCMPBZ128rmi,    0 },<br>
+  { X86::VPCMPBZ256rri,   X86::VPCMPBZ256rmi,    0 },<br>
+  { X86::VPCMPDZ128rri,   X86::VPCMPDZ128rmi,    0 },<br>
+  { X86::VPCMPDZ256rri,   X86::VPCMPDZ256rmi,    0 },<br>
+  { X86::VPCMPEQBZ128rr,  X86::VPCMPEQBZ128rm,   0 },<br>
+  { X86::VPCMPEQBZ256rr,  X86::VPCMPEQBZ256rm,   0 },<br>
+  { X86::VPCMPEQDZ128rr,  X86::VPCMPEQDZ128rm,   0 },<br>
+  { X86::VPCMPEQDZ256rr,  X86::VPCMPEQDZ256rm,   0 },<br>
+  { X86::VPCMPEQQZ128rr,  X86::VPCMPEQQZ128rm,   0 },<br>
+  { X86::VPCMPEQQZ256rr,  X86::VPCMPEQQZ256rm,   0 },<br>
+  { X86::VPCMPEQWZ128rr,  X86::VPCMPEQWZ128rm,   0 },<br>
+  { X86::VPCMPEQWZ256rr,  X86::VPCMPEQWZ256rm,   0 },<br>
+  { X86::VPCMPGTBZ128rr,  X86::VPCMPGTBZ128rm,   0 },<br>
+  { X86::VPCMPGTBZ256rr,  X86::VPCMPGTBZ256rm,   0 },<br>
+  { X86::VPCMPGTDZ128rr,  X86::VPCMPGTDZ128rm,   0 },<br>
+  { X86::VPCMPGTDZ256rr,  X86::VPCMPGTDZ256rm,   0 },<br>
+  { X86::VPCMPGTQZ128rr,  X86::VPCMPGTQZ128rm,   0 },<br>
+  { X86::VPCMPGTQZ256rr,  X86::VPCMPGTQZ256rm,   0 },<br>
+  { X86::VPCMPGTWZ128rr,  X86::VPCMPGTWZ128rm,   0 },<br>
+  { X86::VPCMPGTWZ256rr,  X86::VPCMPGTWZ256rm,   0 },<br>
+  { X86::VPCMPQZ128rri,   X86::VPCMPQZ128rmi,    0 },<br>
+  { X86::VPCMPQZ256rri,   X86::VPCMPQZ256rmi,    0 },<br>
+  { X86::VPCMPUBZ128rri,  X86::VPCMPUBZ128rmi,   0 },<br>
+  { X86::VPCMPUBZ256rri,  X86::VPCMPUBZ256rmi,   0 },<br>
+  { X86::VPCMPUDZ128rri,  X86::VPCMPUDZ128rmi,   0 },<br>
+  { X86::VPCMPUDZ256rri,  X86::VPCMPUDZ256rmi,   0 },<br>
+  { X86::VPCMPUQZ128rri,  X86::VPCMPUQZ128rmi,   0 },<br>
+  { X86::VPCMPUQZ256rri,  X86::VPCMPUQZ256rmi,   0 },<br>
+  { X86::VPCMPUWZ128rri,  X86::VPCMPUWZ128rmi,   0 },<br>
+  { X86::VPCMPUWZ256rri,  X86::VPCMPUWZ256rmi,   0 },<br>
+  { X86::VPCMPWZ128rri,   X86::VPCMPWZ128rmi,    0 },<br>
+  { X86::VPCMPWZ256rri,   X86::VPCMPWZ256rmi,    0 },<br>
+  { X86::VPERMBZ128rr,   X86::VPERMBZ128rm,    0 },<br>
+  { X86::VPERMBZ256rr,   X86::VPERMBZ256rm,    0 },<br>
+  { X86::VPERMDZ256rr,   X86::VPERMDZ256rm,    0 },<br>
+  { X86::VPERMILPDZ128rr,  X86::VPERMILPDZ128rm,   0 },<br>
+  { X86::VPERMILPDZ256rr,  X86::VPERMILPDZ256rm,   0 },<br>
+  { X86::VPERMILPSZ128rr,  X86::VPERMILPSZ128rm,   0 },<br>
+  { X86::VPERMILPSZ256rr,  X86::VPERMILPSZ256rm,   0 },<br>
+  { X86::VPERMPDZ256rr,   X86::VPERMPDZ256rm,    0 },<br>
+  { X86::VPERMPSZ256rr,   X86::VPERMPSZ256rm,    0 },<br>
+  { X86::VPERMQZ256rr,   X86::VPERMQZ256rm,    0 },<br>
+  { X86::VPERMWZ128rr,   X86::VPERMWZ128rm,    0 },<br>
+  { X86::VPERMWZ256rr,   X86::VPERMWZ256rm,    0 },<br>
+  { X86::VPMADDUBSWZ128rr, X86::VPMADDUBSWZ128rm,  0 },<br>
+  { X86::VPMADDUBSWZ256rr, X86::VPMADDUBSWZ256rm,  0 },<br>
+  { X86::VPMADDWDZ128rr,  X86::VPMADDWDZ128rm,   0 },<br>
+  { X86::VPMADDWDZ256rr,  X86::VPMADDWDZ256rm,   0 },<br>
+  { X86::VPMAXSBZ128rr,   X86::VPMAXSBZ128rm,    0 },<br>
+  { X86::VPMAXSBZ256rr,   X86::VPMAXSBZ256rm,    0 },<br>
+  { X86::VPMAXSDZ128rr,   X86::VPMAXSDZ128rm,    0 },<br>
+  { X86::VPMAXSDZ256rr,   X86::VPMAXSDZ256rm,    0 },<br>
+  { X86::VPMAXSQZ128rr,   X86::VPMAXSQZ128rm,    0 },<br>
+  { X86::VPMAXSQZ256rr,   X86::VPMAXSQZ256rm,    0 },<br>
+  { X86::VPMAXSWZ128rr,   X86::VPMAXSWZ128rm,    0 },<br>
+  { X86::VPMAXSWZ256rr,   X86::VPMAXSWZ256rm,    0 },<br>
+  { X86::VPMAXUBZ128rr,   X86::VPMAXUBZ128rm,    0 },<br>
+  { X86::VPMAXUBZ256rr,   X86::VPMAXUBZ256rm,    0 },<br>
+  { X86::VPMAXUDZ128rr,   X86::VPMAXUDZ128rm,    0 },<br>
+  { X86::VPMAXUDZ256rr,   X86::VPMAXUDZ256rm,    0 },<br>
+  { X86::VPMAXUQZ128rr,   X86::VPMAXUQZ128rm,    0 },<br>
+  { X86::VPMAXUQZ256rr,   X86::VPMAXUQZ256rm,    0 },<br>
+  { X86::VPMAXUWZ128rr,   X86::VPMAXUWZ128rm,    0 },<br>
+  { X86::VPMAXUWZ256rr,   X86::VPMAXUWZ256rm,    0 },<br>
+  { X86::VPMINSBZ128rr,   X86::VPMINSBZ128rm,    0 },<br>
+  { X86::VPMINSBZ256rr,   X86::VPMINSBZ256rm,    0 },<br>
+  { X86::VPMINSDZ128rr,   X86::VPMINSDZ128rm,    0 },<br>
+  { X86::VPMINSDZ256rr,   X86::VPMINSDZ256rm,    0 },<br>
+  { X86::VPMINSQZ128rr,   X86::VPMINSQZ128rm,    0 },<br>
+  { X86::VPMINSQZ256rr,   X86::VPMINSQZ256rm,    0 },<br>
+  { X86::VPMINSWZ128rr,   X86::VPMINSWZ128rm,    0 },<br>
+  { X86::VPMINSWZ256rr,   X86::VPMINSWZ256rm,    0 },<br>
+  { X86::VPMINUBZ128rr,   X86::VPMINUBZ128rm,    0 },<br>
+  { X86::VPMINUBZ256rr,   X86::VPMINUBZ256rm,    0 },<br>
+  { X86::VPMINUDZ128rr,   X86::VPMINUDZ128rm,    0 },<br>
+  { X86::VPMINUDZ256rr,   X86::VPMINUDZ256rm,    0 },<br>
+  { X86::VPMINUQZ128rr,   X86::VPMINUQZ128rm,    0 },<br>
+  { X86::VPMINUQZ256rr,   X86::VPMINUQZ256rm,    0 },<br>
+  { X86::VPMINUWZ128rr,   X86::VPMINUWZ128rm,    0 },<br>
+  { X86::VPMINUWZ256rr,   X86::VPMINUWZ256rm,    0 },<br>
+  { X86::VPMULDQZ128rr,   X86::VPMULDQZ128rm,    0 },<br>
+  { X86::VPMULDQZ256rr,   X86::VPMULDQZ256rm,    0 },<br>
+  { X86::VPMULLDZ128rr,   X86::VPMULLDZ128rm,    0 },<br>
+  { X86::VPMULLDZ256rr,   X86::VPMULLDZ256rm,    0 },<br>
+  { X86::VPMULLQZ128rr,   X86::VPMULLQZ128rm,    0 },<br>
+  { X86::VPMULLQZ256rr,   X86::VPMULLQZ256rm,    0 },<br>
+  { X86::VPMULLWZ128rr,   X86::VPMULLWZ128rm,    0 },<br>
+  { X86::VPMULLWZ256rr,   X86::VPMULLWZ256rm,    0 },<br>
+  { X86::VPMULUDQZ128rr,  X86::VPMULUDQZ128rm,   0 },<br>
+  { X86::VPMULUDQZ256rr,  X86::VPMULUDQZ256rm,   0 },<br>
+  { X86::VPORDZ128rr,    X86::VPORDZ128rm,     0 },<br>
+  { X86::VPORDZ256rr,    X86::VPORDZ256rm,     0 },<br>
+  { X86::VPORQZ128rr,    X86::VPORQZ128rm,     0 },<br>
+  { X86::VPORQZ256rr,    X86::VPORQZ256rm,     0 },<br>
+  { X86::VPSADBWZ128rr,   X86::VPSADBWZ128rm,    0 },<br>
+  { X86::VPSADBWZ256rr,   X86::VPSADBWZ256rm,    0 },<br>
+  { X86::VPSHUFBZ128rr,   X86::VPSHUFBZ128rm,    0 },<br>
+  { X86::VPSHUFBZ256rr,   X86::VPSHUFBZ256rm,    0 },<br>
+  { X86::VPSLLDZ128rr,   X86::VPSLLDZ128rm,    0 },<br>
+  { X86::VPSLLDZ256rr,   X86::VPSLLDZ256rm,    0 },<br>
+  { X86::VPSLLQZ128rr,   X86::VPSLLQZ128rm,    0 },<br>
+  { X86::VPSLLQZ256rr,   X86::VPSLLQZ256rm,    0 },<br>
+  { X86::VPSLLVDZ128rr,   X86::VPSLLVDZ128rm,    0 },<br>
+  { X86::VPSLLVDZ256rr,   X86::VPSLLVDZ256rm,    0 },<br>
+  { X86::VPSLLVQZ128rr,   X86::VPSLLVQZ128rm,    0 },<br>
+  { X86::VPSLLVQZ256rr,   X86::VPSLLVQZ256rm,    0 },<br>
+  { X86::VPSLLVWZ128rr,   X86::VPSLLVWZ128rm,    0 },<br>
+  { X86::VPSLLVWZ256rr,   X86::VPSLLVWZ256rm,    0 },<br>
+  { X86::VPSLLWZ128rr,   X86::VPSLLWZ128rm,    0 },<br>
+  { X86::VPSLLWZ256rr,   X86::VPSLLWZ256rm,    0 },<br>
+  { X86::VPSRADZ128rr,   X86::VPSRADZ128rm,    0 },<br>
+  { X86::VPSRADZ256rr,   X86::VPSRADZ256rm,    0 },<br>
+  { X86::VPSRAQZ128rr,   X86::VPSRAQZ128rm,    0 },<br>
+  { X86::VPSRAQZ256rr,   X86::VPSRAQZ256rm,    0 },<br>
+  { X86::VPSRAVDZ128rr,   X86::VPSRAVDZ128rm,    0 },<br>
+  { X86::VPSRAVDZ256rr,   X86::VPSRAVDZ256rm,    0 },<br>
+  { X86::VPSRAVQZ128rr,   X86::VPSRAVQZ128rm,    0 },<br>
+  { X86::VPSRAVQZ256rr,   X86::VPSRAVQZ256rm,    0 },<br>
+  { X86::VPSRAVWZ128rr,   X86::VPSRAVWZ128rm,    0 },<br>
+  { X86::VPSRAVWZ256rr,   X86::VPSRAVWZ256rm,    0 },<br>
+  { X86::VPSRAWZ128rr,   X86::VPSRAWZ128rm,    0 },<br>
+  { X86::VPSRAWZ256rr,   X86::VPSRAWZ256rm,    0 },<br>
+  { X86::VPSRLDZ128rr,   X86::VPSRLDZ128rm,    0 },<br>
+  { X86::VPSRLDZ256rr,   X86::VPSRLDZ256rm,    0 },<br>
+  { X86::VPSRLQZ128rr,   X86::VPSRLQZ128rm,    0 },<br>
+  { X86::VPSRLQZ256rr,   X86::VPSRLQZ256rm,    0 },<br>
+  { X86::VPSRLVDZ128rr,   X86::VPSRLVDZ128rm,    0 },<br>
+  { X86::VPSRLVDZ256rr,   X86::VPSRLVDZ256rm,    0 },<br>
+  { X86::VPSRLVQZ128rr,   X86::VPSRLVQZ128rm,    0 },<br>
+  { X86::VPSRLVQZ256rr,   X86::VPSRLVQZ256rm,    0 },<br>
+  { X86::VPSRLVWZ128rr,   X86::VPSRLVWZ128rm,    0 },<br>
+  { X86::VPSRLVWZ256rr,   X86::VPSRLVWZ256rm,    0 },<br>
+  { X86::VPSRLWZ128rr,   X86::VPSRLWZ128rm,    0 },<br>
+  { X86::VPSRLWZ256rr,   X86::VPSRLWZ256rm,    0 },<br>
+  { X86::VPSUBBZ128rr,   X86::VPSUBBZ128rm,    0 },<br>
+  { X86::VPSUBBZ256rr,   X86::VPSUBBZ256rm,    0 },<br>
+  { X86::VPSUBDZ128rr,   X86::VPSUBDZ128rm,    0 },<br>
+  { X86::VPSUBDZ256rr,   X86::VPSUBDZ256rm,    0 },<br>
+  { X86::VPSUBQZ128rr,   X86::VPSUBQZ128rm,    0 },<br>
+  { X86::VPSUBQZ256rr,   X86::VPSUBQZ256rm,    0 },<br>
+  { X86::VPSUBSBZ128rr,   X86::VPSUBSBZ128rm,    0 },<br>
+  { X86::VPSUBSBZ256rr,   X86::VPSUBSBZ256rm,    0 },<br>
+  { X86::VPSUBSWZ128rr,   X86::VPSUBSWZ128rm,    0 },<br>
+  { X86::VPSUBSWZ256rr,   X86::VPSUBSWZ256rm,    0 },<br>
+  { X86::VPSUBUSBZ128rr,  X86::VPSUBUSBZ128rm,   0 },<br>
+  { X86::VPSUBUSBZ256rr,  X86::VPSUBUSBZ256rm,   0 },<br>
+  { X86::VPSUBUSWZ128rr,  X86::VPSUBUSWZ128rm,   0 },<br>
+  { X86::VPSUBUSWZ256rr,  X86::VPSUBUSWZ256rm,   0 },<br>
+  { X86::VPSUBWZ128rr,   X86::VPSUBWZ128rm,    0 },<br>
+  { X86::VPSUBWZ256rr,   X86::VPSUBWZ256rm,    0 },<br>
+  { X86::VPUNPCKHBWZ128rr, X86::VPUNPCKHBWZ128rm,  0 },<br>
+  { X86::VPUNPCKHBWZ256rr, X86::VPUNPCKHBWZ256rm,  0 },<br>
+  { X86::VPUNPCKHDQZ128rr, X86::VPUNPCKHDQZ128rm,  0 },<br>
+  { X86::VPUNPCKHDQZ256rr, X86::VPUNPCKHDQZ256rm,  0 },<br>
+  { X86::VPUNPCKHQDQZ128rr, X86::VPUNPCKHQDQZ128rm,  0 },<br>
+  { X86::VPUNPCKHQDQZ256rr, X86::VPUNPCKHQDQZ256rm,  0 },<br>
+  { X86::VPUNPCKHWDZ128rr, X86::VPUNPCKHWDZ128rm,  0 },<br>
+  { X86::VPUNPCKHWDZ256rr, X86::VPUNPCKHWDZ256rm,  0 },<br>
+  { X86::VPUNPCKLBWZ128rr, X86::VPUNPCKLBWZ128rm,  0 },<br>
+  { X86::VPUNPCKLBWZ256rr, X86::VPUNPCKLBWZ256rm,  0 },<br>
+  { X86::VPUNPCKLDQZ128rr, X86::VPUNPCKLDQZ128rm,  0 },<br>
+  { X86::VPUNPCKLDQZ256rr, X86::VPUNPCKLDQZ256rm,  0 },<br>
+  { X86::VPUNPCKLQDQZ128rr, X86::VPUNPCKLQDQZ128rm,  0 },<br>
+  { X86::VPUNPCKLQDQZ256rr, X86::VPUNPCKLQDQZ256rm,  0 },<br>
+  { X86::VPUNPCKLWDZ128rr, X86::VPUNPCKLWDZ128rm,  0 },<br>
+  { X86::VPUNPCKLWDZ256rr, X86::VPUNPCKLWDZ256rm,  0 },<br>
+  { X86::VPXORDZ128rr,   X86::VPXORDZ128rm,    0 },<br>
+  { X86::VPXORDZ256rr,   X86::VPXORDZ256rm,    0 },<br>
+  { X86::VPXORQZ128rr,   X86::VPXORQZ128rm,    0 },<br>
+  { X86::VPXORQZ256rr,   X86::VPXORQZ256rm,    0 },<br>
+  { X86::VSHUFPDZ128rri,  X86::VSHUFPDZ128rmi,   0 },<br>
+  { X86::VSHUFPDZ256rri,  X86::VSHUFPDZ256rmi,   0 },<br>
+  { X86::VSHUFPSZ128rri,  X86::VSHUFPSZ128rmi,   0 },<br>
+  { X86::VSHUFPSZ256rri,  X86::VSHUFPSZ256rmi,   0 },<br>
+  { X86::VSUBPDZ128rr,   X86::VSUBPDZ128rm,    0 },<br>
+  { X86::VSUBPDZ256rr,   X86::VSUBPDZ256rm,    0 },<br>
+  { X86::VSUBPSZ128rr,   X86::VSUBPSZ128rm,    0 },<br>
+  { X86::VSUBPSZ256rr,   X86::VSUBPSZ256rm,    0 },<br>
+  { X86::VUNPCKHPDZ128rr,  X86::VUNPCKHPDZ128rm,   0 },<br>
+  { X86::VUNPCKHPDZ256rr,  X86::VUNPCKHPDZ256rm,   0 },<br>
+  { X86::VUNPCKHPSZ128rr,  X86::VUNPCKHPSZ128rm,   0 },<br>
+  { X86::VUNPCKHPSZ256rr,  X86::VUNPCKHPSZ256rm,   0 },<br>
+  { X86::VUNPCKLPDZ128rr,  X86::VUNPCKLPDZ128rm,   0 },<br>
+  { X86::VUNPCKLPDZ256rr,  X86::VUNPCKLPDZ256rm,   0 },<br>
+  { X86::VUNPCKLPSZ128rr,  X86::VUNPCKLPSZ128rm,   0 },<br>
+  { X86::VUNPCKLPSZ256rr,  X86::VUNPCKLPSZ256rm,   0 },<br>
+  { X86::VXORPDZ128rr,   X86::VXORPDZ128rm,    0 },<br>
+  { X86::VXORPDZ256rr,   X86::VXORPDZ256rm,    0 },<br>
+  { X86::VXORPSZ128rr,   X86::VXORPSZ128rm,    0 },<br>
+  { X86::VXORPSZ256rr,   X86::VXORPSZ256rm,    0 },<br>
+<br>
+Â Â // AVX-512 masked foldable instructions<br>
+  { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz,  TB_NO_REVERSE },<br>
+  { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz,  TB_NO_REVERSE },<br>
+  { X86::VPABSBZrrkz,    X86::VPABSBZrmkz,     0 },<br>
+  { X86::VPABSDZrrkz,    X86::VPABSDZrmkz,     0 },<br>
+  { X86::VPABSQZrrkz,    X86::VPABSQZrmkz,     0 },<br>
+  { X86::VPABSWZrrkz,    X86::VPABSWZrmkz,     0 },<br>
+  { X86::VPERMILPDZrikz,  X86::VPERMILPDZmikz,   0 },<br>
+  { X86::VPERMILPSZrikz,  X86::VPERMILPSZmikz,   0 },<br>
+  { X86::VPERMPDZrikz,   X86::VPERMPDZmikz,    0 },<br>
+  { X86::VPERMQZrikz,    X86::VPERMQZmikz,     0 },<br>
+  { X86::VPMOVSXBDZrrkz,  X86::VPMOVSXBDZrmkz,   0 },<br>
+  { X86::VPMOVSXBQZrrkz,  X86::VPMOVSXBQZrmkz,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWZrrkz,  X86::VPMOVSXBWZrmkz,   0 },<br>
+  { X86::VPMOVSXDQZrrkz,  X86::VPMOVSXDQZrmkz,   0 },<br>
+  { X86::VPMOVSXWDZrrkz,  X86::VPMOVSXWDZrmkz,   0 },<br>
+  { X86::VPMOVSXWQZrrkz,  X86::VPMOVSXWQZrmkz,   0 },<br>
+  { X86::VPMOVZXBDZrrkz,  X86::VPMOVZXBDZrmkz,   0 },<br>
+  { X86::VPMOVZXBQZrrkz,  X86::VPMOVZXBQZrmkz,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWZrrkz,  X86::VPMOVZXBWZrmkz,   0 },<br>
+  { X86::VPMOVZXDQZrrkz,  X86::VPMOVZXDQZrmkz,   0 },<br>
+  { X86::VPMOVZXWDZrrkz,  X86::VPMOVZXWDZrmkz,   0 },<br>
+  { X86::VPMOVZXWQZrrkz,  X86::VPMOVZXWQZrmkz,   0 },<br>
+  { X86::VPOPCNTDZrrkz,   X86::VPOPCNTDZrmkz,    0 },<br>
+  { X86::VPOPCNTQZrrkz,   X86::VPOPCNTQZrmkz,    0 },<br>
+  { X86::VPSHUFDZrikz,   X86::VPSHUFDZmikz,    0 },<br>
+  { X86::VPSHUFHWZrikz,   X86::VPSHUFHWZmikz,    0 },<br>
+  { X86::VPSHUFLWZrikz,   X86::VPSHUFLWZmikz,    0 },<br>
+  { X86::VPSLLDZrikz,    X86::VPSLLDZmikz,     0 },<br>
+  { X86::VPSLLQZrikz,    X86::VPSLLQZmikz,     0 },<br>
+  { X86::VPSLLWZrikz,    X86::VPSLLWZmikz,     0 },<br>
+  { X86::VPSRADZrikz,    X86::VPSRADZmikz,     0 },<br>
+  { X86::VPSRAQZrikz,    X86::VPSRAQZmikz,     0 },<br>
+  { X86::VPSRAWZrikz,    X86::VPSRAWZmikz,     0 },<br>
+  { X86::VPSRLDZrikz,    X86::VPSRLDZmikz,     0 },<br>
+  { X86::VPSRLQZrikz,    X86::VPSRLQZmikz,     0 },<br>
+  { X86::VPSRLWZrikz,    X86::VPSRLWZmikz,     0 },<br>
+<br>
+Â Â // AVX-512VL 256-bit masked foldable instructions<br>
+  { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz,   TB_NO_REVERSE },<br>
+  { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz,   TB_NO_REVERSE },<br>
+  { X86::VPABSBZ256rrkz,  X86::VPABSBZ256rmkz,   0 },<br>
+  { X86::VPABSDZ256rrkz,  X86::VPABSDZ256rmkz,   0 },<br>
+  { X86::VPABSQZ256rrkz,  X86::VPABSQZ256rmkz,   0 },<br>
+  { X86::VPABSWZ256rrkz,  X86::VPABSWZ256rmkz,   0 },<br>
+  { X86::VPERMILPDZ256rikz, X86::VPERMILPDZ256mikz,  0 },<br>
+  { X86::VPERMILPSZ256rikz, X86::VPERMILPSZ256mikz,  0 },<br>
+  { X86::VPERMPDZ256rikz,  X86::VPERMPDZ256mikz,   0 },<br>
+  { X86::VPERMQZ256rikz,  X86::VPERMQZ256mikz,   0 },<br>
+  { X86::VPMOVSXBDZ256rrkz, X86::VPMOVSXBDZ256rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBQZ256rrkz, X86::VPMOVSXBQZ256rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWZ256rrkz, X86::VPMOVSXBWZ256rmkz,  0 },<br>
+  { X86::VPMOVSXDQZ256rrkz, X86::VPMOVSXDQZ256rmkz,  0 },<br>
+  { X86::VPMOVSXWDZ256rrkz, X86::VPMOVSXWDZ256rmkz,  0 },<br>
+  { X86::VPMOVSXWQZ256rrkz, X86::VPMOVSXWQZ256rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBDZ256rrkz, X86::VPMOVZXBDZ256rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBQZ256rrkz, X86::VPMOVZXBQZ256rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWZ256rrkz, X86::VPMOVZXBWZ256rmkz,  0 },<br>
+  { X86::VPMOVZXDQZ256rrkz, X86::VPMOVZXDQZ256rmkz,  0 },<br>
+  { X86::VPMOVZXWDZ256rrkz, X86::VPMOVZXWDZ256rmkz,  0 },<br>
+  { X86::VPMOVZXWQZ256rrkz, X86::VPMOVZXWQZ256rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPSHUFDZ256rikz,  X86::VPSHUFDZ256mikz,   0 },<br>
+  { X86::VPSHUFHWZ256rikz, X86::VPSHUFHWZ256mikz,  0 },<br>
+  { X86::VPSHUFLWZ256rikz, X86::VPSHUFLWZ256mikz,  0 },<br>
+  { X86::VPSLLDZ256rikz,  X86::VPSLLDZ256mikz,   0 },<br>
+  { X86::VPSLLQZ256rikz,  X86::VPSLLQZ256mikz,   0 },<br>
+  { X86::VPSLLWZ256rikz,  X86::VPSLLWZ256mikz,   0 },<br>
+  { X86::VPSRADZ256rikz,  X86::VPSRADZ256mikz,   0 },<br>
+  { X86::VPSRAQZ256rikz,  X86::VPSRAQZ256mikz,   0 },<br>
+  { X86::VPSRAWZ256rikz,  X86::VPSRAWZ256mikz,   0 },<br>
+  { X86::VPSRLDZ256rikz,  X86::VPSRLDZ256mikz,   0 },<br>
+  { X86::VPSRLQZ256rikz,  X86::VPSRLQZ256mikz,   0 },<br>
+  { X86::VPSRLWZ256rikz,  X86::VPSRLWZ256mikz,   0 },<br>
+<br>
+Â Â // AVX-512VL 128-bit masked foldable instructions<br>
+  { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz,   TB_NO_REVERSE },<br>
+  { X86::VPABSBZ128rrkz,  X86::VPABSBZ128rmkz,   0 },<br>
+  { X86::VPABSDZ128rrkz,  X86::VPABSDZ128rmkz,   0 },<br>
+  { X86::VPABSQZ128rrkz,  X86::VPABSQZ128rmkz,   0 },<br>
+  { X86::VPABSWZ128rrkz,  X86::VPABSWZ128rmkz,   0 },<br>
+  { X86::VPERMILPDZ128rikz, X86::VPERMILPDZ128mikz,  0 },<br>
+  { X86::VPERMILPSZ128rikz, X86::VPERMILPSZ128mikz,  0 },<br>
+  { X86::VPMOVSXBDZ128rrkz, X86::VPMOVSXBDZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBQZ128rrkz, X86::VPMOVSXBQZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWZ128rrkz, X86::VPMOVSXBWZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVSXDQZ128rrkz, X86::VPMOVSXDQZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVSXWDZ128rrkz, X86::VPMOVSXWDZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVSXWQZ128rrkz, X86::VPMOVSXWQZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBDZ128rrkz, X86::VPMOVZXBDZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBQZ128rrkz, X86::VPMOVZXBQZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWZ128rrkz, X86::VPMOVZXBWZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVZXDQZ128rrkz, X86::VPMOVZXDQZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVZXWDZ128rrkz, X86::VPMOVZXWDZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPMOVZXWQZ128rrkz, X86::VPMOVZXWQZ128rmkz,  TB_NO_REVERSE },<br>
+  { X86::VPSHUFDZ128rikz,  X86::VPSHUFDZ128mikz,   0 },<br>
+  { X86::VPSHUFHWZ128rikz, X86::VPSHUFHWZ128mikz,  0 },<br>
+  { X86::VPSHUFLWZ128rikz, X86::VPSHUFLWZ128mikz,  0 },<br>
+  { X86::VPSLLDZ128rikz,  X86::VPSLLDZ128mikz,   0 },<br>
+  { X86::VPSLLQZ128rikz,  X86::VPSLLQZ128mikz,   0 },<br>
+  { X86::VPSLLWZ128rikz,  X86::VPSLLWZ128mikz,   0 },<br>
+  { X86::VPSRADZ128rikz,  X86::VPSRADZ128mikz,   0 },<br>
+  { X86::VPSRAQZ128rikz,  X86::VPSRAQZ128mikz,   0 },<br>
+  { X86::VPSRAWZ128rikz,  X86::VPSRAWZ128mikz,   0 },<br>
+  { X86::VPSRLDZ128rikz,  X86::VPSRLDZ128mikz,   0 },<br>
+  { X86::VPSRLQZ128rikz,  X86::VPSRLQZ128mikz,   0 },<br>
+  { X86::VPSRLWZ128rikz,  X86::VPSRLWZ128mikz,   0 },<br>
+<br>
+Â Â // AES foldable instructions<br>
+  { X86::AESDECLASTrr,   X86::AESDECLASTrm,    TB_ALIGN_16 },<br>
+  { X86::AESDECrr,     X86::AESDECrm,      TB_ALIGN_16 },<br>
+  { X86::AESENCLASTrr,   X86::AESENCLASTrm,    TB_ALIGN_16 },<br>
+  { X86::AESENCrr,     X86::AESENCrm,      TB_ALIGN_16 },<br>
+  { X86::VAESDECLASTrr,   X86::VAESDECLASTrm,    0 },<br>
+  { X86::VAESDECrr,     X86::VAESDECrm,      0 },<br>
+  { X86::VAESENCLASTrr,   X86::VAESENCLASTrm,    0 },<br>
+  { X86::VAESENCrr,     X86::VAESENCrm,      0 },<br>
+<br>
+Â Â // SHA foldable instructions<br>
+  { X86::SHA1MSG1rr,    X86::SHA1MSG1rm,     TB_ALIGN_16 },<br>
+  { X86::SHA1MSG2rr,    X86::SHA1MSG2rm,     TB_ALIGN_16 },<br>
+  { X86::SHA1NEXTErr,    X86::SHA1NEXTErm,     TB_ALIGN_16 },<br>
+  { X86::SHA1RNDS4rri,   X86::SHA1RNDS4rmi,    TB_ALIGN_16 },<br>
+  { X86::SHA256MSG1rr,   X86::SHA256MSG1rm,    TB_ALIGN_16 },<br>
+  { X86::SHA256MSG2rr,   X86::SHA256MSG2rm,    TB_ALIGN_16 },<br>
+  { X86::SHA256RNDS2rr,   X86::SHA256RNDS2rm,    TB_ALIGN_16 }<br>
+Â };<br>
+<br>
  for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {<br>
   AddTableEntry(<wbr>RegOp2MemOpTable2, MemOp2RegOpTable,<br>
          Entry.RegOp, Entry.MemOp,<br>
@@ -150,12 +2439,1105 @@ X86InstrInfo::X86InstrInfo(<wbr>X86Subtarget<br>
          Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);<br>
  }<br>
<br>
+Â static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {<br>
+Â Â // FMA4 foldable patterns<br>
+  { X86::VFMADDSS4rr,      X86::VFMADDSS4rm,      TB_ALIGN_NONE },<br>
+  { X86::VFMADDSS4rr_Int,    X86::VFMADDSS4rm_Int,    TB_NO_REVERSE },<br>
+  { X86::VFMADDSD4rr,      X86::VFMADDSD4rm,      TB_ALIGN_NONE },<br>
+  { X86::VFMADDSD4rr_Int,    X86::VFMADDSD4rm_Int,    TB_NO_REVERSE },<br>
+  { X86::VFMADDPS4rr,      X86::VFMADDPS4rm,      TB_ALIGN_NONE },<br>
+  { X86::VFMADDPD4rr,      X86::VFMADDPD4rm,      TB_ALIGN_NONE },<br>
+  { X86::VFMADDPS4Yrr,     X86::VFMADDPS4Yrm,     TB_ALIGN_NONE },<br>
+  { X86::VFMADDPD4Yrr,     X86::VFMADDPD4Yrm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMADDSS4rr,     X86::VFNMADDSS4rm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMADDSS4rr_Int,   X86::VFNMADDSS4rm_Int,   TB_NO_REVERSE },<br>
+  { X86::VFNMADDSD4rr,     X86::VFNMADDSD4rm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMADDSD4rr_Int,   X86::VFNMADDSD4rm_Int,   TB_NO_REVERSE },<br>
+  { X86::VFNMADDPS4rr,     X86::VFNMADDPS4rm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMADDPD4rr,     X86::VFNMADDPD4rm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMADDPS4Yrr,     X86::VFNMADDPS4Yrm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMADDPD4Yrr,     X86::VFNMADDPD4Yrm,     TB_ALIGN_NONE },<br>
+  { X86::VFMSUBSS4rr,      X86::VFMSUBSS4rm,      TB_ALIGN_NONE },<br>
+  { X86::VFMSUBSS4rr_Int,    X86::VFMSUBSS4rm_Int,    TB_NO_REVERSE },<br>
+  { X86::VFMSUBSD4rr,      X86::VFMSUBSD4rm,      TB_ALIGN_NONE },<br>
+  { X86::VFMSUBSD4rr_Int,    X86::VFMSUBSD4rm_Int,    TB_NO_REVERSE },<br>
+  { X86::VFMSUBPS4rr,      X86::VFMSUBPS4rm,      TB_ALIGN_NONE },<br>
+  { X86::VFMSUBPD4rr,      X86::VFMSUBPD4rm,      TB_ALIGN_NONE },<br>
+  { X86::VFMSUBPS4Yrr,     X86::VFMSUBPS4Yrm,     TB_ALIGN_NONE },<br>
+  { X86::VFMSUBPD4Yrr,     X86::VFMSUBPD4Yrm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBSS4rr,     X86::VFNMSUBSS4rm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBSS4rr_Int,   X86::VFNMSUBSS4rm_Int,   TB_NO_REVERSE },<br>
+  { X86::VFNMSUBSD4rr,     X86::VFNMSUBSD4rm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBSD4rr_Int,   X86::VFNMSUBSD4rm_Int,   TB_NO_REVERSE },<br>
+  { X86::VFNMSUBPS4rr,     X86::VFNMSUBPS4rm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBPD4rr,     X86::VFNMSUBPD4rm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBPS4Yrr,     X86::VFNMSUBPS4Yrm,     TB_ALIGN_NONE },<br>
+  { X86::VFNMSUBPD4Yrr,     X86::VFNMSUBPD4Yrm,     TB_ALIGN_NONE },<br>
+  { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4rm,    TB_ALIGN_NONE },<br>
+  { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4rm,    TB_ALIGN_NONE },<br>
+  { X86::VFMADDSUBPS4Yrr,    X86::VFMADDSUBPS4Yrm,    TB_ALIGN_NONE },<br>
+  { X86::VFMADDSUBPD4Yrr,    X86::VFMADDSUBPD4Yrm,    TB_ALIGN_NONE },<br>
+  { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4rm,    TB_ALIGN_NONE },<br>
+  { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4rm,    TB_ALIGN_NONE },<br>
+  { X86::VFMSUBADDPS4Yrr,    X86::VFMSUBADDPS4Yrm,    TB_ALIGN_NONE },<br>
+  { X86::VFMSUBADDPD4Yrr,    X86::VFMSUBADDPD4Yrm,    TB_ALIGN_NONE },<br>
+<br>
+Â Â // XOP foldable instructions<br>
+  { X86::VPCMOVrrr,       X86::VPCMOVrrm,       0 },<br>
+  { X86::VPCMOVYrrr,      X86::VPCMOVYrrm,      0 },<br>
+  { X86::VPERMIL2PDrr,     X86::VPERMIL2PDrm,     0 },<br>
+  { X86::VPERMIL2PDYrr,     X86::VPERMIL2PDYrm,     0 },<br>
+  { X86::VPERMIL2PSrr,     X86::VPERMIL2PSrm,     0 },<br>
+  { X86::VPERMIL2PSYrr,     X86::VPERMIL2PSYrm,     0 },<br>
+  { X86::VPPERMrrr,       X86::VPPERMrrm,       0 },<br>
+<br>
+Â Â // AVX-512 instructions with 3 source operands.<br>
+  { X86::VPERMI2Brr,      X86::VPERMI2Brm,      0 },<br>
+  { X86::VPERMI2Drr,      X86::VPERMI2Drm,      0 },<br>
+  { X86::VPERMI2PSrr,      X86::VPERMI2PSrm,      0 },<br>
+  { X86::VPERMI2PDrr,      X86::VPERMI2PDrm,      0 },<br>
+  { X86::VPERMI2Qrr,      X86::VPERMI2Qrm,      0 },<br>
+  { X86::VPERMI2Wrr,      X86::VPERMI2Wrm,      0 },<br>
+  { X86::VPERMT2Brr,      X86::VPERMT2Brm,      0 },<br>
+  { X86::VPERMT2Drr,      X86::VPERMT2Drm,      0 },<br>
+  { X86::VPERMT2PSrr,      X86::VPERMT2PSrm,      0 },<br>
+  { X86::VPERMT2PDrr,      X86::VPERMT2PDrm,      0 },<br>
+  { X86::VPERMT2Qrr,      X86::VPERMT2Qrm,      0 },<br>
+  { X86::VPERMT2Wrr,      X86::VPERMT2Wrm,      0 },<br>
+  { X86::VPTERNLOGDZrri,    X86::VPTERNLOGDZrmi,    0 },<br>
+  { X86::VPTERNLOGQZrri,    X86::VPTERNLOGQZrmi,    0 },<br>
+<br>
+Â Â // AVX-512VL 256-bit instructions with 3 source operands.<br>
+  { X86::VPERMI2B256rr,     X86::VPERMI2B256rm,     0 },<br>
+  { X86::VPERMI2D256rr,     X86::VPERMI2D256rm,     0 },<br>
+  { X86::VPERMI2PD256rr,    X86::VPERMI2PD256rm,    0 },<br>
+  { X86::VPERMI2PS256rr,    X86::VPERMI2PS256rm,    0 },<br>
+  { X86::VPERMI2Q256rr,     X86::VPERMI2Q256rm,     0 },<br>
+  { X86::VPERMI2W256rr,     X86::VPERMI2W256rm,     0 },<br>
+  { X86::VPERMT2B256rr,     X86::VPERMT2B256rm,     0 },<br>
+  { X86::VPERMT2D256rr,     X86::VPERMT2D256rm,     0 },<br>
+  { X86::VPERMT2PD256rr,    X86::VPERMT2PD256rm,    0 },<br>
+  { X86::VPERMT2PS256rr,    X86::VPERMT2PS256rm,    0 },<br>
+  { X86::VPERMT2Q256rr,     X86::VPERMT2Q256rm,     0 },<br>
+  { X86::VPERMT2W256rr,     X86::VPERMT2W256rm,     0 },<br>
+  { X86::VPTERNLOGDZ256rri,   X86::VPTERNLOGDZ256rmi,   0 },<br>
+  { X86::VPTERNLOGQZ256rri,   X86::VPTERNLOGQZ256rmi,   0 },<br>
+<br>
+Â Â // AVX-512VL 128-bit instructions with 3 source operands.<br>
+  { X86::VPERMI2B128rr,     X86::VPERMI2B128rm,     0 },<br>
+  { X86::VPERMI2D128rr,     X86::VPERMI2D128rm,     0 },<br>
+  { X86::VPERMI2PD128rr,    X86::VPERMI2PD128rm,    0 },<br>
+  { X86::VPERMI2PS128rr,    X86::VPERMI2PS128rm,    0 },<br>
+  { X86::VPERMI2Q128rr,     X86::VPERMI2Q128rm,     0 },<br>
+  { X86::VPERMI2W128rr,     X86::VPERMI2W128rm,     0 },<br>
+  { X86::VPERMT2B128rr,     X86::VPERMT2B128rm,     0 },<br>
+  { X86::VPERMT2D128rr,     X86::VPERMT2D128rm,     0 },<br>
+  { X86::VPERMT2PD128rr,    X86::VPERMT2PD128rm,    0 },<br>
+  { X86::VPERMT2PS128rr,    X86::VPERMT2PS128rm,    0 },<br>
+  { X86::VPERMT2Q128rr,     X86::VPERMT2Q128rm,     0 },<br>
+  { X86::VPERMT2W128rr,     X86::VPERMT2W128rm,     0 },<br>
+  { X86::VPTERNLOGDZ128rri,   X86::VPTERNLOGDZ128rmi,   0 },<br>
+  { X86::VPTERNLOGQZ128rri,   X86::VPTERNLOGQZ128rmi,   0 },<br>
+<br>
+Â Â // AVX-512 masked instructions<br>
+  { X86::VADDPDZrrkz,      X86::VADDPDZrmkz,      0 },<br>
+  { X86::VADDPSZrrkz,      X86::VADDPSZrmkz,      0 },<br>
+  { X86::VADDSDZrr_Intkz,    X86::VADDSDZrm_Intkz,    TB_NO_REVERSE },<br>
+  { X86::VADDSSZrr_Intkz,    X86::VADDSSZrm_Intkz,    TB_NO_REVERSE },<br>
+  { X86::VALIGNDZrrikz,     X86::VALIGNDZrmikz,     0 },<br>
+  { X86::VALIGNQZrrikz,     X86::VALIGNQZrmikz,     0 },<br>
+  { X86::VANDNPDZrrkz,     X86::VANDNPDZrmkz,     0 },<br>
+  { X86::VANDNPSZrrkz,     X86::VANDNPSZrmkz,     0 },<br>
+  { X86::VANDPDZrrkz,      X86::VANDPDZrmkz,      0 },<br>
+  { X86::VANDPSZrrkz,      X86::VANDPSZrmkz,      0 },<br>
+  { X86::VDIVPDZrrkz,      X86::VDIVPDZrmkz,      0 },<br>
+  { X86::VDIVPSZrrkz,      X86::VDIVPSZrmkz,      0 },<br>
+  { X86::VDIVSDZrr_Intkz,    X86::VDIVSDZrm_Intkz,    TB_NO_REVERSE },<br>
+  { X86::VDIVSSZrr_Intkz,    X86::VDIVSSZrm_Intkz,    TB_NO_REVERSE },<br>
+  { X86::VINSERTF32x4Zrrkz,   X86::VINSERTF32x4Zrmkz,   0 },<br>
+  { X86::VINSERTF32x8Zrrkz,   X86::VINSERTF32x8Zrmkz,   0 },<br>
+  { X86::VINSERTF64x2Zrrkz,   X86::VINSERTF64x2Zrmkz,   0 },<br>
+  { X86::VINSERTF64x4Zrrkz,   X86::VINSERTF64x4Zrmkz,   0 },<br>
+  { X86::VINSERTI32x4Zrrkz,   X86::VINSERTI32x4Zrmkz,   0 },<br>
+  { X86::VINSERTI32x8Zrrkz,   X86::VINSERTI32x8Zrmkz,   0 },<br>
+  { X86::VINSERTI64x2Zrrkz,   X86::VINSERTI64x2Zrmkz,   0 },<br>
+  { X86::VINSERTI64x4Zrrkz,   X86::VINSERTI64x4Zrmkz,   0 },<br>
+  { X86::VMAXCPDZrrkz,     X86::VMAXCPDZrmkz,     0 },<br>
+  { X86::VMAXCPSZrrkz,     X86::VMAXCPSZrmkz,     0 },<br>
+  { X86::VMAXPDZrrkz,      X86::VMAXPDZrmkz,      0 },<br>
+  { X86::VMAXPSZrrkz,      X86::VMAXPSZrmkz,      0 },<br>
+  { X86::VMAXSDZrr_Intkz,    X86::VMAXSDZrm_Intkz,    0 },<br>
+  { X86::VMAXSSZrr_Intkz,    X86::VMAXSSZrm_Intkz,    0 },<br>
+  { X86::VMINCPDZrrkz,     X86::VMINCPDZrmkz,     0 },<br>
+  { X86::VMINCPSZrrkz,     X86::VMINCPSZrmkz,     0 },<br>
+  { X86::VMINPDZrrkz,      X86::VMINPDZrmkz,      0 },<br>
+  { X86::VMINPSZrrkz,      X86::VMINPSZrmkz,      0 },<br>
+  { X86::VMINSDZrr_Intkz,    X86::VMINSDZrm_Intkz,    0 },<br>
+  { X86::VMINSSZrr_Intkz,    X86::VMINSSZrm_Intkz,    0 },<br>
+  { X86::VMULPDZrrkz,      X86::VMULPDZrmkz,      0 },<br>
+  { X86::VMULPSZrrkz,      X86::VMULPSZrmkz,      0 },<br>
+  { X86::VMULSDZrr_Intkz,    X86::VMULSDZrm_Intkz,    TB_NO_REVERSE },<br>
+  { X86::VMULSSZrr_Intkz,    X86::VMULSSZrm_Intkz,    TB_NO_REVERSE },<br>
+  { X86::VORPDZrrkz,      X86::VORPDZrmkz,      0 },<br>
+  { X86::VORPSZrrkz,      X86::VORPSZrmkz,      0 },<br>
+  { X86::VPACKSSDWZrrkz,    X86::VPACKSSDWZrmkz,    0 },<br>
+  { X86::VPACKSSWBZrrkz,    X86::VPACKSSWBZrmkz,    0 },<br>
+  { X86::VPACKUSDWZrrkz,    X86::VPACKUSDWZrmkz,    0 },<br>
+  { X86::VPACKUSWBZrrkz,    X86::VPACKUSWBZrmkz,    0 },<br>
+  { X86::VPADDBZrrkz,      X86::VPADDBZrmkz,      0 },<br>
+  { X86::VPADDDZrrkz,      X86::VPADDDZrmkz,      0 },<br>
+  { X86::VPADDQZrrkz,      X86::VPADDQZrmkz,      0 },<br>
+  { X86::VPADDSBZrrkz,     X86::VPADDSBZrmkz,     0 },<br>
+  { X86::VPADDSWZrrkz,     X86::VPADDSWZrmkz,     0 },<br>
+  { X86::VPADDUSBZrrkz,     X86::VPADDUSBZrmkz,     0 },<br>
+  { X86::VPADDUSWZrrkz,     X86::VPADDUSWZrmkz,     0 },<br>
+  { X86::VPADDWZrrkz,      X86::VPADDWZrmkz,      0 },<br>
+  { X86::VPALIGNRZrrikz,    X86::VPALIGNRZrmikz,    0 },<br>
+  { X86::VPANDDZrrkz,      X86::VPANDDZrmkz,      0 },<br>
+  { X86::VPANDNDZrrkz,     X86::VPANDNDZrmkz,     0 },<br>
+  { X86::VPANDNQZrrkz,     X86::VPANDNQZrmkz,     0 },<br>
+  { X86::VPANDQZrrkz,      X86::VPANDQZrmkz,      0 },<br>
+  { X86::VPAVGBZrrkz,      X86::VPAVGBZrmkz,      0 },<br>
+  { X86::VPAVGWZrrkz,      X86::VPAVGWZrmkz,      0 },<br>
+  { X86::VPERMBZrrkz,      X86::VPERMBZrmkz,      0 },<br>
+  { X86::VPERMDZrrkz,      X86::VPERMDZrmkz,      0 },<br>
+  { X86::VPERMILPDZrrkz,    X86::VPERMILPDZrmkz,    0 },<br>
+  { X86::VPERMILPSZrrkz,    X86::VPERMILPSZrmkz,    0 },<br>
+  { X86::VPERMPDZrrkz,     X86::VPERMPDZrmkz,     0 },<br>
+  { X86::VPERMPSZrrkz,     X86::VPERMPSZrmkz,     0 },<br>
+  { X86::VPERMQZrrkz,      X86::VPERMQZrmkz,      0 },<br>
+  { X86::VPERMWZrrkz,      X86::VPERMWZrmkz,      0 },<br>
+  { X86::VPMADDUBSWZrrkz,    X86::VPMADDUBSWZrmkz,    0 },<br>
+  { X86::VPMADDWDZrrkz,     X86::VPMADDWDZrmkz,     0 },<br>
+  { X86::VPMAXSBZrrkz,     X86::VPMAXSBZrmkz,     0 },<br>
+  { X86::VPMAXSDZrrkz,     X86::VPMAXSDZrmkz,     0 },<br>
+  { X86::VPMAXSQZrrkz,     X86::VPMAXSQZrmkz,     0 },<br>
+  { X86::VPMAXSWZrrkz,     X86::VPMAXSWZrmkz,     0 },<br>
+  { X86::VPMAXUBZrrkz,     X86::VPMAXUBZrmkz,     0 },<br>
+  { X86::VPMAXUDZrrkz,     X86::VPMAXUDZrmkz,     0 },<br>
+  { X86::VPMAXUQZrrkz,     X86::VPMAXUQZrmkz,     0 },<br>
+  { X86::VPMAXUWZrrkz,     X86::VPMAXUWZrmkz,     0 },<br>
+  { X86::VPMINSBZrrkz,     X86::VPMINSBZrmkz,     0 },<br>
+  { X86::VPMINSDZrrkz,     X86::VPMINSDZrmkz,     0 },<br>
+  { X86::VPMINSQZrrkz,     X86::VPMINSQZrmkz,     0 },<br>
+  { X86::VPMINSWZrrkz,     X86::VPMINSWZrmkz,     0 },<br>
+  { X86::VPMINUBZrrkz,     X86::VPMINUBZrmkz,     0 },<br>
+  { X86::VPMINUDZrrkz,     X86::VPMINUDZrmkz,     0 },<br>
+  { X86::VPMINUQZrrkz,     X86::VPMINUQZrmkz,     0 },<br>
+  { X86::VPMINUWZrrkz,     X86::VPMINUWZrmkz,     0 },<br>
+  { X86::VPMULLDZrrkz,     X86::VPMULLDZrmkz,     0 },<br>
+  { X86::VPMULLQZrrkz,     X86::VPMULLQZrmkz,     0 },<br>
+  { X86::VPMULLWZrrkz,     X86::VPMULLWZrmkz,     0 },<br>
+  { X86::VPMULDQZrrkz,     X86::VPMULDQZrmkz,     0 },<br>
+  { X86::VPMULUDQZrrkz,     X86::VPMULUDQZrmkz,     0 },<br>
+  { X86::VPORDZrrkz,      X86::VPORDZrmkz,      0 },<br>
+  { X86::VPORQZrrkz,      X86::VPORQZrmkz,      0 },<br>
+  { X86::VPSHUFBZrrkz,     X86::VPSHUFBZrmkz,     0 },<br>
+  { X86::VPSLLDZrrkz,      X86::VPSLLDZrmkz,      0 },<br>
+  { X86::VPSLLQZrrkz,      X86::VPSLLQZrmkz,      0 },<br>
+  { X86::VPSLLVDZrrkz,     X86::VPSLLVDZrmkz,     0 },<br>
+  { X86::VPSLLVQZrrkz,     X86::VPSLLVQZrmkz,     0 },<br>
+  { X86::VPSLLVWZrrkz,     X86::VPSLLVWZrmkz,     0 },<br>
+  { X86::VPSLLWZrrkz,      X86::VPSLLWZrmkz,      0 },<br>
+  { X86::VPSRADZrrkz,      X86::VPSRADZrmkz,      0 },<br>
+  { X86::VPSRAQZrrkz,      X86::VPSRAQZrmkz,      0 },<br>
+  { X86::VPSRAVDZrrkz,     X86::VPSRAVDZrmkz,     0 },<br>
+  { X86::VPSRAVQZrrkz,     X86::VPSRAVQZrmkz,     0 },<br>
+  { X86::VPSRAVWZrrkz,     X86::VPSRAVWZrmkz,     0 },<br>
+  { X86::VPSRAWZrrkz,      X86::VPSRAWZrmkz,      0 },<br>
+  { X86::VPSRLDZrrkz,      X86::VPSRLDZrmkz,      0 },<br>
+  { X86::VPSRLQZrrkz,      X86::VPSRLQZrmkz,      0 },<br>
+  { X86::VPSRLVDZrrkz,     X86::VPSRLVDZrmkz,     0 },<br>
+  { X86::VPSRLVQZrrkz,     X86::VPSRLVQZrmkz,     0 },<br>
+  { X86::VPSRLVWZrrkz,     X86::VPSRLVWZrmkz,     0 },<br>
+  { X86::VPSRLWZrrkz,      X86::VPSRLWZrmkz,      0 },<br>
+  { X86::VPSUBBZrrkz,      X86::VPSUBBZrmkz,      0 },<br>
+  { X86::VPSUBDZrrkz,      X86::VPSUBDZrmkz,      0 },<br>
+  { X86::VPSUBQZrrkz,      X86::VPSUBQZrmkz,      0 },<br>
+  { X86::VPSUBSBZrrkz,     X86::VPSUBSBZrmkz,     0 },<br>
+  { X86::VPSUBSWZrrkz,     X86::VPSUBSWZrmkz,     0 },<br>
+  { X86::VPSUBUSBZrrkz,     X86::VPSUBUSBZrmkz,     0 },<br>
+  { X86::VPSUBUSWZrrkz,     X86::VPSUBUSWZrmkz,     0 },<br>
+  { X86::VPSUBWZrrkz,      X86::VPSUBWZrmkz,      0 },<br>
+  { X86::VPUNPCKHBWZrrkz,    X86::VPUNPCKHBWZrmkz,    0 },<br>
+  { X86::VPUNPCKHDQZrrkz,    X86::VPUNPCKHDQZrmkz,    0 },<br>
+  { X86::VPUNPCKHQDQZrrkz,   X86::VPUNPCKHQDQZrmkz,   0 },<br>
+  { X86::VPUNPCKHWDZrrkz,    X86::VPUNPCKHWDZrmkz,    0 },<br>
+  { X86::VPUNPCKLBWZrrkz,    X86::VPUNPCKLBWZrmkz,    0 },<br>
+  { X86::VPUNPCKLDQZrrkz,    X86::VPUNPCKLDQZrmkz,    0 },<br>
+  { X86::VPUNPCKLQDQZrrkz,   X86::VPUNPCKLQDQZrmkz,   0 },<br>
+  { X86::VPUNPCKLWDZrrkz,    X86::VPUNPCKLWDZrmkz,    0 },<br>
+  { X86::VPXORDZrrkz,      X86::VPXORDZrmkz,      0 },<br>
+  { X86::VPXORQZrrkz,      X86::VPXORQZrmkz,      0 },<br>
+  { X86::VSHUFPDZrrikz,     X86::VSHUFPDZrmikz,     0 },<br>
+  { X86::VSHUFPSZrrikz,     X86::VSHUFPSZrmikz,     0 },<br>
+  { X86::VSUBPDZrrkz,      X86::VSUBPDZrmkz,      0 },<br>
+  { X86::VSUBPSZrrkz,      X86::VSUBPSZrmkz,      0 },<br>
+  { X86::VSUBSDZrr_Intkz,    X86::VSUBSDZrm_Intkz,    TB_NO_REVERSE },<br>
+  { X86::VSUBSSZrr_Intkz,    X86::VSUBSSZrm_Intkz,    TB_NO_REVERSE },<br>
+  { X86::VUNPCKHPDZrrkz,    X86::VUNPCKHPDZrmkz,    0 },<br>
+  { X86::VUNPCKHPSZrrkz,    X86::VUNPCKHPSZrmkz,    0 },<br>
+  { X86::VUNPCKLPDZrrkz,    X86::VUNPCKLPDZrmkz,    0 },<br>
+  { X86::VUNPCKLPSZrrkz,    X86::VUNPCKLPSZrmkz,    0 },<br>
+  { X86::VXORPDZrrkz,      X86::VXORPDZrmkz,      0 },<br>
+  { X86::VXORPSZrrkz,      X86::VXORPSZrmkz,      0 },<br>
+<br>
+Â Â // AVX-512{F,VL} masked arithmetic instructions 256-bit<br>
+  { X86::VADDPDZ256rrkz,    X86::VADDPDZ256rmkz,    0 },<br>
+  { X86::VADDPSZ256rrkz,    X86::VADDPSZ256rmkz,    0 },<br>
+  { X86::VALIGNDZ256rrikz,   X86::VALIGNDZ256rmikz,   0 },<br>
+  { X86::VALIGNQZ256rrikz,   X86::VALIGNQZ256rmikz,   0 },<br>
+  { X86::VANDNPDZ256rrkz,    X86::VANDNPDZ256rmkz,    0 },<br>
+  { X86::VANDNPSZ256rrkz,    X86::VANDNPSZ256rmkz,    0 },<br>
+  { X86::VANDPDZ256rrkz,    X86::VANDPDZ256rmkz,    0 },<br>
+  { X86::VANDPSZ256rrkz,    X86::VANDPSZ256rmkz,    0 },<br>
+  { X86::VDIVPDZ256rrkz,    X86::VDIVPDZ256rmkz,    0 },<br>
+  { X86::VDIVPSZ256rrkz,    X86::VDIVPSZ256rmkz,    0 },<br>
+  { X86::VINSERTF32x4Z256rrkz, X86::VINSERTF32x4Z256rmkz, 0 },<br>
+  { X86::VINSERTF64x2Z256rrkz, X86::VINSERTF64x2Z256rmkz, 0 },<br>
+  { X86::VINSERTI32x4Z256rrkz, X86::VINSERTI32x4Z256rmkz, 0 },<br>
+  { X86::VINSERTI64x2Z256rrkz, X86::VINSERTI64x2Z256rmkz, 0 },<br>
+  { X86::VMAXCPDZ256rrkz,    X86::VMAXCPDZ256rmkz,    0 },<br>
+  { X86::VMAXCPSZ256rrkz,    X86::VMAXCPSZ256rmkz,    0 },<br>
+  { X86::VMAXPDZ256rrkz,    X86::VMAXPDZ256rmkz,    0 },<br>
+  { X86::VMAXPSZ256rrkz,    X86::VMAXPSZ256rmkz,    0 },<br>
+  { X86::VMINCPDZ256rrkz,    X86::VMINCPDZ256rmkz,    0 },<br>
+  { X86::VMINCPSZ256rrkz,    X86::VMINCPSZ256rmkz,    0 },<br>
+  { X86::VMINPDZ256rrkz,    X86::VMINPDZ256rmkz,    0 },<br>
+  { X86::VMINPSZ256rrkz,    X86::VMINPSZ256rmkz,    0 },<br>
+  { X86::VMULPDZ256rrkz,    X86::VMULPDZ256rmkz,    0 },<br>
+  { X86::VMULPSZ256rrkz,    X86::VMULPSZ256rmkz,    0 },<br>
+  { X86::VORPDZ256rrkz,     X86::VORPDZ256rmkz,     0 },<br>
+  { X86::VORPSZ256rrkz,     X86::VORPSZ256rmkz,     0 },<br>
+  { X86::VPACKSSDWZ256rrkz,   X86::VPACKSSDWZ256rmkz,   0 },<br>
+  { X86::VPACKSSWBZ256rrkz,   X86::VPACKSSWBZ256rmkz,   0 },<br>
+  { X86::VPACKUSDWZ256rrkz,   X86::VPACKUSDWZ256rmkz,   0 },<br>
+  { X86::VPACKUSWBZ256rrkz,   X86::VPACKUSWBZ256rmkz,   0 },<br>
+  { X86::VPADDBZ256rrkz,    X86::VPADDBZ256rmkz,    0 },<br>
+  { X86::VPADDDZ256rrkz,    X86::VPADDDZ256rmkz,    0 },<br>
+  { X86::VPADDQZ256rrkz,    X86::VPADDQZ256rmkz,    0 },<br>
+  { X86::VPADDSBZ256rrkz,    X86::VPADDSBZ256rmkz,    0 },<br>
+  { X86::VPADDSWZ256rrkz,    X86::VPADDSWZ256rmkz,    0 },<br>
+  { X86::VPADDUSBZ256rrkz,   X86::VPADDUSBZ256rmkz,   0 },<br>
+  { X86::VPADDUSWZ256rrkz,   X86::VPADDUSWZ256rmkz,   0 },<br>
+  { X86::VPADDWZ256rrkz,    X86::VPADDWZ256rmkz,    0 },<br>
+  { X86::VPALIGNRZ256rrikz,   X86::VPALIGNRZ256rmikz,   0 },<br>
+  { X86::VPANDDZ256rrkz,    X86::VPANDDZ256rmkz,    0 },<br>
+  { X86::VPANDNDZ256rrkz,    X86::VPANDNDZ256rmkz,    0 },<br>
+  { X86::VPANDNQZ256rrkz,    X86::VPANDNQZ256rmkz,    0 },<br>
+  { X86::VPANDQZ256rrkz,    X86::VPANDQZ256rmkz,    0 },<br>
+  { X86::VPAVGBZ256rrkz,    X86::VPAVGBZ256rmkz,    0 },<br>
+  { X86::VPAVGWZ256rrkz,    X86::VPAVGWZ256rmkz,    0 },<br>
+  { X86::VPERMBZ256rrkz,    X86::VPERMBZ256rmkz,    0 },<br>
+  { X86::VPERMDZ256rrkz,    X86::VPERMDZ256rmkz,    0 },<br>
+  { X86::VPERMILPDZ256rrkz,   X86::VPERMILPDZ256rmkz,   0 },<br>
+  { X86::VPERMILPSZ256rrkz,   X86::VPERMILPSZ256rmkz,   0 },<br>
+  { X86::VPERMPDZ256rrkz,    X86::VPERMPDZ256rmkz,    0 },<br>
+  { X86::VPERMPSZ256rrkz,    X86::VPERMPSZ256rmkz,    0 },<br>
+  { X86::VPERMQZ256rrkz,    X86::VPERMQZ256rmkz,    0 },<br>
+  { X86::VPERMWZ256rrkz,    X86::VPERMWZ256rmkz,    0 },<br>
+  { X86::VPMADDUBSWZ256rrkz,  X86::VPMADDUBSWZ256rmkz,  0 },<br>
+  { X86::VPMADDWDZ256rrkz,   X86::VPMADDWDZ256rmkz,   0 },<br>
+  { X86::VPMAXSBZ256rrkz,    X86::VPMAXSBZ256rmkz,    0 },<br>
+  { X86::VPMAXSDZ256rrkz,    X86::VPMAXSDZ256rmkz,    0 },<br>
+  { X86::VPMAXSQZ256rrkz,    X86::VPMAXSQZ256rmkz,    0 },<br>
+  { X86::VPMAXSWZ256rrkz,    X86::VPMAXSWZ256rmkz,    0 },<br>
+  { X86::VPMAXUBZ256rrkz,    X86::VPMAXUBZ256rmkz,    0 },<br>
+  { X86::VPMAXUDZ256rrkz,    X86::VPMAXUDZ256rmkz,    0 },<br>
+  { X86::VPMAXUQZ256rrkz,    X86::VPMAXUQZ256rmkz,    0 },<br>
+  { X86::VPMAXUWZ256rrkz,    X86::VPMAXUWZ256rmkz,    0 },<br>
+  { X86::VPMINSBZ256rrkz,    X86::VPMINSBZ256rmkz,    0 },<br>
+  { X86::VPMINSDZ256rrkz,    X86::VPMINSDZ256rmkz,    0 },<br>
+  { X86::VPMINSQZ256rrkz,    X86::VPMINSQZ256rmkz,    0 },<br>
+  { X86::VPMINSWZ256rrkz,    X86::VPMINSWZ256rmkz,    0 },<br>
+  { X86::VPMINUBZ256rrkz,    X86::VPMINUBZ256rmkz,    0 },<br>
+  { X86::VPMINUDZ256rrkz,    X86::VPMINUDZ256rmkz,    0 },<br>
+  { X86::VPMINUQZ256rrkz,    X86::VPMINUQZ256rmkz,    0 },<br>
+  { X86::VPMINUWZ256rrkz,    X86::VPMINUWZ256rmkz,    0 },<br>
+  { X86::VPMULDQZ256rrkz,    X86::VPMULDQZ256rmkz,    0 },<br>
+  { X86::VPMULLDZ256rrkz,    X86::VPMULLDZ256rmkz,    0 },<br>
+  { X86::VPMULLQZ256rrkz,    X86::VPMULLQZ256rmkz,    0 },<br>
+  { X86::VPMULLWZ256rrkz,    X86::VPMULLWZ256rmkz,    0 },<br>
+  { X86::VPMULUDQZ256rrkz,   X86::VPMULUDQZ256rmkz,   0 },<br>
+  { X86::VPORDZ256rrkz,     X86::VPORDZ256rmkz,     0 },<br>
+  { X86::VPORQZ256rrkz,     X86::VPORQZ256rmkz,     0 },<br>
+  { X86::VPSHUFBZ256rrkz,    X86::VPSHUFBZ256rmkz,    0 },<br>
+  { X86::VPSLLDZ256rrkz,    X86::VPSLLDZ256rmkz,    0 },<br>
+  { X86::VPSLLQZ256rrkz,    X86::VPSLLQZ256rmkz,    0 },<br>
+  { X86::VPSLLVDZ256rrkz,    X86::VPSLLVDZ256rmkz,    0 },<br>
+  { X86::VPSLLVQZ256rrkz,    X86::VPSLLVQZ256rmkz,    0 },<br>
+  { X86::VPSLLVWZ256rrkz,    X86::VPSLLVWZ256rmkz,    0 },<br>
+  { X86::VPSLLWZ256rrkz,    X86::VPSLLWZ256rmkz,    0 },<br>
+  { X86::VPSRADZ256rrkz,    X86::VPSRADZ256rmkz,    0 },<br>
+  { X86::VPSRAQZ256rrkz,    X86::VPSRAQZ256rmkz,    0 },<br>
+  { X86::VPSRAVDZ256rrkz,    X86::VPSRAVDZ256rmkz,    0 },<br>
+  { X86::VPSRAVQZ256rrkz,    X86::VPSRAVQZ256rmkz,    0 },<br>
+  { X86::VPSRAVWZ256rrkz,    X86::VPSRAVWZ256rmkz,    0 },<br>
+  { X86::VPSRAWZ256rrkz,    X86::VPSRAWZ256rmkz,    0 },<br>
+  { X86::VPSRLDZ256rrkz,    X86::VPSRLDZ256rmkz,    0 },<br>
+  { X86::VPSRLQZ256rrkz,    X86::VPSRLQZ256rmkz,    0 },<br>
+  { X86::VPSRLVDZ256rrkz,    X86::VPSRLVDZ256rmkz,    0 },<br>
+  { X86::VPSRLVQZ256rrkz,    X86::VPSRLVQZ256rmkz,    0 },<br>
+  { X86::VPSRLVWZ256rrkz,    X86::VPSRLVWZ256rmkz,    0 },<br>
+  { X86::VPSRLWZ256rrkz,    X86::VPSRLWZ256rmkz,    0 },<br>
+  { X86::VPSUBBZ256rrkz,    X86::VPSUBBZ256rmkz,    0 },<br>
+  { X86::VPSUBDZ256rrkz,    X86::VPSUBDZ256rmkz,    0 },<br>
+  { X86::VPSUBQZ256rrkz,    X86::VPSUBQZ256rmkz,    0 },<br>
+  { X86::VPSUBSBZ256rrkz,    X86::VPSUBSBZ256rmkz,    0 },<br>
+  { X86::VPSUBSWZ256rrkz,    X86::VPSUBSWZ256rmkz,    0 },<br>
+  { X86::VPSUBUSBZ256rrkz,   X86::VPSUBUSBZ256rmkz,   0 },<br>
+  { X86::VPSUBUSWZ256rrkz,   X86::VPSUBUSWZ256rmkz,   0 },<br>
+  { X86::VPSUBWZ256rrkz,    X86::VPSUBWZ256rmkz,    0 },<br>
+  { X86::VPUNPCKHBWZ256rrkz,  X86::VPUNPCKHBWZ256rmkz,  0 },<br>
+  { X86::VPUNPCKHDQZ256rrkz,  X86::VPUNPCKHDQZ256rmkz,  0 },<br>
+  { X86::VPUNPCKHQDQZ256rrkz,  X86::VPUNPCKHQDQZ256rmkz,  0 },<br>
+  { X86::VPUNPCKHWDZ256rrkz,  X86::VPUNPCKHWDZ256rmkz,  0 },<br>
+  { X86::VPUNPCKLBWZ256rrkz,  X86::VPUNPCKLBWZ256rmkz,  0 },<br>
+  { X86::VPUNPCKLDQZ256rrkz,  X86::VPUNPCKLDQZ256rmkz,  0 },<br>
+  { X86::VPUNPCKLQDQZ256rrkz,  X86::VPUNPCKLQDQZ256rmkz,  0 },<br>
+  { X86::VPUNPCKLWDZ256rrkz,  X86::VPUNPCKLWDZ256rmkz,  0 },<br>
+  { X86::VPXORDZ256rrkz,    X86::VPXORDZ256rmkz,    0 },<br>
+  { X86::VPXORQZ256rrkz,    X86::VPXORQZ256rmkz,    0 },<br>
+  { X86::VSHUFPDZ256rrikz,   X86::VSHUFPDZ256rmikz,   0 },<br>
+  { X86::VSHUFPSZ256rrikz,   X86::VSHUFPSZ256rmikz,   0 },<br>
+  { X86::VSUBPDZ256rrkz,    X86::VSUBPDZ256rmkz,    0 },<br>
+  { X86::VSUBPSZ256rrkz,    X86::VSUBPSZ256rmkz,    0 },<br>
+  { X86::VUNPCKHPDZ256rrkz,   X86::VUNPCKHPDZ256rmkz,   0 },<br>
+  { X86::VUNPCKHPSZ256rrkz,   X86::VUNPCKHPSZ256rmkz,   0 },<br>
+  { X86::VUNPCKLPDZ256rrkz,   X86::VUNPCKLPDZ256rmkz,   0 },<br>
+  { X86::VUNPCKLPSZ256rrkz,   X86::VUNPCKLPSZ256rmkz,   0 },<br>
+  { X86::VXORPDZ256rrkz,    X86::VXORPDZ256rmkz,    0 },<br>
+  { X86::VXORPSZ256rrkz,    X86::VXORPSZ256rmkz,    0 },<br>
+<br>
+Â Â // AVX-512{F,VL} masked arithmetic instructions 128-bit<br>
+  { X86::VADDPDZ128rrkz,    X86::VADDPDZ128rmkz,    0 },<br>
+  { X86::VADDPSZ128rrkz,    X86::VADDPSZ128rmkz,    0 },<br>
+  { X86::VALIGNDZ128rrikz,   X86::VALIGNDZ128rmikz,   0 },<br>
+  { X86::VALIGNQZ128rrikz,   X86::VALIGNQZ128rmikz,   0 },<br>
+  { X86::VANDNPDZ128rrkz,    X86::VANDNPDZ128rmkz,    0 },<br>
+  { X86::VANDNPSZ128rrkz,    X86::VANDNPSZ128rmkz,    0 },<br>
+  { X86::VANDPDZ128rrkz,    X86::VANDPDZ128rmkz,    0 },<br>
+  { X86::VANDPSZ128rrkz,    X86::VANDPSZ128rmkz,    0 },<br>
+  { X86::VDIVPDZ128rrkz,    X86::VDIVPDZ128rmkz,    0 },<br>
+  { X86::VDIVPSZ128rrkz,    X86::VDIVPSZ128rmkz,    0 },<br>
+  { X86::VMAXCPDZ128rrkz,    X86::VMAXCPDZ128rmkz,    0 },<br>
+  { X86::VMAXCPSZ128rrkz,    X86::VMAXCPSZ128rmkz,    0 },<br>
+  { X86::VMAXPDZ128rrkz,    X86::VMAXPDZ128rmkz,    0 },<br>
+  { X86::VMAXPSZ128rrkz,    X86::VMAXPSZ128rmkz,    0 },<br>
+  { X86::VMINCPDZ128rrkz,    X86::VMINCPDZ128rmkz,    0 },<br>
+  { X86::VMINCPSZ128rrkz,    X86::VMINCPSZ128rmkz,    0 },<br>
+  { X86::VMINPDZ128rrkz,    X86::VMINPDZ128rmkz,    0 },<br>
+  { X86::VMINPSZ128rrkz,    X86::VMINPSZ128rmkz,    0 },<br>
+  { X86::VMULPDZ128rrkz,    X86::VMULPDZ128rmkz,    0 },<br>
+  { X86::VMULPSZ128rrkz,    X86::VMULPSZ128rmkz,    0 },<br>
+  { X86::VORPDZ128rrkz,     X86::VORPDZ128rmkz,     0 },<br>
+  { X86::VORPSZ128rrkz,     X86::VORPSZ128rmkz,     0 },<br>
+  { X86::VPACKSSDWZ128rrkz,   X86::VPACKSSDWZ128rmkz,   0 },<br>
+  { X86::VPACKSSWBZ128rrkz,   X86::VPACKSSWBZ128rmkz,   0 },<br>
+  { X86::VPACKUSDWZ128rrkz,   X86::VPACKUSDWZ128rmkz,   0 },<br>
+  { X86::VPACKUSWBZ128rrkz,   X86::VPACKUSWBZ128rmkz,   0 },<br>
+  { X86::VPADDBZ128rrkz,    X86::VPADDBZ128rmkz,    0 },<br>
+  { X86::VPADDDZ128rrkz,    X86::VPADDDZ128rmkz,    0 },<br>
+  { X86::VPADDQZ128rrkz,    X86::VPADDQZ128rmkz,    0 },<br>
+  { X86::VPADDSBZ128rrkz,    X86::VPADDSBZ128rmkz,    0 },<br>
+  { X86::VPADDSWZ128rrkz,    X86::VPADDSWZ128rmkz,    0 },<br>
+  { X86::VPADDUSBZ128rrkz,   X86::VPADDUSBZ128rmkz,   0 },<br>
+  { X86::VPADDUSWZ128rrkz,   X86::VPADDUSWZ128rmkz,   0 },<br>
+  { X86::VPADDWZ128rrkz,    X86::VPADDWZ128rmkz,    0 },<br>
+  { X86::VPALIGNRZ128rrikz,   X86::VPALIGNRZ128rmikz,   0 },<br>
+  { X86::VPANDDZ128rrkz,    X86::VPANDDZ128rmkz,    0 },<br>
+  { X86::VPANDNDZ128rrkz,    X86::VPANDNDZ128rmkz,    0 },<br>
+  { X86::VPANDNQZ128rrkz,    X86::VPANDNQZ128rmkz,    0 },<br>
+  { X86::VPANDQZ128rrkz,    X86::VPANDQZ128rmkz,    0 },<br>
+  { X86::VPAVGBZ128rrkz,    X86::VPAVGBZ128rmkz,    0 },<br>
+  { X86::VPAVGWZ128rrkz,    X86::VPAVGWZ128rmkz,    0 },<br>
+  { X86::VPERMBZ128rrkz,    X86::VPERMBZ128rmkz,    0 },<br>
+  { X86::VPERMILPDZ128rrkz,   X86::VPERMILPDZ128rmkz,   0 },<br>
+  { X86::VPERMILPSZ128rrkz,   X86::VPERMILPSZ128rmkz,   0 },<br>
+  { X86::VPERMWZ128rrkz,    X86::VPERMWZ128rmkz,    0 },<br>
+  { X86::VPMADDUBSWZ128rrkz,  X86::VPMADDUBSWZ128rmkz,  0 },<br>
+  { X86::VPMADDWDZ128rrkz,   X86::VPMADDWDZ128rmkz,   0 },<br>
+  { X86::VPMAXSBZ128rrkz,    X86::VPMAXSBZ128rmkz,    0 },<br>
+  { X86::VPMAXSDZ128rrkz,    X86::VPMAXSDZ128rmkz,    0 },<br>
+  { X86::VPMAXSQZ128rrkz,    X86::VPMAXSQZ128rmkz,    0 },<br>
+  { X86::VPMAXSWZ128rrkz,    X86::VPMAXSWZ128rmkz,    0 },<br>
+  { X86::VPMAXUBZ128rrkz,    X86::VPMAXUBZ128rmkz,    0 },<br>
+  { X86::VPMAXUDZ128rrkz,    X86::VPMAXUDZ128rmkz,    0 },<br>
+  { X86::VPMAXUQZ128rrkz,    X86::VPMAXUQZ128rmkz,    0 },<br>
+  { X86::VPMAXUWZ128rrkz,    X86::VPMAXUWZ128rmkz,    0 },<br>
+  { X86::VPMINSBZ128rrkz,    X86::VPMINSBZ128rmkz,    0 },<br>
+  { X86::VPMINSDZ128rrkz,    X86::VPMINSDZ128rmkz,    0 },<br>
+  { X86::VPMINSQZ128rrkz,    X86::VPMINSQZ128rmkz,    0 },<br>
+  { X86::VPMINSWZ128rrkz,    X86::VPMINSWZ128rmkz,    0 },<br>
+  { X86::VPMINUBZ128rrkz,    X86::VPMINUBZ128rmkz,    0 },<br>
+  { X86::VPMINUDZ128rrkz,    X86::VPMINUDZ128rmkz,    0 },<br>
+  { X86::VPMINUQZ128rrkz,    X86::VPMINUQZ128rmkz,    0 },<br>
+  { X86::VPMINUWZ128rrkz,    X86::VPMINUWZ128rmkz,    0 },<br>
+  { X86::VPMULDQZ128rrkz,    X86::VPMULDQZ128rmkz,    0 },<br>
+  { X86::VPMULLDZ128rrkz,    X86::VPMULLDZ128rmkz,    0 },<br>
+  { X86::VPMULLQZ128rrkz,    X86::VPMULLQZ128rmkz,    0 },<br>
+  { X86::VPMULLWZ128rrkz,    X86::VPMULLWZ128rmkz,    0 },<br>
+  { X86::VPMULUDQZ128rrkz,   X86::VPMULUDQZ128rmkz,   0 },<br>
+  { X86::VPORDZ128rrkz,     X86::VPORDZ128rmkz,     0 },<br>
+  { X86::VPORQZ128rrkz,     X86::VPORQZ128rmkz,     0 },<br>
+  { X86::VPSHUFBZ128rrkz,    X86::VPSHUFBZ128rmkz,    0 },<br>
+  { X86::VPSLLDZ128rrkz,    X86::VPSLLDZ128rmkz,    0 },<br>
+  { X86::VPSLLQZ128rrkz,    X86::VPSLLQZ128rmkz,    0 },<br>
+  { X86::VPSLLVDZ128rrkz,    X86::VPSLLVDZ128rmkz,    0 },<br>
+  { X86::VPSLLVQZ128rrkz,    X86::VPSLLVQZ128rmkz,    0 },<br>
+  { X86::VPSLLVWZ128rrkz,    X86::VPSLLVWZ128rmkz,    0 },<br>
+  { X86::VPSLLWZ128rrkz,    X86::VPSLLWZ128rmkz,    0 },<br>
+  { X86::VPSRADZ128rrkz,    X86::VPSRADZ128rmkz,    0 },<br>
+  { X86::VPSRAQZ128rrkz,    X86::VPSRAQZ128rmkz,    0 },<br>
+  { X86::VPSRAVDZ128rrkz,    X86::VPSRAVDZ128rmkz,    0 },<br>
+  { X86::VPSRAVQZ128rrkz,    X86::VPSRAVQZ128rmkz,    0 },<br>
+  { X86::VPSRAVWZ128rrkz,    X86::VPSRAVWZ128rmkz,    0 },<br>
+  { X86::VPSRAWZ128rrkz,    X86::VPSRAWZ128rmkz,    0 },<br>
+  { X86::VPSRLDZ128rrkz,    X86::VPSRLDZ128rmkz,    0 },<br>
+  { X86::VPSRLQZ128rrkz,    X86::VPSRLQZ128rmkz,    0 },<br>
+  { X86::VPSRLVDZ128rrkz,    X86::VPSRLVDZ128rmkz,    0 },<br>
+  { X86::VPSRLVQZ128rrkz,    X86::VPSRLVQZ128rmkz,    0 },<br>
+  { X86::VPSRLVWZ128rrkz,    X86::VPSRLVWZ128rmkz,    0 },<br>
+  { X86::VPSRLWZ128rrkz,    X86::VPSRLWZ128rmkz,    0 },<br>
+  { X86::VPSUBBZ128rrkz,    X86::VPSUBBZ128rmkz,    0 },<br>
+  { X86::VPSUBDZ128rrkz,    X86::VPSUBDZ128rmkz,    0 },<br>
+  { X86::VPSUBQZ128rrkz,    X86::VPSUBQZ128rmkz,    0 },<br>
+  { X86::VPSUBSBZ128rrkz,    X86::VPSUBSBZ128rmkz,    0 },<br>
+  { X86::VPSUBSWZ128rrkz,    X86::VPSUBSWZ128rmkz,    0 },<br>
+  { X86::VPSUBUSBZ128rrkz,   X86::VPSUBUSBZ128rmkz,   0 },<br>
+  { X86::VPSUBUSWZ128rrkz,   X86::VPSUBUSWZ128rmkz,   0 },<br>
+  { X86::VPSUBWZ128rrkz,    X86::VPSUBWZ128rmkz,    0 },<br>
+  { X86::VPUNPCKHBWZ128rrkz,  X86::VPUNPCKHBWZ128rmkz,  0 },<br>
+  { X86::VPUNPCKHDQZ128rrkz,  X86::VPUNPCKHDQZ128rmkz,  0 },<br>
+  { X86::VPUNPCKHQDQZ128rrkz,  X86::VPUNPCKHQDQZ128rmkz,  0 },<br>
+  { X86::VPUNPCKHWDZ128rrkz,  X86::VPUNPCKHWDZ128rmkz,  0 },<br>
+  { X86::VPUNPCKLBWZ128rrkz,  X86::VPUNPCKLBWZ128rmkz,  0 },<br>
+  { X86::VPUNPCKLDQZ128rrkz,  X86::VPUNPCKLDQZ128rmkz,  0 },<br>
+  { X86::VPUNPCKLQDQZ128rrkz,  X86::VPUNPCKLQDQZ128rmkz,  0 },<br>
+  { X86::VPUNPCKLWDZ128rrkz,  X86::VPUNPCKLWDZ128rmkz,  0 },<br>
+  { X86::VPXORDZ128rrkz,    X86::VPXORDZ128rmkz,    0 },<br>
+  { X86::VPXORQZ128rrkz,    X86::VPXORQZ128rmkz,    0 },<br>
+  { X86::VSHUFPDZ128rrikz,   X86::VSHUFPDZ128rmikz,   0 },<br>
+  { X86::VSHUFPSZ128rrikz,   X86::VSHUFPSZ128rmikz,   0 },<br>
+  { X86::VSUBPDZ128rrkz,    X86::VSUBPDZ128rmkz,    0 },<br>
+  { X86::VSUBPSZ128rrkz,    X86::VSUBPSZ128rmkz,    0 },<br>
+  { X86::VUNPCKHPDZ128rrkz,   X86::VUNPCKHPDZ128rmkz,   0 },<br>
+  { X86::VUNPCKHPSZ128rrkz,   X86::VUNPCKHPSZ128rmkz,   0 },<br>
+  { X86::VUNPCKLPDZ128rrkz,   X86::VUNPCKLPDZ128rmkz,   0 },<br>
+  { X86::VUNPCKLPSZ128rrkz,   X86::VUNPCKLPSZ128rmkz,   0 },<br>
+  { X86::VXORPDZ128rrkz,    X86::VXORPDZ128rmkz,    0 },<br>
+  { X86::VXORPSZ128rrkz,    X86::VXORPSZ128rmkz,    0 },<br>
+<br>
+Â Â // AVX-512 masked foldable instructions<br>
+  { X86::VBROADCASTSSZrk,    X86::VBROADCASTSSZmk,    TB_NO_REVERSE },<br>
+  { X86::VBROADCASTSDZrk,    X86::VBROADCASTSDZmk,    TB_NO_REVERSE },<br>
+  { X86::VPABSBZrrk,      X86::VPABSBZrmk,      0 },<br>
+  { X86::VPABSDZrrk,      X86::VPABSDZrmk,      0 },<br>
+  { X86::VPABSQZrrk,      X86::VPABSQZrmk,      0 },<br>
+  { X86::VPABSWZrrk,      X86::VPABSWZrmk,      0 },<br>
+  { X86::VPERMILPDZrik,     X86::VPERMILPDZmik,     0 },<br>
+  { X86::VPERMILPSZrik,     X86::VPERMILPSZmik,     0 },<br>
+  { X86::VPERMPDZrik,      X86::VPERMPDZmik,      0 },<br>
+  { X86::VPERMQZrik,      X86::VPERMQZmik,      0 },<br>
+  { X86::VPMOVSXBDZrrk,     X86::VPMOVSXBDZrmk,     0 },<br>
+  { X86::VPMOVSXBQZrrk,     X86::VPMOVSXBQZrmk,     TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWZrrk,     X86::VPMOVSXBWZrmk,     0 },<br>
+  { X86::VPMOVSXDQZrrk,     X86::VPMOVSXDQZrmk,     0 },<br>
+  { X86::VPMOVSXWDZrrk,     X86::VPMOVSXWDZrmk,     0 },<br>
+  { X86::VPMOVSXWQZrrk,     X86::VPMOVSXWQZrmk,     0 },<br>
+  { X86::VPMOVZXBDZrrk,     X86::VPMOVZXBDZrmk,     0 },<br>
+  { X86::VPMOVZXBQZrrk,     X86::VPMOVZXBQZrmk,     TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWZrrk,     X86::VPMOVZXBWZrmk,     0 },<br>
+  { X86::VPMOVZXDQZrrk,     X86::VPMOVZXDQZrmk,     0 },<br>
+  { X86::VPMOVZXWDZrrk,     X86::VPMOVZXWDZrmk,     0 },<br>
+  { X86::VPMOVZXWQZrrk,     X86::VPMOVZXWQZrmk,     0 },<br>
+  { X86::VPOPCNTDZrrk,     X86::VPOPCNTDZrmk,     0 },<br>
+  { X86::VPOPCNTQZrrk,     X86::VPOPCNTQZrmk,     0 },<br>
+  { X86::VPSHUFDZrik,      X86::VPSHUFDZmik,      0 },<br>
+  { X86::VPSHUFHWZrik,     X86::VPSHUFHWZmik,     0 },<br>
+  { X86::VPSHUFLWZrik,     X86::VPSHUFLWZmik,     0 },<br>
+  { X86::VPSLLDZrik,      X86::VPSLLDZmik,      0 },<br>
+  { X86::VPSLLQZrik,      X86::VPSLLQZmik,      0 },<br>
+  { X86::VPSLLWZrik,      X86::VPSLLWZmik,      0 },<br>
+  { X86::VPSRADZrik,      X86::VPSRADZmik,      0 },<br>
+  { X86::VPSRAQZrik,      X86::VPSRAQZmik,      0 },<br>
+  { X86::VPSRAWZrik,      X86::VPSRAWZmik,      0 },<br>
+  { X86::VPSRLDZrik,      X86::VPSRLDZmik,      0 },<br>
+  { X86::VPSRLQZrik,      X86::VPSRLQZmik,      0 },<br>
+  { X86::VPSRLWZrik,      X86::VPSRLWZmik,      0 },<br>
+<br>
+Â Â // AVX-512VL 256-bit masked foldable instructions<br>
+  { X86::VBROADCASTSSZ256rk,  X86::VBROADCASTSSZ256mk,  TB_NO_REVERSE },<br>
+  { X86::VBROADCASTSDZ256rk,  X86::VBROADCASTSDZ256mk,  TB_NO_REVERSE },<br>
+  { X86::VPABSBZ256rrk,     X86::VPABSBZ256rmk,     0 },<br>
+  { X86::VPABSDZ256rrk,     X86::VPABSDZ256rmk,     0 },<br>
+  { X86::VPABSQZ256rrk,     X86::VPABSQZ256rmk,     0 },<br>
+  { X86::VPABSWZ256rrk,     X86::VPABSWZ256rmk,     0 },<br>
+  { X86::VPERMILPDZ256rik,   X86::VPERMILPDZ256mik,   0 },<br>
+  { X86::VPERMILPSZ256rik,   X86::VPERMILPSZ256mik,   0 },<br>
+  { X86::VPERMPDZ256rik,    X86::VPERMPDZ256mik,    0 },<br>
+  { X86::VPERMQZ256rik,     X86::VPERMQZ256mik,     0 },<br>
+  { X86::VPMOVSXBDZ256rrk,   X86::VPMOVSXBDZ256rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBQZ256rrk,   X86::VPMOVSXBQZ256rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWZ256rrk,   X86::VPMOVSXBWZ256rmk,   0 },<br>
+  { X86::VPMOVSXDQZ256rrk,   X86::VPMOVSXDQZ256rmk,   0 },<br>
+  { X86::VPMOVSXWDZ256rrk,   X86::VPMOVSXWDZ256rmk,   0 },<br>
+  { X86::VPMOVSXWQZ256rrk,   X86::VPMOVSXWQZ256rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBDZ256rrk,   X86::VPMOVZXBDZ256rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBQZ256rrk,   X86::VPMOVZXBQZ256rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWZ256rrk,   X86::VPMOVZXBWZ256rmk,   0 },<br>
+  { X86::VPMOVZXDQZ256rrk,   X86::VPMOVZXDQZ256rmk,   0 },<br>
+  { X86::VPMOVZXWDZ256rrk,   X86::VPMOVZXWDZ256rmk,   0 },<br>
+  { X86::VPMOVZXWQZ256rrk,   X86::VPMOVZXWQZ256rmk,   TB_NO_REVERSE },<br>
+  { X86::VPSHUFDZ256rik,    X86::VPSHUFDZ256mik,    0 },<br>
+  { X86::VPSHUFHWZ256rik,    X86::VPSHUFHWZ256mik,    0 },<br>
+  { X86::VPSHUFLWZ256rik,    X86::VPSHUFLWZ256mik,    0 },<br>
+  { X86::VPSLLDZ256rik,     X86::VPSLLDZ256mik,     0 },<br>
+  { X86::VPSLLQZ256rik,     X86::VPSLLQZ256mik,     0 },<br>
+  { X86::VPSLLWZ256rik,     X86::VPSLLWZ256mik,     0 },<br>
+  { X86::VPSRADZ256rik,     X86::VPSRADZ256mik,     0 },<br>
+  { X86::VPSRAQZ256rik,     X86::VPSRAQZ256mik,     0 },<br>
+  { X86::VPSRAWZ256rik,     X86::VPSRAWZ256mik,     0 },<br>
+  { X86::VPSRLDZ256rik,     X86::VPSRLDZ256mik,     0 },<br>
+  { X86::VPSRLQZ256rik,     X86::VPSRLQZ256mik,     0 },<br>
+  { X86::VPSRLWZ256rik,     X86::VPSRLWZ256mik,     0 },<br>
+<br>
+Â Â // AVX-512VL 128-bit masked foldable instructions<br>
+  { X86::VBROADCASTSSZ128rk,  X86::VBROADCASTSSZ128mk,  TB_NO_REVERSE },<br>
+  { X86::VPABSBZ128rrk,     X86::VPABSBZ128rmk,     0 },<br>
+  { X86::VPABSDZ128rrk,     X86::VPABSDZ128rmk,     0 },<br>
+  { X86::VPABSQZ128rrk,     X86::VPABSQZ128rmk,     0 },<br>
+  { X86::VPABSWZ128rrk,     X86::VPABSWZ128rmk,     0 },<br>
+  { X86::VPERMILPDZ128rik,   X86::VPERMILPDZ128mik,   0 },<br>
+  { X86::VPERMILPSZ128rik,   X86::VPERMILPSZ128mik,   0 },<br>
+  { X86::VPMOVSXBDZ128rrk,   X86::VPMOVSXBDZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBQZ128rrk,   X86::VPMOVSXBQZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXBWZ128rrk,   X86::VPMOVSXBWZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXDQZ128rrk,   X86::VPMOVSXDQZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXWDZ128rrk,   X86::VPMOVSXWDZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVSXWQZ128rrk,   X86::VPMOVSXWQZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBDZ128rrk,   X86::VPMOVZXBDZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBQZ128rrk,   X86::VPMOVZXBQZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXBWZ128rrk,   X86::VPMOVZXBWZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXDQZ128rrk,   X86::VPMOVZXDQZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXWDZ128rrk,   X86::VPMOVZXWDZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPMOVZXWQZ128rrk,   X86::VPMOVZXWQZ128rmk,   TB_NO_REVERSE },<br>
+  { X86::VPSHUFDZ128rik,    X86::VPSHUFDZ128mik,    0 },<br>
+  { X86::VPSHUFHWZ128rik,    X86::VPSHUFHWZ128mik,    0 },<br>
+  { X86::VPSHUFLWZ128rik,    X86::VPSHUFLWZ128mik,    0 },<br>
+  { X86::VPSLLDZ128rik,     X86::VPSLLDZ128mik,     0 },<br>
+  { X86::VPSLLQZ128rik,     X86::VPSLLQZ128mik,     0 },<br>
+  { X86::VPSLLWZ128rik,     X86::VPSLLWZ128mik,     0 },<br>
+  { X86::VPSRADZ128rik,     X86::VPSRADZ128mik,     0 },<br>
+  { X86::VPSRAQZ128rik,     X86::VPSRAQZ128mik,     0 },<br>
+  { X86::VPSRAWZ128rik,     X86::VPSRAWZ128mik,     0 },<br>
+  { X86::VPSRLDZ128rik,     X86::VPSRLDZ128mik,     0 },<br>
+  { X86::VPSRLQZ128rik,     X86::VPSRLQZ128mik,     0 },<br>
+  { X86::VPSRLWZ128rik,     X86::VPSRLWZ128mik,     0 },<br>
+Â };<br>
+<br>
  for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {<br>
   AddTableEntry(<wbr>RegOp2MemOpTable3, MemOp2RegOpTable,<br>
          Entry.RegOp, Entry.MemOp,<br>
          // Index 3, folded load<br>
          Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);<br>
  }<br>
+Â auto I = X86InstrFMA3Info::rm_begin();<br>
+Â auto E = X86InstrFMA3Info::rm_end();<br>
+Â for (; I != E; ++I) {<br>
+Â Â if (!I.getGroup()->isKMasked()) {<br>
+Â Â Â // Intrinsic forms need to pass TB_NO_REVERSE.<br>
+Â Â Â if (I.getGroup()->isIntrinsic()) {<br>
+Â Â Â Â AddTableEntry(<wbr>RegOp2MemOpTable3, MemOp2RegOpTable,<br>
+Â Â Â Â Â Â Â Â Â Â Â I.getRegOpcode(), I.getMemOpcode(),<br>
+Â Â Â Â Â Â Â Â Â Â Â TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD | TB_NO_REVERSE);<br>
+Â Â Â } else {<br>
+Â Â Â Â AddTableEntry(<wbr>RegOp2MemOpTable3, MemOp2RegOpTable,<br>
+Â Â Â Â Â Â Â Â Â Â Â I.getRegOpcode(), I.getMemOpcode(),<br>
+Â Â Â Â Â Â Â Â Â Â Â TB_ALIGN_NONE | TB_INDEX_3 | TB_FOLDED_LOAD);<br>
+Â Â Â }<br>
+Â Â }<br>
+Â }<br>
+<br>
+Â static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {<br>
+Â Â // AVX-512 foldable masked instructions<br>
+  { X86::VADDPDZrrk,     X86::VADDPDZrmk,      0 },<br>
+  { X86::VADDPSZrrk,     X86::VADDPSZrmk,      0 },<br>
+  { X86::VADDSDZrr_Intk,   X86::VADDSDZrm_Intk,    TB_NO_REVERSE },<br>
+  { X86::VADDSSZrr_Intk,   X86::VADDSSZrm_Intk,    TB_NO_REVERSE },<br>
+  { X86::VALIGNDZrrik,    X86::VALIGNDZrmik,     0 },<br>
+  { X86::VALIGNQZrrik,    X86::VALIGNQZrmik,     0 },<br>
+  { X86::VANDNPDZrrk,    X86::VANDNPDZrmk,     0 },<br>
+  { X86::VANDNPSZrrk,    X86::VANDNPSZrmk,     0 },<br>
+  { X86::VANDPDZrrk,     X86::VANDPDZrmk,      0 },<br>
+  { X86::VANDPSZrrk,     X86::VANDPSZrmk,      0 },<br>
+  { X86::VDIVPDZrrk,     X86::VDIVPDZrmk,      0 },<br>
+  { X86::VDIVPSZrrk,     X86::VDIVPSZrmk,      0 },<br>
+  { X86::VDIVSDZrr_Intk,   X86::VDIVSDZrm_Intk,    TB_NO_REVERSE },<br>
+  { X86::VDIVSSZrr_Intk,   X86::VDIVSSZrm_Intk,    TB_NO_REVERSE },<br>
+  { X86::VINSERTF32x4Zrrk,  X86::VINSERTF32x4Zrmk,   0 },<br>
+  { X86::VINSERTF32x8Zrrk,  X86::VINSERTF32x8Zrmk,   0 },<br>
+  { X86::VINSERTF64x2Zrrk,  X86::VINSERTF64x2Zrmk,   0 },<br>
+  { X86::VINSERTF64x4Zrrk,  X86::VINSERTF64x4Zrmk,   0 },<br>
+  { X86::VINSERTI32x4Zrrk,  X86::VINSERTI32x4Zrmk,   0 },<br>
+  { X86::VINSERTI32x8Zrrk,  X86::VINSERTI32x8Zrmk,   0 },<br>
+  { X86::VINSERTI64x2Zrrk,  X86::VINSERTI64x2Zrmk,   0 },<br>
+  { X86::VINSERTI64x4Zrrk,  X86::VINSERTI64x4Zrmk,   0 },<br>
+  { X86::VMAXCPDZrrk,    X86::VMAXCPDZrmk,     0 },<br>
+  { X86::VMAXCPSZrrk,    X86::VMAXCPSZrmk,     0 },<br>
+  { X86::VMAXPDZrrk,     X86::VMAXPDZrmk,      0 },<br>
+  { X86::VMAXPSZrrk,     X86::VMAXPSZrmk,      0 },<br>
+  { X86::VMAXSDZrr_Intk,   X86::VMAXSDZrm_Intk,    0 },<br>
+  { X86::VMAXSSZrr_Intk,   X86::VMAXSSZrm_Intk,    0 },<br>
+  { X86::VMINCPDZrrk,    X86::VMINCPDZrmk,     0 },<br>
+  { X86::VMINCPSZrrk,    X86::VMINCPSZrmk,     0 },<br>
+  { X86::VMINPDZrrk,     X86::VMINPDZrmk,      0 },<br>
+  { X86::VMINPSZrrk,     X86::VMINPSZrmk,      0 },<br>
+  { X86::VMINSDZrr_Intk,   X86::VMINSDZrm_Intk,    0 },<br>
+  { X86::VMINSSZrr_Intk,   X86::VMINSSZrm_Intk,    0 },<br>
+  { X86::VMULPDZrrk,     X86::VMULPDZrmk,      0 },<br>
+  { X86::VMULPSZrrk,     X86::VMULPSZrmk,      0 },<br>
+  { X86::VMULSDZrr_Intk,   X86::VMULSDZrm_Intk,    TB_NO_REVERSE },<br>
+  { X86::VMULSSZrr_Intk,   X86::VMULSSZrm_Intk,    TB_NO_REVERSE },<br>
+  { X86::VORPDZrrk,     X86::VORPDZrmk,      0 },<br>
+  { X86::VORPSZrrk,     X86::VORPSZrmk,      0 },<br>
+  { X86::VPACKSSDWZrrk,   X86::VPACKSSDWZrmk,    0 },<br>
+  { X86::VPACKSSWBZrrk,   X86::VPACKSSWBZrmk,    0 },<br>
+  { X86::VPACKUSDWZrrk,   X86::VPACKUSDWZrmk,    0 },<br>
+  { X86::VPACKUSWBZrrk,   X86::VPACKUSWBZrmk,    0 },<br>
+  { X86::VPADDBZrrk,     X86::VPADDBZrmk,      0 },<br>
+  { X86::VPADDDZrrk,     X86::VPADDDZrmk,      0 },<br>
+  { X86::VPADDQZrrk,     X86::VPADDQZrmk,      0 },<br>
+  { X86::VPADDSBZrrk,    X86::VPADDSBZrmk,     0 },<br>
+  { X86::VPADDSWZrrk,    X86::VPADDSWZrmk,     0 },<br>
+  { X86::VPADDUSBZrrk,    X86::VPADDUSBZrmk,     0 },<br>
+  { X86::VPADDUSWZrrk,    X86::VPADDUSWZrmk,     0 },<br>
+  { X86::VPADDWZrrk,     X86::VPADDWZrmk,      0 },<br>
+  { X86::VPALIGNRZrrik,   X86::VPALIGNRZrmik,    0 },<br>
+  { X86::VPANDDZrrk,     X86::VPANDDZrmk,      0 },<br>
+  { X86::VPANDNDZrrk,    X86::VPANDNDZrmk,     0 },<br>
+  { X86::VPANDNQZrrk,    X86::VPANDNQZrmk,     0 },<br>
+  { X86::VPANDQZrrk,     X86::VPANDQZrmk,      0 },<br>
+  { X86::VPAVGBZrrk,     X86::VPAVGBZrmk,      0 },<br>
+  { X86::VPAVGWZrrk,     X86::VPAVGWZrmk,      0 },<br>
+  { X86::VPERMBZrrk,     X86::VPERMBZrmk,      0 },<br>
+  { X86::VPERMDZrrk,     X86::VPERMDZrmk,      0 },<br>
+  { X86::VPERMI2Brrk,    X86::VPERMI2Brmk,     0 },<br>
+  { X86::VPERMI2Drrk,    X86::VPERMI2Drmk,     0 },<br>
+  { X86::VPERMI2PSrrk,    X86::VPERMI2PSrmk,     0 },<br>
+  { X86::VPERMI2PDrrk,    X86::VPERMI2PDrmk,     0 },<br>
+  { X86::VPERMI2Qrrk,    X86::VPERMI2Qrmk,     0 },<br>
+  { X86::VPERMI2Wrrk,    X86::VPERMI2Wrmk,     0 },<br>
+  { X86::VPERMILPDZrrk,   X86::VPERMILPDZrmk,    0 },<br>
+  { X86::VPERMILPSZrrk,   X86::VPERMILPSZrmk,    0 },<br>
+  { X86::VPERMPDZrrk,    X86::VPERMPDZrmk,     0 },<br>
+  { X86::VPERMPSZrrk,    X86::VPERMPSZrmk,     0 },<br>
+  { X86::VPERMQZrrk,     X86::VPERMQZrmk,      0 },<br>
+  { X86::VPERMT2Brrk,    X86::VPERMT2Brmk,     0 },<br>
+  { X86::VPERMT2Drrk,    X86::VPERMT2Drmk,     0 },<br>
+  { X86::VPERMT2PSrrk,    X86::VPERMT2PSrmk,     0 },<br>
+  { X86::VPERMT2PDrrk,    X86::VPERMT2PDrmk,     0 },<br>
+  { X86::VPERMT2Qrrk,    X86::VPERMT2Qrmk,     0 },<br>
+  { X86::VPERMT2Wrrk,    X86::VPERMT2Wrmk,     0 },<br>
+  { X86::VPERMWZrrk,     X86::VPERMWZrmk,      0 },<br>
+  { X86::VPMADDUBSWZrrk,   X86::VPMADDUBSWZrmk,    0 },<br>
+  { X86::VPMADDWDZrrk,    X86::VPMADDWDZrmk,     0 },<br>
+  { X86::VPMAXSBZrrk,    X86::VPMAXSBZrmk,     0 },<br>
+  { X86::VPMAXSDZrrk,    X86::VPMAXSDZrmk,     0 },<br>
+  { X86::VPMAXSQZrrk,    X86::VPMAXSQZrmk,     0 },<br>
+  { X86::VPMAXSWZrrk,    X86::VPMAXSWZrmk,     0 },<br>
+  { X86::VPMAXUBZrrk,    X86::VPMAXUBZrmk,     0 },<br>
+  { X86::VPMAXUDZrrk,    X86::VPMAXUDZrmk,     0 },<br>
+  { X86::VPMAXUQZrrk,    X86::VPMAXUQZrmk,     0 },<br>
+  { X86::VPMAXUWZrrk,    X86::VPMAXUWZrmk,     0 },<br>
+  { X86::VPMINSBZrrk,    X86::VPMINSBZrmk,     0 },<br>
+  { X86::VPMINSDZrrk,    X86::VPMINSDZrmk,     0 },<br>
+  { X86::VPMINSQZrrk,    X86::VPMINSQZrmk,     0 },<br>
+  { X86::VPMINSWZrrk,    X86::VPMINSWZrmk,     0 },<br>
+  { X86::VPMINUBZrrk,    X86::VPMINUBZrmk,     0 },<br>
+  { X86::VPMINUDZrrk,    X86::VPMINUDZrmk,     0 },<br>
+  { X86::VPMINUQZrrk,    X86::VPMINUQZrmk,     0 },<br>
+  { X86::VPMINUWZrrk,    X86::VPMINUWZrmk,     0 },<br>
+  { X86::VPMULDQZrrk,    X86::VPMULDQZrmk,     0 },<br>
+  { X86::VPMULLDZrrk,    X86::VPMULLDZrmk,     0 },<br>
+  { X86::VPMULLQZrrk,    X86::VPMULLQZrmk,     0 },<br>
+  { X86::VPMULLWZrrk,    X86::VPMULLWZrmk,     0 },<br>
+  { X86::VPMULUDQZrrk,    X86::VPMULUDQZrmk,     0 },<br>
+  { X86::VPORDZrrk,     X86::VPORDZrmk,      0 },<br>
+  { X86::VPORQZrrk,     X86::VPORQZrmk,      0 },<br>
+  { X86::VPSHUFBZrrk,    X86::VPSHUFBZrmk,     0 },<br>
+  { X86::VPSLLDZrrk,     X86::VPSLLDZrmk,      0 },<br>
+  { X86::VPSLLQZrrk,     X86::VPSLLQZrmk,      0 },<br>
+  { X86::VPSLLVDZrrk,    X86::VPSLLVDZrmk,     0 },<br>
+  { X86::VPSLLVQZrrk,    X86::VPSLLVQZrmk,     0 },<br>
+  { X86::VPSLLVWZrrk,    X86::VPSLLVWZrmk,     0 },<br>
+  { X86::VPSLLWZrrk,     X86::VPSLLWZrmk,      0 },<br>
+  { X86::VPSRADZrrk,     X86::VPSRADZrmk,      0 },<br>
+  { X86::VPSRAQZrrk,     X86::VPSRAQZrmk,      0 },<br>
+  { X86::VPSRAVDZrrk,    X86::VPSRAVDZrmk,     0 },<br>
+  { X86::VPSRAVQZrrk,    X86::VPSRAVQZrmk,     0 },<br>
+  { X86::VPSRAVWZrrk,    X86::VPSRAVWZrmk,     0 },<br>
+  { X86::VPSRAWZrrk,     X86::VPSRAWZrmk,      0 },<br>
+  { X86::VPSRLDZrrk,     X86::VPSRLDZrmk,      0 },<br>
+  { X86::VPSRLQZrrk,     X86::VPSRLQZrmk,      0 },<br>
+  { X86::VPSRLVDZrrk,    X86::VPSRLVDZrmk,     0 },<br>
+  { X86::VPSRLVQZrrk,    X86::VPSRLVQZrmk,     0 },<br>
+  { X86::VPSRLVWZrrk,    X86::VPSRLVWZrmk,     0 },<br>
+  { X86::VPSRLWZrrk,     X86::VPSRLWZrmk,      0 },<br>
+  { X86::VPSUBBZrrk,     X86::VPSUBBZrmk,      0 },<br>
+  { X86::VPSUBDZrrk,     X86::VPSUBDZrmk,      0 },<br>
+  { X86::VPSUBQZrrk,     X86::VPSUBQZrmk,      0 },<br>
+  { X86::VPSUBSBZrrk,    X86::VPSUBSBZrmk,     0 },<br>
+  { X86::VPSUBSWZrrk,    X86::VPSUBSWZrmk,     0 },<br>
+  { X86::VPSUBUSBZrrk,    X86::VPSUBUSBZrmk,     0 },<br>
+  { X86::VPSUBUSWZrrk,    X86::VPSUBUSWZrmk,     0 },<br>
+  { X86::VPTERNLOGDZrrik,  X86::VPTERNLOGDZrmik,   0 },<br>
+  { X86::VPTERNLOGQZrrik,  X86::VPTERNLOGQZrmik,   0 },<br>
+  { X86::VPUNPCKHBWZrrk,   X86::VPUNPCKHBWZrmk,    0 },<br>
+  { X86::VPUNPCKHDQZrrk,   X86::VPUNPCKHDQZrmk,    0 },<br>
+  { X86::VPUNPCKHQDQZrrk,  X86::VPUNPCKHQDQZrmk,   0 },<br>
+  { X86::VPUNPCKHWDZrrk,   X86::VPUNPCKHWDZrmk,    0 },<br>
+  { X86::VPUNPCKLBWZrrk,   X86::VPUNPCKLBWZrmk,    0 },<br>
+  { X86::VPUNPCKLDQZrrk,   X86::VPUNPCKLDQZrmk,    0 },<br>
+  { X86::VPUNPCKLQDQZrrk,  X86::VPUNPCKLQDQZrmk,   0 },<br>
+  { X86::VPUNPCKLWDZrrk,   X86::VPUNPCKLWDZrmk,    0 },<br>
+  { X86::VPXORDZrrk,     X86::VPXORDZrmk,      0 },<br>
+  { X86::VPXORQZrrk,     X86::VPXORQZrmk,      0 },<br>
+  { X86::VSHUFPDZrrik,    X86::VSHUFPDZrmik,     0 },<br>
+  { X86::VSHUFPSZrrik,    X86::VSHUFPSZrmik,     0 },<br>
+  { X86::VSUBPDZrrk,     X86::VSUBPDZrmk,      0 },<br>
+  { X86::VSUBPSZrrk,     X86::VSUBPSZrmk,      0 },<br>
+  { X86::VSUBSDZrr_Intk,   X86::VSUBSDZrm_Intk,    TB_NO_REVERSE },<br>
+  { X86::VSUBSSZrr_Intk,   X86::VSUBSSZrm_Intk,    TB_NO_REVERSE },<br>
+  { X86::VUNPCKHPDZrrk,   X86::VUNPCKHPDZrmk,    0 },<br>
+  { X86::VUNPCKHPSZrrk,   X86::VUNPCKHPSZrmk,    0 },<br>
+  { X86::VUNPCKLPDZrrk,   X86::VUNPCKLPDZrmk,    0 },<br>
+  { X86::VUNPCKLPSZrrk,   X86::VUNPCKLPSZrmk,    0 },<br>
+  { X86::VXORPDZrrk,     X86::VXORPDZrmk,      0 },<br>
+  { X86::VXORPSZrrk,     X86::VXORPSZrmk,      0 },<br>
+<br>
+Â Â // AVX-512{F,VL} foldable masked instructions 256-bit<br>
+  { X86::VADDPDZ256rrk,   X86::VADDPDZ256rmk,    0 },<br>
+  { X86::VADDPSZ256rrk,   X86::VADDPSZ256rmk,    0 },<br>
+  { X86::VALIGNDZ256rrik,  X86::VALIGNDZ256rmik,   0 },<br>
+  { X86::VALIGNQZ256rrik,  X86::VALIGNQZ256rmik,   0 },<br>
+  { X86::VANDNPDZ256rrk,   X86::VANDNPDZ256rmk,    0 },<br>
+  { X86::VANDNPSZ256rrk,   X86::VANDNPSZ256rmk,    0 },<br>
+  { X86::VANDPDZ256rrk,   X86::VANDPDZ256rmk,    0 },<br>
+  { X86::VANDPSZ256rrk,   X86::VANDPSZ256rmk,    0 },<br>
+  { X86::VDIVPDZ256rrk,   X86::VDIVPDZ256rmk,    0 },<br>
+  { X86::VDIVPSZ256rrk,   X86::VDIVPSZ256rmk,    0 },<br>
+  { X86::VINSERTF32x4Z256rrk,X86::<wbr>VINSERTF32x4Z256rmk, 0 },<br>
+  { X86::VINSERTF64x2Z256rrk,X86::<wbr>VINSERTF64x2Z256rmk, 0 },<br>
+  { X86::VINSERTI32x4Z256rrk,X86::<wbr>VINSERTI32x4Z256rmk, 0 },<br>
+  { X86::VINSERTI64x2Z256rrk,X86::<wbr>VINSERTI64x2Z256rmk, 0 },<br>
+  { X86::VMAXCPDZ256rrk,   X86::VMAXCPDZ256rmk,    0 },<br>
+  { X86::VMAXCPSZ256rrk,   X86::VMAXCPSZ256rmk,    0 },<br>
+  { X86::VMAXPDZ256rrk,   X86::VMAXPDZ256rmk,    0 },<br>
+  { X86::VMAXPSZ256rrk,   X86::VMAXPSZ256rmk,    0 },<br>
+  { X86::VMINCPDZ256rrk,   X86::VMINCPDZ256rmk,    0 },<br>
+  { X86::VMINCPSZ256rrk,   X86::VMINCPSZ256rmk,    0 },<br>
+  { X86::VMINPDZ256rrk,   X86::VMINPDZ256rmk,    0 },<br>
+  { X86::VMINPSZ256rrk,   X86::VMINPSZ256rmk,    0 },<br>
+  { X86::VMULPDZ256rrk,   X86::VMULPDZ256rmk,    0 },<br>
+  { X86::VMULPSZ256rrk,   X86::VMULPSZ256rmk,    0 },<br>
+  { X86::VORPDZ256rrk,    X86::VORPDZ256rmk,     0 },<br>
+  { X86::VORPSZ256rrk,    X86::VORPSZ256rmk,     0 },<br>
+  { X86::VPACKSSDWZ256rrk,  X86::VPACKSSDWZ256rmk,   0 },<br>
+  { X86::VPACKSSWBZ256rrk,  X86::VPACKSSWBZ256rmk,   0 },<br>
+  { X86::VPACKUSDWZ256rrk,  X86::VPACKUSDWZ256rmk,   0 },<br>
+  { X86::VPACKUSWBZ256rrk,  X86::VPACKUSWBZ256rmk,   0 },<br>
+  { X86::VPADDBZ256rrk,   X86::VPADDBZ256rmk,    0 },<br>
+  { X86::VPADDDZ256rrk,   X86::VPADDDZ256rmk,    0 },<br>
+  { X86::VPADDQZ256rrk,   X86::VPADDQZ256rmk,    0 },<br>
+  { X86::VPADDSBZ256rrk,   X86::VPADDSBZ256rmk,    0 },<br>
+  { X86::VPADDSWZ256rrk,   X86::VPADDSWZ256rmk,    0 },<br>
+  { X86::VPADDUSBZ256rrk,  X86::VPADDUSBZ256rmk,   0 },<br>
+  { X86::VPADDUSWZ256rrk,  X86::VPADDUSWZ256rmk,   0 },<br>
+  { X86::VPADDWZ256rrk,   X86::VPADDWZ256rmk,    0 },<br>
+  { X86::VPALIGNRZ256rrik,  X86::VPALIGNRZ256rmik,   0 },<br>
+  { X86::VPANDDZ256rrk,   X86::VPANDDZ256rmk,    0 },<br>
+  { X86::VPANDNDZ256rrk,   X86::VPANDNDZ256rmk,    0 },<br>
+  { X86::VPANDNQZ256rrk,   X86::VPANDNQZ256rmk,    0 },<br>
+  { X86::VPANDQZ256rrk,   X86::VPANDQZ256rmk,    0 },<br>
+  { X86::VPAVGBZ256rrk,   X86::VPAVGBZ256rmk,    0 },<br>
+  { X86::VPAVGWZ256rrk,   X86::VPAVGWZ256rmk,    0 },<br>
+  { X86::VPERMBZ256rrk,   X86::VPERMBZ256rmk,    0 },<br>
+  { X86::VPERMDZ256rrk,   X86::VPERMDZ256rmk,    0 },<br>
+  { X86::VPERMI2B256rrk,   X86::VPERMI2B256rmk,    0 },<br>
+  { X86::VPERMI2D256rrk,   X86::VPERMI2D256rmk,    0 },<br>
+  { X86::VPERMI2PD256rrk,  X86::VPERMI2PD256rmk,   0 },<br>
+  { X86::VPERMI2PS256rrk,  X86::VPERMI2PS256rmk,   0 },<br>
+  { X86::VPERMI2Q256rrk,   X86::VPERMI2Q256rmk,    0 },<br>
+  { X86::VPERMI2W256rrk,   X86::VPERMI2W256rmk,    0 },<br>
+  { X86::VPERMILPDZ256rrk,  X86::VPERMILPDZ256rmk,   0 },<br>
+  { X86::VPERMILPSZ256rrk,  X86::VPERMILPSZ256rmk,   0 },<br>
+  { X86::VPERMPDZ256rrk,   X86::VPERMPDZ256rmk,    0 },<br>
+  { X86::VPERMPSZ256rrk,   X86::VPERMPSZ256rmk,    0 },<br>
+  { X86::VPERMQZ256rrk,   X86::VPERMQZ256rmk,    0 },<br>
+  { X86::VPERMT2B256rrk,   X86::VPERMT2B256rmk,    0 },<br>
+  { X86::VPERMT2D256rrk,   X86::VPERMT2D256rmk,    0 },<br>
+  { X86::VPERMT2PD256rrk,  X86::VPERMT2PD256rmk,   0 },<br>
+  { X86::VPERMT2PS256rrk,  X86::VPERMT2PS256rmk,   0 },<br>
+  { X86::VPERMT2Q256rrk,   X86::VPERMT2Q256rmk,    0 },<br>
+  { X86::VPERMT2W256rrk,   X86::VPERMT2W256rmk,    0 },<br>
+  { X86::VPERMWZ256rrk,   X86::VPERMWZ256rmk,    0 },<br>
+  { X86::VPMADDUBSWZ256rrk, X86::VPMADDUBSWZ256rmk,  0 },<br>
+  { X86::VPMADDWDZ256rrk,  X86::VPMADDWDZ256rmk,   0 },<br>
+  { X86::VPMAXSBZ256rrk,   X86::VPMAXSBZ256rmk,    0 },<br>
+  { X86::VPMAXSDZ256rrk,   X86::VPMAXSDZ256rmk,    0 },<br>
+  { X86::VPMAXSQZ256rrk,   X86::VPMAXSQZ256rmk,    0 },<br>
+  { X86::VPMAXSWZ256rrk,   X86::VPMAXSWZ256rmk,    0 },<br>
+  { X86::VPMAXUBZ256rrk,   X86::VPMAXUBZ256rmk,    0 },<br>
+  { X86::VPMAXUDZ256rrk,   X86::VPMAXUDZ256rmk,    0 },<br>
+  { X86::VPMAXUQZ256rrk,   X86::VPMAXUQZ256rmk,    0 },<br>
+  { X86::VPMAXUWZ256rrk,   X86::VPMAXUWZ256rmk,    0 },<br>
+  { X86::VPMINSBZ256rrk,   X86::VPMINSBZ256rmk,    0 },<br>
+  { X86::VPMINSDZ256rrk,   X86::VPMINSDZ256rmk,    0 },<br>
+  { X86::VPMINSQZ256rrk,   X86::VPMINSQZ256rmk,    0 },<br>
+  { X86::VPMINSWZ256rrk,   X86::VPMINSWZ256rmk,    0 },<br>
+  { X86::VPMINUBZ256rrk,   X86::VPMINUBZ256rmk,    0 },<br>
+  { X86::VPMINUDZ256rrk,   X86::VPMINUDZ256rmk,    0 },<br>
+  { X86::VPMINUQZ256rrk,   X86::VPMINUQZ256rmk,    0 },<br>
+  { X86::VPMINUWZ256rrk,   X86::VPMINUWZ256rmk,    0 },<br>
+  { X86::VPMULDQZ256rrk,   X86::VPMULDQZ256rmk,    0 },<br>
+  { X86::VPMULLDZ256rrk,   X86::VPMULLDZ256rmk,    0 },<br>
+  { X86::VPMULLQZ256rrk,   X86::VPMULLQZ256rmk,    0 },<br>
+  { X86::VPMULLWZ256rrk,   X86::VPMULLWZ256rmk,    0 },<br>
+  { X86::VPMULUDQZ256rrk,  X86::VPMULUDQZ256rmk,   0 },<br>
+  { X86::VPORDZ256rrk,    X86::VPORDZ256rmk,     0 },<br>
+  { X86::VPORQZ256rrk,    X86::VPORQZ256rmk,     0 },<br>
+  { X86::VPSHUFBZ256rrk,   X86::VPSHUFBZ256rmk,    0 },<br>
+  { X86::VPSLLDZ256rrk,   X86::VPSLLDZ256rmk,    0 },<br>
+  { X86::VPSLLQZ256rrk,   X86::VPSLLQZ256rmk,    0 },<br>
+  { X86::VPSLLVDZ256rrk,   X86::VPSLLVDZ256rmk,    0 },<br>
+  { X86::VPSLLVQZ256rrk,   X86::VPSLLVQZ256rmk,    0 },<br>
+  { X86::VPSLLVWZ256rrk,   X86::VPSLLVWZ256rmk,    0 },<br>
+  { X86::VPSLLWZ256rrk,   X86::VPSLLWZ256rmk,    0 },<br>
+  { X86::VPSRADZ256rrk,   X86::VPSRADZ256rmk,    0 },<br>
+  { X86::VPSRAQZ256rrk,   X86::VPSRAQZ256rmk,    0 },<br>
+  { X86::VPSRAVDZ256rrk,   X86::VPSRAVDZ256rmk,    0 },<br>
+  { X86::VPSRAVQZ256rrk,   X86::VPSRAVQZ256rmk,    0 },<br>
+  { X86::VPSRAVWZ256rrk,   X86::VPSRAVWZ256rmk,    0 },<br>
+  { X86::VPSRAWZ256rrk,   X86::VPSRAWZ256rmk,    0 },<br>
+  { X86::VPSRLDZ256rrk,   X86::VPSRLDZ256rmk,    0 },<br>
+  { X86::VPSRLQZ256rrk,   X86::VPSRLQZ256rmk,    0 },<br>
+  { X86::VPSRLVDZ256rrk,   X86::VPSRLVDZ256rmk,    0 },<br>
+  { X86::VPSRLVQZ256rrk,   X86::VPSRLVQZ256rmk,    0 },<br>
+  { X86::VPSRLVWZ256rrk,   X86::VPSRLVWZ256rmk,    0 },<br>
+  { X86::VPSRLWZ256rrk,   X86::VPSRLWZ256rmk,    0 },<br>
+  { X86::VPSUBBZ256rrk,   X86::VPSUBBZ256rmk,    0 },<br>
+  { X86::VPSUBDZ256rrk,   X86::VPSUBDZ256rmk,    0 },<br>
+  { X86::VPSUBQZ256rrk,   X86::VPSUBQZ256rmk,    0 },<br>
+  { X86::VPSUBSBZ256rrk,   X86::VPSUBSBZ256rmk,    0 },<br>
+  { X86::VPSUBSWZ256rrk,   X86::VPSUBSWZ256rmk,    0 },<br>
+  { X86::VPSUBUSBZ256rrk,  X86::VPSUBUSBZ256rmk,   0 },<br>
+  { X86::VPSUBUSWZ256rrk,  X86::VPSUBUSWZ256rmk,   0 },<br>
+  { X86::VPSUBWZ256rrk,   X86::VPSUBWZ256rmk,    0 },<br>
+  { X86::VPTERNLOGDZ256rrik, X86::VPTERNLOGDZ256rmik,  0 },<br>
+  { X86::VPTERNLOGQZ256rrik, X86::VPTERNLOGQZ256rmik,  0 },<br>
+  { X86::VPUNPCKHBWZ256rrk, X86::VPUNPCKHBWZ256rmk,  0 },<br>
+  { X86::VPUNPCKHDQZ256rrk, X86::VPUNPCKHDQZ256rmk,  0 },<br>
+  { X86::VPUNPCKHQDQZ256rrk, X86::VPUNPCKHQDQZ256rmk,  0 },<br>
+  { X86::VPUNPCKHWDZ256rrk, X86::VPUNPCKHWDZ256rmk,  0 },<br>
+  { X86::VPUNPCKLBWZ256rrk, X86::VPUNPCKLBWZ256rmk,  0 },<br>
+  { X86::VPUNPCKLDQZ256rrk, X86::VPUNPCKLDQZ256rmk,  0 },<br>
+  { X86::VPUNPCKLQDQZ256rrk, X86::VPUNPCKLQDQZ256rmk,  0 },<br>
+  { X86::VPUNPCKLWDZ256rrk, X86::VPUNPCKLWDZ256rmk,  0 },<br>
+  { X86::VPXORDZ256rrk,   X86::VPXORDZ256rmk,    0 },<br>
+  { X86::VPXORQZ256rrk,   X86::VPXORQZ256rmk,    0 },<br>
+  { X86::VSHUFPDZ256rrik,  X86::VSHUFPDZ256rmik,   0 },<br>
+  { X86::VSHUFPSZ256rrik,  X86::VSHUFPSZ256rmik,   0 },<br>
+  { X86::VSUBPDZ256rrk,   X86::VSUBPDZ256rmk,    0 },<br>
+  { X86::VSUBPSZ256rrk,   X86::VSUBPSZ256rmk,    0 },<br>
+  { X86::VUNPCKHPDZ256rrk,  X86::VUNPCKHPDZ256rmk,   0 },<br>
+  { X86::VUNPCKHPSZ256rrk,  X86::VUNPCKHPSZ256rmk,   0 },<br>
+  { X86::VUNPCKLPDZ256rrk,  X86::VUNPCKLPDZ256rmk,   0 },<br>
+  { X86::VUNPCKLPSZ256rrk,  X86::VUNPCKLPSZ256rmk,   0 },<br>
+  { X86::VXORPDZ256rrk,   X86::VXORPDZ256rmk,    0 },<br>
+  { X86::VXORPSZ256rrk,   X86::VXORPSZ256rmk,    0 },<br>
+<br>
+Â Â // AVX-512{F,VL} foldable instructions 128-bit<br>
+  { X86::VADDPDZ128rrk,   X86::VADDPDZ128rmk,    0 },<br>
+  { X86::VADDPSZ128rrk,   X86::VADDPSZ128rmk,    0 },<br>
+  { X86::VALIGNDZ128rrik,  X86::VALIGNDZ128rmik,   0 },<br>
+  { X86::VALIGNQZ128rrik,  X86::VALIGNQZ128rmik,   0 },<br>
+  { X86::VANDNPDZ128rrk,   X86::VANDNPDZ128rmk,    0 },<br>
+  { X86::VANDNPSZ128rrk,   X86::VANDNPSZ128rmk,    0 },<br>
+  { X86::VANDPDZ128rrk,   X86::VANDPDZ128rmk,    0 },<br>
+  { X86::VANDPSZ128rrk,   X86::VANDPSZ128rmk,    0 },<br>
+  { X86::VDIVPDZ128rrk,   X86::VDIVPDZ128rmk,    0 },<br>
+  { X86::VDIVPSZ128rrk,   X86::VDIVPSZ128rmk,    0 },<br>
+  { X86::VMAXCPDZ128rrk,   X86::VMAXCPDZ128rmk,    0 },<br>
+  { X86::VMAXCPSZ128rrk,   X86::VMAXCPSZ128rmk,    0 },<br>
+  { X86::VMAXPDZ128rrk,   X86::VMAXPDZ128rmk,    0 },<br>
+  { X86::VMAXPSZ128rrk,   X86::VMAXPSZ128rmk,    0 },<br>
+  { X86::VMINCPDZ128rrk,   X86::VMINCPDZ128rmk,    0 },<br>
+  { X86::VMINCPSZ128rrk,   X86::VMINCPSZ128rmk,    0 },<br>
+  { X86::VMINPDZ128rrk,   X86::VMINPDZ128rmk,    0 },<br>
+  { X86::VMINPSZ128rrk,   X86::VMINPSZ128rmk,    0 },<br>
+  { X86::VMULPDZ128rrk,   X86::VMULPDZ128rmk,    0 },<br>
+  { X86::VMULPSZ128rrk,   X86::VMULPSZ128rmk,    0 },<br>
+  { X86::VORPDZ128rrk,    X86::VORPDZ128rmk,     0 },<br>
+  { X86::VORPSZ128rrk,    X86::VORPSZ128rmk,     0 },<br>
+  { X86::VPACKSSDWZ128rrk,  X86::VPACKSSDWZ128rmk,   0 },<br>
+  { X86::VPACKSSWBZ128rrk,  X86::VPACKSSWBZ128rmk,   0 },<br>
+  { X86::VPACKUSDWZ128rrk,  X86::VPACKUSDWZ128rmk,   0 },<br>
+  { X86::VPACKUSWBZ128rrk,  X86::VPACKUSWBZ128rmk,   0 },<br>
+  { X86::VPADDBZ128rrk,   X86::VPADDBZ128rmk,    0 },<br>
+  { X86::VPADDDZ128rrk,   X86::VPADDDZ128rmk,    0 },<br>
+  { X86::VPADDQZ128rrk,   X86::VPADDQZ128rmk,    0 },<br>
+  { X86::VPADDSBZ128rrk,   X86::VPADDSBZ128rmk,    0 },<br>
+  { X86::VPADDSWZ128rrk,   X86::VPADDSWZ128rmk,    0 },<br>
+  { X86::VPADDUSBZ128rrk,  X86::VPADDUSBZ128rmk,   0 },<br>
+  { X86::VPADDUSWZ128rrk,  X86::VPADDUSWZ128rmk,   0 },<br>
+  { X86::VPADDWZ128rrk,   X86::VPADDWZ128rmk,    0 },<br>
+  { X86::VPALIGNRZ128rrik,  X86::VPALIGNRZ128rmik,   0 },<br>
+  { X86::VPANDDZ128rrk,   X86::VPANDDZ128rmk,    0 },<br>
+  { X86::VPANDNDZ128rrk,   X86::VPANDNDZ128rmk,    0 },<br>
+  { X86::VPANDNQZ128rrk,   X86::VPANDNQZ128rmk,    0 },<br>
+  { X86::VPANDQZ128rrk,   X86::VPANDQZ128rmk,    0 },<br>
+  { X86::VPAVGBZ128rrk,   X86::VPAVGBZ128rmk,    0 },<br>
+  { X86::VPAVGWZ128rrk,   X86::VPAVGWZ128rmk,    0 },<br>
+  { X86::VPERMBZ128rrk,   X86::VPERMBZ128rmk,    0 },<br>
+  { X86::VPERMI2B128rrk,   X86::VPERMI2B128rmk,    0 },<br>
+  { X86::VPERMI2D128rrk,   X86::VPERMI2D128rmk,    0 },<br>
+  { X86::VPERMI2PD128rrk,  X86::VPERMI2PD128rmk,   0 },<br>
+  { X86::VPERMI2PS128rrk,  X86::VPERMI2PS128rmk,   0 },<br>
+  { X86::VPERMI2Q128rrk,   X86::VPERMI2Q128rmk,    0 },<br>
+  { X86::VPERMI2W128rrk,   X86::VPERMI2W128rmk,    0 },<br>
+  { X86::VPERMILPDZ128rrk,  X86::VPERMILPDZ128rmk,   0 },<br>
+  { X86::VPERMILPSZ128rrk,  X86::VPERMILPSZ128rmk,   0 },<br>
+  { X86::VPERMT2B128rrk,   X86::VPERMT2B128rmk,    0 },<br>
+  { X86::VPERMT2D128rrk,   X86::VPERMT2D128rmk,    0 },<br>
+  { X86::VPERMT2PD128rrk,  X86::VPERMT2PD128rmk,   0 },<br>
+  { X86::VPERMT2PS128rrk,  X86::VPERMT2PS128rmk,   0 },<br>
+  { X86::VPERMT2Q128rrk,   X86::VPERMT2Q128rmk,    0 },<br>
+  { X86::VPERMT2W128rrk,   X86::VPERMT2W128rmk,    0 },<br>
+  { X86::VPERMWZ128rrk,   X86::VPERMWZ128rmk,    0 },<br>
+  { X86::VPMADDUBSWZ128rrk, X86::VPMADDUBSWZ128rmk,  0 },<br>
+  { X86::VPMADDWDZ128rrk,  X86::VPMADDWDZ128rmk,   0 },<br>
+  { X86::VPMAXSBZ128rrk,   X86::VPMAXSBZ128rmk,    0 },<br>
+  { X86::VPMAXSDZ128rrk,   X86::VPMAXSDZ128rmk,    0 },<br>
+  { X86::VPMAXSQZ128rrk,   X86::VPMAXSQZ128rmk,    0 },<br>
+  { X86::VPMAXSWZ128rrk,   X86::VPMAXSWZ128rmk,    0 },<br>
+  { X86::VPMAXUBZ128rrk,   X86::VPMAXUBZ128rmk,    0 },<br>
+  { X86::VPMAXUDZ128rrk,   X86::VPMAXUDZ128rmk,    0 },<br>
+  { X86::VPMAXUQZ128rrk,   X86::VPMAXUQZ128rmk,    0 },<br>
+  { X86::VPMAXUWZ128rrk,   X86::VPMAXUWZ128rmk,    0 },<br>
+  { X86::VPMINSBZ128rrk,   X86::VPMINSBZ128rmk,    0 },<br>
+  { X86::VPMINSDZ128rrk,   X86::VPMINSDZ128rmk,    0 },<br>
+  { X86::VPMINSQZ128rrk,   X86::VPMINSQZ128rmk,    0 },<br>
+  { X86::VPMINSWZ128rrk,   X86::VPMINSWZ128rmk,    0 },<br>
+  { X86::VPMINUBZ128rrk,   X86::VPMINUBZ128rmk,    0 },<br>
+  { X86::VPMINUDZ128rrk,   X86::VPMINUDZ128rmk,    0 },<br>
+  { X86::VPMINUQZ128rrk,   X86::VPMINUQZ128rmk,    0 },<br>
+  { X86::VPMINUWZ128rrk,   X86::VPMINUWZ128rmk,    0 },<br>
+  { X86::VPMULDQZ128rrk,   X86::VPMULDQZ128rmk,    0 },<br>
+  { X86::VPMULLDZ128rrk,   X86::VPMULLDZ128rmk,    0 },<br>
+  { X86::VPMULLQZ128rrk,   X86::VPMULLQZ128rmk,    0 },<br>
+  { X86::VPMULLWZ128rrk,   X86::VPMULLWZ128rmk,    0 },<br>
+  { X86::VPMULUDQZ128rrk,  X86::VPMULUDQZ128rmk,   0 },<br>
+  { X86::VPORDZ128rrk,    X86::VPORDZ128rmk,     0 },<br>
+  { X86::VPORQZ128rrk,    X86::VPORQZ128rmk,     0 },<br>
+  { X86::VPSHUFBZ128rrk,   X86::VPSHUFBZ128rmk,    0 },<br>
+  { X86::VPSLLDZ128rrk,   X86::VPSLLDZ128rmk,    0 },<br>
+  { X86::VPSLLQZ128rrk,   X86::VPSLLQZ128rmk,    0 },<br>
+  { X86::VPSLLVDZ128rrk,   X86::VPSLLVDZ128rmk,    0 },<br>
+  { X86::VPSLLVQZ128rrk,   X86::VPSLLVQZ128rmk,    0 },<br>
+  { X86::VPSLLVWZ128rrk,   X86::VPSLLVWZ128rmk,    0 },<br>
+  { X86::VPSLLWZ128rrk,   X86::VPSLLWZ128rmk,    0 },<br>
+  { X86::VPSRADZ128rrk,   X86::VPSRADZ128rmk,    0 },<br>
+  { X86::VPSRAQZ128rrk,   X86::VPSRAQZ128rmk,    0 },<br>
+  { X86::VPSRAVDZ128rrk,   X86::VPSRAVDZ128rmk,    0 },<br>
+  { X86::VPSRAVQZ128rrk,   X86::VPSRAVQZ128rmk,    0 },<br>
+  { X86::VPSRAVWZ128rrk,   X86::VPSRAVWZ128rmk,    0 },<br>
+  { X86::VPSRAWZ128rrk,   X86::VPSRAWZ128rmk,    0 },<br>
+  { X86::VPSRLDZ128rrk,   X86::VPSRLDZ128rmk,    0 },<br>
+  { X86::VPSRLQZ128rrk,   X86::VPSRLQZ128rmk,    0 },<br>
+  { X86::VPSRLVDZ128rrk,   X86::VPSRLVDZ128rmk,    0 },<br>
+  { X86::VPSRLVQZ128rrk,   X86::VPSRLVQZ128rmk,    0 },<br>
+  { X86::VPSRLVWZ128rrk,   X86::VPSRLVWZ128rmk,    0 },<br>
+  { X86::VPSRLWZ128rrk,   X86::VPSRLWZ128rmk,    0 },<br>
+  { X86::VPSUBBZ128rrk,   X86::VPSUBBZ128rmk,    0 },<br>
+  { X86::VPSUBDZ128rrk,   X86::VPSUBDZ128rmk,    0 },<br>
+  { X86::VPSUBQZ128rrk,   X86::VPSUBQZ128rmk,    0 },<br>
+  { X86::VPSUBSBZ128rrk,   X86::VPSUBSBZ128rmk,    0 },<br>
+  { X86::VPSUBSWZ128rrk,   X86::VPSUBSWZ128rmk,    0 },<br>
+  { X86::VPSUBUSBZ128rrk,  X86::VPSUBUSBZ128rmk,   0 },<br>
+  { X86::VPSUBUSWZ128rrk,  X86::VPSUBUSWZ128rmk,   0 },<br>
+  { X86::VPSUBWZ128rrk,   X86::VPSUBWZ128rmk,    0 },<br>
+  { X86::VPTERNLOGDZ128rrik, X86::VPTERNLOGDZ128rmik,  0 },<br>
+  { X86::VPTERNLOGQZ128rrik, X86::VPTERNLOGQZ128rmik,  0 },<br>
+  { X86::VPUNPCKHBWZ128rrk, X86::VPUNPCKHBWZ128rmk,  0 },<br>
+  { X86::VPUNPCKHDQZ128rrk, X86::VPUNPCKHDQZ128rmk,  0 },<br>
+  { X86::VPUNPCKHQDQZ128rrk, X86::VPUNPCKHQDQZ128rmk,  0 },<br>
+  { X86::VPUNPCKHWDZ128rrk, X86::VPUNPCKHWDZ128rmk,  0 },<br>
+  { X86::VPUNPCKLBWZ128rrk, X86::VPUNPCKLBWZ128rmk,  0 },<br>
+  { X86::VPUNPCKLDQZ128rrk, X86::VPUNPCKLDQZ128rmk,  0 },<br>
+  { X86::VPUNPCKLQDQZ128rrk, X86::VPUNPCKLQDQZ128rmk,  0 },<br>
+  { X86::VPUNPCKLWDZ128rrk, X86::VPUNPCKLWDZ128rmk,  0 },<br>
+  { X86::VPXORDZ128rrk,   X86::VPXORDZ128rmk,    0 },<br>
+  { X86::VPXORQZ128rrk,   X86::VPXORQZ128rmk,    0 },<br>
+  { X86::VSHUFPDZ128rrik,  X86::VSHUFPDZ128rmik,   0 },<br>
+  { X86::VSHUFPSZ128rrik,  X86::VSHUFPSZ128rmik,   0 },<br>
+  { X86::VSUBPDZ128rrk,   X86::VSUBPDZ128rmk,    0 },<br>
+  { X86::VSUBPSZ128rrk,   X86::VSUBPSZ128rmk,    0 },<br>
+  { X86::VUNPCKHPDZ128rrk,  X86::VUNPCKHPDZ128rmk,   0 },<br>
+  { X86::VUNPCKHPSZ128rrk,  X86::VUNPCKHPSZ128rmk,   0 },<br>
+  { X86::VUNPCKLPDZ128rrk,  X86::VUNPCKLPDZ128rmk,   0 },<br>
+  { X86::VUNPCKLPSZ128rrk,  X86::VUNPCKLPSZ128rmk,   0 },<br>
+  { X86::VXORPDZ128rrk,   X86::VXORPDZ128rmk,    0 },<br>
+  { X86::VXORPSZ128rrk,   X86::VXORPSZ128rmk,    0 },<br>
+<br>
+Â Â // 512-bit three source instructions with zero masking.<br>
+  { X86::VPERMI2Brrkz,    X86::VPERMI2Brmkz,     0 },<br>
+  { X86::VPERMI2Drrkz,    X86::VPERMI2Drmkz,     0 },<br>
+  { X86::VPERMI2PSrrkz,   X86::VPERMI2PSrmkz,    0 },<br>
+  { X86::VPERMI2PDrrkz,   X86::VPERMI2PDrmkz,    0 },<br>
+  { X86::VPERMI2Qrrkz,    X86::VPERMI2Qrmkz,     0 },<br>
+  { X86::VPERMI2Wrrkz,    X86::VPERMI2Wrmkz,     0 },<br>
+  { X86::VPERMT2Brrkz,    X86::VPERMT2Brmkz,     0 },<br>
+  { X86::VPERMT2Drrkz,    X86::VPERMT2Drmkz,     0 },<br>
+  { X86::VPERMT2PSrrkz,   X86::VPERMT2PSrmkz,    0 },<br>
+  { X86::VPERMT2PDrrkz,   X86::VPERMT2PDrmkz,    0 },<br>
+  { X86::VPERMT2Qrrkz,    X86::VPERMT2Qrmkz,     0 },<br>
+  { X86::VPERMT2Wrrkz,    X86::VPERMT2Wrmkz,     0 },<br>
+  { X86::VPTERNLOGDZrrikz,  X86::VPTERNLOGDZrmikz,   0 },<br>
+  { X86::VPTERNLOGQZrrikz,  X86::VPTERNLOGQZrmikz,   0 },<br>
+<br>
+Â Â // 256-bit three source instructions with zero masking.<br>
+  { X86::VPERMI2B256rrkz,  X86::VPERMI2B256rmkz,   0 },<br>
+  { X86::VPERMI2D256rrkz,  X86::VPERMI2D256rmkz,   0 },<br>
+  { X86::VPERMI2PD256rrkz,  X86::VPERMI2PD256rmkz,   0 },<br>
+  { X86::VPERMI2PS256rrkz,  X86::VPERMI2PS256rmkz,   0 },<br>
+  { X86::VPERMI2Q256rrkz,  X86::VPERMI2Q256rmkz,   0 },<br>
+  { X86::VPERMI2W256rrkz,  X86::VPERMI2W256rmkz,   0 },<br>
+  { X86::VPERMT2B256rrkz,  X86::VPERMT2B256rmkz,   0 },<br>
+  { X86::VPERMT2D256rrkz,  X86::VPERMT2D256rmkz,   0 },<br>
+  { X86::VPERMT2PD256rrkz,  X86::VPERMT2PD256rmkz,   0 },<br>
+  { X86::VPERMT2PS256rrkz,  X86::VPERMT2PS256rmkz,   0 },<br>
+  { X86::VPERMT2Q256rrkz,  X86::VPERMT2Q256rmkz,   0 },<br>
+  { X86::VPERMT2W256rrkz,  X86::VPERMT2W256rmkz,   0 },<br>
+  { X86::VPTERNLOGDZ256rrikz,X86::<wbr>VPTERNLOGDZ256rmikz, 0 },<br>
+  { X86::VPTERNLOGQZ256rrikz,X86::<wbr>VPTERNLOGQZ256rmikz, 0 },<br>
+<br>
+Â Â // 128-bit three source instructions with zero masking.<br>
+  { X86::VPERMI2B128rrkz,  X86::VPERMI2B128rmkz,   0 },<br>
+  { X86::VPERMI2D128rrkz,  X86::VPERMI2D128rmkz,   0 },<br>
+  { X86::VPERMI2PD128rrkz,  X86::VPERMI2PD128rmkz,   0 },<br>
+  { X86::VPERMI2PS128rrkz,  X86::VPERMI2PS128rmkz,   0 },<br>
+  { X86::VPERMI2Q128rrkz,  X86::VPERMI2Q128rmkz,   0 },<br>
+  { X86::VPERMI2W128rrkz,  X86::VPERMI2W128rmkz,   0 },<br>
+  { X86::VPERMT2B128rrkz,  X86::VPERMT2B128rmkz,   0 },<br>
+  { X86::VPERMT2D128rrkz,  X86::VPERMT2D128rmkz,   0 },<br>
+  { X86::VPERMT2PD128rrkz,  X86::VPERMT2PD128rmkz,   0 },<br>
+  { X86::VPERMT2PS128rrkz,  X86::VPERMT2PS128rmkz,   0 },<br>
+  { X86::VPERMT2Q128rrkz,  X86::VPERMT2Q128rmkz,   0 },<br>
+  { X86::VPERMT2W128rrkz,  X86::VPERMT2W128rmkz,   0 },<br>
+  { X86::VPTERNLOGDZ128rrikz,X86::<wbr>VPTERNLOGDZ128rmikz, 0 },<br>
+  { X86::VPTERNLOGQZ128rrikz,X86::<wbr>VPTERNLOGQZ128rmikz, 0 },<br>
+Â };<br>
<br>
  for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {<br>
   AddTableEntry(<wbr>RegOp2MemOpTable4, MemOp2RegOpTable,<br>
@@ -163,6 +3545,20 @@ X86InstrInfo::X86InstrInfo(<wbr>X86Subtarget<br>
          // Index 4, folded load<br>
          Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);<br>
  }<br>
+Â for (I = X86InstrFMA3Info::rm_begin(); I != E; ++I) {<br>
+Â Â if (I.getGroup()->isKMasked()) {<br>
+Â Â Â // Intrinsics need to pass TB_NO_REVERSE.<br>
+Â Â Â if (I.getGroup()->isIntrinsic()) {<br>
+Â Â Â Â AddTableEntry(<wbr>RegOp2MemOpTable4, MemOp2RegOpTable,<br>
+Â Â Â Â Â Â Â Â Â Â Â I.getRegOpcode(), I.getMemOpcode(),<br>
+Â Â Â Â Â Â Â Â Â Â Â TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD | TB_NO_REVERSE);<br>
+Â Â Â } else {<br>
+Â Â Â Â AddTableEntry(<wbr>RegOp2MemOpTable4, MemOp2RegOpTable,<br>
+Â Â Â Â Â Â Â Â Â Â Â I.getRegOpcode(), I.getMemOpcode(),<br>
+Â Â Â Â Â Â Â Â Â Â Â TB_ALIGN_NONE | TB_INDEX_4 | TB_FOLDED_LOAD);<br>
+Â Â Â }<br>
+Â Â }<br>
+Â }<br>
 }<br>
<br>
 void<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>sse42-intrinsics-fast-isel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll?rev=304121&r1=304120&r2=304121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/sse42-intrinsics-<wbr>fast-isel.ll?rev=304121&r1=<wbr>304120&r2=304121&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>sse42-intrinsics-fast-isel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>sse42-intrinsics-fast-isel.ll Sun May 28 20:48:53 2017<br>
@@ -354,8 +354,9 @@ declare i32 @llvm.x86.sse42.pcmpistriz12<br>
 define i32 @test_mm_crc32_u8(i32 %a0, i8 %a1) {<br>
 ; X32-LABEL: test_mm_crc32_u8:<br>
 ; X32:    # BB#0:<br>
+; X32-NEXT:Â Â movb {{[0-9]+}}(%esp), %cl<br>
 ; X32-NEXT:  movl {{[0-9]+}}(%esp), %eax<br>
-; X32-NEXT:Â Â crc32b {{[0-9]+}}(%esp), %eax<br>
+; X32-NEXT:Â Â crc32b %cl, %eax<br>
 ; X32-NEXT:  retl<br>
 ;<br>
 ; X64-LABEL: test_mm_crc32_u8:<br>
@@ -371,8 +372,9 @@ declare i32 @llvm.x86.sse42.crc32.32.8(i<br>
 define i32 @test_mm_crc32_u16(i32 %a0, i16 %a1) {<br>
 ; X32-LABEL: test_mm_crc32_u16:<br>
 ; X32:    # BB#0:<br>
+; X32-NEXT:Â Â movzwl {{[0-9]+}}(%esp), %ecx<br>
 ; X32-NEXT:  movl {{[0-9]+}}(%esp), %eax<br>
-; X32-NEXT:Â Â crc32w {{[0-9]+}}(%esp), %eax<br>
+; X32-NEXT:Â Â crc32w %cx, %eax<br>
 ; X32-NEXT:  retl<br>
 ;<br>
 ; X64-LABEL: test_mm_crc32_u16:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>stack-folding-fp-avx1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll?rev=304121&r1=304120&r2=304121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/stack-folding-fp-<wbr>avx1.ll?rev=304121&r1=304120&<wbr>r2=304121&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>stack-folding-fp-avx1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>stack-folding-fp-avx1.ll Sun May 28 20:48:53 2017<br>
@@ -1651,9 +1651,26 @@ define <8 x float> @stack_fold_sqrtps_ym<br>
 }<br>
 declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone<br>
<br>
-; TODO stack_fold_sqrtsd<br>
+define double @stack_fold_sqrtsd(double %a0) {<br>
+Â ;CHECK-LABEL: stack_fold_sqrtsd<br>
+Â ;CHECK:Â Â Â Â vsqrtsd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 8-byte Folded Reload<br>
+Â %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{<wbr>xmm4},~{xmm5},~{xmm6},~{xmm7},<wbr>~{xmm8},~{xmm9},~{xmm10},~{<wbr>xmm11},~{xmm12},~{xmm13},~{<wbr>xmm14},~{xmm15},~{flags}"()<br>
+Â %2 = call double @llvm.sqrt.f64(double %a0)<br>
+Â ret double %2<br>
+}<br>
+declare double @llvm.sqrt.f64(double) nounwind readnone<br>
+<br>
 ; TODO stack_fold_sqrtsd_int<br>
-; TODO stack_fold_sqrtss<br>
+<br>
+define float @stack_fold_sqrtss(float %a0) {<br>
+Â ;CHECK-LABEL: stack_fold_sqrtss<br>
+Â ;CHECK:Â Â Â Â vsqrtss {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 4-byte Folded Reload<br>
+Â %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{<wbr>xmm4},~{xmm5},~{xmm6},~{xmm7},<wbr>~{xmm8},~{xmm9},~{xmm10},~{<wbr>xmm11},~{xmm12},~{xmm13},~{<wbr>xmm14},~{xmm15},~{flags}"()<br>
+Â %2 = call float @llvm.sqrt.f32(float %a0)<br>
+Â ret float %2<br>
+}<br>
+declare float @llvm.sqrt.f32(float) nounwind readnone<br>
+<br>
 ; TODO stack_fold_sqrtss_int<br>
<br>
 define <2 x double> @stack_fold_subpd(<2 x double> %a0, <2 x double> %a1) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>vector-sqrt.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-sqrt.ll?rev=304121&r1=304120&r2=304121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/vector-sqrt.ll?<wbr>rev=304121&r1=304120&r2=<wbr>304121&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>vector-sqrt.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>vector-sqrt.ll Sun May 28 20:48:53 2017<br>
@@ -5,10 +5,8 @@<br>
 define <2 x double> @sqrtd2(double* nocapture readonly %v) local_unnamed_addr #0 {<br>
 ; CHECK-LABEL: sqrtd2:<br>
 ; CHECK:    # BB#0: # %entry<br>
-; CHECK-NEXT:Â Â vmovsd {{.*#+}} xmm0 = mem[0],zero<br>
-; CHECK-NEXT:Â Â vmovsd {{.*#+}} xmm1 = mem[0],zero<br>
-; CHECK-NEXT:Â Â vsqrtsd %xmm0, %xmm0, %xmm0<br>
-; CHECK-NEXT:Â Â vsqrtsd %xmm1, %xmm1, %xmm1<br>
+; CHECK-NEXT:Â Â vsqrtsd (%rdi), %xmm0, %xmm0<br>
+; CHECK-NEXT:Â Â vsqrtsd 8(%rdi), %xmm1, %xmm1<br>
 ; CHECK-NEXT:  vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
 ; CHECK-NEXT:  retq<br>
 entry:<br>
@@ -29,14 +27,10 @@ declare double @sqrt(double) local_unnam<br>
 define <4 x float> @sqrtf4(float* nocapture readonly %v) local_unnamed_addr #0 {<br>
 ; CHECK-LABEL: sqrtf4:<br>
 ; CHECK:    # BB#0: # %entry<br>
-; CHECK-NEXT:Â Â vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
-; CHECK-NEXT:Â Â vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
-; CHECK-NEXT:Â Â vsqrtss %xmm0, %xmm0, %xmm0<br>
-; CHECK-NEXT:Â Â vsqrtss %xmm1, %xmm1, %xmm1<br>
-; CHECK-NEXT:Â Â vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; CHECK-NEXT:Â Â vsqrtss %xmm2, %xmm2, %xmm2<br>
-; CHECK-NEXT:Â Â vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero<br>
-; CHECK-NEXT:Â Â vsqrtss %xmm3, %xmm3, %xmm3<br>
+; CHECK-NEXT:Â Â vsqrtss (%rdi), %xmm0, %xmm0<br>
+; CHECK-NEXT:Â Â vsqrtss 4(%rdi), %xmm1, %xmm1<br>
+; CHECK-NEXT:Â Â vsqrtss 8(%rdi), %xmm2, %xmm2<br>
+; CHECK-NEXT:Â Â vsqrtss 12(%rdi), %xmm3, %xmm3<br>
 ; CHECK-NEXT:  vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]<br>
 ; CHECK-NEXT:  vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]<br>
 ; CHECK-NEXT:  vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]<br>
<br>
Modified: llvm/trunk/utils/TableGen/<wbr>CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=304121&r1=304120&r2=304121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/CMakeLists.txt?rev=<wbr>304121&r1=304120&r2=304121&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>CMakeLists.txt (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>CMakeLists.txt Sun May 28 20:48:53 2017<br>
@@ -35,7 +35,6 @@ add_tablegen(llvm-tblgen LLVM<br>
  TableGen.cpp<br>
  Types.cpp<br>
  X86DisassemblerTables.cpp<br>
-Â X86FoldTablesEmitter.cpp<br>
  X86EVEX2VEXTablesEmitter.cpp<br>
  X86ModRMFilters.cpp<br>
  X86RecognizableInstr.cpp<br>
<br>
Modified: llvm/trunk/utils/TableGen/<wbr>TableGen.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=304121&r1=304120&r2=304121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/TableGen.cpp?rev=<wbr>304121&r1=304120&r2=304121&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>TableGen.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>TableGen.cpp Sun May 28 20:48:53 2017<br>
@@ -46,7 +46,6 @@ enum ActionType {<br>
  GenAttributes,<br>
  GenSearchableTables,<br>
  GenGlobalISel,<br>
-Â GenX86FoldTables,<br>
  GenX86EVEX2VEXTables,<br>
  GenRegisterBank,<br>
 };<br>
@@ -98,8 +97,6 @@ namespace {<br>
                "Generate generic binary-searchable table"),<br>
           clEnumValN(GenGlobalISel, "gen-global-isel",<br>
                "Generate GlobalISel selector"),<br>
-Â Â Â Â Â Â Â Â Â Â clEnumValN(GenX86FoldTables, "gen-x86-fold-tables",<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "Generate X86 fold tables"),<br>
           clEnumValN(<wbr>GenX86EVEX2VEXTables, "gen-x86-EVEX2VEX-tables",<br>
                "Generate X86 EVEX to VEX compress tables"),<br>
           clEnumValN(GenRegisterBank, "gen-register-bank",<br>
@@ -193,9 +190,6 @@ bool LLVMTableGenMain(raw_ostream &OS, R<br>
  case GenGlobalISel:<br>
   EmitGlobalISel(Records, OS);<br>
   break;<br>
-Â case GenX86FoldTables:<br>
-Â Â EmitX86FoldTables(Records, OS);<br>
-Â Â break;<br>
  case GenRegisterBank:<br>
   EmitRegisterBank(Records, OS);<br>
   break;<br>
<br>
Modified: llvm/trunk/utils/TableGen/<wbr>TableGenBackends.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGenBackends.h?rev=304121&r1=304120&r2=304121&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/TableGenBackends.h?<wbr>rev=304121&r1=304120&r2=<wbr>304121&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>TableGenBackends.h (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>TableGenBackends.h Sun May 28 20:48:53 2017<br>
@@ -81,7 +81,6 @@ void EmitCTags(RecordKeeper &RK, raw_ost<br>
 void EmitAttributes(RecordKeeper &RK, raw_ostream &OS);<br>
 void EmitSearchableTables(<wbr>RecordKeeper &RK, raw_ostream &OS);<br>
 void EmitGlobalISel(RecordKeeper &RK, raw_ostream &OS);<br>
-void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &OS);<br>
 void EmitX86EVEX2VEXTables(<wbr>RecordKeeper &RK, raw_ostream &OS);<br>
 void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);<br>
<br>
<br>
Removed: llvm/trunk/utils/TableGen/<wbr>X86FoldTablesEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp?rev=304120&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/X86FoldTablesEmitter.<wbr>cpp?rev=304120&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>X86FoldTablesEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>X86FoldTablesEmitter.cpp (removed)<br>
@@ -1,720 +0,0 @@<br>
-//===- utils/TableGen/<wbr>X86FoldTablesEmitter.cpp - X86 backend-*- C++ -*-===//<br>
-//<br>
-//Â Â Â Â Â Â Â Â Â Â Â The LLVM Compiler Infrastructure<br>
-//<br>
-// This file is distributed under the University of Illinois Open Source<br>
-// License. See LICENSE.TXT for details.<br>
-//<br>
-//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
-//<br>
-// This tablegen backend is responsible for emitting the memory fold tables of<br>
-// the X86 backend instructions.<br>
-//<br>
-//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
-<br>
-#include "CodeGenDAGPatterns.h"<br>
-#include "CodeGenTarget.h"<br>
-#include "X86RecognizableInstr.h"<br>
-#include "llvm/TableGen/Error.h"<br>
-#include "llvm/TableGen/<wbr>TableGenBackend.h"<br>
-<br>
-using namespace llvm;<br>
-<br>
-namespace {<br>
-<br>
-// 3 possible strategies for the unfolding flag (TB_NO_REVERSE) of the<br>
-// manual added entries.<br>
-enum UnfoldStrategy {<br>
- UNFOLD,   // Allow unfolding<br>
- NO_UNFOLD, // Prevent unfolding<br>
-Â NO_STRATEGY // Make decision according to operands' sizes<br>
-};<br>
-<br>
-// Represents an entry in the manual mapped instructions set.<br>
-struct ManualMapEntry {<br>
-Â const char *RegInstStr;<br>
-Â const char *MemInstStr;<br>
-Â UnfoldStrategy Strategy;<br>
-<br>
-Â ManualMapEntry(const char *RegInstStr, const char *MemInstStr,<br>
-Â Â Â Â Â Â Â Â Â UnfoldStrategy Strategy = NO_STRATEGY)<br>
-Â Â Â : RegInstStr(RegInstStr), MemInstStr(MemInstStr), Strategy(Strategy) {}<br>
-};<br>
-<br>
-class IsMatch;<br>
-<br>
-// List of instructions requiring explicitly aligned memory.<br>
-const char *const ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS",<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "MOVNTPD", "MOVNTDQ", "MOVNTDQA"};<br>
-<br>
-// List of instructions NOT requiring explicit memory alignment.<br>
-const char *const ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD"};<br>
-<br>
-// For manually mapping instructions that do not match by their encoding.<br>
-const ManualMapEntry ManualMapSet[] = {<br>
-  { "ADD16ri_DB",    "ADD16mi",     NO_UNFOLD },<br>
-  { "ADD16ri8_DB",   "ADD16mi8",    NO_UNFOLD },<br>
-  { "ADD16rr_DB",    "ADD16mr",     NO_UNFOLD },<br>
-  { "ADD32ri_DB",    "ADD32mi",     NO_UNFOLD },<br>
-  { "ADD32ri8_DB",   "ADD32mi8",    NO_UNFOLD },<br>
-  { "ADD32rr_DB",    "ADD32mr",     NO_UNFOLD },<br>
-  { "ADD64ri32_DB",   "ADD64mi32",    NO_UNFOLD },<br>
-  { "ADD64ri8_DB",   "ADD64mi8",    NO_UNFOLD },<br>
-  { "ADD64rr_DB",    "ADD64mr",     NO_UNFOLD },<br>
-  { "ADD16rr_DB",    "ADD16rm",     NO_UNFOLD },<br>
-  { "ADD32rr_DB",    "ADD32rm",     NO_UNFOLD },<br>
-  { "ADD64rr_DB",    "ADD64rm",     NO_UNFOLD },<br>
-  { "PUSH16r",     "PUSH16rmm",    NO_UNFOLD },<br>
-  { "PUSH32r",     "PUSH32rmm",    NO_UNFOLD },<br>
-  { "PUSH64r",     "PUSH64rmm",    NO_UNFOLD },<br>
-  { "TAILJMPr",     "TAILJMPm",    UNFOLD },<br>
-  { "TAILJMPr64",    "TAILJMPm64",   UNFOLD },<br>
-  { "TAILJMPr64_REX",  "TAILJMPm64_REX", UNFOLD },<br>
-};<br>
-<br>
-// Do not add these instructions to any of the folding tables.<br>
-const char *const NoFoldSet[] = {<br>
-Â Â "TCRETURNri64",<br>
-Â Â "TCRETURNmi64", // Special dealing (in X86InstrCompiler.td under<br>
-  "TCRETURNri",  // "tailcall stuff" section).<br>
-Â Â "TCRETURNmi"<br>
-<br>
-Â Â // Different calculations of the folded operand between<br>
-Â Â // memory and register forms (folding is illegal).<br>
-Â Â // - In their register form, the second register operand's relevant<br>
-Â Â //Â Â bits are only the first 4/5/6 (depending on mode and reg size).<br>
-Â Â // - In their memory form, the second register operand's relevant<br>
-Â Â //Â Â bits are only the first 16/32/64 (depending on mode and reg size).<br>
-  "BT16rr", "BT32rr", "BT64rr",<br>
-  "BT16mr", "BT32mr", "BT64mr",<br>
-Â Â "BTC16rr", "BTC32rr", "BTC64rr",<br>
-Â Â "BTC16mr", "BTC32mr", "BTC64mr",<br>
-Â Â "BTR16rr", "BTR32rr", "BTR64rr",<br>
-Â Â "BTR16mr", "BTR32mr", "BTR64mr",<br>
-Â Â "BTS16rr", "BTS32rr", "BTS64rr",<br>
-Â Â "BTS16mr", "BTS32mr", "BTS64mr",<br>
-<br>
-Â Â // Memory folding is enabled only when optimizing for size by DAG<br>
-Â Â // patterns only. (issue detailed in D28744 review)<br>
-  "VCVTSS2SDrm",      "VCVTSS2SDrr",<br>
-  "VCVTSS2SDZrm",      "VCVTSS2SDZrr",<br>
-  "VCVTSS2SDZrmk",     "VCVTSS2SDZrrk",<br>
-  "VCVTSS2SDZrmkz",     "VCVTSS2SDZrrkz",<br>
-  "VCVTSS2SDZrm_Int",    "VCVTSS2SDZrr_Int",<br>
-  "VCVTSS2SDZrm_Intk",   "VCVTSS2SDZrr_Intk",<br>
-  "VCVTSS2SDZrm_Intkz",   "VCVTSS2SDZrr_Intkz",<br>
-  "VCVTSD2SSrm",      "VCVTSD2SSrr",<br>
-  "VCVTSD2SSZrm",      "VCVTSD2SSZrr",<br>
-  "VCVTSD2SSZrmk",     "VCVTSD2SSZrrk",<br>
-  "VCVTSD2SSZrmkz",     "VCVTSD2SSZrrkz",<br>
-  "VCVTSD2SSZrm_Int",    "VCVTSD2SSZrr_Int",<br>
-  "VCVTSD2SSZrm_Intk",   "VCVTSD2SSZrr_Intk",<br>
-  "VCVTSD2SSZrm_Intkz",   "VCVTSD2SSZrr_Intkz",<br>
-  "VRCP14SSrm",       "VRCP14SSrr",<br>
-  "VRCP14SDrm",       "VRCP14SDrr",<br>
-  "VRSQRT14SSrm",      "VRSQRT14SSrr",<br>
-  "VRSQRT14SDrm",      "VRSQRT14SDrr",<br>
-  "VSQRTSSm",        "VSQRTSSr",<br>
-  "VSQRTSSm_Int",      "VSQRTSSr_Int",<br>
-  "VSQRTSSZm",       "VSQRTSSZr",<br>
-  "VSQRTSSZm_Int",     "VSQRTSSZr_Int",<br>
-  "VSQRTSSZm_Intk",     "VSQRTSSZr_Intk",<br>
-  "VSQRTSSZm_Intkz",    "VSQRTSSZr_Intkz",<br>
-  "VSQRTSDm",        "VSQRTSDr",<br>
-  "VSQRTSDm_Int",      "VSQRTSDr_Int",<br>
-  "VSQRTSDZm",       "VSQRTSDZr",<br>
-  "VSQRTSDZm_Int",     "VSQRTSDZr_Int",<br>
-  "VSQRTSDZm_Intk",     "VSQRTSDZr_Intk",<br>
-  "VSQRTSDZm_Intkz",    "VSQRTSDZr_Intkz",<br>
-};<br>
-<br>
-static bool isExplicitAlign(const CodeGenInstruction *Inst) {<br>
-Â return any_of(ExplicitAlign, [Inst](const char *InstStr) {<br>
-Â Â return Inst->TheDef->getName().find(<wbr>InstStr) != StringRef::npos;<br>
-Â });<br>
-}<br>
-<br>
-static bool isExplicitUnalign(const CodeGenInstruction *Inst) {<br>
-Â return any_of(ExplicitUnalign, [Inst](const char *InstStr) {<br>
-Â Â return Inst->TheDef->getName().find(<wbr>InstStr) != StringRef::npos;<br>
-Â });<br>
-}<br>
-<br>
-class X86FoldTablesEmitter {<br>
-Â RecordKeeper &Records;<br>
-Â CodeGenTarget Target;<br>
-<br>
-Â // Represents an entry in the folding table<br>
-Â class X86FoldTableEntry {<br>
-Â Â const CodeGenInstruction *RegInst;<br>
-Â Â const CodeGenInstruction *MemInst;<br>
-<br>
-Â public:<br>
-Â Â bool CannotUnfold = false;<br>
-Â Â bool IsLoad = false;<br>
-Â Â bool IsStore = false;<br>
-Â Â bool IsAligned = false;<br>
-Â Â unsigned int Alignment = 0;<br>
-<br>
-Â Â X86FoldTableEntry(const CodeGenInstruction *RegInst,<br>
-Â Â Â Â Â Â Â Â Â Â Â const CodeGenInstruction *MemInst)<br>
-Â Â Â Â : RegInst(RegInst), MemInst(MemInst) {}<br>
-<br>
-Â Â friend raw_ostream &operator<<(raw_ostream &OS,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const X86FoldTableEntry &E) {<br>
-Â Â Â OS << "{ X86::" << E.RegInst->TheDef->getName()<br>
-Â Â Â Â Â << ", X86::" << E.MemInst->TheDef->getName() << ", ";<br>
-<br>
-Â Â Â if (E.IsLoad)<br>
-Â Â Â Â OS << "TB_FOLDED_LOAD | ";<br>
-Â Â Â if (E.IsStore)<br>
-Â Â Â Â OS << "TB_FOLDED_STORE | ";<br>
-Â Â Â if (E.CannotUnfold)<br>
-Â Â Â Â OS << "TB_NO_REVERSE | ";<br>
-Â Â Â if (E.IsAligned)<br>
-Â Â Â Â OS << "TB_ALIGN_" << E.Alignment << " | ";<br>
-<br>
-Â Â Â OS << "0 },\n";<br>
-<br>
-Â Â Â return OS;<br>
-Â Â }<br>
-Â };<br>
-<br>
-Â typedef std::vector<X86FoldTableEntry> FoldTable;<br>
-Â // std::vector for each folding table.<br>
-Â // Table2Addr - Holds instructions which their memory form performs load+store<br>
-Â // Table#i - Holds instructions which the their memory form perform a load OR<br>
- //      a store, and their #i'th operand is folded.<br>
-Â FoldTable Table2Addr;<br>
-Â FoldTable Table0;<br>
-Â FoldTable Table1;<br>
-Â FoldTable Table2;<br>
-Â FoldTable Table3;<br>
-Â FoldTable Table4;<br>
-<br>
-public:<br>
-Â X86FoldTablesEmitter(<wbr>RecordKeeper &R) : Records(R), Target(R) {}<br>
-<br>
-Â // run - Generate the 6 X86 memory fold tables.<br>
-Â void run(raw_ostream &OS);<br>
-<br>
-private:<br>
-Â // Decides to which table to add the entry with the given instructions.<br>
-Â // S sets the strategy of adding the TB_NO_REVERSE flag.<br>
-Â void updateTables(const CodeGenInstruction *RegInstr,<br>
-Â Â Â Â Â Â Â Â Â Â const CodeGenInstruction *MemInstr,<br>
-Â Â Â Â Â Â Â Â Â Â const UnfoldStrategy S = NO_STRATEGY);<br>
-<br>
-Â // Generates X86FoldTableEntry with the given instructions and fill it with<br>
-Â // the appropriate flags - then adds it to Table.<br>
-Â void addEntryWithFlags(FoldTable &Table, const CodeGenInstruction *RegInstr,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â const CodeGenInstruction *MemInstr,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â const UnfoldStrategy S, const unsigned int FoldedInd);<br>
-<br>
-Â // Print the given table as a static const C++ array of type<br>
-Â // X86MemoryFoldTableEntry.<br>
-Â void printTable(const FoldTable &Table, std::string TableName,<br>
-Â Â Â Â Â Â Â Â Â raw_ostream &OS) {<br>
-Â Â OS << "\nstatic const X86MemoryFoldTableEntry MemoryFold" << TableName<br>
-Â Â Â Â << "[] = {\n";<br>
-<br>
-Â Â for (const X86FoldTableEntry &E : Table)<br>
-Â Â Â OS.indent(2) << E;<br>
-<br>
-Â Â OS << "};\n";<br>
-Â }<br>
-};<br>
-<br>
-// Return true if one of the instruction's operands is a RST register class<br>
-static bool hasRSTRegClass(const CodeGenInstruction *Inst) {<br>
-Â return any_of(Inst->Operands, [](const CGIOperandList::OperandInfo &OpIn) {<br>
-Â Â return OpIn.Rec->getName() == "RST";<br>
-Â });<br>
-}<br>
-<br>
-// Return true if one of the instruction's operands is a ptr_rc_tailcall<br>
-static bool hasPtrTailcallRegClass(const CodeGenInstruction *Inst) {<br>
-Â return any_of(Inst->Operands, [](const CGIOperandList::OperandInfo &OpIn) {<br>
-Â Â return OpIn.Rec->getName() == "ptr_rc_tailcall";<br>
-Â });<br>
-}<br>
-<br>
-// Calculates the integer value representing the BitsInit object<br>
-static inline uint64_t getValueFromBitsInit(const BitsInit *B) {<br>
-Â assert(B->getNumBits() <= sizeof(uint64_t) * CHAR_BIT &&<br>
-Â Â Â Â Â "BitInits' too long!");<br>
-<br>
-Â uint64_t Value = 0;<br>
-Â for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {<br>
-Â Â BitInit *Bit = cast<BitInit>(B->getBit(i));<br>
-Â Â Value |= uint64_t(Bit->getValue()) << i;<br>
-Â }<br>
-Â return Value;<br>
-}<br>
-<br>
-// Returns true if the two given BitsInits represent the same integer value<br>
-static inline bool equalBitsInits(const BitsInit *B1, const BitsInit *B2) {<br>
-Â if (B1->getNumBits() != B2->getNumBits())<br>
-Â Â PrintFatalError("Comparing two BitsInits with different sizes!");<br>
-<br>
-Â for (unsigned i = 0, e = B1->getNumBits(); i != e; ++i) {<br>
-Â Â BitInit *Bit1 = cast<BitInit>(B1->getBit(i));<br>
-Â Â BitInit *Bit2 = cast<BitInit>(B2->getBit(i));<br>
-Â Â if (Bit1->getValue() != Bit2->getValue())<br>
-Â Â Â return false;<br>
-Â }<br>
-Â return true;<br>
-}<br>
-<br>
-// Return the size of the register operand<br>
-static inline unsigned int getRegOperandSize(const Record *RegRec) {<br>
-Â if (RegRec->isSubClassOf("<wbr>RegisterOperand"))<br>
-Â Â RegRec = RegRec->getValueAsDef("<wbr>RegClass");<br>
-Â if (RegRec->isSubClassOf("<wbr>RegisterClass"))<br>
-Â Â return RegRec->getValueAsListOfDefs("<wbr>RegTypes")[0]->getValueAsInt("<wbr>Size");<br>
-<br>
-Â llvm_unreachable("Register operand's size not known!");<br>
-}<br>
-<br>
-// Return the size of the memory operand<br>
-static inline unsigned int<br>
-getMemOperandSize(const Record *MemRec, const bool IntrinsicSensitive = false) {<br>
-Â if (MemRec->isSubClassOf("<wbr>Operand")) {<br>
-Â Â // Intrinsic memory instructions use ssmem/sdmem.<br>
-Â Â if (IntrinsicSensitive &&<br>
-Â Â Â Â (MemRec->getName() == "sdmem" || MemRec->getName() == "ssmem"))<br>
-Â Â Â return 128;<br>
-<br>
-Â Â StringRef Name =<br>
-Â Â Â Â MemRec->getValueAsDef("<wbr>ParserMatchClass")-><wbr>getValueAsString("Name");<br>
-Â Â if (Name == "Mem8")<br>
-Â Â Â return 8;<br>
-Â Â if (Name == "Mem16")<br>
-Â Â Â return 16;<br>
-Â Â if (Name == "Mem32")<br>
-Â Â Â return 32;<br>
-Â Â if (Name == "Mem64")<br>
-Â Â Â return 64;<br>
-Â Â if (Name == "Mem80")<br>
-Â Â Â return 80;<br>
-Â Â if (Name == "Mem128")<br>
-Â Â Â return 128;<br>
-Â Â if (Name == "Mem256")<br>
-Â Â Â return 256;<br>
-Â Â if (Name == "Mem512")<br>
-Â Â Â return 512;<br>
-Â }<br>
-<br>
-Â llvm_unreachable("Memory operand's size not known!");<br>
-}<br>
-<br>
-// Returns true if the record's list of defs includes the given def.<br>
-static inline bool hasDefInList(const Record *Rec, const StringRef List,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const StringRef Def) {<br>
-Â if (!Rec->isValueUnset(List)) {<br>
-Â Â return any_of(*(Rec-><wbr>getValueAsListInit(List)),<br>
-Â Â Â Â Â Â Â Â Â [Def](const Init *I) { return I->getAsString() == Def; });<br>
-Â }<br>
-Â return false;<br>
-}<br>
-<br>
-// Return true if the instruction defined as a register flavor.<br>
-static inline bool hasRegisterFormat(const Record *Inst) {<br>
-Â const BitsInit *FormBits = Inst->getValueAsBitsInit("<wbr>FormBits");<br>
-Â uint64_t FormBitsNum = getValueFromBitsInit(FormBits)<wbr>;<br>
-<br>
-Â // Values from X86Local namespace defined in X86RecognizableInstr.cpp<br>
-Â return FormBitsNum >= X86Local::MRMDestReg && FormBitsNum <= X86Local::MRM7r;<br>
-}<br>
-<br>
-// Return true if the instruction defined as a memory flavor.<br>
-static inline bool hasMemoryFormat(const Record *Inst) {<br>
-Â const BitsInit *FormBits = Inst->getValueAsBitsInit("<wbr>FormBits");<br>
-Â uint64_t FormBitsNum = getValueFromBitsInit(FormBits)<wbr>;<br>
-<br>
-Â // Values from X86Local namespace defined in X86RecognizableInstr.cpp<br>
-Â return FormBitsNum >= X86Local::MRMDestMem && FormBitsNum <= X86Local::MRM7m;<br>
-}<br>
-<br>
-static inline bool isNOREXRegClass(const Record *Op) {<br>
-Â return Op->getName().find("_NOREX") != StringRef::npos;<br>
-}<br>
-<br>
-static inline bool isRegisterOperand(const Record *Rec) {<br>
-Â return Rec->isSubClassOf("<wbr>RegisterClass") ||<br>
-Â Â Â Â Â Rec->isSubClassOf("<wbr>RegisterOperand") ||<br>
-Â Â Â Â Â Rec->isSubClassOf("<wbr>PointerLikeRegClass");<br>
-}<br>
-<br>
-static inline bool isMemoryOperand(const Record *Rec) {<br>
-Â return Rec->isSubClassOf("Operand") &&<br>
-Â Â Â Â Â Rec->getValueAsString("<wbr>OperandType") == "OPERAND_MEMORY";<br>
-}<br>
-<br>
-static inline bool isImmediateOperand(const Record *Rec) {<br>
-Â return Rec->isSubClassOf("Operand") &&<br>
-Â Â Â Â Â Rec->getValueAsString("<wbr>OperandType") == "OPERAND_IMMEDIATE";<br>
-}<br>
-<br>
-// Get the alternative instruction pointed by "FoldGenRegForm" field.<br>
-static inline const CodeGenInstruction *<br>
-getAltRegInst(const CodeGenInstruction *I, const RecordKeeper &Records,<br>
-Â Â Â Â Â Â Â const CodeGenTarget &Target) {<br>
-<br>
-Â std::string AltRegInstStr = I->TheDef->getValueAsString("<wbr>FoldGenRegForm");<br>
-Â Record *AltRegInstRec = Records.getDef(AltRegInstStr);<br>
-Â assert(AltRegInstRec &&<br>
-Â Â Â Â Â "Alternative register form instruction def not found");<br>
-Â CodeGenInstruction &AltRegInst = Target.getInstruction(<wbr>AltRegInstRec);<br>
-Â return &AltRegInst;<br>
-}<br>
-<br>
-// Function object - Operator() returns true if the given VEX instruction<br>
-// matches the EVEX instruction of this object.<br>
-class IsMatch {<br>
-Â const CodeGenInstruction *MemInst;<br>
-Â const RecordKeeper &Records;<br>
-<br>
-public:<br>
-Â IsMatch(const CodeGenInstruction *Inst, const RecordKeeper &Records)<br>
-Â Â Â : MemInst(Inst), Records(Records) {}<br>
-<br>
-Â bool operator()(const CodeGenInstruction *RegInst) {<br>
-Â Â Record *MemRec = MemInst->TheDef;<br>
-Â Â Record *RegRec = RegInst->TheDef;<br>
-<br>
-Â Â // Return false if one (at least) of the encoding fields of both<br>
-Â Â // instructions do not match.<br>
-Â Â if (RegRec->getValueAsDef("OpEnc"<wbr>) != MemRec->getValueAsDef("OpEnc") ||<br>
-Â Â Â Â !equalBitsInits(RegRec-><wbr>getValueAsBitsInit("Opcode"),<br>
-Â Â Â Â Â Â Â Â Â Â Â Â MemRec->getValueAsBitsInit("<wbr>Opcode")) ||<br>
-Â Â Â Â // VEX/EVEX fields<br>
-Â Â Â Â RegRec->getValueAsDef("<wbr>OpPrefix") !=<br>
-Â Â Â Â Â Â MemRec->getValueAsDef("<wbr>OpPrefix") ||<br>
-Â Â Â Â RegRec->getValueAsDef("OpMap") != MemRec->getValueAsDef("OpMap") ||<br>
-Â Â Â Â RegRec->getValueAsDef("OpSize"<wbr>) != MemRec->getValueAsDef("OpSize"<wbr>) ||<br>
-Â Â Â Â RegRec->getValueAsBit("hasVEX_<wbr>4V") !=<br>
-Â Â Â Â Â Â MemRec->getValueAsBit("hasVEX_<wbr>4V") ||<br>
-Â Â Â Â RegRec->getValueAsBit("<wbr>hasEVEX_K") !=<br>
-Â Â Â Â Â Â MemRec->getValueAsBit("<wbr>hasEVEX_K") ||<br>
-Â Â Â Â RegRec->getValueAsBit("<wbr>hasEVEX_Z") !=<br>
-Â Â Â Â Â Â MemRec->getValueAsBit("<wbr>hasEVEX_Z") ||<br>
-Â Â Â Â RegRec->getValueAsBit("<wbr>hasEVEX_B") !=<br>
-Â Â Â Â Â Â MemRec->getValueAsBit("<wbr>hasEVEX_B") ||<br>
-Â Â Â Â RegRec->getValueAsBit("<wbr>hasEVEX_RC") !=<br>
-Â Â Â Â Â Â MemRec->getValueAsBit("<wbr>hasEVEX_RC") ||<br>
-Â Â Â Â RegRec->getValueAsBit("hasREX_<wbr>WPrefix") !=<br>
-Â Â Â Â Â Â MemRec->getValueAsBit("hasREX_<wbr>WPrefix") ||<br>
-Â Â Â Â RegRec->getValueAsBit("<wbr>hasLockPrefix") !=<br>
-Â Â Â Â Â Â MemRec->getValueAsBit("<wbr>hasLockPrefix") ||<br>
-Â Â Â Â !equalBitsInits(RegRec-><wbr>getValueAsBitsInit("EVEX_LL"),<br>
-Â Â Â Â Â Â Â Â Â Â Â Â MemRec->getValueAsBitsInit("<wbr>EVEX_LL")) ||<br>
-Â Â Â Â !equalBitsInits(RegRec-><wbr>getValueAsBitsInit("VEX_<wbr>WPrefix"),<br>
-Â Â Â Â Â Â Â Â Â Â Â Â MemRec->getValueAsBitsInit("<wbr>VEX_WPrefix")) ||<br>
-Â Â Â Â // Instruction's format - The register form's "Form" field should be<br>
-Â Â Â Â // the opposite of the memory form's "Form" field.<br>
-Â Â Â Â !areOppositeForms(RegRec-><wbr>getValueAsBitsInit("FormBits")<wbr>,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â MemRec->getValueAsBitsInit("<wbr>FormBits")) ||<br>
-Â Â Â Â RegRec->getValueAsBit("<wbr>isAsmParserOnly") !=<br>
-Â Â Â Â Â Â MemRec->getValueAsBit("<wbr>isAsmParserOnly"))<br>
-Â Â Â return false;<br>
-<br>
-Â Â // Make sure the sizes of the operands of both instructions suit each other.<br>
-Â Â // This is needed for instructions with intrinsic version (_Int).<br>
-Â Â // Where the only difference is the size of the operands.<br>
-Â Â // For example: VUCOMISDZrm and Int_VUCOMISDrm<br>
-Â Â // Also for instructions that their EVEX version was upgraded to work with<br>
-Â Â // k-registers. For example VPCMPEQBrm (xmm output register) and<br>
-Â Â // VPCMPEQBZ128rm (k register output register).<br>
-Â Â bool ArgFolded = false;<br>
-Â Â unsigned MemOutSize = MemRec->getValueAsDag("<wbr>OutOperandList")->getNumArgs()<wbr>;<br>
-Â Â unsigned RegOutSize = RegRec->getValueAsDag("<wbr>OutOperandList")->getNumArgs()<wbr>;<br>
-Â Â unsigned MemInSize = MemRec->getValueAsDag("<wbr>InOperandList")->getNumArgs();<br>
-Â Â unsigned RegInSize = RegRec->getValueAsDag("<wbr>InOperandList")->getNumArgs();<br>
-<br>
-Â Â // Instructions with one output in their memory form use the memory folded<br>
-Â Â // operand as source and destination (Read-Modify-Write).<br>
-Â Â unsigned RegStartIdx =<br>
-Â Â Â Â (MemOutSize + 1 == RegOutSize) && (MemInSize == RegInSize) ? 1 : 0;<br>
-<br>
-Â Â for (unsigned i = 0, e = MemInst->Operands.size(); i < e; i++) {<br>
-Â Â Â Record *MemOpRec = MemInst->Operands[i].Rec;<br>
-Â Â Â Record *RegOpRec = RegInst->Operands[i + RegStartIdx].Rec;<br>
-<br>
-Â Â Â if (MemOpRec == RegOpRec)<br>
-Â Â Â Â continue;<br>
-<br>
-Â Â Â if (isRegisterOperand(MemOpRec) && isRegisterOperand(RegOpRec)) {<br>
-Â Â Â Â if (getRegOperandSize(MemOpRec) != getRegOperandSize(RegOpRec) ||<br>
-Â Â Â Â Â Â isNOREXRegClass(MemOpRec) != isNOREXRegClass(RegOpRec))<br>
-Â Â Â Â Â return false;<br>
-Â Â Â } else if (isMemoryOperand(MemOpRec) && isMemoryOperand(RegOpRec)) {<br>
-Â Â Â Â if (getMemOperandSize(MemOpRec) != getMemOperandSize(RegOpRec))<br>
-Â Â Â Â Â return false;<br>
-Â Â Â } else if (isImmediateOperand(MemOpRec) && isImmediateOperand(RegOpRec)) {<br>
-Â Â Â Â if (MemOpRec->getValueAsDef("<wbr>Type") != RegOpRec->getValueAsDef("Type"<wbr>))<br>
-Â Â Â Â Â return false;<br>
-Â Â Â } else {<br>
-Â Â Â Â // Only one operand can be folded.<br>
-Â Â Â Â if (ArgFolded)<br>
-Â Â Â Â Â return false;<br>
-<br>
-Â Â Â Â assert(isRegisterOperand(<wbr>RegOpRec) && isMemoryOperand(MemOpRec));<br>
-Â Â Â Â ArgFolded = true;<br>
-Â Â Â }<br>
-Â Â }<br>
-<br>
-Â Â return true;<br>
-Â }<br>
-<br>
-private:<br>
-Â // Return true of the 2 given forms are the opposite of each other.<br>
-Â bool areOppositeForms(const BitsInit *RegFormBits,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â const BitsInit *MemFormBits) {<br>
-Â Â uint64_t MemFormNum = getValueFromBitsInit(<wbr>MemFormBits);<br>
-Â Â uint64_t RegFormNum = getValueFromBitsInit(<wbr>RegFormBits);<br>
-<br>
-Â Â if ((MemFormNum == X86Local::MRM0m && RegFormNum == X86Local::MRM0r) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRM1m && RegFormNum == X86Local::MRM1r) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRM2m && RegFormNum == X86Local::MRM2r) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRM3m && RegFormNum == X86Local::MRM3r) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRM4m && RegFormNum == X86Local::MRM4r) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRM5m && RegFormNum == X86Local::MRM5r) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRM6m && RegFormNum == X86Local::MRM6r) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRM7m && RegFormNum == X86Local::MRM7r) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRMXm && RegFormNum == X86Local::MRMXr) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRMDestMem &&<br>
-Â Â Â Â Â RegFormNum == X86Local::MRMDestReg) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRMSrcMem &&<br>
-Â Â Â Â Â RegFormNum == X86Local::MRMSrcReg) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRMSrcMem4VOp3 &&<br>
-Â Â Â Â Â RegFormNum == X86Local::MRMSrcReg4VOp3) ||<br>
-Â Â Â Â (MemFormNum == X86Local::MRMSrcMemOp4 &&<br>
-Â Â Â Â Â RegFormNum == X86Local::MRMSrcRegOp4))<br>
-Â Â Â return true;<br>
-<br>
-Â Â return false;<br>
-Â }<br>
-};<br>
-<br>
-} // end anonymous namespace<br>
-<br>
-void X86FoldTablesEmitter::<wbr>addEntryWithFlags(FoldTable &Table,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const CodeGenInstruction *RegInstr,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const CodeGenInstruction *MemInstr,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const UnfoldStrategy S,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const unsigned int FoldedInd) {<br>
-<br>
-Â X86FoldTableEntry Result = X86FoldTableEntry(RegInstr, MemInstr);<br>
-Â Record *RegRec = RegInstr->TheDef;<br>
-Â Record *MemRec = MemInstr->TheDef;<br>
-<br>
-Â // Only table0 entries should explicitly specify a load or store flag.<br>
-Â if (&Table == &Table0) {<br>
-Â Â unsigned MemInOpsNum = MemRec->getValueAsDag("<wbr>InOperandList")->getNumArgs();<br>
-Â Â unsigned RegInOpsNum = RegRec->getValueAsDag("<wbr>InOperandList")->getNumArgs();<br>
-Â Â // If the instruction writes to the folded operand, it will appear as an<br>
-Â Â // output in the register form instruction and as an input in the memory<br>
-Â Â // form instruction.<br>
-Â Â // If the instruction reads from the folded operand, it well appear as in<br>
-Â Â // input in both forms.<br>
-Â Â if (MemInOpsNum == RegInOpsNum)<br>
-Â Â Â Result.IsLoad = true;<br>
-Â Â else<br>
-Â Â Â Result.IsStore = true;<br>
-Â }<br>
-<br>
-Â Record *RegOpRec = RegInstr->Operands[FoldedInd].<wbr>Rec;<br>
-Â Record *MemOpRec = MemInstr->Operands[FoldedInd].<wbr>Rec;<br>
-<br>
-Â // Unfolding code generates a load/store instruction according to the size of<br>
-Â // the register in the register form instruction.<br>
-Â // If the register's size is greater than the memory's operand size, do not<br>
-Â // allow unfolding.<br>
-Â if (S == UNFOLD)<br>
-Â Â Result.CannotUnfold = false;<br>
-Â else if (S == NO_UNFOLD)<br>
-Â Â Result.CannotUnfold = true;<br>
-Â else if (getRegOperandSize(RegOpRec) > getMemOperandSize(MemOpRec))<br>
-Â Â Result.CannotUnfold = true; // S == NO_STRATEGY<br>
-<br>
-Â uint64_t Enc = getValueFromBitsInit(RegRec-><wbr>getValueAsBitsInit("OpEncBits"<wbr>));<br>
-Â if (isExplicitAlign(RegInstr)) {<br>
-Â Â // The instruction require explicitly aligned memory.<br>
-Â Â BitsInit *VectSize = RegRec->getValueAsBitsInit("<wbr>VectSize");<br>
-Â Â uint64_t Value = getValueFromBitsInit(VectSize)<wbr>;<br>
-Â Â Result.IsAligned = true;<br>
-Â Â Result.Alignment = Value;<br>
-Â } else if (Enc != X86Local::XOP && Enc != X86Local::VEX &&<br>
-Â Â Â Â Â Â Â Enc != X86Local::EVEX) {<br>
-Â Â // Instructions with VEX encoding do not require alignment.<br>
-Â Â if (!isExplicitUnalign(RegInstr) && getMemOperandSize(MemOpRec) > 64) {<br>
-Â Â Â // SSE packed vector instructions require a 16 byte alignment.<br>
-Â Â Â Result.IsAligned = true;<br>
-Â Â Â Result.Alignment = 16;<br>
-Â Â }<br>
-Â }<br>
-<br>
-Â Table.push_back(Result);<br>
-}<br>
-<br>
-void X86FoldTablesEmitter::<wbr>updateTables(const CodeGenInstruction *RegInstr,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const CodeGenInstruction *MemInstr,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const UnfoldStrategy S) {<br>
-<br>
-Â Record *RegRec = RegInstr->TheDef;<br>
-Â Record *MemRec = MemInstr->TheDef;<br>
-Â unsigned MemOutSize = MemRec->getValueAsDag("<wbr>OutOperandList")->getNumArgs()<wbr>;<br>
-Â unsigned RegOutSize = RegRec->getValueAsDag("<wbr>OutOperandList")->getNumArgs()<wbr>;<br>
-Â unsigned MemInSize = MemRec->getValueAsDag("<wbr>InOperandList")->getNumArgs();<br>
-Â unsigned RegInSize = RegRec->getValueAsDag("<wbr>InOperandList")->getNumArgs();<br>
-<br>
-Â // Instructions which have the WriteRMW value (Read-Modify-Write) should be<br>
-Â // added to Table2Addr.<br>
-Â if (hasDefInList(MemRec, "SchedRW", "WriteRMW") && MemOutSize != RegOutSize &&<br>
-Â Â Â MemInSize == RegInSize) {<br>
-Â Â addEntryWithFlags(Table2Addr, RegInstr, MemInstr, S, 0);<br>
-Â Â return;<br>
-Â }<br>
-<br>
-Â if (MemInSize == RegInSize && MemOutSize == RegOutSize) {<br>
-Â Â // Load-Folding cases.<br>
-Â Â // If the i'th register form operand is a register and the i'th memory form<br>
-Â Â // operand is a memory operand, add instructions to Table#i.<br>
-Â Â for (unsigned i = RegOutSize, e = RegInstr->Operands.size(); i < e; i++) {<br>
-Â Â Â Record *RegOpRec = RegInstr->Operands[i].Rec;<br>
-Â Â Â Record *MemOpRec = MemInstr->Operands[i].Rec;<br>
-Â Â Â if (isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec)) {<br>
-Â Â Â Â switch (i) {<br>
-Â Â Â Â default: llvm_unreachable("Unexpected operand count!");<br>
-Â Â Â Â case 0:<br>
-Â Â Â Â Â addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0);<br>
-Â Â Â Â Â return;<br>
-Â Â Â Â case 1:<br>
-Â Â Â Â Â addEntryWithFlags(Table1, RegInstr, MemInstr, S, 1);<br>
-Â Â Â Â Â return;<br>
-Â Â Â Â case 2:<br>
-Â Â Â Â Â addEntryWithFlags(Table2, RegInstr, MemInstr, S, 2);<br>
-Â Â Â Â Â return;<br>
-Â Â Â Â case 3:<br>
-Â Â Â Â Â addEntryWithFlags(Table3, RegInstr, MemInstr, S, 3);<br>
-Â Â Â Â Â return;<br>
-Â Â Â Â case 4:<br>
-Â Â Â Â Â addEntryWithFlags(Table4, RegInstr, MemInstr, S, 4);<br>
-Â Â Â Â Â return;<br>
-Â Â Â Â }<br>
-Â Â Â }<br>
-Â Â }<br>
-Â } else if (MemInSize == RegInSize + 1 && MemOutSize + 1 == RegOutSize) {<br>
-Â Â // Store-Folding cases.<br>
-Â Â // If the memory form instruction performs performs a store, the *output*<br>
-Â Â // register of the register form instructions disappear and instead a<br>
-Â Â // memory *input* operand appears in the memory form instruction.<br>
-Â Â // For example:<br>
-Â Â //Â Â MOVAPSrr => (outs VR128:$dst), (ins VR128:$src)<br>
-Â Â //Â Â MOVAPSmr => (outs), (ins f128mem:$dst, VR128:$src)<br>
-Â Â Record *RegOpRec = RegInstr->Operands[RegOutSize - 1].Rec;<br>
-Â Â Record *MemOpRec = MemInstr->Operands[RegOutSize - 1].Rec;<br>
-Â Â if (isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec))<br>
-Â Â Â addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0);<br>
-Â }<br>
-<br>
-Â return;<br>
-}<br>
-<br>
-void X86FoldTablesEmitter::run(raw_<wbr>ostream &OS) {<br>
-Â emitSourceFileHeader("X86 fold tables", OS);<br>
-<br>
-Â // Holds all memory instructions<br>
-Â std::vector<const CodeGenInstruction *> MemInsts;<br>
-Â // Holds all register instructions - divided according to opcode.<br>
-Â std::map<uint8_t, std::vector<const CodeGenInstruction *>> RegInsts;<br>
-<br>
-Â ArrayRef<const CodeGenInstruction *> NumberedInstructions =<br>
-Â Â Â Target.<wbr>getInstructionsByEnumValue();<br>
-<br>
-Â for (const CodeGenInstruction *Inst : NumberedInstructions) {<br>
-Â Â if (!Inst->TheDef->getNameInit() || !Inst->TheDef->isSubClassOf("<wbr>X86Inst"))<br>
-Â Â Â continue;<br>
-<br>
-Â Â const Record *Rec = Inst->TheDef;<br>
-<br>
-Â Â // - Do not proceed matching if the instruction in NoFoldSet.<br>
-Â Â // - Instructions including RST register class operands are not relevant<br>
-Â Â //Â Â for memory folding (for further details check the explanation in<br>
-Â Â //Â Â lib/Target/X86/<wbr>X86InstrFPStack.td file).<br>
-Â Â // - Some instructions (listed in the manual map above) use the register<br>
-Â Â //Â Â class ptr_rc_tailcall, which can be of a size 32 or 64, to ensure<br>
-Â Â //Â Â safe mapping of these instruction we manually map them and exclude<br>
-Â Â //Â Â them from the automation.<br>
-Â Â if (find(NoFoldSet, Rec->getName()) != std::end(NoFoldSet) ||<br>
-Â Â Â Â hasRSTRegClass(Inst) || hasPtrTailcallRegClass(Inst))<br>
-Â Â Â continue;<br>
-<br>
-Â Â // Add all the memory form instructions to MemInsts, and all the register<br>
-Â Â // form instructions to RegInsts[Opc], where Opc in the opcode of each<br>
-Â Â // instructions. this helps reducing the runtime of the backend.<br>
-Â Â if (hasMemoryFormat(Rec))<br>
-Â Â Â MemInsts.push_back(Inst);<br>
-Â Â else if (hasRegisterFormat(Rec)) {<br>
-Â Â Â uint8_t Opc = getValueFromBitsInit(Rec-><wbr>getValueAsBitsInit("Opcode"));<br>
-Â Â Â RegInsts[Opc].push_back(Inst);<br>
-Â Â }<br>
-Â }<br>
-<br>
-Â // For each memory form instruction, try to find its register form<br>
-Â // instruction.<br>
-Â for (const CodeGenInstruction *MemInst : MemInsts) {<br>
-Â Â uint8_t Opc =<br>
-Â Â Â Â getValueFromBitsInit(MemInst-><wbr>TheDef->getValueAsBitsInit("<wbr>Opcode"));<br>
-<br>
-Â Â if (RegInsts.count(Opc) == 0)<br>
-Â Â Â continue;<br>
-<br>
-Â Â // Two forms (memory & register) of the same instruction must have the same<br>
-Â Â // opcode. try matching only with register form instructions with the same<br>
-Â Â // opcode.<br>
-Â Â std::vector<const CodeGenInstruction *> &OpcRegInsts =<br>
-Â Â Â Â RegInsts.find(Opc)->second;<br>
-<br>
-Â Â auto Match = find_if(OpcRegInsts, IsMatch(MemInst, Records));<br>
-Â Â if (Match != OpcRegInsts.end()) {<br>
-Â Â Â const CodeGenInstruction *RegInst = *Match;<br>
-Â Â Â // If the matched instruction has it's "FoldGenRegForm" set, map the<br>
-Â Â Â // memory form instruction to the register form instruction pointed by<br>
-Â Â Â // this field<br>
-Â Â Â if (RegInst->TheDef-><wbr>isValueUnset("FoldGenRegForm")<wbr>) {<br>
-Â Â Â Â updateTables(RegInst, MemInst);<br>
-Â Â Â } else {<br>
-Â Â Â Â const CodeGenInstruction *AltRegInst =<br>
-Â Â Â Â Â Â getAltRegInst(RegInst, Records, Target);<br>
-Â Â Â Â updateTables(AltRegInst, MemInst);<br>
-Â Â Â }<br>
-Â Â Â OpcRegInsts.erase(Match);<br>
-Â Â }<br>
-Â }<br>
-<br>
-Â // Add the manually mapped instructions listed above.<br>
-Â for (const ManualMapEntry &Entry : ManualMapSet) {<br>
-Â Â Record *RegInstIter = Records.getDef(Entry.<wbr>RegInstStr);<br>
-Â Â Record *MemInstIter = Records.getDef(Entry.<wbr>MemInstStr);<br>
-<br>
-Â Â updateTables(&(Target.<wbr>getInstruction(RegInstIter)),<br>
-Â Â Â Â Â Â Â Â Â &(Target.getInstruction(<wbr>MemInstIter)), Entry.Strategy);<br>
-Â }<br>
-<br>
-Â // Print all tables to raw_ostream OS.<br>
-Â printTable(Table2Addr, "Table2Addr", OS);<br>
-Â printTable(Table0, "Table0", OS);<br>
-Â printTable(Table1, "Table1", OS);<br>
-Â printTable(Table2, "Table2", OS);<br>
-Â printTable(Table3, "Table3", OS);<br>
-Â printTable(Table4, "Table4", OS);<br>
-}<br>
-<br>
-namespace llvm {<br>
-<br>
-void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &OS) {<br>
-Â X86FoldTablesEmitter(RK).run(<wbr>OS);<br>
-}<br>
-} // namespace llvm<br>
<br>
<br>
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