<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Unfortunately that didn't fix it. I notice that the test is passing on the other builder that is running on that buildslave (<a href="http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/9844" class="">http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/9844</a>) so it's unlikely to be something to do with the machine.<div class=""><br class=""></div><div class="">I don't see any mention of generating X86GenGlobalISel.inc in <a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/2552" class="">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/2552</a> so I've started a clean build.<br class=""><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On 24 May 2017, at 07:13, Daniel Sanders via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><meta http-equiv="Content-Type" content="text/html charset=us-ascii" class=""><div style="word-wrap: break-word; -webkit-nbsp-mode: space; line-break: after-white-space;" class="">Hi Galina,<div class=""><br class=""></div><div class="">That test is new in this commit and it seems that optsize isn't having the desired effect on this machine. I'd hazard a guess that this buildbot has +slow-incdec set via the default processor and this is telling the instruction selector not to use inc/dec even when optimizing for size. I've tweaked the test to disable this feature using -mattr.</div><div class=""><br class=""></div><div class="">Sorry for leaving this broken overnight. I was keeping an eye on <a href="http://lab.llvm.org:8011/console" class="">lab.llvm.org:8011/console</a> but that didn't report this builder.</div><div class=""><br class=""><div class=""><blockquote type="cite" class=""><div class="">On 24 May 2017, at 00:11, Galina Kistanova <<a href="mailto:gkistanova@gmail.com" class="">gkistanova@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Hello Daniel,<br class=""><br class="">This commit broke tests on one of our builders:<br class=""><br class="">Failing Tests (1):<br class=""> LLVM :: CodeGen/X86/GlobalISel/select-leaf-constant.mir<br class=""><br class=""><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win" class="">http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win</a><br class=""><br class="">Please have a look at this?<br class=""><br class="">Thanks<br class=""><br class="">Galina<br class=""><br class=""></div><div class="gmail_extra"><br class=""><div class="gmail_quote">On Tue, May 23, 2017 at 12:33 PM, Daniel Sanders via llvm-commits <span dir="ltr" class=""><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: dsanders<br class="">
Date: Tue May 23 14:33:16 2017<br class="">
New Revision: 303678<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=303678&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project?rev=303678&view=rev</a><br class="">
Log:<br class="">
[globalisel][tablegen] Add support for (set $dst, 1) and test X86's OptForSize predicate.<br class="">
<br class="">
Summary:<br class="">
It's rare but a small number of patterns use IntInit's at the root of the match.<br class="">
On X86, one such rule is enabled by the OptForSize predicate and causes the<br class="">
compiler to use the smaller:<br class="">
%0 = MOV32r1<br class="">
instead of the usual:<br class="">
%0 = MOV32ri 1<br class="">
<br class="">
This patch adds support for matching IntInit's at the root and uses this as a<br class="">
test case for the optsize attribute that was implemented in r301750<br class="">
<br class="">
Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls, aditya_nandakumar<br class="">
<br class="">
Reviewed By: qcolombet<br class="">
<br class="">
Subscribers: igorb, llvm-commits<br class="">
<br class="">
Differential Revision: <a href="https://reviews.llvm.org/D32791" rel="noreferrer" target="_blank" class="">https://reviews.llvm.org/<wbr class="">D32791</a><br class="">
<br class="">
Added:<br class="">
llvm/trunk/test/CodeGen/X86/<wbr class="">GlobalISel/select-leaf-<wbr class="">constant.mir<br class="">
Modified:<br class="">
llvm/trunk/test/TableGen/<wbr class="">GlobalISelEmitter.td<br class="">
llvm/trunk/utils/TableGen/<wbr class="">GlobalISelEmitter.cpp<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/X86/<wbr class="">GlobalISel/select-leaf-<wbr class="">constant.mir<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir?rev=303678&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/X86/GlobalISel/select-<wbr class="">leaf-constant.mir?rev=303678&<wbr class="">view=auto</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/X86/<wbr class="">GlobalISel/select-leaf-<wbr class="">constant.mir (added)<br class="">
+++ llvm/trunk/test/CodeGen/X86/<wbr class="">GlobalISel/select-leaf-<wbr class="">constant.mir Tue May 23 14:33:16 2017<br class="">
@@ -0,0 +1,96 @@<br class="">
+# RUN: llc -mtriple=i586-linux-gnu -global-isel -run-pass=instruction-select %s -o - | FileCheck %s --check-prefix=CHECK<br class="">
+#<br class="">
+# This is necessary to test that attribute-based rule predicates work and that<br class="">
+# they properly reset between functions.<br class="">
+<br class="">
+--- |<br class="">
+ define i32 @const_i32_1() {<br class="">
+ ret i32 1<br class="">
+ }<br class="">
+<br class="">
+ define i32 @const_i32_1_optsize() #0 {<br class="">
+ ret i32 1<br class="">
+ }<br class="">
+<br class="">
+ define i32 @const_i32_1b() {<br class="">
+ ret i32 1<br class="">
+ }<br class="">
+<br class="">
+ define i32 @const_i32_1_optsizeb() #0 {<br class="">
+ ret i32 1<br class="">
+ }<br class="">
+<br class="">
+ attributes #0 = { optsize }<br class="">
+...<br class="">
+---<br class="">
+name: const_i32_1<br class="">
+legalized: true<br class="">
+regBankSelected: true<br class="">
+selected: false<br class="">
+# CHECK-LABEL: name: const_i32_1<br class="">
+# CHECK: registers:<br class="">
+# CHECK-NEXT: - { id: 0, class: gr32 }<br class="">
+registers:<br class="">
+ - { id: 0, class: gpr }<br class="">
+# CHECK: body:<br class="">
+# CHECK: %0 = MOV32ri 1<br class="">
+body: |<br class="">
+ bb.1 (%ir-block.0):<br class="">
+ %0(s32) = G_CONSTANT i32 1<br class="">
+ %eax = COPY %0(s32)<br class="">
+ RET 0, implicit %eax<br class="">
+...<br class="">
+---<br class="">
+name: const_i32_1_optsize<br class="">
+legalized: true<br class="">
+regBankSelected: true<br class="">
+selected: false<br class="">
+# CHECK-LABEL: name: const_i32_1_optsize<br class="">
+# CHECK: registers:<br class="">
+# CHECK-NEXT: - { id: 0, class: gr32 }<br class="">
+registers:<br class="">
+ - { id: 0, class: gpr }<br class="">
+# CHECK: body:<br class="">
+# CHECK: %0 = MOV32r1<br class="">
+body: |<br class="">
+ bb.1 (%ir-block.0):<br class="">
+ %0(s32) = G_CONSTANT i32 1<br class="">
+ %eax = COPY %0(s32)<br class="">
+ RET 0, implicit %eax<br class="">
+...<br class="">
+---<br class="">
+name: const_i32_1b<br class="">
+legalized: true<br class="">
+regBankSelected: true<br class="">
+selected: false<br class="">
+# CHECK-LABEL: name: const_i32_1b<br class="">
+# CHECK: registers:<br class="">
+# CHECK-NEXT: - { id: 0, class: gr32 }<br class="">
+registers:<br class="">
+ - { id: 0, class: gpr }<br class="">
+# CHECK: body:<br class="">
+# CHECK: %0 = MOV32ri 1<br class="">
+body: |<br class="">
+ bb.1 (%ir-block.0):<br class="">
+ %0(s32) = G_CONSTANT i32 1<br class="">
+ %eax = COPY %0(s32)<br class="">
+ RET 0, implicit %eax<br class="">
+...<br class="">
+---<br class="">
+name: const_i32_1_optsizeb<br class="">
+legalized: true<br class="">
+regBankSelected: true<br class="">
+selected: false<br class="">
+# CHECK-LABEL: name: const_i32_1_optsizeb<br class="">
+# CHECK: registers:<br class="">
+# CHECK-NEXT: - { id: 0, class: gr32 }<br class="">
+registers:<br class="">
+ - { id: 0, class: gpr }<br class="">
+# CHECK: body:<br class="">
+# CHECK: %0 = MOV32r1<br class="">
+body: |<br class="">
+ bb.1 (%ir-block.0):<br class="">
+ %0(s32) = G_CONSTANT i32 1<br class="">
+ %eax = COPY %0(s32)<br class="">
+ RET 0, implicit %eax<br class="">
+...<br class="">
<br class="">
Modified: llvm/trunk/test/TableGen/<wbr class="">GlobalISelEmitter.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/GlobalISelEmitter.td?rev=303678&r1=303677&r2=303678&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">TableGen/GlobalISelEmitter.td?<wbr class="">rev=303678&r1=303677&r2=<wbr class="">303678&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/TableGen/<wbr class="">GlobalISelEmitter.td (original)<br class="">
+++ llvm/trunk/test/TableGen/<wbr class="">GlobalISelEmitter.td Tue May 23 14:33:16 2017<br class="">
@@ -462,6 +462,32 @@ def XORManyDefaults : I<(outs GPR32:$dst<br class="">
def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;<br class="">
def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>;<br class="">
<br class="">
+//===- Test a simple pattern with just a leaf immediate. ------------------===//<br class="">
+<br class="">
+// CHECK-LABEL: if ([&]() {<br class="">
+// CHECK-NEXT: MachineInstr &MI0 = I;<br class="">
+// CHECK-NEXT: if (MI0.getNumOperands() < 2)<br class="">
+// CHECK-NEXT: return false;<br class="">
+// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_CONSTANT) &&<br class="">
+// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0)<wbr class="">.getReg()) == (LLT::scalar(32))) &&<br class="">
+// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(<wbr class="">MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(<wbr class="">0).getReg(), MRI, TRI))))) &&<br class="">
+// CHECK-NEXT: ((/* Operand 1 */ (MI0.getOperand(1).isCImm() && MI0.getOperand(1).getCImm()-><wbr class="">equalsInt(1))))) {<br class="">
+// CHECK-NEXT: // 1:i32 => (MOV1:i32)<br class="">
+// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MOV1));<br class="">
+// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*<wbr class="">dst*/);<br class="">
+// CHECK-NEXT: for (const auto *FromMI : {&MI0, })<br class="">
+// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())<br class="">
+// CHECK-NEXT: MIB.addMemOperand(MMO);<br class="">
+// CHECK-NEXT: I.eraseFromParent();<br class="">
+// CHECK-NEXT: MachineInstr &NewI = *MIB;<br class="">
+// CHECK-NEXT: constrainSelectedInstRegOperan<wbr class="">ds(NewI, TII, TRI, RBI);<br class="">
+// CHECK-NEXT: return true;<br class="">
+// CHECK-NEXT: }<br class="">
+// CHECK-NEXT: return false;<br class="">
+// CHECK-NEXT: }()) { return true; }<br class="">
+<br class="">
+def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>;<br class="">
+<br class="">
//===- Test a pattern with an MBB operand. ------------------------------<wbr class="">--===//<br class="">
<br class="">
// CHECK-LABEL: if ([&]() {<br class="">
<br class="">
Modified: llvm/trunk/utils/TableGen/<wbr class="">GlobalISelEmitter.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=303678&r1=303677&r2=303678&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/utils/<wbr class="">TableGen/GlobalISelEmitter.<wbr class="">cpp?rev=303678&r1=303677&r2=<wbr class="">303678&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/utils/TableGen/<wbr class="">GlobalISelEmitter.cpp (original)<br class="">
+++ llvm/trunk/utils/TableGen/<wbr class="">GlobalISelEmitter.cpp Tue May 23 14:33:16 2017<br class="">
@@ -135,6 +135,9 @@ static Error isTrivialOperatorNode(const<br class="">
std::string Explanation = "";<br class="">
std::string Separator = "";<br class="">
if (N->isLeaf()) {<br class="">
+ if (IntInit *Int = dyn_cast<IntInit>(N-><wbr class="">getLeafValue()))<br class="">
+ return Error::success();<br class="">
+<br class="">
Explanation = "Is a leaf";<br class="">
Separator = ", ";<br class="">
}<br class="">
@@ -272,6 +275,7 @@ public:<br class="">
OPM_ComplexPattern,<br class="">
OPM_Instruction,<br class="">
OPM_Int,<br class="">
+ OPM_LiteralInt,<br class="">
OPM_LLT,<br class="">
OPM_RegBank,<br class="">
OPM_MBB,<br class="">
@@ -406,13 +410,14 @@ public:<br class="">
}<br class="">
};<br class="">
<br class="">
-/// Generates code to check that an operand is a particular int.<br class="">
-class IntOperandMatcher : public OperandPredicateMatcher {<br class="">
+/// Generates code to check that an operand is a G_CONSTANT with a particular<br class="">
+/// int.<br class="">
+class ConstantIntOperandMatcher : public OperandPredicateMatcher {<br class="">
protected:<br class="">
int64_t Value;<br class="">
<br class="">
public:<br class="">
- IntOperandMatcher(int64_t Value)<br class="">
+ ConstantIntOperandMatcher(<wbr class="">int64_t Value)<br class="">
: OperandPredicateMatcher(OPM_<wbr class="">Int), Value(Value) {}<br class="">
<br class="">
static bool classof(const OperandPredicateMatcher *P) {<br class="">
@@ -425,6 +430,27 @@ public:<br class="">
}<br class="">
};<br class="">
<br class="">
+/// Generates code to check that an operand is a raw int (where MO.isImm() or<br class="">
+/// MO.isCImm() is true).<br class="">
+class LiteralIntOperandMatcher : public OperandPredicateMatcher {<br class="">
+protected:<br class="">
+ int64_t Value;<br class="">
+<br class="">
+public:<br class="">
+ LiteralIntOperandMatcher(<wbr class="">int64_t Value)<br class="">
+ : OperandPredicateMatcher(OPM_<wbr class="">LiteralInt), Value(Value) {}<br class="">
+<br class="">
+ static bool classof(const OperandPredicateMatcher *P) {<br class="">
+ return P->getKind() == OPM_LiteralInt;<br class="">
+ }<br class="">
+<br class="">
+ void emitCxxPredicateExpr(raw_<wbr class="">ostream &OS, RuleMatcher &Rule,<br class="">
+ StringRef OperandExpr) const override {<br class="">
+ OS << OperandExpr << ".isCImm() && " << OperandExpr<br class="">
+ << ".getCImm()->equalsInt(" << Value << ")";<br class="">
+ }<br class="">
+};<br class="">
+<br class="">
/// Generates code to check that a set of predicates match for a particular<br class="">
/// operand.<br class="">
class OperandMatcher : public PredicateListMatcher<<wbr class="">OperandPredicateMatcher> {<br class="">
@@ -1236,7 +1262,7 @@ private:<br class="">
createAndImportSelDAGMatcher(<wbr class="">InstructionMatcher &InsnMatcher,<br class="">
const TreePatternNode *Src) const;<br class="">
Error importChildMatcher(<wbr class="">InstructionMatcher &InsnMatcher,<br class="">
- TreePatternNode *SrcChild, unsigned OpIdx,<br class="">
+ const TreePatternNode *SrcChild, unsigned OpIdx,<br class="">
unsigned &TempOpIdx) const;<br class="">
Expected<BuildMIAction &> createAndImportInstructionRend<wbr class="">erer(<br class="">
RuleMatcher &M, const TreePatternNode *Dst,<br class="">
@@ -1299,14 +1325,23 @@ Expected<InstructionMatcher &> GlobalISe<br class="">
if (Src->getExtTypes().size() > 1)<br class="">
return failedImport("Src pattern has multiple results");<br class="">
<br class="">
- auto SrcGIOrNull = findNodeEquiv(Src-><wbr class="">getOperator());<br class="">
- if (!SrcGIOrNull)<br class="">
- return failedImport("Pattern operator lacks an equivalent Instruction" +<br class="">
- explainOperator(Src-><wbr class="">getOperator()));<br class="">
- auto &SrcGI = *SrcGIOrNull;<br class="">
+ if (Src->isLeaf()) {<br class="">
+ Init *SrcInit = Src->getLeafValue();<br class="">
+ if (IntInit *SrcIntInit = dyn_cast<IntInit>(SrcInit)) {<br class="">
+ InsnMatcher.addPredicate<<wbr class="">InstructionOpcodeMatcher>(<br class="">
+ &Target.getInstruction(RK.<wbr class="">getDef("G_CONSTANT")));<br class="">
+ } else<br class="">
+ return failedImport("Unable to deduce gMIR opcode to handle Src (which is a leaf)");<br class="">
+ } else {<br class="">
+ auto SrcGIOrNull = findNodeEquiv(Src-><wbr class="">getOperator());<br class="">
+ if (!SrcGIOrNull)<br class="">
+ return failedImport("Pattern operator lacks an equivalent Instruction" +<br class="">
+ explainOperator(Src-><wbr class="">getOperator()));<br class="">
+ auto &SrcGI = *SrcGIOrNull;<br class="">
<br class="">
- // The operators look good: match the opcode and mutate it to the new one.<br class="">
- InsnMatcher.addPredicate<<wbr class="">InstructionOpcodeMatcher>(&<wbr class="">SrcGI);<br class="">
+ // The operators look good: match the opcode<br class="">
+ InsnMatcher.addPredicate<<wbr class="">InstructionOpcodeMatcher>(&<wbr class="">SrcGI);<br class="">
+ }<br class="">
<br class="">
unsigned OpIdx = 0;<br class="">
unsigned TempOpIdx = 0;<br class="">
@@ -1323,18 +1358,27 @@ Expected<InstructionMatcher &> GlobalISe<br class="">
OM.addPredicate<<wbr class="">LLTOperandMatcher>(*<wbr class="">OpTyOrNone);<br class="">
}<br class="">
<br class="">
- // Match the used operands (i.e. the children of the operator).<br class="">
- for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) {<br class="">
- if (auto Error = importChildMatcher(<wbr class="">InsnMatcher, Src->getChild(i), OpIdx++,<br class="">
- TempOpIdx))<br class="">
- return std::move(Error);<br class="">
+ if (Src->isLeaf()) {<br class="">
+ Init *SrcInit = Src->getLeafValue();<br class="">
+ if (IntInit *SrcIntInit = dyn_cast<IntInit>(SrcInit)) {<br class="">
+ OperandMatcher &OM = InsnMatcher.addOperand(OpIdx++<wbr class="">, "", TempOpIdx);<br class="">
+ OM.addPredicate<<wbr class="">LiteralIntOperandMatcher>(<wbr class="">SrcIntInit->getValue());<br class="">
+ } else<br class="">
+ return failedImport("Unable to deduce gMIR opcode to handle Src (which is a leaf)");<br class="">
+ } else {<br class="">
+ // Match the used operands (i.e. the children of the operator).<br class="">
+ for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) {<br class="">
+ if (auto Error = importChildMatcher(<wbr class="">InsnMatcher, Src->getChild(i),<br class="">
+ OpIdx++, TempOpIdx))<br class="">
+ return std::move(Error);<br class="">
+ }<br class="">
}<br class="">
<br class="">
return InsnMatcher;<br class="">
}<br class="">
<br class="">
Error GlobalISelEmitter::<wbr class="">importChildMatcher(<wbr class="">InstructionMatcher &InsnMatcher,<br class="">
- TreePatternNode *SrcChild,<br class="">
+ const TreePatternNode *SrcChild,<br class="">
unsigned OpIdx,<br class="">
unsigned &TempOpIdx) const {<br class="">
OperandMatcher &OM =<br class="">
@@ -1379,7 +1423,7 @@ Error GlobalISelEmitter::<wbr class="">importChildMatc<br class="">
<br class="">
// Check for constant immediates.<br class="">
if (auto *ChildInt = dyn_cast<IntInit>(SrcChild-><wbr class="">getLeafValue())) {<br class="">
- OM.addPredicate<<wbr class="">IntOperandMatcher>(ChildInt-><wbr class="">getValue());<br class="">
+ OM.addPredicate<<wbr class="">ConstantIntOperandMatcher>(<wbr class="">ChildInt->getValue());<br class="">
return Error::success();<br class="">
}<br class="">
<br class="">
@@ -1605,6 +1649,9 @@ Expected<RuleMatcher> GlobalISelEmitter:<br class="">
return failedImport("Src pattern root isn't a trivial operator (" +<br class="">
toString(std::move(Err)) + ")");<br class="">
<br class="">
+ if (Dst->isLeaf())<br class="">
+ return failedImport("Dst pattern root isn't a known leaf");<br class="">
+<br class="">
// Start with the defined operands (i.e., the results of the root operator).<br class="">
Record *DstOp = Dst->getOperator();<br class="">
if (!DstOp->isSubClassOf("<wbr class="">Instruction"))<br class="">
<br class="">
<br class="">
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