<div dir="ltr">You could change the first one to use assert(llvm::all_of(...)), if you like.</div><br><div class="gmail_quote"><div dir="ltr">On Mon, May 15, 2017 at 9:14 PM NAKAMURA Takumi via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: chapuni<br>
Date: Mon May 15 23:01:23 2017<br>
New Revision: 303137<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=303137&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=303137&view=rev</a><br>
Log:<br>
AMDGPUCodeGen: Fix warnings in r303111. [-Wunused-variable]<br>
<br>
Modified:<br>
    llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp<br>
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp?rev=303137&r1=303136&r2=303137&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp?rev=303137&r1=303136&r2=303137&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp Mon May 15 23:01:23 2017<br>
@@ -136,9 +136,11 @@ void PHILinearize::phiInfoElementAddSour<br>
   // sources, because we cannot have different registers with<br>
   // identical predecessors, but we can have the same register for<br>
   // multiple predecessors.<br>
+#if !defined(NDEBUG)<br>
   for (auto SI : phiInfoElementGetSources(Info)) {<br>
     assert((SI.second != SourceMBB || SourceReg == SI.first));<br>
   }<br>
+#endif<br>
<br>
   phiInfoElementGetSources(Info).insert(PHISourceT(SourceReg, SourceMBB));<br>
 }<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=303137&r1=303136&r2=303137&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=303137&r1=303136&r2=303137&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Mon May 15 23:01:23 2017<br>
@@ -564,8 +564,8 @@ void SIInstrInfo::insertVectorSelect(Mac<br>
                                      unsigned TrueReg,<br>
                                      unsigned FalseReg) const {<br>
   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();<br>
-  const TargetRegisterClass *RegClass = MRI.getRegClass(DstReg);<br>
-  assert(RegClass == &AMDGPU::VGPR_32RegClass && "Not a VGPR32 reg");<br>
+  assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&<br>
+         "Not a VGPR32 reg");<br>
<br>
   if (Cond.size() == 1) {<br>
     BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)<br>
<br>
<br>
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</blockquote></div>