<div dir="ltr">Is it not possible to use the llvm iterator_facade helper to avoid implementing an iterator from scratch? (this would provide != if you implement ==, i++ if you implement ++i, and sometimes some other operations - maybe not many for this particular case, I'm not sure)</div><br><div class="gmail_quote"><div dir="ltr">On Tue, May 16, 2017 at 6:21 PM Francis Visoiu Mistrih via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: thegameg<br>
Date: Tue May 16 20:07:53 2017<br>
New Revision: 303227<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=303227&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=303227&view=rev</a><br>
Log:<br>
BitVector: add iterators for set bits<br>
<br>
Differential revision: <a href="https://reviews.llvm.org/D32060" rel="noreferrer" target="_blank">https://reviews.llvm.org/D32060</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/ADT/BitVector.h<br>
llvm/trunk/include/llvm/ADT/SmallBitVector.h<br>
llvm/trunk/lib/Analysis/DependenceAnalysis.cpp<br>
llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp<br>
llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp<br>
llvm/trunk/lib/CodeGen/MachineVerifier.cpp<br>
llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp<br>
llvm/trunk/lib/CodeGen/SpillPlacement.cpp<br>
llvm/trunk/lib/CodeGen/StackColoring.cpp<br>
llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br>
llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp<br>
llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp<br>
llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp<br>
llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp<br>
llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp<br>
llvm/trunk/lib/Transforms/Scalar/NewGVN.cpp<br>
llvm/trunk/unittests/ADT/BitVectorTest.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/ADT/BitVector.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/BitVector.h?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/BitVector.h?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/ADT/BitVector.h (original)<br>
+++ llvm/trunk/include/llvm/ADT/BitVector.h Tue May 16 20:07:53 2017<br>
@@ -15,6 +15,7 @@<br>
#define LLVM_ADT_BITVECTOR_H<br>
<br>
#include "llvm/ADT/ArrayRef.h"<br>
+#include "llvm/ADT/iterator_range.h"<br>
#include "llvm/Support/MathExtras.h"<br>
#include <algorithm><br>
#include <cassert><br>
@@ -26,6 +27,50 @@<br>
<br>
namespace llvm {<br>
<br>
+/// ForwardIterator for the bits that are set.<br>
+/// Iterators get invalidated when resize / reserve is called.<br>
+template <typename BitVectorT> class const_set_bits_iterator_impl {<br>
+ const BitVectorT &Parent;<br>
+ int Current = 0;<br>
+<br>
+ void advance() {<br>
+ assert(Current != -1 && "Trying to advance past end.");<br>
+ Current = Parent.find_next(Current);<br>
+ }<br>
+<br>
+public:<br>
+ const_set_bits_iterator_impl(const BitVectorT &Parent, int Current)<br>
+ : Parent(Parent), Current(Current) {}<br>
+ explicit const_set_bits_iterator_impl(const BitVectorT &Parent)<br>
+ : const_set_bits_iterator_impl(Parent, Parent.find_first()) {}<br>
+ const_set_bits_iterator_impl(const const_set_bits_iterator_impl &) = default;<br>
+<br>
+ const_set_bits_iterator_impl operator++(int) {<br>
+ auto Prev = *this;<br>
+ advance();<br>
+ return Prev;<br>
+ }<br>
+<br>
+ const_set_bits_iterator_impl &operator++() {<br>
+ advance();<br>
+ return *this;<br>
+ }<br>
+<br>
+ unsigned operator*() const { return Current; }<br>
+<br>
+ bool operator==(const const_set_bits_iterator_impl &Other) const {<br>
+ assert(&Parent == &Other.Parent &&<br>
+ "Comparing iterators from different BitVectors");<br>
+ return Current == Other.Current;<br>
+ }<br>
+<br>
+ bool operator!=(const const_set_bits_iterator_impl &Other) const {<br>
+ assert(&Parent == &Other.Parent &&<br>
+ "Comparing iterators from different BitVectors");<br>
+ return Current != Other.Current;<br>
+ }<br>
+};<br>
+<br>
class BitVector {<br>
typedef unsigned long BitWord;<br>
<br>
@@ -73,6 +118,18 @@ public:<br>
}<br>
};<br>
<br>
+ typedef const_set_bits_iterator_impl<BitVector> const_set_bits_iterator;<br>
+ typedef const_set_bits_iterator set_iterator;<br>
+<br>
+ const_set_bits_iterator set_bits_begin() const {<br>
+ return const_set_bits_iterator(*this);<br>
+ }<br>
+ const_set_bits_iterator set_bits_end() const {<br>
+ return const_set_bits_iterator(*this, -1);<br>
+ }<br>
+ iterator_range<const_set_bits_iterator> set_bits() const {<br>
+ return make_range(set_bits_begin(), set_bits_end());<br>
+ }<br>
<br>
/// BitVector default ctor - Creates an empty bitvector.<br>
BitVector() : Size(0) {}<br>
<br>
Modified: llvm/trunk/include/llvm/ADT/SmallBitVector.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallBitVector.h?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallBitVector.h?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/ADT/SmallBitVector.h (original)<br>
+++ llvm/trunk/include/llvm/ADT/SmallBitVector.h Tue May 16 20:07:53 2017<br>
@@ -134,6 +134,19 @@ private:<br>
}<br>
<br>
public:<br>
+ typedef const_set_bits_iterator_impl<SmallBitVector> const_set_bits_iterator;<br>
+ typedef const_set_bits_iterator set_iterator;<br>
+<br>
+ const_set_bits_iterator set_bits_begin() const {<br>
+ return const_set_bits_iterator(*this);<br>
+ }<br>
+ const_set_bits_iterator set_bits_end() const {<br>
+ return const_set_bits_iterator(*this, -1);<br>
+ }<br>
+ iterator_range<const_set_bits_iterator> set_bits() const {<br>
+ return make_range(set_bits_begin(), set_bits_end());<br>
+ }<br>
+<br>
/// Creates an empty bitvector.<br>
SmallBitVector() : X(1) {}<br>
<br>
<br>
Modified: llvm/trunk/lib/Analysis/DependenceAnalysis.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DependenceAnalysis.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DependenceAnalysis.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Analysis/DependenceAnalysis.cpp (original)<br>
+++ llvm/trunk/lib/Analysis/DependenceAnalysis.cpp Tue May 16 20:07:53 2017<br>
@@ -2984,7 +2984,7 @@ bool DependenceInfo::propagate(const SCE<br>
SmallVectorImpl<Constraint> &Constraints,<br>
bool &Consistent) {<br>
bool Result = false;<br>
- for (int LI = Loops.find_first(); LI >= 0; LI = Loops.find_next(LI)) {<br>
+ for (unsigned LI : Loops.set_bits()) {<br>
DEBUG(dbgs() << "\t Constraint[" << LI << "] is");<br>
DEBUG(Constraints[LI].dump(dbgs()));<br>
if (Constraints[LI].isDistance())<br>
@@ -3266,7 +3266,7 @@ bool DependenceInfo::tryDelinearize(Inst<br>
// For debugging purposes, dump a small bit vector to dbgs().<br>
static void dumpSmallBitVector(SmallBitVector &BV) {<br>
dbgs() << "{";<br>
- for (int VI = BV.find_first(); VI >= 0; VI = BV.find_next(VI)) {<br>
+ for (unsigned VI : BV.set_bits()) {<br>
dbgs() << VI;<br>
if (BV.find_next(VI) >= 0)<br>
dbgs() << ' ';<br>
@@ -3506,7 +3506,7 @@ DependenceInfo::depends(Instruction *Src<br>
NewConstraint.setAny(SE);<br>
<br>
// test separable subscripts<br>
- for (int SI = Separable.find_first(); SI >= 0; SI = Separable.find_next(SI)) {<br>
+ for (unsigned SI : Separable.set_bits()) {<br>
DEBUG(dbgs() << "testing subscript " << SI);<br>
switch (Pair[SI].Classification) {<br>
case Subscript::ZIV:<br>
@@ -3545,14 +3545,14 @@ DependenceInfo::depends(Instruction *Src<br>
SmallVector<Constraint, 4> Constraints(MaxLevels + 1);<br>
for (unsigned II = 0; II <= MaxLevels; ++II)<br>
Constraints[II].setAny(SE);<br>
- for (int SI = Coupled.find_first(); SI >= 0; SI = Coupled.find_next(SI)) {<br>
+ for (unsigned SI : Coupled.set_bits()) {<br>
DEBUG(dbgs() << "testing subscript group " << SI << " { ");<br>
SmallBitVector Group(Pair[SI].Group);<br>
SmallBitVector Sivs(Pairs);<br>
SmallBitVector Mivs(Pairs);<br>
SmallBitVector ConstrainedLevels(MaxLevels + 1);<br>
SmallVector<Subscript *, 4> PairsInGroup;<br>
- for (int SJ = Group.find_first(); SJ >= 0; SJ = Group.find_next(SJ)) {<br>
+ for (unsigned SJ : Group.set_bits()) {<br>
DEBUG(dbgs() << SJ << " ");<br>
if (Pair[SJ].Classification == Subscript::SIV)<br>
Sivs.set(SJ);<br>
@@ -3564,7 +3564,7 @@ DependenceInfo::depends(Instruction *Src<br>
DEBUG(dbgs() << "}\n");<br>
while (Sivs.any()) {<br>
bool Changed = false;<br>
- for (int SJ = Sivs.find_first(); SJ >= 0; SJ = Sivs.find_next(SJ)) {<br>
+ for (unsigned SJ : Sivs.set_bits()) {<br>
DEBUG(dbgs() << "testing subscript " << SJ << ", SIV\n");<br>
// SJ is an SIV subscript that's part of the current coupled group<br>
unsigned Level;<br>
@@ -3588,7 +3588,7 @@ DependenceInfo::depends(Instruction *Src<br>
DEBUG(dbgs() << " propagating\n");<br>
DEBUG(dbgs() << "\tMivs = ");<br>
DEBUG(dumpSmallBitVector(Mivs));<br>
- for (int SJ = Mivs.find_first(); SJ >= 0; SJ = Mivs.find_next(SJ)) {<br>
+ for (unsigned SJ : Mivs.set_bits()) {<br>
// SJ is an MIV subscript that's part of the current coupled group<br>
DEBUG(dbgs() << "\tSJ = " << SJ << "\n");<br>
if (propagate(Pair[SJ].Src, Pair[SJ].Dst, Pair[SJ].Loops,<br>
@@ -3622,7 +3622,7 @@ DependenceInfo::depends(Instruction *Src<br>
}<br>
<br>
// test & propagate remaining RDIVs<br>
- for (int SJ = Mivs.find_first(); SJ >= 0; SJ = Mivs.find_next(SJ)) {<br>
+ for (unsigned SJ : Mivs.set_bits()) {<br>
if (Pair[SJ].Classification == Subscript::RDIV) {<br>
DEBUG(dbgs() << "RDIV test\n");<br>
if (testRDIV(Pair[SJ].Src, Pair[SJ].Dst, Result))<br>
@@ -3635,7 +3635,7 @@ DependenceInfo::depends(Instruction *Src<br>
// test remaining MIVs<br>
// This code is temporary.<br>
// Better to somehow test all remaining subscripts simultaneously.<br>
- for (int SJ = Mivs.find_first(); SJ >= 0; SJ = Mivs.find_next(SJ)) {<br>
+ for (unsigned SJ : Mivs.set_bits()) {<br>
if (Pair[SJ].Classification == Subscript::MIV) {<br>
DEBUG(dbgs() << "MIV test\n");<br>
if (testMIV(Pair[SJ].Src, Pair[SJ].Dst, Pair[SJ].Loops, Result))<br>
@@ -3647,9 +3647,8 @@ DependenceInfo::depends(Instruction *Src<br>
<br>
// update Result.DV from constraint vector<br>
DEBUG(dbgs() << " updating\n");<br>
- for (int SJ = ConstrainedLevels.find_first(); SJ >= 0;<br>
- SJ = ConstrainedLevels.find_next(SJ)) {<br>
- if (SJ > (int)CommonLevels)<br>
+ for (unsigned SJ : ConstrainedLevels.set_bits()) {<br>
+ if (SJ > CommonLevels)<br>
break;<br>
updateDirection(Result.DV[SJ - 1], Constraints[SJ]);<br>
if (Result.DV[SJ - 1].Direction == Dependence::DVEntry::NONE)<br>
@@ -3859,7 +3858,7 @@ const SCEV *DependenceInfo::getSplitIter<br>
NewConstraint.setAny(SE);<br>
<br>
// test separable subscripts<br>
- for (int SI = Separable.find_first(); SI >= 0; SI = Separable.find_next(SI)) {<br>
+ for (unsigned SI : Separable.set_bits()) {<br>
switch (Pair[SI].Classification) {<br>
case Subscript::SIV: {<br>
unsigned Level;<br>
@@ -3886,12 +3885,12 @@ const SCEV *DependenceInfo::getSplitIter<br>
SmallVector<Constraint, 4> Constraints(MaxLevels + 1);<br>
for (unsigned II = 0; II <= MaxLevels; ++II)<br>
Constraints[II].setAny(SE);<br>
- for (int SI = Coupled.find_first(); SI >= 0; SI = Coupled.find_next(SI)) {<br>
+ for (unsigned SI : Coupled.set_bits()) {<br>
SmallBitVector Group(Pair[SI].Group);<br>
SmallBitVector Sivs(Pairs);<br>
SmallBitVector Mivs(Pairs);<br>
SmallBitVector ConstrainedLevels(MaxLevels + 1);<br>
- for (int SJ = Group.find_first(); SJ >= 0; SJ = Group.find_next(SJ)) {<br>
+ for (unsigned SJ : Group.set_bits()) {<br>
if (Pair[SJ].Classification == Subscript::SIV)<br>
Sivs.set(SJ);<br>
else<br>
@@ -3899,7 +3898,7 @@ const SCEV *DependenceInfo::getSplitIter<br>
}<br>
while (Sivs.any()) {<br>
bool Changed = false;<br>
- for (int SJ = Sivs.find_first(); SJ >= 0; SJ = Sivs.find_next(SJ)) {<br>
+ for (unsigned SJ : Sivs.set_bits()) {<br>
// SJ is an SIV subscript that's part of the current coupled group<br>
unsigned Level;<br>
const SCEV *SplitIter = nullptr;<br>
@@ -3914,7 +3913,7 @@ const SCEV *DependenceInfo::getSplitIter<br>
}<br>
if (Changed) {<br>
// propagate, possibly creating new SIVs and ZIVs<br>
- for (int SJ = Mivs.find_first(); SJ >= 0; SJ = Mivs.find_next(SJ)) {<br>
+ for (unsigned SJ : Mivs.set_bits()) {<br>
// SJ is an MIV subscript that's part of the current coupled group<br>
if (propagate(Pair[SJ].Src, Pair[SJ].Dst,<br>
Pair[SJ].Loops, Constraints, Result.Consistent)) {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Tue May 16 20:07:53 2017<br>
@@ -128,8 +128,7 @@ AggressiveAntiDepBreaker::AggressiveAnti<br>
}<br>
<br>
DEBUG(dbgs() << "AntiDep Critical-Path Registers:");<br>
- DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;<br>
- r = CriticalPathSet.find_next(r))<br>
+ DEBUG(for (unsigned r : CriticalPathSet.set_bits())<br>
dbgs() << " " << TRI->getName(r));<br>
DEBUG(dbgs() << '\n');<br>
}<br>
@@ -571,7 +570,7 @@ bool AggressiveAntiDepBreaker::FindSuita<br>
<br>
DEBUG({<br>
dbgs() << " ::";<br>
- for (int r = BV.find_first(); r != -1; r = BV.find_next(r))<br>
+ for (unsigned r : BV.set_bits())<br>
dbgs() << " " << TRI->getName(r);<br>
dbgs() << "\n";<br>
});<br>
<br>
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp Tue May 16 20:07:53 2017<br>
@@ -209,8 +209,7 @@ void llvm::calculateDbgValueHistory(cons<br>
} else if (MO.isRegMask()) {<br>
// If this is a register mask operand, clobber all debug values in<br>
// non-CSRs.<br>
- for (int I = ChangingRegs.find_first(); I != -1;<br>
- I = ChangingRegs.find_next(I)) {<br>
+ for (unsigned I : ChangingRegs.set_bits()) {<br>
// Don't consider SP to be clobbered by register masks.<br>
if (unsigned(I) != SP && TRI->isPhysicalRegister(I) &&<br>
MO.clobbersPhysReg(I)) {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue May 16 20:07:53 2017<br>
@@ -760,7 +760,7 @@ MachineVerifier::visitMachineBasicBlockB<br>
<br>
const MachineFrameInfo &MFI = MF->getFrameInfo();<br>
BitVector PR = MFI.getPristineRegs(*MF);<br>
- for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {<br>
+ for (unsigned I : PR.set_bits()) {<br>
for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);<br>
SubRegs.isValid(); ++SubRegs)<br>
regsLive.insert(*SubRegs);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue May 16 20:07:53 2017<br>
@@ -285,8 +285,7 @@ class RAGreedy : public MachineFunctionP<br>
// Set B[i] = C for every live bundle where B[i] was NoCand.<br>
unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {<br>
unsigned Count = 0;<br>
- for (int i = LiveBundles.find_first(); i >= 0;<br>
- i = LiveBundles.find_next(i))<br>
+ for (unsigned i : LiveBundles.set_bits())<br>
if (B[i] == NoCand) {<br>
B[i] = C;<br>
Count++;<br>
@@ -1162,9 +1161,8 @@ bool RAGreedy::calcCompactRegion(GlobalS<br>
}<br>
<br>
DEBUG({<br>
- for (int i = Cand.LiveBundles.find_first(); i>=0;<br>
- i = Cand.LiveBundles.find_next(i))<br>
- dbgs() << " EB#" << i;<br>
+ for (int i : Cand.LiveBundles.set_bits())<br>
+ dbgs() << " EB#" << i;<br>
dbgs() << ".\n";<br>
});<br>
return true;<br>
@@ -1482,8 +1480,7 @@ unsigned RAGreedy::calculateRegionSplitC<br>
DEBUG({<br>
dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost)<br>
<< " with bundles";<br>
- for (int i = Cand.LiveBundles.find_first(); i>=0;<br>
- i = Cand.LiveBundles.find_next(i))<br>
+ for (int i : Cand.LiveBundles.set_bits())<br>
dbgs() << " EB#" << i;<br>
dbgs() << ".\n";<br>
});<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SpillPlacement.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SpillPlacement.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SpillPlacement.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SpillPlacement.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SpillPlacement.cpp Tue May 16 20:07:53 2017<br>
@@ -310,7 +310,7 @@ void SpillPlacement::addLinks(ArrayRef<u<br>
<br>
bool SpillPlacement::scanActiveBundles() {<br>
RecentPositive.clear();<br>
- for (int n = ActiveNodes->find_first(); n>=0; n = ActiveNodes->find_next(n)) {<br>
+ for (unsigned n : ActiveNodes->set_bits()) {<br>
update(n);<br>
// A node that must spill, or a node without any links is not going to<br>
// change its value ever again, so exclude it from iterations.<br>
@@ -365,7 +365,7 @@ SpillPlacement::finish() {<br>
<br>
// Write preferences back to ActiveNodes.<br>
bool Perfect = true;<br>
- for (int n = ActiveNodes->find_first(); n>=0; n = ActiveNodes->find_next(n))<br>
+ for (unsigned n : ActiveNodes->set_bits())<br>
if (!nodes[n].preferReg()) {<br>
ActiveNodes->reset(n);<br>
Perfect = false;<br>
<br>
Modified: llvm/trunk/lib/CodeGen/StackColoring.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackColoring.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackColoring.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/StackColoring.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/StackColoring.cpp Tue May 16 20:07:53 2017<br>
@@ -703,12 +703,10 @@ void StackColoring::calculateLiveInterva<br>
<br>
// Create the interval of the blocks that we previously found to be 'alive'.<br>
BlockLifetimeInfo &MBBLiveness = BlockLiveness[&MBB];<br>
- for (int pos = MBBLiveness.LiveIn.find_first(); pos != -1;<br>
- pos = MBBLiveness.LiveIn.find_next(pos)) {<br>
+ for (unsigned pos : MBBLiveness.LiveIn.set_bits()) {<br>
Starts[pos] = Indexes->getMBBStartIdx(&MBB);<br>
}<br>
- for (int pos = MBBLiveness.LiveOut.find_first(); pos != -1;<br>
- pos = MBBLiveness.LiveOut.find_next(pos)) {<br>
+ for (unsigned pos : MBBLiveness.LiveOut.set_bits()) {<br>
Finishes[pos] = Indexes->getMBBEndIdx(&MBB);<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Tue May 16 20:07:53 2017<br>
@@ -1312,7 +1312,7 @@ TargetLoweringBase::findRepresentativeCl<br>
<br>
// Find the first legal register class with the largest spill size.<br>
const TargetRegisterClass *BestRC = RC;<br>
- for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {<br>
+ for (unsigned i : SuperRegRC.set_bits()) {<br>
const TargetRegisterClass *SuperRC = TRI->getRegClass(i);<br>
// We want the largest possible spill size.<br>
if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))<br>
<br>
Modified: llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp Tue May 16 20:07:53 2017<br>
@@ -50,8 +50,7 @@ bool TargetRegisterInfo::checkAllSuperRe<br>
ArrayRef<MCPhysReg> Exceptions) const {<br>
// Check that all super registers of reserved regs are reserved as well.<br>
BitVector Checked(getNumRegs());<br>
- for (int Reg = RegisterSet.find_first(); Reg>=0;<br>
- Reg = RegisterSet.find_next(Reg)) {<br>
+ for (unsigned Reg : RegisterSet.set_bits()) {<br>
if (Checked[Reg])<br>
continue;<br>
for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp Tue May 16 20:07:53 2017<br>
@@ -1158,8 +1158,7 @@ void AArch64FrameLowering::determineCall<br>
}<br>
<br>
DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:";<br>
- for (int Reg = SavedRegs.find_first(); Reg != -1;<br>
- Reg = SavedRegs.find_next(Reg))<br>
+ for (unsigned Reg : SavedRegs.set_bits())<br>
dbgs() << ' ' << PrintReg(Reg, RegInfo);<br>
dbgs() << "\n";);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Tue May 16 20:07:53 2017<br>
@@ -571,8 +571,7 @@ bool Thumb1FrameLowering::emitPopSpecial<br>
GPRsNoLRSP.reset(ARM::LR);<br>
GPRsNoLRSP.reset(ARM::SP);<br>
GPRsNoLRSP.reset(ARM::PC);<br>
- for (int Register = GPRsNoLRSP.find_first(); Register != -1;<br>
- Register = GPRsNoLRSP.find_next(Register)) {<br>
+ for (unsigned Register : GPRsNoLRSP.set_bits()) {<br>
if (!UsedRegs.contains(Register)) {<br>
// Remember the first pop-friendly register and exit.<br>
if (PopFriendly.test(Register)) {<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Tue May 16 20:07:53 2017<br>
@@ -386,7 +386,7 @@ void RegDefsUses::setCallerSaved(const M<br>
void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) {<br>
BitVector AllocSet = TRI.getAllocatableSet(MF);<br>
<br>
- for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R))<br>
+ for (unsigned R : AllocSet.set_bits())<br>
for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI)<br>
AllocSet.set(*AI);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp (original)<br>
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp Tue May 16 20:07:53 2017<br>
@@ -140,8 +140,7 @@ bool WebAssemblyRegColoring::runOnMachin<br>
<br>
// Check if it's possible to reuse any of the used colors.<br>
if (!MRI->isLiveIn(Old))<br>
- for (int C(UsedColors.find_first()); C != -1;<br>
- C = UsedColors.find_next(C)) {<br>
+ for (unsigned C : UsedColors.set_bits()) {<br>
if (MRI->getRegClass(SortedIntervals[C]->reg) != RC)<br>
continue;<br>
for (LiveInterval *OtherLI : Assignments[C])<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue May 16 20:07:53 2017<br>
@@ -3902,8 +3902,7 @@ void LSRInstance::GenerateCrossUseConsta<br>
<br>
// Compute the difference between the two.<br>
int64_t Imm = (uint64_t)JImm - M->first;<br>
- for (int LUIdx = UsedByIndices.find_first(); LUIdx != -1;<br>
- LUIdx = UsedByIndices.find_next(LUIdx))<br>
+ for (unsigned LUIdx : UsedByIndices.set_bits())<br>
// Make a memo of this use, offset, and register tuple.<br>
if (UniqueItems.insert(std::make_pair(LUIdx, Imm)).second)<br>
WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg));<br>
<br>
Modified: llvm/trunk/lib/Transforms/Scalar/NewGVN.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/NewGVN.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/NewGVN.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Transforms/Scalar/NewGVN.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Scalar/NewGVN.cpp Tue May 16 20:07:53 2017<br>
@@ -2678,8 +2678,7 @@ void NewGVN::iterateTouchedInstructions(<br>
// TODO: As we hit a new block, we should push and pop equalities into a<br>
// table lookupOperandLeader can use, to catch things PredicateInfo<br>
// might miss, like edge-only equivalences.<br>
- for (int InstrNum = TouchedInstructions.find_first(); InstrNum != -1;<br>
- InstrNum = TouchedInstructions.find_next(InstrNum)) {<br>
+ for (unsigned InstrNum : TouchedInstructions.set_bits()) {<br>
<br>
// This instruction was found to be dead. We don't bother looking<br>
// at it again.<br>
<br>
Modified: llvm/trunk/unittests/ADT/BitVectorTest.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/BitVectorTest.cpp?rev=303227&r1=303226&r2=303227&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/BitVectorTest.cpp?rev=303227&r1=303226&r2=303227&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/unittests/ADT/BitVectorTest.cpp (original)<br>
+++ llvm/trunk/unittests/ADT/BitVectorTest.cpp Tue May 16 20:07:53 2017<br>
@@ -660,5 +660,34 @@ TYPED_TEST(BitVectorTest, EmptyVector) {<br>
testEmpty(E);<br>
}<br>
<br>
+TYPED_TEST(BitVectorTest, Iterators) {<br>
+ TypeParam Filled(10, true);<br>
+ EXPECT_NE(Filled.set_bits_begin(), Filled.set_bits_end());<br>
+ unsigned Counter = 0;<br>
+ for (unsigned Bit : Filled.set_bits())<br>
+ EXPECT_EQ(Bit, Counter++);<br>
+<br>
+ TypeParam Empty;<br>
+ EXPECT_EQ(Empty.set_bits_begin(), Empty.set_bits_end());<br>
+ for (unsigned Bit : Empty.set_bits()) {<br>
+ (void)Bit;<br>
+ EXPECT_TRUE(false);<br>
+ }<br>
+<br>
+ TypeParam ToFill(100, false);<br>
+ ToFill.set(0);<br>
+ EXPECT_NE(ToFill.set_bits_begin(), ToFill.set_bits_end());<br>
+ EXPECT_EQ(++ToFill.set_bits_begin(), ToFill.set_bits_end());<br>
+ EXPECT_EQ(*ToFill.set_bits_begin(), 0U);<br>
+ ToFill.reset(0);<br>
+ EXPECT_EQ(ToFill.set_bits_begin(), ToFill.set_bits_end());<br>
+<br>
+ const unsigned List[] = {1, 10, 25, 99};<br>
+ for (unsigned Num : List)<br>
+ ToFill.set(Num);<br>
+ unsigned i = 0;<br>
+ for (unsigned Bit : ToFill.set_bits())<br>
+ EXPECT_EQ(List[i++], Bit);<br>
+}<br>
}<br>
#endif<br>
<br>
<br>
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</blockquote></div>