<div dir="ltr"><div>We probably should revert this and investigate compile time regression.<br></div><div><br></div>I noticed that starting from <a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/1360">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/1360</a> "build clang/msan" sometimes hangs.<br><div><br></div><div>I bisected on my workstation using:</div>BUILDBOT_CLOBBER=1 BUILDBOT_REVISION=303341 llvm/projects/zorg/zorg/buildbot/builders/sanitizers/buildbot_bootstrap.sh<div><br></div><div>I noticed consistent regression on r303341. Time of "build clang/msan" increased from 8.5 min to 20 min (on 24 cores). r303341 spends a lot of time compiling just 3 files. Also I was able to reproduce this difference on ToT reverting r303341.</div><div><br></div><div>One of the slow commands of "build clang/msan" is below.<br></div><div>ToT takes 13.5 min to compile it and about 1.5Gb of RAM.</div><div>"ToT without r303341 (reverted)" takes just 1.2 min to compile and about 0.7Gb of RAM.</div><div><br></div><div>Also after removing -fsanitize=memory difference is about 1.4 min vs 0.3 min.</div><div><br></div><div>/tmp/bot/llvm_build0/bin/clang-5.0 -cc1 -triple x86_64-unknown-linux-gnu -emit-obj -disable-free -main-file-name AArch64InstructionSelector.cpp -mrelocation-model pic -pic-level 2 -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -momit-leaf-frame-pointer -dwarf-column-info -debug-info-kind=line-tables-only -dwarf-version=4 -debugger-tuning=gdb -ffunction-sections -fdata-sections -coverage-notes-file /tmp/bot/llvm_build_msan/lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64InstructionSelector.cpp.gcno -nostdinc++ -resource-dir /tmp/bot/llvm_build0/lib/clang/5.0.0 -dependency-file lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64InstructionSelector.cpp.o.d -sys-header-deps -MT lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64InstructionSelector.cpp.o -isystem /tmp/bot/libcxx_build_msan/include -isystem /tmp/bot/libcxx_build_msan/include/c++/v1 -D GTEST_HAS_RTTI=0 -D LLVM_BUILD_GLOBAL_ISEL -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/AArch64 -I /tmp/bot/llvm/lib/Target/AArch64 -I include -I /tmp/bot/llvm/include -U NDEBUG -internal-isystem /usr/local/include -internal-isystem /tmp/bot/llvm_build0/lib/clang/5.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O3 -Werror=date-time -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -Wno-long-long -Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -pedantic -w -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /tmp/bot/llvm_build_msan -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fsanitize=memory -fsanitize-blacklist=/tmp/bot/llvm_build0/lib/clang/5.0.0/msan_blacklist.txt -fno-assume-sane-operator-new -fno-rtti -fobjc-runtime=gcc -fdiagnostics-show-option -fcolor-diagnostics -vectorize-loops -vectorize-slp -o lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64InstructionSelector.cpp.o -x c++ /tmp/bot/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp<br></div><div><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, May 18, 2017 at 3:33 AM, Daniel Sanders via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: dsanders<br>
Date: Thu May 18 05:33:36 2017<br>
New Revision: 303341<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=303341&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=303341&view=rev</a><br>
Log:<br>
Re-commit: [globalisel][tablegen] Import rules containing intrinsic_wo_chain.<br>
<br>
Summary:<br>
As of this patch, 1018 out of 3938 rules are currently imported.<br>
<br>
Depends on D32275<br>
<br>
Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar<br>
<br>
Reviewed By: qcolombet<br>
<br>
Subscribers: dberris, igorb, llvm-commits<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D32278" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D32278</a><br>
<br>
The previous commit failed on test-suite/Bitcode/simd_ops/<wbr>AArch64_halide_runtime.bc<br>
because isImmOperandEqual() assumed MO was a register operand and that's not<br>
always true.<br>
<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/<wbr>Target/GlobalISel/<wbr>SelectionDAGCompat.td<br>
llvm/trunk/lib/CodeGen/<wbr>GlobalISel/<wbr>InstructionSelector.cpp<br>
llvm/trunk/test/TableGen/<wbr>GlobalISelEmitter.td<br>
llvm/trunk/utils/TableGen/<wbr>GlobalISelEmitter.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>Target/GlobalISel/<wbr>SelectionDAGCompat.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td?rev=303341&r1=303340&r2=303341&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/Target/GlobalISel/<wbr>SelectionDAGCompat.td?rev=<wbr>303341&r1=303340&r2=303341&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>Target/GlobalISel/<wbr>SelectionDAGCompat.td (original)<br>
+++ llvm/trunk/include/llvm/<wbr>Target/GlobalISel/<wbr>SelectionDAGCompat.td Thu May 18 05:33:36 2017<br>
@@ -62,6 +62,7 @@ def : GINodeEquiv<G_FMUL, fmul>;<br>
def : GINodeEquiv<G_FDIV, fdiv>;<br>
def : GINodeEquiv<G_FREM, frem>;<br>
def : GINodeEquiv<G_FPOW, fpow>;<br>
+def : GINodeEquiv<G_INTRINSIC, intrinsic_wo_chain>;<br>
def : GINodeEquiv<G_BR, br>;<br>
<br>
// Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>GlobalISel/<wbr>InstructionSelector.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp?rev=303341&r1=303340&r2=303341&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/GlobalISel/<wbr>InstructionSelector.cpp?rev=<wbr>303341&r1=303340&r2=303341&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>GlobalISel/<wbr>InstructionSelector.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>GlobalISel/<wbr>InstructionSelector.cpp Thu May 18 05:33:36 2017<br>
@@ -73,7 +73,7 @@ bool InstructionSelector::<wbr>isOperandImmEq<br>
const MachineOperand &MO, int64_t Value,<br>
const MachineRegisterInfo &MRI) const {<br>
<br>
- if (MO.getReg())<br>
+ if (MO.isReg() && MO.getReg())<br>
if (auto VRegVal = getConstantVRegVal(MO.getReg()<wbr>, MRI))<br>
return *VRegVal == Value;<br>
return false;<br>
<br>
Modified: llvm/trunk/test/TableGen/<wbr>GlobalISelEmitter.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/GlobalISelEmitter.td?rev=303341&r1=303340&r2=303341&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>TableGen/GlobalISelEmitter.td?<wbr>rev=303341&r1=303340&r2=<wbr>303341&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/TableGen/<wbr>GlobalISelEmitter.td (original)<br>
+++ llvm/trunk/test/TableGen/<wbr>GlobalISelEmitter.td Thu May 18 05:33:36 2017<br>
@@ -7,6 +7,10 @@ include "llvm/Target/Target.td"<br>
def MyTargetISA : InstrInfo;<br>
def MyTarget : Target { let InstructionSet = MyTargetISA; }<br>
<br>
+let TargetPrefix = "mytarget" in {<br>
+def int_mytarget_nop : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;<br>
+}<br>
+<br>
def R0 : Register<"r0"> { let Namespace = "MyTarget"; }<br>
def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;<br>
def GPR32Op : RegisterOperand<GPR32>;<br>
@@ -127,6 +131,37 @@ def : Pat<(select GPR32:$src1, complex:$<br>
def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),<br>
[(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;<br>
<br>
+//===- Test a simple pattern with an intrinsic. ---------------------------===<wbr>//<br>
+//<br>
+<br>
+// CHECK-LABEL: if ([&]() {<br>
+// CHECK-NEXT: MachineInstr &MI0 = I;<br>
+// CHECK-NEXT: if (MI0.getNumOperands() < 3)<br>
+// CHECK-NEXT: return false;<br>
+// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_INTRINSIC) &&<br>
+// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0)<wbr>.getReg()) == (LLT::scalar(32))) &&<br>
+// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(<wbr>MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(<wbr>0).getReg(), MRI, TRI))))) &&<br>
+// CHECK-NEXT: ((/* Operand 1 */ (isOperandImmEqual(MI0.<wbr>getOperand(1), [[ID:[0-9]+]], MRI)))) &&<br>
+// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(2)<wbr>.getReg()) == (LLT::scalar(32))) &&<br>
+// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(<wbr>MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(<wbr>2).getReg(), MRI, TRI)))))) {<br>
+// CHECK-NEXT: // (intrinsic_wo_chain:i32 [[ID]]:iPTR, GPR32:i32:$src1) => (MOV:i32 GPR32:i32:$src1)<br>
+// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MOV));<br>
+// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*<wbr>dst*/);<br>
+// CHECK-NEXT: MIB.add(MI0.getOperand(2)/*<wbr>src1*/);<br>
+// CHECK-NEXT: for (const auto *FromMI : {&MI0, })<br>
+// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())<br>
+// CHECK-NEXT: MIB.addMemOperand(MMO);<br>
+// CHECK-NEXT: I.eraseFromParent();<br>
+// CHECK-NEXT: MachineInstr &NewI = *MIB;<br>
+// CHECK-NEXT: constrainSelectedInstRegOperan<wbr>ds(NewI, TII, TRI, RBI);<br>
+// CHECK-NEXT: return true;<br>
+// CHECK-NEXT: }<br>
+// CHECK-NEXT: return false;<br>
+// CHECK-NEXT: }()) { return true; }<br>
+<br>
+def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1),<br>
+ [(set GPR32:$dst, (int_mytarget_nop GPR32:$src1))]>;<br>
+<br>
//===- Test a nested instruction match. ------------------------------<wbr>-----===//<br>
<br>
// CHECK-LABEL: if ([&]() {<br>
<br>
Modified: llvm/trunk/utils/TableGen/<wbr>GlobalISelEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=303341&r1=303340&r2=303341&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/GlobalISelEmitter.<wbr>cpp?rev=303341&r1=303340&r2=<wbr>303341&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>GlobalISelEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>GlobalISelEmitter.cpp Thu May 18 05:33:36 2017<br>
@@ -1325,8 +1325,27 @@ Expected<InstructionMatcher &> GlobalISe<br>
<br>
// Match the used operands (i.e. the children of the operator).<br>
for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) {<br>
- if (auto Error = importChildMatcher(<wbr>InsnMatcher, Src->getChild(i), OpIdx++,<br>
- TempOpIdx))<br>
+ TreePatternNode *SrcChild = Src->getChild(i);<br>
+<br>
+ // For G_INTRINSIC, the operand immediately following the defs is an<br>
+ // intrinsic ID.<br>
+ if (SrcGI.TheDef->getName() == "G_INTRINSIC" && i == 0) {<br>
+ if (!SrcChild->isLeaf())<br>
+ return failedImport("Expected IntInit containing intrinsic ID");<br>
+<br>
+ if (IntInit *SrcChildIntInit =<br>
+ dyn_cast<IntInit>(SrcChild-><wbr>getLeafValue())) {<br>
+ OperandMatcher &OM =<br>
+ InsnMatcher.addOperand(OpIdx++<wbr>, SrcChild->getName(), TempOpIdx);<br>
+ OM.addPredicate<<wbr>IntOperandMatcher>(<wbr>SrcChildIntInit->getValue());<br>
+ continue;<br>
+ }<br>
+<br>
+ return failedImport("Expected IntInit containing instrinsic ID)");<br>
+ }<br>
+<br>
+ if (auto Error =<br>
+ importChildMatcher(<wbr>InsnMatcher, SrcChild, OpIdx++, TempOpIdx))<br>
return std::move(Error);<br>
}<br>
<br>
@@ -1361,7 +1380,7 @@ Error GlobalISelEmitter::<wbr>importChildMatc<br>
<br>
auto OpTyOrNone = MVTToLLT(ChildTypes.front().<wbr>getConcrete());<br>
if (!OpTyOrNone)<br>
- return failedImport("Src operand has an unsupported type");<br>
+ return failedImport("Src operand has an unsupported type (" + to_string(*SrcChild) + ")");<br>
OM.addPredicate<<wbr>LLTOperandMatcher>(*<wbr>OpTyOrNone);<br>
<br>
// Check for nested instructions.<br>
<br>
<br>
______________________________<wbr>_________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/<wbr>mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br></div>