<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Hi Matthias,<div class=""><div class=""><br class=""></div><div class="">There is a typo in the test. Could you check my comment below?</div><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On May 19, 2017, at 1:18 AM, Matthias Braun via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="">Author: matze<br class="">Date: Thu May 18 19:18:03 2017<br class="">New Revision: 303396<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=303396&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=303396&view=rev</a><br class="">Log:<br class="">LiveIntervalAnalysis: Fix missing case in pruneSubRegValues()<br class=""><br class="">pruneSubRegValues() needs to remove subregister ranges starting at<br class="">instructions that later get removed by eraseInstrs(). It missed to check<br class="">one case in which eraseInstrs() would remove an instruction.<br class=""><br class="">Fixes <a href="http://llvm.org/PR32688" class="">http://llvm.org/PR32688</a><br class=""><br class="">Added:<br class=""> llvm/trunk/test/CodeGen/AMDGPU/regcoalesce-prune.mir<br class="">Modified:<br class=""> llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=303396&r1=303395&r2=303396&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=303396&r1=303395&r2=303396&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu May 18 19:18:03 2017<br class="">@@ -2666,11 +2666,17 @@ void JoinVals::pruneSubRegValues(LiveInt<br class=""> // Look for values being erased.<br class=""> bool DidPrune = false;<br class=""> for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {<br class="">- if (Vals[i].Resolution != CR_Erase)<br class="">+ // We should trigger in all cases in which eraseInstrs() does something.<br class="">+ // match what eraseInstrs() is doing, print a message so<br class="">+ if (Vals[i].Resolution != CR_Erase &&<br class="">+ (Vals[i].Resolution != CR_Keep || !Vals[i].ErasableImplicitDef ||<br class="">+ !Vals[i].Pruned))<br class=""> continue;<br class=""><br class=""> // Check subranges at the point where the copy will be removed.<br class=""> SlotIndex Def = LR.getValNumInfo(i)->def;<br class="">+ // Print message so mismatches with eraseInstrs() can be diagnosed.<br class="">+ DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Def << '\n');<br class=""> for (LiveInterval::SubRange &S : LI.subranges()) {<br class=""> LiveQueryResult Q = S.Query(Def);<br class=""><br class=""><br class="">Added: llvm/trunk/test/CodeGen/AMDGPU/regcoalesce-prune.mir<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/regcoalesce-prune.mir?rev=303396&view=auto" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/regcoalesce-prune.mir?rev=303396&view=auto</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/regcoalesce-prune.mir (added)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/regcoalesce-prune.mir Thu May 18 19:18:03 2017<br class="">@@ -0,0 +1,31 @@<br class="">+# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -run-pass=simple-register-coalescing | FileCheck %s<br class="">+---<br class="">+# Checks for a bug where subregister liveranges were not properly pruned for<br class="">+# an IMPLCITI_DEF that gets removed completely.<br class="">+#<br class="">+# CHECK-LABEL: name: func<br class="">+# IMPLICIT_DEF should be gone without llc hitting assertion failures.<br class="">+# CHECK-NOT: IMPLCITI_DEF<br class=""></div></div></blockquote><div><br class=""></div><div>IMPLCITI_DEF —> IMPLICIT_DEF</div><br class=""><blockquote type="cite" class=""><div class=""><div class="">+name: func<br class="">+tracksRegLiveness: true<br class="">+body: |<br class="">+ bb.0:<br class="">+ undef %5.sub1 = V_MOV_B32_e32 0, implicit %exec<br class="">+ %6 = COPY %5<br class="">+ S_CBRANCH_VCCZ %bb.2, implicit undef %vcc<br class="">+<br class="">+ bb.1:<br class="">+ %1 : sreg_32_xm0 = S_MOV_B32 0<br class="">+ undef %0.sub0 : sreg_64 = COPY %1<br class="">+ %0.sub1 = COPY %1<br class="">+ %4 : vreg_64 = COPY killed %0<br class="">+ %5 : vreg_64 = IMPLICIT_DEF<br class="">+ %6 : vreg_64 = COPY killed %4<br class="">+<br class="">+ bb.2:<br class="">+ %2 : vgpr_32 = V_CVT_F32_I32_e32 killed %5.sub1, implicit %exec<br class="">+<br class="">+ bb.3:<br class="">+ %3 : vgpr_32 = V_CVT_F32_I32_e32 killed %6.sub1, implicit %exec<br class="">+ S_ENDPGM<br class="">+...<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class=""><a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br class=""></div></div></blockquote><br class=""></div><div>Thanks,</div><div>Volkan</div><br class=""></div></div></body></html>