<div dir="ltr">On a side note: it doesn't seem like any buildbots detected this. Are there no buildbots covering WebAssembly?</div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Apr 5, 2017 at 1:34 PM, Alexander Kornienko <span dir="ltr"><<a href="mailto:alexfh@google.com" target="_blank">alexfh@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div>FYI, this patch breaks our build:</div><div><br></div><div>lib/Target/WebAssembly/<wbr>MCTargetDesc/<wbr>WebAssemblyAsmBackend.cpp:41:<wbr>55: error: non-virtual member function marked 'override' hides virtual member function</div><span class=""><div> uint64_t Value, bool IsPCRel) const override;</div></span><div> ^</div><div><br></div><div>Please fix or revert.</div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Apr 5, 2017 at 12:16 PM, Alex Bradbury via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: asb<br>
Date: Wed Apr 5 05:16:14 2017<br>
New Revision: 299529<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=299529&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=299529&view=rev</a><br>
Log:<br>
Add MCContext argument to MCAsmBackend::applyFixup for error reporting<br>
<br>
A number of backends (AArch64, MIPS, ARM) have been using<br>
MCContext::reportError to report issues such as out-of-range fixup values in<br>
their TgtAsmBackend. This is great, but because MCContext couldn't easily be<br>
threaded through to the adjustFixupValue helper function from its usual<br>
callsite (applyFixup), these backends ended up adding an MCContext* argument<br>
and adding another call to applyFixup to processFixupValue. Adding an<br>
MCContext parameter to applyFixup makes this unnecessary, and even better -<br>
applyFixup can take a reference to MCContext rather than a potentially null<br>
pointer.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D30264" rel="noreferrer" target="_blank">https://reviews.llvm.org/D3026<wbr>4</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/MC/MCA<wbr>smBackend.h<br>
llvm/trunk/lib/MC/MCAssembler.<wbr>cpp<br>
llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64AsmBackend<wbr>.cpp<br>
llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUAsmBackend.c<wbr>pp<br>
llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.cpp<br>
llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.h<br>
llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMELFObjectWriter.<wbr>cpp<br>
llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFAsmBackend.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp<br>
llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiAsmBackend.cpp<br>
llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.cpp<br>
llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.h<br>
llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCAsmBackend.cpp<br>
llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVAsmBackend.cpp<br>
llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcAsmBackend.cpp<br>
llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCAsmBacke<wbr>nd.cpp<br>
llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86AsmBackend.cpp<br>
llvm/trunk/test/MC/ARM/quad-re<wbr>location.s<br>
<br>
Modified: llvm/trunk/include/llvm/MC/MCA<wbr>smBackend.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmBackend.h?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/llvm/<wbr>MC/MCAsmBackend.h?rev=299529&<wbr>r1=299528&r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/MC/MCA<wbr>smBackend.h (original)<br>
+++ llvm/trunk/include/llvm/MC/MCA<wbr>smBackend.h Wed Apr 5 05:16:14 2017<br>
@@ -71,9 +71,11 @@ public:<br>
<br>
/// Apply the \p Value for given \p Fixup into the provided data fragment, at<br>
/// the offset specified by the fixup and following the fixup kind as<br>
- /// appropriate.<br>
+ /// appropriate. Errors (such as an out of range fixup value) should be<br>
+ /// reported via \p Ctx.<br>
virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const = 0;<br>
+ uint64_t Value, bool IsPCRel,<br>
+ MCContext &Ctx) const = 0;<br>
<br>
/// @}<br>
<br>
<br>
Modified: llvm/trunk/lib/MC/MCAssembler.<wbr>cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/MC/MCAsse<wbr>mbler.cpp?rev=299529&r1=299528<wbr>&r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/MC/MCAssembler.<wbr>cpp (original)<br>
+++ llvm/trunk/lib/MC/MCAssembler.<wbr>cpp Wed Apr 5 05:16:14 2017<br>
@@ -732,8 +732,8 @@ void MCAssembler::layout(MCAsmLayou<wbr>t &La<br>
uint64_t FixedValue;<br>
bool IsPCRel;<br>
std::tie(FixedValue, IsPCRel) = handleFixup(Layout, Frag, Fixup);<br>
- getBackend().applyFixup(Fixup, Contents.data(),<br>
- Contents.size(), FixedValue, IsPCRel);<br>
+ getBackend().applyFixup(Fixup, Contents.data(), Contents.size(),<br>
+ FixedValue, IsPCRel, getContext());<br>
}<br>
}<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64AsmBackend<wbr>.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AA<wbr>rch64/MCTargetDesc/AArch64AsmB<wbr>ackend.cpp?rev=299529&r1=<wbr>299528&r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64AsmBackend<wbr>.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>MCTargetDesc/AArch64AsmBackend<wbr>.cpp Wed Apr 5 05:16:14 2017<br>
@@ -73,7 +73,7 @@ public:<br>
}<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override;<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;<br>
<br>
bool mayNeedRelaxation(const MCInst &Inst) const override;<br>
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,<br>
@@ -138,15 +138,15 @@ static unsigned AdrImmBits(unsigned Valu<br>
}<br>
<br>
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,<br>
- MCContext *Ctx) {<br>
+ MCContext &Ctx) {<br>
unsigned Kind = Fixup.getKind();<br>
int64_t SignedValue = static_cast<int64_t>(Value);<br>
switch (Kind) {<br>
default:<br>
llvm_unreachable("Unknown fixup kind!");<br>
case AArch64::fixup_aarch64_pcrel_a<wbr>dr_imm21:<br>
- if (Ctx && (SignedValue > 2097151 || SignedValue < -2097152))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup value out of range");<br>
+ if (SignedValue > 2097151 || SignedValue < -2097152)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup value out of range");<br>
return AdrImmBits(Value & 0x1fffffULL);<br>
case AArch64::fixup_aarch64_pcrel_a<wbr>drp_imm21:<br>
return AdrImmBits((Value & 0x1fffff000ULL) >> 12);<br>
@@ -154,66 +154,65 @@ static uint64_t adjustFixupValue(const M<br>
case AArch64::fixup_aarch64_pcrel_b<wbr>ranch19:<br>
// Signed 21-bit immediate<br>
if (SignedValue > 2097151 || SignedValue < -2097152)<br>
- if (Ctx) Ctx->reportError(Fixup.getLoc(<wbr>), "fixup value out of range");<br>
- if (Ctx && (Value & 0x3))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup not sufficiently aligned");<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup value out of range");<br>
+ if (Value & 0x3)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup not sufficiently aligned");<br>
// Low two bits are not encoded.<br>
return (Value >> 2) & 0x7ffff;<br>
case AArch64::fixup_aarch64_add_imm<wbr>12:<br>
case AArch64::fixup_aarch64_ldst_im<wbr>m12_scale1:<br>
// Unsigned 12-bit immediate<br>
- if (Ctx && Value >= 0x1000)<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup value out of range");<br>
+ if (Value >= 0x1000)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup value out of range");<br>
return Value;<br>
case AArch64::fixup_aarch64_ldst_im<wbr>m12_scale2:<br>
// Unsigned 12-bit immediate which gets multiplied by 2<br>
- if (Ctx && (Value >= 0x2000))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup value out of range");<br>
- if (Ctx && (Value & 0x1))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup must be 2-byte aligned");<br>
+ if (Value >= 0x2000)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup value out of range");<br>
+ if (Value & 0x1)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup must be 2-byte aligned");<br>
return Value >> 1;<br>
case AArch64::fixup_aarch64_ldst_im<wbr>m12_scale4:<br>
// Unsigned 12-bit immediate which gets multiplied by 4<br>
- if (Ctx && (Value >= 0x4000))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup value out of range");<br>
- if (Ctx && (Value & 0x3))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup must be 4-byte aligned");<br>
+ if (Value >= 0x4000)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup value out of range");<br>
+ if (Value & 0x3)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup must be 4-byte aligned");<br>
return Value >> 2;<br>
case AArch64::fixup_aarch64_ldst_im<wbr>m12_scale8:<br>
// Unsigned 12-bit immediate which gets multiplied by 8<br>
- if (Ctx && (Value >= 0x8000))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup value out of range");<br>
- if (Ctx && (Value & 0x7))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup must be 8-byte aligned");<br>
+ if (Value >= 0x8000)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup value out of range");<br>
+ if (Value & 0x7)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup must be 8-byte aligned");<br>
return Value >> 3;<br>
case AArch64::fixup_aarch64_ldst_im<wbr>m12_scale16:<br>
// Unsigned 12-bit immediate which gets multiplied by 16<br>
- if (Ctx && (Value >= 0x10000))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup value out of range");<br>
- if (Ctx && (Value & 0xf))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup must be 16-byte aligned");<br>
+ if (Value >= 0x10000)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup value out of range");<br>
+ if (Value & 0xf)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup must be 16-byte aligned");<br>
return Value >> 4;<br>
case AArch64::fixup_aarch64_movw:<br>
- if (Ctx)<br>
- Ctx->reportError(Fixup.getLoc(<wbr>),<br>
- "no resolvable MOVZ/MOVK fixups supported yet");<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>,<br>
+ "no resolvable MOVZ/MOVK fixups supported yet");<br>
return Value;<br>
case AArch64::fixup_aarch64_pcrel_b<wbr>ranch14:<br>
// Signed 16-bit immediate<br>
- if (Ctx && (SignedValue > 32767 || SignedValue < -32768))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup value out of range");<br>
+ if (SignedValue > 32767 || SignedValue < -32768)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup value out of range");<br>
// Low two bits are not encoded (4-byte alignment assumed).<br>
- if (Ctx && (Value & 0x3))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup not sufficiently aligned");<br>
+ if (Value & 0x3)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup not sufficiently aligned");<br>
return (Value >> 2) & 0x3fff;<br>
case AArch64::fixup_aarch64_pcrel_b<wbr>ranch26:<br>
case AArch64::fixup_aarch64_pcrel_c<wbr>all26:<br>
// Signed 28-bit immediate<br>
- if (Ctx && (SignedValue > 134217727 || SignedValue < -134217728))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup value out of range");<br>
+ if (SignedValue > 134217727 || SignedValue < -134217728)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup value out of range");<br>
// Low two bits are not encoded (4-byte alignment assumed).<br>
- if (Ctx && (Value & 0x3))<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "fixup not sufficiently aligned");<br>
+ if (Value & 0x3)<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "fixup not sufficiently aligned");<br>
return (Value >> 2) & 0x3ffffff;<br>
case FK_Data_1:<br>
case FK_Data_2:<br>
@@ -264,13 +263,13 @@ unsigned AArch64AsmBackend::getFixupKin<wbr>d<br>
<br>
void AArch64AsmBackend::applyFixup(<wbr>const MCFixup &Fixup, char *Data,<br>
unsigned DataSize, uint64_t Value,<br>
- bool IsPCRel) const {<br>
+ bool IsPCRel, MCContext &Ctx) const {<br>
unsigned NumBytes = getFixupKindNumBytes(Fixup.get<wbr>Kind());<br>
if (!Value)<br>
return; // Doesn't change encoding.<br>
MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind<wbr>());<br>
// Apply any target-specific value adjustments.<br>
- Value = adjustFixupValue(Fixup, Value, nullptr);<br>
+ Value = adjustFixupValue(Fixup, Value, Ctx);<br>
<br>
// Shift the value into position.<br>
Value <<= Info.TargetOffset;<br>
@@ -521,17 +520,6 @@ public:<br>
<br>
return CompactUnwindEncoding;<br>
}<br>
-<br>
- void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,<br>
- const MCFixup &Fixup, const MCFragment *DF,<br>
- const MCValue &Target, uint64_t &Value,<br>
- bool &IsResolved) override {<br>
- // Try to get the encoded value for the fixup as-if we're mapping it into<br>
- // the instruction. This allows adjustFixupValue() to issue a diagnostic<br>
- // if the value is invalid.<br>
- if (IsResolved)<br>
- (void)adjustFixupValue(Fixup, Value, &Asm.getContext());<br>
- }<br>
};<br>
<br>
} // end anonymous namespace<br>
@@ -575,12 +563,6 @@ void ELFAArch64AsmBackend::processF<wbr>ixupV<br>
// to the linker -- a relocation!<br>
if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_a<wbr>drp_imm21)<br>
IsResolved = false;<br>
-<br>
- // Try to get the encoded value for the fixup as-if we're mapping it into<br>
- // the instruction. This allows adjustFixupValue() to issue a diagnostic<br>
- // if the value is invalid.<br>
- if (IsResolved)<br>
- (void)adjustFixupValue(Fixup, Value, &Asm.getContext());<br>
}<br>
<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUAsmBackend.c<wbr>pp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AM<wbr>DGPU/MCTargetDesc/AMDGPUAsmBac<wbr>kend.cpp?rev=299529&r1=299528&<wbr>r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUAsmBackend.c<wbr>pp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/M<wbr>CTargetDesc/AMDGPUAsmBackend.c<wbr>pp Wed Apr 5 05:16:14 2017<br>
@@ -37,7 +37,7 @@ public:<br>
bool &IsResolved) override;<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override;<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;<br>
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,<br>
const MCRelaxableFragment *DF,<br>
const MCAsmLayout &Layout) const override {<br>
@@ -131,7 +131,7 @@ void AMDGPUAsmBackend::processFixup<wbr>Value<br>
<br>
void AMDGPUAsmBackend::applyFixup(c<wbr>onst MCFixup &Fixup, char *Data,<br>
unsigned DataSize, uint64_t Value,<br>
- bool IsPCRel) const {<br>
+ bool IsPCRel, MCContext &Ctx) const {<br>
if (!Value)<br>
return; // Doesn't change encoding.<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AR<wbr>M/MCTargetDesc/ARMAsmBackend.<wbr>cpp?rev=299529&r1=299528&r2=<wbr>299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.cpp Wed Apr 5 05:16:14 2017<br>
@@ -357,13 +357,13 @@ static uint32_t joinHalfWords(uint32_t F<br>
}<br>
<br>
unsigned ARMAsmBackend::adjustFixupValu<wbr>e(const MCFixup &Fixup, uint64_t Value,<br>
- bool IsPCRel, MCContext *Ctx,<br>
+ bool IsPCRel, MCContext &Ctx,<br>
bool IsLittleEndian,<br>
bool IsResolved) const {<br>
unsigned Kind = Fixup.getKind();<br>
switch (Kind) {<br>
default:<br>
- if (Ctx) Ctx->reportError(Fixup.getLoc(<wbr>), "bad relocation fixup type");<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "bad relocation fixup type");<br>
return 0;<br>
case FK_Data_1:<br>
case FK_Data_2:<br>
@@ -413,8 +413,8 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
Value = -Value;<br>
isAdd = false;<br>
}<br>
- if (Ctx && Value >= 4096) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range pc-relative fixup value");<br>
+ if (Value >= 4096) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range pc-relative fixup value");<br>
return 0;<br>
}<br>
Value |= isAdd << 23;<br>
@@ -434,8 +434,8 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
Value = -Value;<br>
opc = 2; // 0b0010<br>
}<br>
- if (Ctx && ARM_AM::getSOImmVal(Value) == -1) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range pc-relative fixup value");<br>
+ if (ARM_AM::getSOImmVal(Value) == -1) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range pc-relative fixup value");<br>
return 0;<br>
}<br>
// Encode the immediate and shift the opcode into place.<br>
@@ -542,8 +542,8 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
//<br>
// Note that the halfwords are stored high first, low second; so we need<br>
// to transpose the fixup value here to map properly.<br>
- if (Ctx && Value % 4 != 0) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "misaligned ARM call destination");<br>
+ if (Value % 4 != 0) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "misaligned ARM call destination");<br>
return 0;<br>
}<br>
<br>
@@ -569,10 +569,10 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
case ARM::fixup_arm_thumb_cp:<br>
// On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we<br>
// could have an error on our hands.<br>
- if (Ctx && !STI->getFeatureBits()[ARM::Fe<wbr>atureThumb2] && IsResolved) {<br>
+ if (!STI->getFeatureBits()[ARM::F<wbr>eatureThumb2] && IsResolved) {<br>
const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup<wbr>, Value);<br>
if (FixupDiagnostic) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), FixupDiagnostic);<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, FixupDiagnostic);<br>
return 0;<br>
}<br>
}<br>
@@ -582,8 +582,8 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
// CB instructions can only branch to offsets in [4, 126] in multiples of 2<br>
// so ensure that the raw value LSB is zero and it lies in [2, 130].<br>
// An offset of 2 will be relaxed to a NOP.<br>
- if (Ctx && ((int64_t)Value < 2 || Value > 0x82 || Value & 1)) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range pc-relative fixup value");<br>
+ if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range pc-relative fixup value");<br>
return 0;<br>
}<br>
// Offset by 4 and don't encode the lower bit, which is always 0.<br>
@@ -593,21 +593,21 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
}<br>
case ARM::fixup_arm_thumb_br:<br>
// Offset by 4 and don't encode the lower bit, which is always 0.<br>
- if (Ctx && !STI->getFeatureBits()[ARM::Fe<wbr>atureThumb2] &&<br>
- !STI->getFeatureBits()[ARM::H<wbr>asV8MBaselineOps]) {<br>
+ if (!STI->getFeatureBits()[ARM::F<wbr>eatureThumb2] &&<br>
+ !STI->getFeatureBits()[ARM::Ha<wbr>sV8MBaselineOps]) {<br>
const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup<wbr>, Value);<br>
if (FixupDiagnostic) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), FixupDiagnostic);<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, FixupDiagnostic);<br>
return 0;<br>
}<br>
}<br>
return ((Value - 4) >> 1) & 0x7ff;<br>
case ARM::fixup_arm_thumb_bcc:<br>
// Offset by 4 and don't encode the lower bit, which is always 0.<br>
- if (Ctx && !STI->getFeatureBits()[ARM::Fe<wbr>atureThumb2]) {<br>
+ if (!STI->getFeatureBits()[ARM::F<wbr>eatureThumb2]) {<br>
const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup<wbr>, Value);<br>
if (FixupDiagnostic) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), FixupDiagnostic);<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, FixupDiagnostic);<br>
return 0;<br>
}<br>
}<br>
@@ -621,8 +621,8 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
isAdd = false;<br>
}<br>
// The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].<br>
- if (Ctx && Value >= 256) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range pc-relative fixup value");<br>
+ if (Value >= 256) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range pc-relative fixup value");<br>
return 0;<br>
}<br>
Value = (Value & 0xf) | ((Value & 0xf0) << 4);<br>
@@ -642,8 +642,8 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
}<br>
// These values don't encode the low two bits since they're always zero.<br>
Value >>= 2;<br>
- if (Ctx && Value >= 256) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range pc-relative fixup value");<br>
+ if (Value >= 256) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range pc-relative fixup value");<br>
return 0;<br>
}<br>
Value |= isAdd << 23;<br>
@@ -668,13 +668,13 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
isAdd = false;<br>
}<br>
// These values don't encode the low bit since it's always zero.<br>
- if (Ctx && (Value & 1)) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "invalid value for this fixup");<br>
+ if (Value & 1) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "invalid value for this fixup");<br>
return 0;<br>
}<br>
Value >>= 1;<br>
- if (Ctx && Value >= 256) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range pc-relative fixup value");<br>
+ if (Value >= 256) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range pc-relative fixup value");<br>
return 0;<br>
}<br>
Value |= isAdd << 23;<br>
@@ -688,8 +688,8 @@ unsigned ARMAsmBackend::adjustFixupValu<wbr>e<br>
}<br>
case ARM::fixup_arm_mod_imm:<br>
Value = ARM_AM::getSOImmVal(Value);<br>
- if (Ctx && Value >> 12) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range immediate fixup value");<br>
+ if (Value >> 12) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range immediate fixup value");<br>
return 0;<br>
}<br>
return Value;<br>
@@ -738,12 +738,6 @@ void ARMAsmBackend::processFixupVal<wbr>ue(co<br>
(unsigned)Fixup.getKind() == ARM::fixup_arm_uncondbl ||<br>
(unsigned)Fixup.getKind() == ARM::fixup_arm_condbl))<br>
IsResolved = false;<br>
-<br>
- // Try to get the encoded value for the fixup as-if we're mapping it into<br>
- // the instruction. This allows adjustFixupValue() to issue a diagnostic<br>
- // if the value is invalid.<br>
- (void)adjustFixupValue(Fixup, Value, false, &Asm.getContext(),<br>
- IsLittleEndian, IsResolved);<br>
}<br>
<br>
/// getFixupKindNumBytes - The number of bytes the fixup may change.<br>
@@ -847,11 +841,10 @@ static unsigned getFixupKindContainerSiz<br>
}<br>
<br>
void ARMAsmBackend::applyFixup(cons<wbr>t MCFixup &Fixup, char *Data,<br>
- unsigned DataSize, uint64_t Value,<br>
- bool IsPCRel) const {<br>
+ unsigned DataSize, uint64_t Value, bool IsPCRel,<br>
+ MCContext &Ctx) const {<br>
unsigned NumBytes = getFixupKindNumBytes(Fixup.get<wbr>Kind());<br>
- Value =<br>
- adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian, true);<br>
+ Value = adjustFixupValue(Fixup, Value, IsPCRel, Ctx, IsLittleEndian, true);<br>
if (!Value)<br>
return; // Doesn't change encoding.<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AR<wbr>M/MCTargetDesc/ARMAsmBackend.<wbr>h?rev=299529&r1=299528&r2=<wbr>299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMAsmBackend.h Wed Apr 5 05:16:14 2017<br>
@@ -46,11 +46,11 @@ public:<br>
bool &IsResolved) override;<br>
<br>
unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, bool IsPCRel,<br>
- MCContext *Ctx, bool IsLittleEndian,<br>
+ MCContext &Ctx, bool IsLittleEndian,<br>
bool IsResolved) const;<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override;<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;<br>
<br>
unsigned getRelaxedOpcode(unsigned Op) const;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMELFObjectWriter.<wbr>cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/AR<wbr>M/MCTargetDesc/ARMELFObjectWri<wbr>ter.cpp?rev=299529&r1=299528&<wbr>r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMELFObjectWriter.<wbr>cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTa<wbr>rgetDesc/ARMELFObjectWriter.<wbr>cpp Wed Apr 5 05:16:14 2017<br>
@@ -9,6 +9,7 @@<br>
<br>
#include "MCTargetDesc/ARMFixupKinds.h"<br>
#include "MCTargetDesc/ARMMCTargetDesc.<wbr>h"<br>
+#include "llvm/MC/MCContext.h"<br>
#include "llvm/MC/MCELFObjectWriter.h"<br>
#include "llvm/MC/MCExpr.h"<br>
#include "llvm/MC/MCFixup.h"<br>
@@ -25,9 +26,8 @@ namespace {<br>
class ARMELFObjectWriter : public MCELFObjectTargetWriter {<br>
enum { DefaultEABIVersion = 0x05000000U };<br>
<br>
- unsigned GetRelocTypeInner(const MCValue &Target,<br>
- const MCFixup &Fixup,<br>
- bool IsPCRel) const;<br>
+ unsigned GetRelocTypeInner(const MCValue &Target, const MCFixup &Fixup,<br>
+ bool IsPCRel, MCContext &Ctx) const;<br>
<br>
public:<br>
ARMELFObjectWriter(uint8_t OSABI);<br>
@@ -69,19 +69,20 @@ bool ARMELFObjectWriter::needsReloc<wbr>ateWi<br>
unsigned ARMELFObjectWriter::getRelocTy<wbr>pe(MCContext &Ctx, const MCValue &Target,<br>
const MCFixup &Fixup,<br>
bool IsPCRel) const {<br>
- return GetRelocTypeInner(Target, Fixup, IsPCRel);<br>
+ return GetRelocTypeInner(Target, Fixup, IsPCRel, Ctx);<br>
}<br>
<br>
unsigned ARMELFObjectWriter::GetRelocTy<wbr>peInner(const MCValue &Target,<br>
const MCFixup &Fixup,<br>
- bool IsPCRel) const {<br>
+ bool IsPCRel,<br>
+ MCContext &Ctx) const {<br>
MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant();<br>
<br>
unsigned Type = 0;<br>
if (IsPCRel) {<br>
switch ((unsigned)Fixup.getKind()) {<br>
default:<br>
- report_fatal_error("unsupporte<wbr>d relocation on symbol");<br>
+ Ctx.reportFatalError(Fixup.get<wbr>Loc(), "unsupported relocation on symbol");<br>
return ELF::R_ARM_NONE;<br>
case FK_Data_4:<br>
switch (Modifier) {<br>
@@ -160,7 +161,7 @@ unsigned ARMELFObjectWriter::GetRelocTy<wbr>p<br>
} else {<br>
switch ((unsigned)Fixup.getKind()) {<br>
default:<br>
- report_fatal_error("unsupporte<wbr>d relocation on symbol");<br>
+ Ctx.reportFatalError(Fixup.get<wbr>Loc(), "unsupported relocation on symbol");<br>
return ELF::R_ARM_NONE;<br>
case FK_Data_1:<br>
switch (Modifier) {<br>
<br>
Modified: llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/BP<wbr>F/MCTargetDesc/BPFAsmBackend.<wbr>cpp?rev=299529&r1=299528&r2=<wbr>299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/BPF/MCTa<wbr>rgetDesc/BPFAsmBackend.cpp Wed Apr 5 05:16:14 2017<br>
@@ -28,7 +28,7 @@ public:<br>
~BPFAsmBackend() override = default;<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override;<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;<br>
<br>
MCObjectWriter *createObjectWriter(raw_pwrite<wbr>_stream &OS) const override;<br>
<br>
@@ -62,8 +62,8 @@ bool BPFAsmBackend::writeNopData(ui<wbr>nt64_<br>
}<br>
<br>
void BPFAsmBackend::applyFixup(cons<wbr>t MCFixup &Fixup, char *Data,<br>
- unsigned DataSize, uint64_t Value,<br>
- bool IsPCRel) const {<br>
+ unsigned DataSize, uint64_t Value, bool IsPCRel,<br>
+ MCContext &Ctx) const {<br>
if (Fixup.getKind() == FK_SecRel_4 || Fixup.getKind() == FK_SecRel_8) {<br>
assert(Value == 0);<br>
} else if (Fixup.getKind() == FK_Data_4 || Fixup.getKind() == FK_Data_8) {<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonAsmB<wbr>ackend.cpp?rev=299529&r1=<wbr>299528&r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp Wed Apr 5 05:16:14 2017<br>
@@ -402,7 +402,8 @@ public:<br>
/// data fragment, at the offset specified by the fixup and following the<br>
/// fixup kind as appropriate.<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t FixupValue, bool IsPCRel) const override {<br>
+ uint64_t FixupValue, bool IsPCRel,<br>
+ MCContext &Ctx) const override {<br>
<br>
// When FixupValue is 0 the relocation is external and there<br>
// is nothing for us to do.<br>
<br>
Modified: llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/La<wbr>nai/MCTargetDesc/LanaiAsmBacke<wbr>nd.cpp?rev=299529&r1=299528&<wbr>r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/Lanai/MC<wbr>TargetDesc/LanaiAsmBackend.cpp Wed Apr 5 05:16:14 2017<br>
@@ -50,7 +50,7 @@ public:<br>
: MCAsmBackend(), OSType(OST) {}<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override;<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;<br>
<br>
MCObjectWriter *createObjectWriter(raw_pwrite<wbr>_stream &OS) const override;<br>
<br>
@@ -90,7 +90,7 @@ bool LanaiAsmBackend::writeNopData(<wbr>uint6<br>
<br>
void LanaiAsmBackend::applyFixup(co<wbr>nst MCFixup &Fixup, char *Data,<br>
unsigned /*DataSize*/, uint64_t Value,<br>
- bool /*IsPCRel*/) const {<br>
+ bool /*IsPCRel*/, MCContext & /*Ctx*/) const {<br>
MCFixupKind Kind = Fixup.getKind();<br>
Value = adjustFixupValue(static_cast<u<wbr>nsigned>(Kind), Value);<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Mi<wbr>ps/MCTargetDesc/MipsAsmBackend<wbr>.cpp?rev=299529&r1=299528&r2=<wbr>299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.cpp Wed Apr 5 05:16:14 2017<br>
@@ -34,7 +34,7 @@ using namespace llvm;<br>
<br>
// Prepare value for the target space for it<br>
static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,<br>
- MCContext *Ctx = nullptr) {<br>
+ MCContext &Ctx) {<br>
<br>
unsigned Kind = Fixup.getKind();<br>
<br>
@@ -74,8 +74,8 @@ static unsigned adjustFixupValue(const M<br>
// address range. Forcing a signed division because Value can be negative.<br>
Value = (int64_t)Value / 4;<br>
// We now check if Value can be encoded as a 16-bit signed immediate.<br>
- if (!isInt<16>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC16 fixup");<br>
+ if (!isInt<16>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC16 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -84,8 +84,8 @@ static unsigned adjustFixupValue(const M<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t)Value / 4;<br>
// We now check if Value can be encoded as a 19-bit signed immediate.<br>
- if (!isInt<19>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC19 fixup");<br>
+ if (!isInt<19>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC19 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -121,8 +121,8 @@ static unsigned adjustFixupValue(const M<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t) Value / 2;<br>
// We now check if Value can be encoded as a 7-bit signed immediate.<br>
- if (!isInt<7>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC7 fixup");<br>
+ if (!isInt<7>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC7 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -131,8 +131,8 @@ static unsigned adjustFixupValue(const M<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t) Value / 2;<br>
// We now check if Value can be encoded as a 10-bit signed immediate.<br>
- if (!isInt<10>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC10 fixup");<br>
+ if (!isInt<10>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC10 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -141,8 +141,8 @@ static unsigned adjustFixupValue(const M<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t)Value / 2;<br>
// We now check if Value can be encoded as a 16-bit signed immediate.<br>
- if (!isInt<16>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC16 fixup");<br>
+ if (!isInt<16>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC16 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -150,21 +150,21 @@ static unsigned adjustFixupValue(const M<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t)Value / 8;<br>
// We now check if Value can be encoded as a 18-bit signed immediate.<br>
- if (!isInt<18>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC18 fixup");<br>
+ if (!isInt<18>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC18 fixup");<br>
return 0;<br>
}<br>
break;<br>
case Mips::fixup_MICROMIPS_PC18_S3:<br>
// Check alignment.<br>
- if ((Value & 7) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC18 fixup");<br>
+ if ((Value & 7)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC18 fixup");<br>
}<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t)Value / 8;<br>
// We now check if Value can be encoded as a 18-bit signed immediate.<br>
- if (!isInt<18>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC18 fixup");<br>
+ if (!isInt<18>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC18 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -172,8 +172,8 @@ static unsigned adjustFixupValue(const M<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t) Value / 4;<br>
// We now check if Value can be encoded as a 21-bit signed immediate.<br>
- if (!isInt<21>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC21 fixup");<br>
+ if (!isInt<21>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC21 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -181,8 +181,8 @@ static unsigned adjustFixupValue(const M<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t) Value / 4;<br>
// We now check if Value can be encoded as a 26-bit signed immediate.<br>
- if (!isInt<26>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC26 fixup");<br>
+ if (!isInt<26>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC26 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -190,8 +190,8 @@ static unsigned adjustFixupValue(const M<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t)Value / 2;<br>
// We now check if Value can be encoded as a 26-bit signed immediate.<br>
- if (!isInt<26>(Value) && Ctx) {<br>
- Ctx->reportFatalError(Fixup.ge<wbr>tLoc(), "out of range PC26 fixup");<br>
+ if (!isInt<26>(Value)) {<br>
+ Ctx.reportFatalError(Fixup.get<wbr>Loc(), "out of range PC26 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -199,8 +199,8 @@ static unsigned adjustFixupValue(const M<br>
// Forcing a signed division because Value can be negative.<br>
Value = (int64_t)Value / 2;<br>
// We now check if Value can be encoded as a 21-bit signed immediate.<br>
- if (!isInt<21>(Value) && Ctx) {<br>
- Ctx->reportError(Fixup.getLoc(<wbr>), "out of range PC21 fixup");<br>
+ if (!isInt<21>(Value)) {<br>
+ Ctx.reportError(Fixup.getLoc()<wbr>, "out of range PC21 fixup");<br>
return 0;<br>
}<br>
break;<br>
@@ -236,10 +236,10 @@ static unsigned calculateMMLEIndex(unsig<br>
/// data fragment, at the offset specified by the fixup and following the<br>
/// fixup kind as appropriate.<br>
void MipsAsmBackend::applyFixup(con<wbr>st MCFixup &Fixup, char *Data,<br>
- unsigned DataSize, uint64_t Value,<br>
- bool IsPCRel) const {<br>
+ unsigned DataSize, uint64_t Value, bool IsPCRel,<br>
+ MCContext &Ctx) const {<br>
MCFixupKind Kind = Fixup.getKind();<br>
- Value = adjustFixupValue(Fixup, Value);<br>
+ Value = adjustFixupValue(Fixup, Value, Ctx);<br>
<br>
if (!Value)<br>
return; // Doesn't change encoding.<br>
@@ -471,24 +471,6 @@ bool MipsAsmBackend::writeNopData(u<wbr>int64<br>
return true;<br>
}<br>
<br>
-/// processFixupValue - Target hook to process the literal value of a fixup<br>
-/// if necessary.<br>
-void MipsAsmBackend::processFixupVa<wbr>lue(const MCAssembler &Asm,<br>
- const MCAsmLayout &Layout,<br>
- const MCFixup &Fixup,<br>
- const MCFragment *DF,<br>
- const MCValue &Target,<br>
- uint64_t &Value,<br>
- bool &IsResolved) {<br>
- // At this point we'll ignore the value returned by adjustFixupValue as<br>
- // we are only checking if the fixup can be applied correctly. We have<br>
- // access to MCContext from here which allows us to report a fatal error<br>
- // with *possibly* a source code location.<br>
- // The caller will also ignore any changes we make to Value<br>
- // (recordRelocation() overwrites it with it's own calculation).<br>
- (void)adjustFixupValue(Fixup, Value, &Asm.getContext());<br>
-}<br>
-<br>
// MCAsmBackend<br>
MCAsmBackend *llvm::createMipsAsmBackendEL3<wbr>2(const Target &T,<br>
const MCRegisterInfo &MRI,<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Mi<wbr>ps/MCTargetDesc/MipsAsmBackend<wbr>.h?rev=299529&r1=299528&r2=<wbr>299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.h (original)<br>
+++ llvm/trunk/lib/Target/Mips/MCT<wbr>argetDesc/MipsAsmBackend.h Wed Apr 5 05:16:14 2017<br>
@@ -39,7 +39,7 @@ public:<br>
MCObjectWriter *createObjectWriter(raw_pwrite<wbr>_stream &OS) const override;<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override;<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;<br>
<br>
Optional<MCFixupKind> getFixupKind(StringRef Name) const override;<br>
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;<br>
@@ -82,11 +82,6 @@ public:<br>
<br>
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;<br>
<br>
- void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,<br>
- const MCFixup &Fixup, const MCFragment *DF,<br>
- const MCValue &Target, uint64_t &Value,<br>
- bool &IsResolved) override;<br>
-<br>
}; // class MipsAsmBackend<br>
<br>
} // namespace<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Po<wbr>werPC/MCTargetDesc/PPCAsmBacke<wbr>nd.cpp?rev=299529&r1=299528&<wbr>r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/<wbr>MCTargetDesc/PPCAsmBackend.cpp Wed Apr 5 05:16:14 2017<br>
@@ -114,7 +114,7 @@ public:<br>
}<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override {<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override {<br>
Value = adjustFixupValue(Fixup.getKind<wbr>(), Value);<br>
if (!Value) return; // Doesn't change encoding.<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/RI<wbr>SCV/MCTargetDesc/RISCVAsmBacke<wbr>nd.cpp?rev=299529&r1=299528&<wbr>r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/RISCV/MC<wbr>TargetDesc/RISCVAsmBackend.cpp Wed Apr 5 05:16:14 2017<br>
@@ -33,7 +33,7 @@ public:<br>
~RISCVAsmBackend() override {}<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override;<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;<br>
<br>
MCObjectWriter *createObjectWriter(raw_pwrite<wbr>_stream &OS) const override;<br>
<br>
@@ -71,7 +71,7 @@ bool RISCVAsmBackend::writeNopData(<wbr>uint6<br>
<br>
void RISCVAsmBackend::applyFixup(co<wbr>nst MCFixup &Fixup, char *Data,<br>
unsigned DataSize, uint64_t Value,<br>
- bool IsPCRel) const {<br>
+ bool IsPCRel, MCContext &Ctx) const {<br>
return;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Sp<wbr>arc/MCTargetDesc/SparcAsmBacke<wbr>nd.cpp?rev=299529&r1=299528&<wbr>r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/Sparc/MC<wbr>TargetDesc/SparcAsmBackend.cpp Wed Apr 5 05:16:14 2017<br>
@@ -274,7 +274,8 @@ namespace {<br>
SparcAsmBackend(T), OSType(OSType) { }<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override {<br>
+ uint64_t Value, bool IsPCRel,<br>
+ MCContext &Ctx) const override {<br>
<br>
Value = adjustFixupValue(Fixup.getKind<wbr>(), Value);<br>
if (!Value) return; // Doesn't change encoding.<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCAsmBacke<wbr>nd.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Sy<wbr>stemZ/MCTargetDesc/SystemZMCAs<wbr>mBackend.cpp?rev=299529&r1=<wbr>299528&r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCAsmBacke<wbr>nd.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/<wbr>MCTargetDesc/SystemZMCAsmBacke<wbr>nd.cpp Wed Apr 5 05:16:14 2017<br>
@@ -51,7 +51,7 @@ public:<br>
}<br>
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override;<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;<br>
bool mayNeedRelaxation(const MCInst &Inst) const override {<br>
return false;<br>
}<br>
@@ -91,7 +91,7 @@ SystemZMCAsmBackend::getFixupK<wbr>indInfo(MC<br>
<br>
void SystemZMCAsmBackend::applyFixu<wbr>p(const MCFixup &Fixup, char *Data,<br>
unsigned DataSize, uint64_t Value,<br>
- bool IsPCRel) const {<br>
+ bool IsPCRel, MCContext &Ctx) const {<br>
MCFixupKind Kind = Fixup.getKind();<br>
unsigned Offset = Fixup.getOffset();<br>
unsigned BitSize = getFixupKindInfo(Kind).TargetS<wbr>ize;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86AsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/X8<wbr>6/MCTargetDesc/X86AsmBackend.<wbr>cpp?rev=299529&r1=299528&r2=<wbr>299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86AsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86AsmBackend.cpp Wed Apr 5 05:16:14 2017<br>
@@ -109,7 +109,7 @@ public:<br>
}<br>
<br>
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,<br>
- uint64_t Value, bool IsPCRel) const override {<br>
+ uint64_t Value, bool IsPCRel, MCContext &Ctx) const override {<br>
unsigned Size = 1 << getFixupKindLog2Size(Fixup.get<wbr>Kind());<br>
<br>
assert(Fixup.getOffset() + Size <= DataSize &&<br>
<br>
Modified: llvm/trunk/test/MC/ARM/quad-re<wbr>location.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/quad-relocation.s?rev=299529&r1=299528&r2=299529&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/MC/ARM/<wbr>quad-relocation.s?rev=299529&<wbr>r1=299528&r2=299529&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/ARM/quad-re<wbr>location.s (original)<br>
+++ llvm/trunk/test/MC/ARM/quad-re<wbr>location.s Wed Apr 5 05:16:14 2017<br>
@@ -4,6 +4,6 @@<br>
symbol:<br>
.quad(symbol)<br>
<br>
-@ CHECK: error: bad relocation fixup type<br>
+@ CHECK: error: unsupported relocation on symbol<br>
@ CHECK-NEXT: .quad(symbol)<br>
@ CHECK-NEXT: ^<br>
<br>
<br>
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</blockquote></div><br></div>
</div></div></blockquote></div><br></div>