<div dir="ltr">This is still breaking on bots:<div><a href="http://green.lab.llvm.org/green/job/clang-stage2-configure-Rlto_check/14126/consoleFull#7076833928254eaf0-7326-4999-85b0-388101f2d404">http://green.lab.llvm.org/green/job/clang-stage2-configure-Rlto_check/14126/consoleFull#7076833928254eaf0-7326-4999-85b0-388101f2d404</a><br></div><div><br></div><div>Please fix or revert asap.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Mar 19, 2017 at 9:53 AM, Oren Ben Simhon via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: orenb<br>
Date: Sun Mar 19 03:53:42 2017<br>
New Revision: 298209<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=298209&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=298209&view=rev</a><br>
Log:<br>
Moving the test to x86 because other architectures do not suport regcall calling convention.<br>
<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/MIR/<wbr>X86/dynamic-regmask.ll<br>
Removed:<br>
llvm/trunk/test/CodeGen/MIR/<wbr>Generic/dynamic-regmask.ll<br>
<br>
Removed: llvm/trunk/test/CodeGen/MIR/<wbr>Generic/dynamic-regmask.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/dynamic-regmask.ll?rev=298208&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/MIR/Generic/dynamic-<wbr>regmask.ll?rev=298208&view=<wbr>auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/MIR/<wbr>Generic/dynamic-regmask.ll (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/<wbr>Generic/dynamic-regmask.ll (removed)<br>
@@ -1,30 +0,0 @@<br>
-; RUN: llc -stop-after machine-sink %s -o %t.mir<br>
-; RUN: FileCheck %s < %t.mir<br>
-; RUN: llc %t.mir -run-pass machine-sink<br>
-; Check that callee saved registers are printed in a format that can then be parsed.<br>
-<br>
-declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)<br>
-<br>
-define i32 @caller(i32 %a0) nounwind {<br>
- %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)<br>
- %b2 = add i32 %b1, %a0<br>
- ret i32 %b2<br>
-}<br>
-; CHECK: name: caller<br>
-; CHECK: CALL64pcrel32 @callee, CustomRegMask(%bh,%bl,%bp,%<wbr>bpl,%bx,%ebp,%ebx,%esp,%rbp,%<wbr>rbx,%rsp,%sp,%spl,%r10,%r11,%<wbr>r12,%r13,%r14,%r15,%xmm8,%<wbr>xmm9,%xmm10,%xmm11,%xmm12,%<wbr>xmm13,%xmm14,%xmm15,%r10b,%<wbr>r11b,%r12b,%r13b,%r14b,%r15b,%<wbr>r10d,%r11d,%r12d,%r13d,%r14d,%<wbr>r15d,%r10w,%r11w,%r12w,%r13w,%<wbr>r14w,%r15w)<br>
-; CHECK: RET 0, %eax<br>
-<br>
-define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {<br>
- %b1 = mul i32 7, %e0<br>
- %b2 = udiv i32 5, %e0<br>
- %b3 = mul i32 7, %d0<br>
- %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0<br>
- %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1<br>
- %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2<br>
- ret {i32, i32, i32} %b6<br>
-}<br>
-; CHECK: name: test_callee<br>
-; CHECK: calleeSavedRegisters: [ '%rbx', '%rbp', '%rsp', '%r10', '%r11', '%r12',<br>
-; CHECK: '%r13', '%r14', '%r15', '%xmm8', '%xmm9', '%xmm10',<br>
-; CHECK: '%xmm11', '%xmm12', '%xmm13', '%xmm14', '%xmm15' ]<br>
-; CHECK: RET 0, %eax, %ecx, %edx<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/<wbr>X86/dynamic-regmask.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/dynamic-regmask.ll?rev=298209&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/MIR/X86/dynamic-<wbr>regmask.ll?rev=298209&view=<wbr>auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/MIR/<wbr>X86/dynamic-regmask.ll (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/<wbr>X86/dynamic-regmask.ll Sun Mar 19 03:53:42 2017<br>
@@ -0,0 +1,30 @@<br>
+; RUN: llc -stop-after machine-sink %s -o %t.mir<br>
+; RUN: FileCheck %s < %t.mir<br>
+; RUN: llc %t.mir -run-pass machine-sink<br>
+; Check that callee saved registers are printed in a format that can then be parsed.<br>
+<br>
+declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)<br>
+<br>
+define i32 @caller(i32 %a0) nounwind {<br>
+ %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)<br>
+ %b2 = add i32 %b1, %a0<br>
+ ret i32 %b2<br>
+}<br>
+; CHECK: name: caller<br>
+; CHECK: CALL64pcrel32 @callee, CustomRegMask(%bh,%bl,%bp,%<wbr>bpl,%bx,%ebp,%ebx,%esp,%rbp,%<wbr>rbx,%rsp,%sp,%spl,%r10,%r11,%<wbr>r12,%r13,%r14,%r15,%xmm8,%<wbr>xmm9,%xmm10,%xmm11,%xmm12,%<wbr>xmm13,%xmm14,%xmm15,%r10b,%<wbr>r11b,%r12b,%r13b,%r14b,%r15b,%<wbr>r10d,%r11d,%r12d,%r13d,%r14d,%<wbr>r15d,%r10w,%r11w,%r12w,%r13w,%<wbr>r14w,%r15w)<br>
+; CHECK: RET 0, %eax<br>
+<br>
+define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {<br>
+ %b1 = mul i32 7, %e0<br>
+ %b2 = udiv i32 5, %e0<br>
+ %b3 = mul i32 7, %d0<br>
+ %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0<br>
+ %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1<br>
+ %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2<br>
+ ret {i32, i32, i32} %b6<br>
+}<br>
+; CHECK: name: test_callee<br>
+; CHECK: calleeSavedRegisters: [ '%rbx', '%rbp', '%rsp', '%r10', '%r11', '%r12',<br>
+; CHECK: '%r13', '%r14', '%r15', '%xmm8', '%xmm9', '%xmm10',<br>
+; CHECK: '%xmm11', '%xmm12', '%xmm13', '%xmm14', '%xmm15' ]<br>
+; CHECK: RET 0, %eax, %ecx, %edx<br>
<br>
<br>
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</blockquote></div><br></div>