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<div id="x_divtagdefaultwrapper" dir="ltr" style="font-size:12pt; color:#000000; font-family:Calibri,Arial,Helvetica,sans-serif">
<p>Hi Rafael,</p>
<p><br>
</p>
<p>Yes, Andre is already looking into it.</p>
<p><br>
</p>
<p>cheers,</p>
<p>sam</p>
<p><br>
</p>
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<div id="x_divtagdefaultwrapper" style="font-size:12pt; color:#000000; background-color:#FFFFFF; font-family:Calibri,Arial,Helvetica,sans-serif">
<p>Sam Parker</p>
<p>Software Engineer, Compilation Tools</p>
<p>Development Solutions Group</p>
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<div id="x_divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>From:</b> Rafael Avila de Espindola <rafael.espindola@gmail.com><br>
<b>Sent:</b> 15 March 2017 12:37:26<br>
<b>To:</b> Sam Parker; llvm-commits@lists.llvm.org<br>
<b>Subject:</b> Re: [llvm] r297821 - [ARM] Fix for branch label disassembly for Thumb</font>
<div> </div>
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<font size="2"><span style="font-size:10pt;">
<div class="PlainText">I guess some tests in lld need to be updated. Could you please take a look:<br>
<br>
<a href="http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/5756/steps/test_lld/logs/stdio">http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/5756/steps/test_lld/logs/stdio</a><br>
<br>
Thanks,<br>
Rafael<br>
<br>
Sam Parker via llvm-commits <llvm-commits@lists.llvm.org> writes:<br>
<br>
> Author: sam_parker<br>
> Date: Wed Mar 15 05:21:23 2017<br>
> New Revision: 297821<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=297821&view=rev">http://llvm.org/viewvc/llvm-project?rev=297821&view=rev</a><br>
> Log:<br>
> [ARM] Fix for branch label disassembly for Thumb<br>
><br>
> Different MCInstrAnalysis classes for arm and thumb mode, each with<br>
> their own evaluateBranch implementation. I added a test case and<br>
> fixed the coff-relocations test to use '<label>:' rather than<br>
> '<label>' in the CHECK-LABEL entries, since the ones without the<br>
> colon would match branch targets. Might be worth noticing that<br>
> llvm-objdump does not lookup the relocation and thus assigns it a<br>
> target depending on the encoded immediate which #0, so it thinks it<br>
> branches to the next instruction.<br>
><br>
> Committed on behalf of Andre Vieira (avieira).<br>
><br>
> Differential Revision: <a href="https://reviews.llvm.org/D30943">https://reviews.llvm.org/D30943</a><br>
><br>
><br>
> Added:<br>
> llvm/trunk/test/MC/ARM/branch-disassemble.s<br>
> Modified:<br>
> llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp<br>
> llvm/trunk/test/MC/ARM/coff-relocations.s<br>
><br>
> Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=297821&r1=297820&r2=297821&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp?rev=297821&r1=297820&r2=297821&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp (original)<br>
> +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp Wed Mar 15 05:21:23 2017<br>
> @@ -257,24 +257,43 @@ public:<br>
> uint64_t Size, uint64_t &Target) const override {<br>
> // We only handle PCRel branches for now.<br>
> if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)<br>
> - return false;<br>
> -<br>
> - int64_t Imm = Inst.getOperand(0).getImm();<br>
> - // FIXME: This is not right for thumb.<br>
> - Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.<br>
> - return true;<br>
> - }<br>
> -};<br>
> -<br>
> -}<br>
> -<br>
> -static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {<br>
> - return new ARMMCInstrAnalysis(Info);<br>
> -}<br>
> -<br>
> -// Force static initialization.<br>
> -extern "C" void LLVMInitializeARMTargetMC() {<br>
> - for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),<br>
> + return false;<br>
> +<br>
> + int64_t Imm = Inst.getOperand(0).getImm();<br>
> + Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.<br>
> + return true;<br>
> + }<br>
> +};<br>
> +<br>
> +class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {<br>
> +public:<br>
> + ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}<br>
> +<br>
> + bool evaluateBranch(const MCInst &Inst, uint64_t Addr,<br>
> + uint64_t Size, uint64_t &Target) const override {<br>
> + // We only handle PCRel branches for now.<br>
> + if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)<br>
> + return false;<br>
> +<br>
> + int64_t Imm = Inst.getOperand(0).getImm();<br>
> + Target = Addr+Imm+4; // In Thumb mode the PC is always off by 4 bytes.<br>
> + return true;<br>
> + }<br>
> +};<br>
> +<br>
> +}<br>
> +<br>
> +static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {<br>
> + return new ARMMCInstrAnalysis(Info);<br>
> +}<br>
> +<br>
> +static MCInstrAnalysis *createThumbMCInstrAnalysis(const MCInstrInfo *Info) {<br>
> + return new ThumbMCInstrAnalysis(Info);<br>
> +}<br>
> +<br>
> +// Force static initialization.<br>
> +extern "C" void LLVMInitializeARMTargetMC() {<br>
> + for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget(),<br>
> &getTheThumbLETarget(), &getTheThumbBETarget()}) {<br>
> // Register the MC asm info.<br>
> RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo);<br>
> @@ -286,15 +305,12 @@ extern "C" void LLVMInitializeARMTargetM<br>
> TargetRegistry::RegisterMCRegInfo(*T, createARMMCRegisterInfo);<br>
> <br>
> // Register the MC subtarget info.<br>
> - TargetRegistry::RegisterMCSubtargetInfo(*T,<br>
> - ARM_MC::createARMMCSubtargetInfo);<br>
> -<br>
> - // Register the MC instruction analyzer.<br>
> - TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);<br>
> -<br>
> - TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);<br>
> - TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);<br>
> - TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);<br>
> + TargetRegistry::RegisterMCSubtargetInfo(*T,<br>
> + ARM_MC::createARMMCSubtargetInfo);<br>
> +<br>
> + TargetRegistry::RegisterELFStreamer(*T, createELFStreamer);<br>
> + TargetRegistry::RegisterCOFFStreamer(*T, createARMWinCOFFStreamer);<br>
> + TargetRegistry::RegisterMachOStreamer(*T, createARMMachOStreamer);<br>
> <br>
> // Register the obj target streamer.<br>
> TargetRegistry::RegisterObjectTargetStreamer(*T,<br>
> @@ -310,12 +326,18 @@ extern "C" void LLVMInitializeARMTargetM<br>
> TargetRegistry::RegisterMCInstPrinter(*T, createARMMCInstPrinter);<br>
> <br>
> // Register the MC relocation info.<br>
> - TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);<br>
> - }<br>
> -<br>
> - // Register the MC Code Emitter<br>
> - for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()})<br>
> - TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);<br>
> + TargetRegistry::RegisterMCRelocationInfo(*T, createARMMCRelocationInfo);<br>
> + }<br>
> +<br>
> + // Register the MC instruction analyzer.<br>
> + for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()})<br>
> + TargetRegistry::RegisterMCInstrAnalysis(*T, createARMMCInstrAnalysis);<br>
> + for (Target *T : {&getTheThumbLETarget(), &getTheThumbBETarget()})<br>
> + TargetRegistry::RegisterMCInstrAnalysis(*T, createThumbMCInstrAnalysis);<br>
> +<br>
> + // Register the MC Code Emitter<br>
> + for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()})<br>
> + TargetRegistry::RegisterMCCodeEmitter(*T, createARMLEMCCodeEmitter);<br>
> for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()})<br>
> TargetRegistry::RegisterMCCodeEmitter(*T, createARMBEMCCodeEmitter);<br>
> <br>
><br>
> Added: llvm/trunk/test/MC/ARM/branch-disassemble.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/branch-disassemble.s?rev=297821&view=auto">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/branch-disassemble.s?rev=297821&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/ARM/branch-disassemble.s (added)<br>
> +++ llvm/trunk/test/MC/ARM/branch-disassemble.s Wed Mar 15 05:21:23 2017<br>
> @@ -0,0 +1,15 @@<br>
> +@ RUN: llvm-mc -mcpu=cortex-a9 -triple armv7.arm-none-eabi -filetype obj -o - %s \<br>
> +@ RUN: | llvm-objdump -mcpu=cortex-a9 -triple armv7.arm-none-eabi -d - \<br>
> +@ RUN: | FileCheck %s -check-prefix CHECK-ARM<br>
> +<br>
> +@ RUN: llvm-mc -mcpu=cortex-m3 -triple thumbv7.arm-none-eabi -filetype obj -o - %s \<br>
> +@ RUN: | llvm-objdump -mcpu=cortex-m3 -triple thumbv7.arm-none-eabi -d - \<br>
> +@ RUN: | FileCheck %s -check-prefix CHECK-THUMB<br>
> +<br>
> +b.w .Lbranch<br>
> +@ CHECK-ARM: b #4 <$a.0+0xC><br>
> +@ CHECK-THUMB: b.w #8 <$t.0+0xC><br>
> +adds r0, r1, #42<br>
> +adds r1, r2, #42<br>
> +.Lbranch:<br>
> +movs r2, r3<br>
><br>
> Modified: llvm/trunk/test/MC/ARM/coff-relocations.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/coff-relocations.s?rev=297821&r1=297820&r2=297821&view=diff">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/coff-relocations.s?rev=297821&r1=297820&r2=297821&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/ARM/coff-relocations.s (original)<br>
> +++ llvm/trunk/test/MC/ARM/coff-relocations.s Wed Mar 15 05:21:23 2017<br>
> @@ -11,49 +11,49 @@<br>
> .global target<br>
> <br>
> .thumb_func<br>
> -branch24t:<br>
> - b target<br>
> -<br>
> -@ CHECK-ENCODING-LABEL: branch24t<br>
> -@ CHECK-ENCODING-NEXT: b.w #0<br>
> -<br>
> - .thumb_func<br>
> -branch20t:<br>
> - bcc target<br>
> -<br>
> -@ CHECK-ENCODING-LABEL: branch20t<br>
> -@ CHECK-ENCODING-NEXT: blo.w #0<br>
> -<br>
> - .thumb_func<br>
> -blx23t:<br>
> - bl target<br>
> -<br>
> -@ CHECK-ENCODING-LABEL: blx23t<br>
> -@ CHECK-ENCODING-NEXT: bl #0<br>
> -<br>
> - .thumb_func<br>
> +branch24t:<br>
> + b target<br>
> +<br>
> +@ CHECK-ENCODING-LABEL: branch24t:<br>
> +@ CHECK-ENCODING-NEXT: b.w #0<br>
> +<br>
> + .thumb_func<br>
> +branch20t:<br>
> + bcc target<br>
> +<br>
> +@ CHECK-ENCODING-LABEL: branch20t:<br>
> +@ CHECK-ENCODING-NEXT: blo.w #0<br>
> +<br>
> + .thumb_func<br>
> +blx23t:<br>
> + bl target<br>
> +<br>
> +@ CHECK-ENCODING-LABEL: blx23t:<br>
> +@ CHECK-ENCODING-NEXT: bl #0<br>
> +<br>
> + .thumb_func<br>
> mov32t:<br>
> movw r0, :lower16:target<br>
> - movt r0, :upper16:target<br>
> - blx r0<br>
> -<br>
> -@ CHECK-ENCODING-LABEL: mov32t<br>
> -@ CHECK-ENCODING-NEXT: movw r0, #0<br>
> -@ CHECK-ENCODING-NEXT: movt r0, #0<br>
> -@ CHECK-ENCODING-NEXT: blx r0<br>
> + movt r0, :upper16:target<br>
> + blx r0<br>
> +<br>
> +@ CHECK-ENCODING-LABEL: mov32t:<br>
> +@ CHECK-ENCODING-NEXT: movw r0, #0<br>
> +@ CHECK-ENCODING-NEXT: movt r0, #0<br>
> +@ CHECK-ENCODING-NEXT: blx r0<br>
> <br>
> .thumb_func<br>
> addr32:<br>
> ldr r0, .Laddr32<br>
> bx r0<br>
> trap<br>
> -.Laddr32:<br>
> - .long target<br>
> -<br>
> -@ CHECK-ENCODING-LABEL: addr32<br>
> -@ CHECK-ENCODING-NEXT: ldr r0, [pc, #4]<br>
> -@ CHECK-ENCODING-NEXT: bx r0<br>
> -@ CHECK-ENCODING-NEXT: trap<br>
> +.Laddr32:<br>
> + .long target<br>
> +<br>
> +@ CHECK-ENCODING-LABEL: addr32:<br>
> +@ CHECK-ENCODING-NEXT: ldr r0, [pc, #4]<br>
> +@ CHECK-ENCODING-NEXT: bx r0<br>
> +@ CHECK-ENCODING-NEXT: trap<br>
> @ CHECK-ENCODING-NEXT: movs r0, r0<br>
> @ CHECK-ENCODING-NEXT: movs r0, r0<br>
> <br>
> @@ -62,13 +62,13 @@ addr32nb:<br>
> ldr r0, .Laddr32nb<br>
> bx r0<br>
> trap<br>
> -.Laddr32nb:<br>
> - .long target(imgrel)<br>
> -<br>
> -@ CHECK-ENCODING-LABEL: addr32nb<br>
> -@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]<br>
> -@ CHECK-ENCODING-NEXT: bx r0<br>
> -@ CHECK-ENCODING-NEXT: trap<br>
> +.Laddr32nb:<br>
> + .long target(imgrel)<br>
> +<br>
> +@ CHECK-ENCODING-LABEL: addr32nb:<br>
> +@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]<br>
> +@ CHECK-ENCODING-NEXT: bx r0<br>
> +@ CHECK-ENCODING-NEXT: trap<br>
> @ CHECK-ENCODING-NEXT: movs r0, r0<br>
> @ CHECK-ENCODING-NEXT: movs r0, r0<br>
> <br>
> @@ -77,13 +77,13 @@ secrel:<br>
> ldr r0, .Lsecrel<br>
> bx r0<br>
> trap<br>
> -.Lsecrel:<br>
> - .long target(secrel32)<br>
> -<br>
> -@ CHECK-ENCODING-LABEL: secrel<br>
> -@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]<br>
> -@ CHECK-ENCODING-NEXT: bx r0<br>
> -@ CHECK-ENCODING-NEXT: trap<br>
> +.Lsecrel:<br>
> + .long target(secrel32)<br>
> +<br>
> +@ CHECK-ENCODING-LABEL: secrel:<br>
> +@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4]<br>
> +@ CHECK-ENCODING-NEXT: bx r0<br>
> +@ CHECK-ENCODING-NEXT: trap<br>
> @ CHECK-ENCODING-NEXT: movs r0, r0<br>
> @ CHECK-ENCODING-NEXT: movs r0, r0<br>
> <br>
><br>
><br>
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