<div dir="ltr">Will you also be restoring my fix for i256-add.ll?</div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Mon, Mar 13, 2017 at 5:34 PM, Nirav Dave via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: niravd<br>
Date: Mon Mar 13 19:34:14 2017<br>
New Revision: 297695<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=297695&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=297695&view=rev</a><br>
Log:<br>
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.<br>
<br>
Recommiting with compiler time improvements<br>
<br>
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.<br>
<br>
* Simplify Consecutive Merge Store Candidate Search<br>
<br>
Now that address aliasing is much less conservative, push through<br>
simplified store merging search and chain alias analysis which only<br>
checks for parallel stores through the chain subgraph. This is cleaner<br>
as the separation of non-interfering loads/stores from the<br>
store-merging logic.<br>
<br>
When merging stores search up the chain through a single load, and<br>
finds all possible stores by looking down from through a load and a<br>
TokenFactor to all stores visited.<br>
<br>
This improves the quality of the output SelectionDAG and the output<br>
Codegen (save perhaps for some ARM cases where we correctly constructs<br>
wider loads, but then promotes them to float operations which appear<br>
but requires more expensive constant generation).<br>
<br>
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)<br>
<br>
Additional Minor Changes:<br>
<br>
1. Finishes removing unused AliasLoad code<br>
<br>
2. Unifies the chain aggregation in the merged stores across code<br>
paths<br>
<br>
3. Re-add the Store node to the worklist after calling<br>
SimplifyDemandedBits.<br>
<br>
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is<br>
arbitrary, but seems sufficient to not cause regressions in<br>
tests.<br>
<br>
5. Remove Chain dependencies of Memory operations on CopyfromReg<br>
nodes as these are captured by data dependence<br>
<br>
6. Forward loads-store values through tokenfactors containing<br>
{CopyToReg,CopyFromReg} Values.<br>
<br>
7. Peephole to convert buildvector of extract_vector_elt to<br>
extract_subvector if possible (see<br>
CodeGen/AArch64/store-merge.<wbr>ll)<br>
<br>
8. Store merging for the ARM target is restricted to 32-bit as<br>
some in some contexts invalid 64-bit operations are being<br>
generated. This can be removed once appropriate checks are<br>
added.<br>
<br>
This finishes the change Matt Arsenault started in r246307 and<br>
jyknight's original patch.<br>
<br>
Many tests required some changes as memory operations are now<br>
reorderable, improving load-store forwarding. One test in<br>
particular is worth noting:<br>
<br>
CodeGen/PowerPC/ppc64-align-<wbr>long-double.ll - Improved load-store<br>
forwarding converts a load-store pair into a parallel store and<br>
a memory-realized bitcast of the same value. However, because we<br>
lose the sharing of the explicit and implicit store values we<br>
must create another local store. A similar transformation<br>
happens before SelectionDAG as well.<br>
<br>
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/<wbr>pr32108.ll<br>
Removed:<br>
llvm/trunk/test/CodeGen/X86/<wbr>combiner-aa-0.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>combiner-aa-1.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>pr18023.ll<br>
Modified:<br>
llvm/trunk/include/llvm/<wbr>Target/TargetLowering.h<br>
llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/lib/CodeGen/<wbr>TargetLoweringBase.cpp<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64ISelLowering.cpp<br>
llvm/trunk/lib/Target/ARM/<wbr>ARMISelLowering.h<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/argument-blocks.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-abi.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-memset-inline.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-variadic-aapcs.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/merge-store.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/vector_merge_dep_<wbr>check.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/debugger-insert-nops.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/insert_vector_elt.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/merge-stores.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/private-element-size.ll<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/si-triv-disjoint-mem-<wbr>access.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>2012-10-04-AAPCS-byval-align8.<wbr>ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>alloc-no-stack-realign.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>gpr-paired-spill.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>ifcvt10.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>illegal-bitfield-loadstore.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>static-addr-hoisting.ll<br>
llvm/trunk/test/CodeGen/BPF/<wbr>undef.ll<br>
llvm/trunk/test/CodeGen/<wbr>MSP430/Inst16mm.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>cconv/arguments-float.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>cconv/arguments-varargs.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>fastcc.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>load-store-left-right.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>micromips-li.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>mips64-f128-call.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>mips64-f128.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>mno-ldc1-sdc1.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>msa/f16-llvm-ir.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>msa/i5_ld_st.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_byval.ll<br>
llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_vararg.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/anon_aggr.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/complex-return.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/jaggedstructs.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/ppc64-align-long-<wbr>double.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/structsinmem.ll<br>
llvm/trunk/test/CodeGen/<wbr>PowerPC/structsinregs.ll<br>
llvm/trunk/test/CodeGen/<wbr>SystemZ/unaligned-01.ll<br>
llvm/trunk/test/CodeGen/Thumb/<wbr>2010-07-15-debugOrdering.ll<br>
llvm/trunk/test/CodeGen/Thumb/<wbr>stack-access.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>2010-09-17-SideEffectsInChain.<wbr>ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>2012-11-28-merge-store-alias.<wbr>ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>MergeConsecutiveStores.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>avx-vbroadcast.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>avx512-mask-op.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>chain_order.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>copy-eflags.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>dag-merge-fast-accesses.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>dont-trunc-store-double-to-<wbr>float.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>extractelement-legalization-<wbr>store-ordering.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>i256-add.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>i386-shrink-wrapping.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>live-range-nosubreg.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>longlong-deadload.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>merge-consecutive-loads-128.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>merge-consecutive-loads-256.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>merge-store-partially-alias-<wbr>loads.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>split-store.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>stores-merging.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>vector-compare-results.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-variable-128.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-variable-256.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>vectorcall.ll<br>
llvm/trunk/test/CodeGen/X86/<wbr>win32-eh.ll<br>
llvm/trunk/test/CodeGen/XCore/<wbr>varargs.ll<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>Target/TargetLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/Target/TargetLowering.h?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>Target/TargetLowering.h (original)<br>
+++ llvm/trunk/include/llvm/<wbr>Target/TargetLowering.h Mon Mar 13 19:34:14 2017<br>
@@ -363,6 +363,9 @@ public:<br>
return false;<br>
}<br>
<br>
+ /// Returns if it's reasonable to merge stores to MemVT size.<br>
+ virtual bool canMergeStoresTo(EVT MemVT) const { return true; }<br>
+<br>
/// \brief Return true if it is cheap to speculate a call to intrinsic cttz.<br>
virtual bool isCheapToSpeculateCttz() const {<br>
return false;<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/SelectionDAG/<wbr>DAGCombiner.cpp?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp Mon Mar 13 19:34:14 2017<br>
@@ -53,10 +53,6 @@ STATISTIC(SlicedLoads, "Number of load s<br>
<br>
namespace {<br>
static cl::opt<bool><br>
- CombinerAA("combiner-alias-<wbr>analysis", cl::Hidden,<br>
- cl::desc("Enable DAG combiner alias-analysis heuristics"));<br>
-<br>
- static cl::opt<bool><br>
CombinerGlobalAA("combiner-<wbr>global-alias-analysis", cl::Hidden,<br>
cl::desc("Enable DAG combiner's use of IR alias analysis"));<br>
<br>
@@ -133,6 +129,9 @@ namespace {<br>
/// Add to the worklist making sure its instance is at the back (next to be<br>
/// processed.)<br>
void AddToWorklist(SDNode *N) {<br>
+ assert(N->getOpcode() != ISD::DELETED_NODE &&<br>
+ "Deleted Node added to Worklist");<br>
+<br>
// Skip handle nodes as they can't usefully be combined and confuse the<br>
// zero-use deletion strategy.<br>
if (N->getOpcode() == ISD::HANDLENODE)<br>
@@ -177,6 +176,7 @@ namespace {<br>
void CommitTargetLoweringOpt(const TargetLowering::<wbr>TargetLoweringOpt &TLO);<br>
<br>
private:<br>
+ unsigned MaximumLegalStoreInBits;<br>
<br>
/// Check the specified integer node value to see if it can be simplified or<br>
/// if things it uses can be simplified by bit propagation.<br>
@@ -422,15 +422,12 @@ namespace {<br>
/// Holds a pointer to an LSBaseSDNode as well as information on where it<br>
/// is located in a sequence of memory operations connected by a chain.<br>
struct MemOpLink {<br>
- MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):<br>
- MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }<br>
+ MemOpLink(LSBaseSDNode *N, int64_t Offset)<br>
+ : MemNode(N), OffsetFromBase(Offset) {}<br>
// Ptr to the mem node.<br>
LSBaseSDNode *MemNode;<br>
// Offset from the base ptr.<br>
int64_t OffsetFromBase;<br>
- // What is the sequence number of this mem node.<br>
- // Lowest mem operand in the DAG starts at zero.<br>
- unsigned SequenceNum;<br>
};<br>
<br>
/// This is a helper function for visitMUL to check the profitability<br>
@@ -441,12 +438,6 @@ namespace {<br>
SDValue &AddNode,<br>
SDValue &ConstNode);<br>
<br>
- /// This is a helper function for MergeStoresOfConstantsOrVecElt<wbr>s. Returns a<br>
- /// constant build_vector of the stored constant values in Stores.<br>
- SDValue getMergedConstantVectorStore(<wbr>SelectionDAG &DAG, const SDLoc &SL,<br>
- ArrayRef<MemOpLink> Stores,<br>
- SmallVectorImpl<SDValue> &Chains,<br>
- EVT Ty) const;<br>
<br>
/// This is a helper function for visitAND and visitZERO_EXTEND. Returns<br>
/// true if the (and (load x) c) pattern matches an extload. ExtVT returns<br>
@@ -460,18 +451,15 @@ namespace {<br>
/// This is a helper function for MergeConsecutiveStores. When the source<br>
/// elements of the consecutive stores are all constants or all extracted<br>
/// vector elements, try to merge them into one larger store.<br>
- /// \return number of stores that were merged into a merged store (always<br>
- /// a prefix of \p StoreNode).<br>
- bool MergeStoresOfConstantsOrVecElt<wbr>s(<br>
- SmallVectorImpl<MemOpLink> &StoreNodes, EVT MemVT, unsigned NumStores,<br>
- bool IsConstantSrc, bool UseVector);<br>
+ /// \return True if a merged store was created.<br>
+ bool MergeStoresOfConstantsOrVecElt<wbr>s(SmallVectorImpl<MemOpLink> &StoreNodes,<br>
+ EVT MemVT, unsigned NumStores,<br>
+ bool IsConstantSrc, bool UseVector);<br>
<br>
/// This is a helper function for MergeConsecutiveStores.<br>
/// Stores that may be merged are placed in StoreNodes.<br>
- /// Loads that may alias with those stores are placed in AliasLoadNodes.<br>
- void getStoreMergeAndAliasCandidate<wbr>s(<br>
- StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,<br>
- SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes);<br>
+ void getStoreMergeCandidates(<wbr>StoreSDNode *St,<br>
+ SmallVectorImpl<MemOpLink> &StoreNodes);<br>
<br>
/// Helper function for MergeConsecutiveStores. Checks if<br>
/// Candidate stores have indirect dependency through their<br>
@@ -483,8 +471,7 @@ namespace {<br>
/// This optimization uses wide integers or vectors when possible.<br>
/// \return number of stores that were merged into a merged store (the<br>
/// affected nodes are stored as a prefix in \p StoreNodes).<br>
- bool MergeConsecutiveStores(<wbr>StoreSDNode *N,<br>
- SmallVectorImpl<MemOpLink> &StoreNodes);<br>
+ bool MergeConsecutiveStores(<wbr>StoreSDNode *N);<br>
<br>
/// \brief Try to transform a truncation where C is a constant:<br>
/// (trunc (and X, C)) -> (and (trunc X), (trunc C))<br>
@@ -499,6 +486,13 @@ namespace {<br>
: DAG(D), TLI(D.getTargetLoweringInfo())<wbr>, Level(BeforeLegalizeTypes),<br>
OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {<br>
ForCodeSize = DAG.getMachineFunction().<wbr>getFunction()->optForSize();<br>
+<br>
+ MaximumLegalStoreInBits = 0;<br>
+ for (MVT VT : MVT::all_valuetypes())<br>
+ if (EVT(VT).isSimple() && VT != MVT::Other &&<br>
+ TLI.isTypeLegal(EVT(VT)) &&<br>
+ VT.getSizeInBits() >= MaximumLegalStoreInBits)<br>
+ MaximumLegalStoreInBits = VT.getSizeInBits();<br>
}<br>
<br>
/// Runs the dag combiner on all nodes in the work list<br>
@@ -1589,7 +1583,7 @@ SDValue DAGCombiner::visitTokenFactor(<wbr>SD<br>
}<br>
<br>
SmallVector<SDNode *, 8> TFs; // List of token factors to visit.<br>
- SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.<br>
+ SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.<br>
SmallPtrSet<SDNode*, 16> SeenOps;<br>
bool Changed = false; // If we should replace this token factor.<br>
<br>
@@ -1633,6 +1627,86 @@ SDValue DAGCombiner::visitTokenFactor(<wbr>SD<br>
}<br>
}<br>
<br>
+ // Remove Nodes that are chained to another node in the list. Do so<br>
+ // by walking up chains breath-first stopping when we've seen<br>
+ // another operand. In general we must climb to the EntryNode, but we can exit<br>
+ // early if we find all remaining work is associated with just one operand as<br>
+ // no further pruning is possible.<br>
+<br>
+ // List of nodes to search through and original Ops from which they originate.<br>
+ SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;<br>
+ SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.<br>
+ SmallPtrSet<SDNode *, 16> SeenChains;<br>
+ bool DidPruneOps = false;<br>
+<br>
+ unsigned NumLeftToConsider = 0;<br>
+ for (const SDValue &Op : Ops) {<br>
+ Worklist.push_back(std::make_<wbr>pair(Op.getNode(), NumLeftToConsider++));<br>
+ OpWorkCount.push_back(1);<br>
+ }<br>
+<br>
+ auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {<br>
+ // If this is an Op, we can remove the op from the list. Remark any<br>
+ // search associated with it as from the current OpNumber.<br>
+ if (SeenOps.count(Op) != 0) {<br>
+ Changed = true;<br>
+ DidPruneOps = true;<br>
+ unsigned OrigOpNumber = 0;<br>
+ while (Ops[OrigOpNumber].getNode() != Op && OrigOpNumber < Ops.size())<br>
+ OrigOpNumber++;<br>
+ assert((OrigOpNumber != Ops.size()) &&<br>
+ "expected to find TokenFactor Operand");<br>
+ // Re-mark worklist from OrigOpNumber to OpNumber<br>
+ for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {<br>
+ if (Worklist[i].second == OrigOpNumber) {<br>
+ Worklist[i].second = OpNumber;<br>
+ }<br>
+ }<br>
+ OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];<br>
+ OpWorkCount[OrigOpNumber] = 0;<br>
+ NumLeftToConsider--;<br>
+ }<br>
+ // Add if it's a new chain<br>
+ if (SeenChains.insert(Op).second) {<br>
+ OpWorkCount[OpNumber]++;<br>
+ Worklist.push_back(std::make_<wbr>pair(Op, OpNumber));<br>
+ }<br>
+ };<br>
+<br>
+ for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {<br>
+ // We need at least be consider at least 2 Ops to prune.<br>
+ if (NumLeftToConsider <= 1)<br>
+ break;<br>
+ auto CurNode = Worklist[i].first;<br>
+ auto CurOpNumber = Worklist[i].second;<br>
+ assert((OpWorkCount[<wbr>CurOpNumber] > 0) &&<br>
+ "Node should not appear in worklist");<br>
+ switch (CurNode->getOpcode()) {<br>
+ case ISD::EntryToken:<br>
+ // Hitting EntryToken is the only way for the search to terminate without<br>
+ // hitting<br>
+ // another operand's search. Prevent us from marking this operand<br>
+ // considered.<br>
+ NumLeftToConsider++;<br>
+ break;<br>
+ case ISD::TokenFactor:<br>
+ for (const SDValue &Op : CurNode->op_values())<br>
+ AddToWorklist(i, Op.getNode(), CurOpNumber);<br>
+ break;<br>
+ case ISD::CopyFromReg:<br>
+ case ISD::CopyToReg:<br>
+ AddToWorklist(i, CurNode->getOperand(0).<wbr>getNode(), CurOpNumber);<br>
+ break;<br>
+ default:<br>
+ if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))<br>
+ AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);<br>
+ break;<br>
+ }<br>
+ OpWorkCount[CurOpNumber]--;<br>
+ if (OpWorkCount[CurOpNumber] == 0)<br>
+ NumLeftToConsider--;<br>
+ }<br>
+<br>
SDValue Result;<br>
<br>
// If we've changed things around then replace token factor.<br>
@@ -1641,15 +1715,22 @@ SDValue DAGCombiner::visitTokenFactor(<wbr>SD<br>
// The entry token is the only possible outcome.<br>
Result = DAG.getEntryNode();<br>
} else {<br>
- // New and improved token factor.<br>
- Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);<br>
+ if (DidPruneOps) {<br>
+ SmallVector<SDValue, 8> PrunedOps;<br>
+ //<br>
+ for (const SDValue &Op : Ops) {<br>
+ if (SeenChains.count(Op.getNode()<wbr>) == 0)<br>
+ PrunedOps.push_back(Op);<br>
+ }<br>
+ Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, PrunedOps);<br>
+ } else {<br>
+ Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);<br>
+ }<br>
}<br>
<br>
- // Add users to worklist if AA is enabled, since it may introduce<br>
- // a lot of new chained token factors while removing memory deps.<br>
- bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA<br>
- : DAG.getSubtarget().useAA();<br>
- return CombineTo(N, Result, UseAA /*add to worklist*/);<br>
+ // Add users to worklist, since we may introduce a lot of new<br>
+ // chained token factors while removing memory deps.<br>
+ return CombineTo(N, Result, true /*add to worklist*/);<br>
}<br>
<br>
return Result;<br>
@@ -6792,6 +6873,9 @@ SDValue DAGCombiner::CombineExtLoad(<wbr>SDNo<br>
SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);<br>
SDValue NewValue = DAG.getNode(ISD::CONCAT_<wbr>VECTORS, DL, DstVT, Loads);<br>
<br>
+ // Simplify TF.<br>
+ AddToWorklist(NewChain.<wbr>getNode());<br>
+<br>
CombineTo(N, NewValue);<br>
<br>
// Replace uses of the original load (before extension)<br>
@@ -10947,7 +11031,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N<br>
dbgs() << "\n");<br>
WorklistRemover DeadNodes(*this);<br>
DAG.ReplaceAllUsesOfValueWith(<wbr>SDValue(N, 1), Chain);<br>
-<br>
+ AddUsersToWorklist(Chain.<wbr>getNode());<br>
if (N->use_empty())<br>
deleteAndRecombine(N);<br>
<br>
@@ -11000,7 +11084,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N<br>
StoreSDNode *PrevST = cast<StoreSDNode>(Chain);<br>
if (PrevST->getBasePtr() == Ptr &&<br>
PrevST->getValue().<wbr>getValueType() == N->getValueType(0))<br>
- return CombineTo(N, Chain.getOperand(1), Chain);<br>
+ return CombineTo(N, PrevST->getOperand(1), Chain);<br>
}<br>
}<br>
<br>
@@ -11018,14 +11102,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N<br>
}<br>
}<br>
<br>
- bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA<br>
- : DAG.getSubtarget().useAA();<br>
-#ifndef NDEBUG<br>
- if (CombinerAAOnlyFunc.<wbr>getNumOccurrences() &&<br>
- CombinerAAOnlyFunc != DAG.getMachineFunction().<wbr>getName())<br>
- UseAA = false;<br>
-#endif<br>
- if (UseAA && LD->isUnindexed()) {<br>
+ if (LD->isUnindexed()) {<br>
// Walk up chain skipping non-aliasing memory nodes.<br>
SDValue BetterChain = FindBetterChain(N, Chain);<br>
<br>
@@ -11607,6 +11684,7 @@ bool DAGCombiner::SliceUpLoad(<wbr>SDNode *N)<br>
SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,<br>
ArgChains);<br>
DAG.ReplaceAllUsesOfValueWith(<wbr>SDValue(N, 1), Chain);<br>
+ AddToWorklist(Chain.getNode())<wbr>;<br>
return true;<br>
}<br>
<br>
@@ -12000,20 +12078,6 @@ bool DAGCombiner::<wbr>isMulAddWithConstProfi<br>
return false;<br>
}<br>
<br>
-SDValue DAGCombiner::<wbr>getMergedConstantVectorStore(<br>
- SelectionDAG &DAG, const SDLoc &SL, ArrayRef<MemOpLink> Stores,<br>
- SmallVectorImpl<SDValue> &Chains, EVT Ty) const {<br>
- SmallVector<SDValue, 8> BuildVector;<br>
-<br>
- for (unsigned I = 0, E = Ty.getVectorNumElements(); I != E; ++I) {<br>
- StoreSDNode *St = cast<StoreSDNode>(Stores[I].<wbr>MemNode);<br>
- Chains.push_back(St->getChain(<wbr>));<br>
- BuildVector.push_back(St-><wbr>getValue());<br>
- }<br>
-<br>
- return DAG.getBuildVector(Ty, SL, BuildVector);<br>
-}<br>
-<br>
bool DAGCombiner::<wbr>MergeStoresOfConstantsOrVecElt<wbr>s(<br>
SmallVectorImpl<MemOpLink> &StoreNodes, EVT MemVT,<br>
unsigned NumStores, bool IsConstantSrc, bool UseVector) {<br>
@@ -12022,22 +12086,8 @@ bool DAGCombiner::<wbr>MergeStoresOfConstants<br>
return false;<br>
<br>
int64_t ElementSizeBytes = MemVT.getSizeInBits() / 8;<br>
- LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;<br>
- unsigned LatestNodeUsed = 0;<br>
-<br>
- for (unsigned i=0; i < NumStores; ++i) {<br>
- // Find a chain for the new wide-store operand. Notice that some<br>
- // of the store nodes that we found may not be selected for inclusion<br>
- // in the wide store. The chain we use needs to be the chain of the<br>
- // latest store node which is *used* and replaced by the wide store.<br>
- if (StoreNodes[i].SequenceNum < StoreNodes[LatestNodeUsed].<wbr>SequenceNum)<br>
- LatestNodeUsed = i;<br>
- }<br>
-<br>
- SmallVector<SDValue, 8> Chains;<br>
<br>
// The latest Node in the DAG.<br>
- LSBaseSDNode *LatestOp = StoreNodes[LatestNodeUsed].<wbr>MemNode;<br>
SDLoc DL(StoreNodes[0].MemNode);<br>
<br>
SDValue StoredVal;<br>
@@ -12053,7 +12103,18 @@ bool DAGCombiner::<wbr>MergeStoresOfConstants<br>
assert(TLI.isTypeLegal(Ty) && "Illegal vector store");<br>
<br>
if (IsConstantSrc) {<br>
- StoredVal = getMergedConstantVectorStore(<wbr>DAG, DL, StoreNodes, Chains, Ty);<br>
+ SmallVector<SDValue, 8> BuildVector;<br>
+ for (unsigned I = 0, E = Ty.getVectorNumElements(); I != E; ++I) {<br>
+ StoreSDNode *St = cast<StoreSDNode>(StoreNodes[<wbr>I].MemNode);<br>
+ SDValue Val = St->getValue();<br>
+ if (MemVT.getScalarType().<wbr>isInteger())<br>
+ if (auto *CFP = dyn_cast<ConstantFPSDNode>(St-<wbr>>getValue()))<br>
+ Val = DAG.getConstant(<br>
+ (uint32_t)CFP->getValueAPF().<wbr>bitcastToAPInt().getZExtValue(<wbr>),<br>
+ SDLoc(CFP), MemVT);<br>
+ BuildVector.push_back(Val);<br>
+ }<br>
+ StoredVal = DAG.getBuildVector(Ty, DL, BuildVector);<br>
} else {<br>
SmallVector<SDValue, 8> Ops;<br>
for (unsigned i = 0; i < NumStores; ++i) {<br>
@@ -12063,7 +12124,6 @@ bool DAGCombiner::<wbr>MergeStoresOfConstants<br>
if (Val.getValueType() != MemVT)<br>
return false;<br>
Ops.push_back(Val);<br>
- Chains.push_back(St->getChain(<wbr>));<br>
}<br>
<br>
// Build the extracted vector elements back into a vector.<br>
@@ -12083,7 +12143,6 @@ bool DAGCombiner::<wbr>MergeStoresOfConstants<br>
for (unsigned i = 0; i < NumStores; ++i) {<br>
unsigned Idx = IsLE ? (NumStores - 1 - i) : i;<br>
StoreSDNode *St = cast<StoreSDNode>(StoreNodes[<wbr>Idx].MemNode);<br>
- Chains.push_back(St->getChain(<wbr>));<br>
<br>
SDValue Val = St->getValue();<br>
StoreInt <<= ElementSizeBytes * 8;<br>
@@ -12101,54 +12160,36 @@ bool DAGCombiner::<wbr>MergeStoresOfConstants<br>
StoredVal = DAG.getConstant(StoreInt, DL, StoreTy);<br>
}<br>
<br>
- assert(!Chains.empty());<br>
+ SmallVector<SDValue, 8> Chains;<br>
+<br>
+ // Gather all Chains we're inheriting. As generally all chains are<br>
+ // equal, do minor check to remove obvious redundancies.<br>
+ Chains.push_back(StoreNodes[0]<wbr>.MemNode->getChain());<br>
+ for (unsigned i = 1; i < NumStores; ++i)<br>
+ if (StoreNodes[0].MemNode-><wbr>getChain() != StoreNodes[i].MemNode-><wbr>getChain())<br>
+ Chains.push_back(StoreNodes[i]<wbr>.MemNode->getChain());<br>
<br>
+ LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;<br>
SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);<br>
SDValue NewStore = DAG.getStore(NewChain, DL, StoredVal,<br>
FirstInChain->getBasePtr(),<br>
FirstInChain->getPointerInfo()<wbr>,<br>
FirstInChain->getAlignment());<br>
<br>
- bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA<br>
- : DAG.getSubtarget().useAA();<br>
- if (UseAA) {<br>
- // Replace all merged stores with the new store.<br>
- for (unsigned i = 0; i < NumStores; ++i)<br>
- CombineTo(StoreNodes[i].<wbr>MemNode, NewStore);<br>
- } else {<br>
- // Replace the last store with the new store.<br>
- CombineTo(LatestOp, NewStore);<br>
- // Erase all other stores.<br>
- for (unsigned i = 0; i < NumStores; ++i) {<br>
- if (StoreNodes[i].MemNode == LatestOp)<br>
- continue;<br>
- StoreSDNode *St = cast<StoreSDNode>(StoreNodes[<wbr>i].MemNode);<br>
- // ReplaceAllUsesWith will replace all uses that existed when it was<br>
- // called, but graph optimizations may cause new ones to appear. For<br>
- // example, the case in pr14333 looks like<br>
- //<br>
- // St's chain -> St -> another store -> X<br>
- //<br>
- // And the only difference from St to the other store is the chain.<br>
- // When we change it's chain to be St's chain they become identical,<br>
- // get CSEed and the net result is that X is now a use of St.<br>
- // Since we know that St is redundant, just iterate.<br>
- while (!St->use_empty())<br>
- DAG.ReplaceAllUsesWith(<wbr>SDValue(St, 0), St->getChain());<br>
- deleteAndRecombine(St);<br>
- }<br>
- }<br>
+ // Replace all merged stores with the new store.<br>
+ for (unsigned i = 0; i < NumStores; ++i)<br>
+ CombineTo(StoreNodes[i].<wbr>MemNode, NewStore);<br>
<br>
- StoreNodes.erase(StoreNodes.<wbr>begin() + NumStores, StoreNodes.end());<br>
+ AddToWorklist(NewChain.<wbr>getNode());<br>
return true;<br>
}<br>
<br>
-void DAGCombiner::<wbr>getStoreMergeAndAliasCandidate<wbr>s(<br>
- StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,<br>
- SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes) {<br>
+void DAGCombiner::<wbr>getStoreMergeCandidates(<br>
+ StoreSDNode *St, SmallVectorImpl<MemOpLink> &StoreNodes) {<br>
// This holds the base pointer, index, and the offset in bytes from the base<br>
// pointer.<br>
BaseIndexOffset BasePtr = BaseIndexOffset::match(St-><wbr>getBasePtr(), DAG);<br>
+ EVT MemVT = St->getMemoryVT();<br>
<br>
// We must have a base and an offset.<br>
if (!BasePtr.Base.getNode())<br>
@@ -12158,104 +12199,70 @@ void DAGCombiner::<wbr>getStoreMergeAndAliasC<br>
if (BasePtr.Base.isUndef())<br>
return;<br>
<br>
- // Walk up the chain and look for nodes with offsets from the same<br>
- // base pointer. Stop when reaching an instruction with a different kind<br>
- // or instruction which has a different base pointer.<br>
- EVT MemVT = St->getMemoryVT();<br>
- unsigned Seq = 0;<br>
- StoreSDNode *Index = St;<br>
-<br>
-<br>
- bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA<br>
- : DAG.getSubtarget().useAA();<br>
-<br>
- if (UseAA) {<br>
- // Look at other users of the same chain. Stores on the same chain do not<br>
- // alias. If combiner-aa is enabled, non-aliasing stores are canonicalized<br>
- // to be on the same chain, so don't bother looking at adjacent chains.<br>
-<br>
- SDValue Chain = St->getChain();<br>
- for (auto I = Chain->use_begin(), E = Chain->use_end(); I != E; ++I) {<br>
- if (StoreSDNode *OtherST = dyn_cast<StoreSDNode>(*I)) {<br>
- if (I.getOperandNo() != 0)<br>
- continue;<br>
-<br>
- if (OtherST->isVolatile() || OtherST->isIndexed())<br>
- continue;<br>
-<br>
- if (OtherST->getMemoryVT() != MemVT)<br>
- continue;<br>
-<br>
- BaseIndexOffset Ptr = BaseIndexOffset::match(<wbr>OtherST->getBasePtr(), DAG);<br>
-<br>
- if (Ptr.equalBaseIndex(BasePtr))<br>
- StoreNodes.push_back(<wbr>MemOpLink(OtherST, Ptr.Offset, Seq++));<br>
- }<br>
- }<br>
-<br>
- return;<br>
- }<br>
-<br>
- while (Index) {<br>
- // If the chain has more than one use, then we can't reorder the mem ops.<br>
- if (Index != St && !SDValue(Index, 0)->hasOneUse())<br>
- break;<br>
-<br>
- // Find the base pointer and offset for this memory node.<br>
- BaseIndexOffset Ptr = BaseIndexOffset::match(Index-><wbr>getBasePtr(), DAG);<br>
-<br>
- // Check that the base pointer is the same as the original one.<br>
- if (!Ptr.equalBaseIndex(BasePtr))<br>
- break;<br>
+ // We looking for a root node which is an ancestor to all mergable<br>
+ // stores. We search up through a load, to our root and then down<br>
+ // through all children. For instance we will find Store{1,2,3} if<br>
+ // St is Store1, Store2. or Store3 where the root is not a load<br>
+ // which always true for nonvolatile ops. TODO: Expand<br>
+ // the search to find all valid candidates through multiple layers of loads.<br>
+ //<br>
+ // Root<br>
+ // |-------|-------|<br>
+ // Load Load Store3<br>
+ // | |<br>
+ // Store1 Store2<br>
+ //<br>
+ // FIXME: We should be able to climb and<br>
+ // descend TokenFactors to find candidates as well.<br>
<br>
- // The memory operands must not be volatile.<br>
- if (Index->isVolatile() || Index->isIndexed())<br>
- break;<br>
+ SDNode *RootNode = (St->getChain()).getNode();<br>
<br>
- // No truncation.<br>
- if (Index->isTruncatingStore())<br>
- break;<br>
+ // Set of Parents of Candidates<br>
+ std::set<SDNode *> CandidateParents;<br>
<br>
- // The stored memory type must be the same.<br>
- if (Index->getMemoryVT() != MemVT)<br>
- break;<br>
-<br>
- // We do not allow under-aligned stores in order to prevent<br>
- // overriding stores. NOTE: this is a bad hack. Alignment SHOULD<br>
- // be irrelevant here; what MATTERS is that we not move memory<br>
- // operations that potentially overlap past each-other.<br>
- if (Index->getAlignment() < MemVT.getStoreSize())<br>
- break;<br>
+ if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(RootNode)<wbr>) {<br>
+ RootNode = Ldn->getChain().getNode();<br>
+ for (auto I = RootNode->use_begin(), E = RootNode->use_end(); I != E; ++I)<br>
+ if (I.getOperandNo() == 0 && isa<LoadSDNode>(*I)) // walk down chain<br>
+ CandidateParents.insert(*I);<br>
+ } else<br>
+ CandidateParents.insert(<wbr>RootNode);<br>
<br>
- // We found a potential memory operand to merge.<br>
- StoreNodes.push_back(<wbr>MemOpLink(Index, Ptr.Offset, Seq++));<br>
+ bool IsLoadSrc = isa<LoadSDNode>(St->getValue()<wbr>);<br>
+ bool IsConstantSrc = isa<ConstantSDNode>(St-><wbr>getValue()) ||<br>
+ isa<ConstantFPSDNode>(St-><wbr>getValue());<br>
+ bool IsExtractVecSrc =<br>
+ (St->getValue().getOpcode() == ISD::EXTRACT_VECTOR_ELT ||<br>
+ St->getValue().getOpcode() == ISD::EXTRACT_SUBVECTOR);<br>
+ auto CorrectValueKind = [&](StoreSDNode *Other) -> bool {<br>
+ if (IsLoadSrc)<br>
+ return isa<LoadSDNode>(Other-><wbr>getValue());<br>
+ if (IsConstantSrc)<br>
+ return (isa<ConstantSDNode>(Other-><wbr>getValue()) ||<br>
+ isa<ConstantFPSDNode>(Other-><wbr>getValue()));<br>
+ if (IsExtractVecSrc)<br>
+ return (Other->getValue().getOpcode() == ISD::EXTRACT_VECTOR_ELT ||<br>
+ Other->getValue().getOpcode() == ISD::EXTRACT_SUBVECTOR);<br>
+ return false;<br>
+ };<br>
<br>
- // Find the next memory operand in the chain. If the next operand in the<br>
- // chain is a store then move up and continue the scan with the next<br>
- // memory operand. If the next operand is a load save it and use alias<br>
- // information to check if it interferes with anything.<br>
- SDNode *NextInChain = Index->getChain().getNode();<br>
- while (1) {<br>
- if (StoreSDNode *STn = dyn_cast<StoreSDNode>(<wbr>NextInChain)) {<br>
- // We found a store node. Use it for the next iteration.<br>
- Index = STn;<br>
- break;<br>
- } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(<wbr>NextInChain)) {<br>
- if (Ldn->isVolatile()) {<br>
- Index = nullptr;<br>
- break;<br>
+ // check all parents of mergable children<br>
+ for (auto P = CandidateParents.begin(); P != CandidateParents.end(); ++P)<br>
+ for (auto I = (*P)->use_begin(), E = (*P)->use_end(); I != E; ++I)<br>
+ if (I.getOperandNo() == 0)<br>
+ if (StoreSDNode *OtherST = dyn_cast<StoreSDNode>(*I)) {<br>
+ if (OtherST->isVolatile() || OtherST->isIndexed())<br>
+ continue;<br>
+ // We can merge constant floats to equivalent integers<br>
+ if (OtherST->getMemoryVT() != MemVT)<br>
+ if (!(MemVT.isInteger() && MemVT.bitsEq(OtherST-><wbr>getMemoryVT()) &&<br>
+ isa<ConstantFPSDNode>(OtherST-<wbr>>getValue())))<br>
+ continue;<br>
+ BaseIndexOffset Ptr =<br>
+ BaseIndexOffset::match(<wbr>OtherST->getBasePtr(), DAG);<br>
+ if (Ptr.equalBaseIndex(BasePtr) && CorrectValueKind(OtherST))<br>
+ StoreNodes.push_back(<wbr>MemOpLink(OtherST, Ptr.Offset));<br>
}<br>
-<br>
- // Save the load node for later. Continue the scan.<br>
- AliasLoadNodes.push_back(Ldn);<br>
- NextInChain = Ldn->getChain().getNode();<br>
- continue;<br>
- } else {<br>
- Index = nullptr;<br>
- break;<br>
- }<br>
- }<br>
- }<br>
}<br>
<br>
// We need to check that merging these stores does not cause a loop<br>
@@ -12282,13 +12289,16 @@ bool DAGCombiner::<wbr>checkMergeStoreCandida<br>
return true;<br>
}<br>
<br>
-bool DAGCombiner::<wbr>MergeConsecutiveStores(<br>
- StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes) {<br>
+bool DAGCombiner::<wbr>MergeConsecutiveStores(<wbr>StoreSDNode *St) {<br>
if (OptLevel == CodeGenOpt::None)<br>
return false;<br>
<br>
EVT MemVT = St->getMemoryVT();<br>
int64_t ElementSizeBytes = MemVT.getSizeInBits() / 8;<br>
+<br>
+ if (MemVT.getSizeInBits() * 2 > MaximumLegalStoreInBits)<br>
+ return false;<br>
+<br>
bool NoVectors = DAG.getMachineFunction().<wbr>getFunction()->hasFnAttribute(<br>
Attribute::NoImplicitFloat);<br>
<br>
@@ -12317,145 +12327,136 @@ bool DAGCombiner::<wbr>MergeConsecutiveStores<br>
if (MemVT.isVector() && IsLoadSrc)<br>
return false;<br>
<br>
- // Only look at ends of store sequences.<br>
- SDValue Chain = SDValue(St, 0);<br>
- if (Chain->hasOneUse() && Chain->use_begin()->getOpcode(<wbr>) == ISD::STORE)<br>
- return false;<br>
-<br>
- // Save the LoadSDNodes that we find in the chain.<br>
- // We need to make sure that these nodes do not interfere with<br>
- // any of the store nodes.<br>
- SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;<br>
-<br>
- getStoreMergeAndAliasCandidate<wbr>s(St, StoreNodes, AliasLoadNodes);<br>
+ SmallVector<MemOpLink, 8> StoreNodes;<br>
+ // Find potential store merge candidates by searching through chain sub-DAG<br>
+ getStoreMergeCandidates(St, StoreNodes);<br>
<br>
// Check if there is anything to merge.<br>
if (StoreNodes.size() < 2)<br>
return false;<br>
<br>
- // only do dependence check in AA case<br>
- bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA<br>
- : DAG.getSubtarget().useAA();<br>
- if (UseAA && !<wbr>checkMergeStoreCandidatesForDe<wbr>pendencies(StoreNodes))<br>
+ // Check that we can merge these candidates without causing a cycle<br>
+ if (!<wbr>checkMergeStoreCandidatesForDe<wbr>pendencies(StoreNodes))<br>
return false;<br>
<br>
// Sort the memory operands according to their distance from the<br>
- // base pointer. As a secondary criteria: make sure stores coming<br>
- // later in the code come first in the list. This is important for<br>
- // the non-UseAA case, because we're merging stores into the FINAL<br>
- // store along a chain which potentially contains aliasing stores.<br>
- // Thus, if there are multiple stores to the same address, the last<br>
- // one can be considered for merging but not the others.<br>
+ // base pointer.<br>
std::sort(StoreNodes.begin(), StoreNodes.end(),<br>
[](MemOpLink LHS, MemOpLink RHS) {<br>
- return LHS.OffsetFromBase < RHS.OffsetFromBase ||<br>
- (LHS.OffsetFromBase == RHS.OffsetFromBase &&<br>
- LHS.SequenceNum < RHS.SequenceNum);<br>
- });<br>
+ return LHS.OffsetFromBase < RHS.OffsetFromBase;<br>
+ });<br>
<br>
// Scan the memory operations on the chain and find the first non-consecutive<br>
// store memory address.<br>
- unsigned LastConsecutiveStore = 0;<br>
+ unsigned NumConsecutiveStores = 0;<br>
int64_t StartAddress = StoreNodes[0].OffsetFromBase;<br>
- for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {<br>
-<br>
- // Check that the addresses are consecutive starting from the second<br>
- // element in the list of stores.<br>
- if (i > 0) {<br>
- int64_t CurrAddress = StoreNodes[i].OffsetFromBase;<br>
- if (CurrAddress - StartAddress != (ElementSizeBytes * i))<br>
- break;<br>
- }<br>
<br>
- // Check if this store interferes with any of the loads that we found.<br>
- // If we find a load that alias with this store. Stop the sequence.<br>
- if (any_of(AliasLoadNodes, [&](LSBaseSDNode *Ldn) {<br>
- return isAlias(Ldn, StoreNodes[i].MemNode);<br>
- }))<br>
+ // Check that the addresses are consecutive starting from the second<br>
+ // element in the list of stores.<br>
+ for (unsigned i = 1, e = StoreNodes.size(); i < e; ++i) {<br>
+ int64_t CurrAddress = StoreNodes[i].OffsetFromBase;<br>
+ if (CurrAddress - StartAddress != (ElementSizeBytes * i))<br>
break;<br>
-<br>
- // Mark this node as useful.<br>
- LastConsecutiveStore = i;<br>
+ NumConsecutiveStores = i + 1;<br>
}<br>
<br>
+ if (NumConsecutiveStores < 2)<br>
+ return false;<br>
+<br>
// The node with the lowest store address.<br>
- LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;<br>
- unsigned FirstStoreAS = FirstInChain->getAddressSpace(<wbr>);<br>
- unsigned FirstStoreAlign = FirstInChain->getAlignment();<br>
LLVMContext &Context = *DAG.getContext();<br>
const DataLayout &DL = DAG.getDataLayout();<br>
<br>
// Store the constants into memory as one consecutive store.<br>
if (IsConstantSrc) {<br>
- unsigned LastLegalType = 0;<br>
- unsigned LastLegalVectorType = 0;<br>
- bool NonZero = false;<br>
- for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {<br>
- StoreSDNode *St = cast<StoreSDNode>(StoreNodes[<wbr>i].MemNode);<br>
- SDValue StoredVal = St->getValue();<br>
-<br>
- if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(<wbr>StoredVal)) {<br>
- NonZero |= !C->isNullValue();<br>
- } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(<wbr>StoredVal)) {<br>
- NonZero |= !C->getConstantFPValue()-><wbr>isNullValue();<br>
- } else {<br>
- // Non-constant.<br>
- break;<br>
- }<br>
+ bool RV = false;<br>
+ while (NumConsecutiveStores > 1) {<br>
+ LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;<br>
+ unsigned FirstStoreAS = FirstInChain->getAddressSpace(<wbr>);<br>
+ unsigned FirstStoreAlign = FirstInChain->getAlignment();<br>
+ unsigned LastLegalType = 0;<br>
+ unsigned LastLegalVectorType = 0;<br>
+ bool NonZero = false;<br>
+ for (unsigned i = 0; i < NumConsecutiveStores; ++i) {<br>
+ StoreSDNode *ST = cast<StoreSDNode>(StoreNodes[<wbr>i].MemNode);<br>
+ SDValue StoredVal = ST->getValue();<br>
+<br>
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(<wbr>StoredVal)) {<br>
+ NonZero |= !C->isNullValue();<br>
+ } else if (ConstantFPSDNode *C =<br>
+ dyn_cast<ConstantFPSDNode>(<wbr>StoredVal)) {<br>
+ NonZero |= !C->getConstantFPValue()-><wbr>isNullValue();<br>
+ } else {<br>
+ // Non-constant.<br>
+ break;<br>
+ }<br>
<br>
- // Find a legal type for the constant store.<br>
- unsigned SizeInBits = (i+1) * ElementSizeBytes * 8;<br>
- EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits);<br>
- bool IsFast;<br>
- if (TLI.isTypeLegal(StoreTy) &&<br>
- TLI.allowsMemoryAccess(<wbr>Context, DL, StoreTy, FirstStoreAS,<br>
- FirstStoreAlign, &IsFast) && IsFast) {<br>
- LastLegalType = i+1;<br>
- // Or check whether a truncstore is legal.<br>
- } else if (TLI.getTypeAction(Context, StoreTy) ==<br>
- TargetLowering::<wbr>TypePromoteInteger) {<br>
- EVT LegalizedStoredValueTy =<br>
- TLI.getTypeToTransformTo(<wbr>Context, StoredVal.getValueType());<br>
- if (TLI.isTruncStoreLegal(<wbr>LegalizedStoredValueTy, StoreTy) &&<br>
- TLI.allowsMemoryAccess(<wbr>Context, DL, LegalizedStoredValueTy,<br>
- FirstStoreAS, FirstStoreAlign, &IsFast) &&<br>
+ // Find a legal type for the constant store.<br>
+ unsigned SizeInBits = (i + 1) * ElementSizeBytes * 8;<br>
+ EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits);<br>
+ bool IsFast = false;<br>
+ if (TLI.isTypeLegal(StoreTy) &&<br>
+ TLI.allowsMemoryAccess(<wbr>Context, DL, StoreTy, FirstStoreAS,<br>
+ FirstStoreAlign, &IsFast) &&<br>
IsFast) {<br>
LastLegalType = i + 1;<br>
+ // Or check whether a truncstore is legal.<br>
+ } else if (TLI.getTypeAction(Context, StoreTy) ==<br>
+ TargetLowering::<wbr>TypePromoteInteger) {<br>
+ EVT LegalizedStoredValueTy =<br>
+ TLI.getTypeToTransformTo(<wbr>Context, StoredVal.getValueType());<br>
+ if (TLI.isTruncStoreLegal(<wbr>LegalizedStoredValueTy, StoreTy) &&<br>
+ TLI.allowsMemoryAccess(<wbr>Context, DL, LegalizedStoredValueTy,<br>
+ FirstStoreAS, FirstStoreAlign, &IsFast) &&<br>
+ IsFast) {<br>
+ LastLegalType = i + 1;<br>
+ }<br>
}<br>
- }<br>
<br>
- // We only use vectors if the constant is known to be zero or the target<br>
- // allows it and the function is not marked with the noimplicitfloat<br>
- // attribute.<br>
- if ((!NonZero || TLI.<wbr>storeOfVectorConstantIsCheap(<wbr>MemVT, i+1,<br>
- FirstStoreAS)) &&<br>
- !NoVectors) {<br>
- // Find a legal type for the vector store.<br>
- EVT Ty = EVT::getVectorVT(Context, MemVT, i+1);<br>
- if (TLI.isTypeLegal(Ty) &&<br>
- TLI.allowsMemoryAccess(<wbr>Context, DL, Ty, FirstStoreAS,<br>
- FirstStoreAlign, &IsFast) && IsFast)<br>
- LastLegalVectorType = i + 1;<br>
+ // We only use vectors if the constant is known to be zero or the target<br>
+ // allows it and the function is not marked with the noimplicitfloat<br>
+ // attribute.<br>
+ if ((!NonZero ||<br>
+ TLI.<wbr>storeOfVectorConstantIsCheap(<wbr>MemVT, i + 1, FirstStoreAS)) &&<br>
+ !NoVectors) {<br>
+ // Find a legal type for the vector store.<br>
+ EVT Ty = EVT::getVectorVT(Context, MemVT, i + 1);<br>
+ if (TLI.isTypeLegal(Ty) && TLI.canMergeStoresTo(Ty) &&<br>
+ TLI.allowsMemoryAccess(<wbr>Context, DL, Ty, FirstStoreAS,<br>
+ FirstStoreAlign, &IsFast) &&<br>
+ IsFast)<br>
+ LastLegalVectorType = i + 1;<br>
+ }<br>
}<br>
- }<br>
<br>
- // Check if we found a legal integer type to store.<br>
- if (LastLegalType == 0 && LastLegalVectorType == 0)<br>
- return false;<br>
+ // Check if we found a legal integer type that creates a meaningful merge.<br>
+ if (LastLegalType < 2 && LastLegalVectorType < 2)<br>
+ break;<br>
<br>
- bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;<br>
- unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;<br>
+ bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;<br>
+ unsigned NumElem = (UseVector) ? LastLegalVectorType : LastLegalType;<br>
<br>
- return MergeStoresOfConstantsOrVecElt<wbr>s(StoreNodes, MemVT, NumElem,<br>
- true, UseVector);<br>
+ bool Merged = MergeStoresOfConstantsOrVecElt<wbr>s(StoreNodes, MemVT, NumElem,<br>
+ true, UseVector);<br>
+ if (!Merged)<br>
+ break;<br>
+ // Remove merged stores for next iteration.<br>
+ StoreNodes.erase(StoreNodes.<wbr>begin(), StoreNodes.begin() + NumElem);<br>
+ RV = true;<br>
+ NumConsecutiveStores -= NumElem;<br>
+ }<br>
+ return RV;<br>
}<br>
<br>
// When extracting multiple vector elements, try to store them<br>
// in one vector store rather than a sequence of scalar stores.<br>
if (IsExtractVecSrc) {<br>
+ LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;<br>
+ unsigned FirstStoreAS = FirstInChain->getAddressSpace(<wbr>);<br>
+ unsigned FirstStoreAlign = FirstInChain->getAlignment();<br>
unsigned NumStoresToMerge = 0;<br>
bool IsVec = MemVT.isVector();<br>
- for (unsigned i = 0; i < LastConsecutiveStore + 1; ++i) {<br>
+ for (unsigned i = 0; i < NumConsecutiveStores; ++i) {<br>
StoreSDNode *St = cast<StoreSDNode>(StoreNodes[<wbr>i].MemNode);<br>
unsigned StoreValOpcode = St->getValue().getOpcode();<br>
// This restriction could be loosened.<br>
@@ -12495,7 +12496,7 @@ bool DAGCombiner::<wbr>MergeConsecutiveStores<br>
// Find acceptable loads. Loads need to have the same chain (token factor),<br>
// must not be zext, volatile, indexed, and they must be consecutive.<br>
BaseIndexOffset LdBasePtr;<br>
- for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {<br>
+ for (unsigned i = 0; i < NumConsecutiveStores; ++i) {<br>
StoreSDNode *St = cast<StoreSDNode>(StoreNodes[<wbr>i].MemNode);<br>
LoadSDNode *Ld = dyn_cast<LoadSDNode>(St-><wbr>getValue());<br>
if (!Ld) break;<br>
@@ -12528,7 +12529,7 @@ bool DAGCombiner::<wbr>MergeConsecutiveStores<br>
}<br>
<br>
// We found a potential memory operand to merge.<br>
- LoadNodes.push_back(MemOpLink(<wbr>Ld, LdPtr.Offset, 0));<br>
+ LoadNodes.push_back(MemOpLink(<wbr>Ld, LdPtr.Offset));<br>
}<br>
<br>
if (LoadNodes.size() < 2)<br>
@@ -12540,7 +12541,9 @@ bool DAGCombiner::<wbr>MergeConsecutiveStores<br>
if (LoadNodes.size() == 2 && TLI.hasPairedLoad(MemVT, RequiredAlignment) &&<br>
St->getAlignment() >= RequiredAlignment)<br>
return false;<br>
-<br>
+ LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;<br>
+ unsigned FirstStoreAS = FirstInChain->getAddressSpace(<wbr>);<br>
+ unsigned FirstStoreAlign = FirstInChain->getAlignment();<br>
LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].<wbr>MemNode);<br>
unsigned FirstLoadAS = FirstLoad->getAddressSpace();<br>
unsigned FirstLoadAlign = FirstLoad->getAlignment();<br>
@@ -12609,30 +12612,19 @@ bool DAGCombiner::<wbr>MergeConsecutiveStores<br>
<br>
// We add +1 here because the LastXXX variables refer to location while<br>
// the NumElem refers to array/index size.<br>
- unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;<br>
+ unsigned NumElem = std::min(NumConsecutiveStores, LastConsecutiveLoad + 1);<br>
NumElem = std::min(LastLegalType, NumElem);<br>
<br>
if (NumElem < 2)<br>
return false;<br>
<br>
- // Collect the chains from all merged stores.<br>
+ // Collect the chains from all merged stores. Because the common case<br>
+ // all chains are the same, check if we match the first Chain.<br>
SmallVector<SDValue, 8> MergeStoreChains;<br>
MergeStoreChains.push_back(<wbr>StoreNodes[0].MemNode-><wbr>getChain());<br>
-<br>
- // The latest Node in the DAG.<br>
- unsigned LatestNodeUsed = 0;<br>
- for (unsigned i=1; i<NumElem; ++i) {<br>
- // Find a chain for the new wide-store operand. Notice that some<br>
- // of the store nodes that we found may not be selected for inclusion<br>
- // in the wide store. The chain we use needs to be the chain of the<br>
- // latest store node which is *used* and replaced by the wide store.<br>
- if (StoreNodes[i].SequenceNum < StoreNodes[LatestNodeUsed].<wbr>SequenceNum)<br>
- LatestNodeUsed = i;<br>
-<br>
- MergeStoreChains.push_back(<wbr>StoreNodes[i].MemNode-><wbr>getChain());<br>
- }<br>
-<br>
- LSBaseSDNode *LatestOp = StoreNodes[LatestNodeUsed].<wbr>MemNode;<br>
+ for (unsigned i = 1; i < NumElem; ++i)<br>
+ if (StoreNodes[0].MemNode-><wbr>getChain() != StoreNodes[i].MemNode-><wbr>getChain())<br>
+ MergeStoreChains.push_back(<wbr>StoreNodes[i].MemNode-><wbr>getChain());<br>
<br>
// Find if it is better to use vectors or integers to load and store<br>
// to memory.<br>
@@ -12656,6 +12648,8 @@ bool DAGCombiner::<wbr>MergeConsecutiveStores<br>
SDValue NewStoreChain =<br>
DAG.getNode(ISD::TokenFactor, StoreDL, MVT::Other, MergeStoreChains);<br>
<br>
+ AddToWorklist(NewStoreChain.<wbr>getNode());<br>
+<br>
SDValue NewStore =<br>
DAG.getStore(NewStoreChain, StoreDL, NewLoad, FirstInChain->getBasePtr(),<br>
FirstInChain->getPointerInfo()<wbr>, FirstStoreAlign);<br>
@@ -12667,25 +12661,9 @@ bool DAGCombiner::<wbr>MergeConsecutiveStores<br>
SDValue(NewLoad.getNode(), 1));<br>
}<br>
<br>
- if (UseAA) {<br>
- // Replace the all stores with the new store.<br>
- for (unsigned i = 0; i < NumElem; ++i)<br>
- CombineTo(StoreNodes[i].<wbr>MemNode, NewStore);<br>
- } else {<br>
- // Replace the last store with the new store.<br>
- CombineTo(LatestOp, NewStore);<br>
- // Erase all other stores.<br>
- for (unsigned i = 0; i < NumElem; ++i) {<br>
- // Remove all Store nodes.<br>
- if (StoreNodes[i].MemNode == LatestOp)<br>
- continue;<br>
- StoreSDNode *St = cast<StoreSDNode>(StoreNodes[<wbr>i].MemNode);<br>
- DAG.ReplaceAllUsesOfValueWith(<wbr>SDValue(St, 0), St->getChain());<br>
- deleteAndRecombine(St);<br>
- }<br>
- }<br>
-<br>
- StoreNodes.erase(StoreNodes.<wbr>begin() + NumElem, StoreNodes.end());<br>
+ // Replace the all stores with the new store.<br>
+ for (unsigned i = 0; i < NumElem; ++i)<br>
+ CombineTo(StoreNodes[i].<wbr>MemNode, NewStore);<br>
return true;<br>
}<br>
<br>
@@ -12842,19 +12820,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *<br>
if (SDValue NewST = TransformFPLoadStorePair(N))<br>
return NewST;<br>
<br>
- bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA<br>
- : DAG.getSubtarget().useAA();<br>
-#ifndef NDEBUG<br>
- if (CombinerAAOnlyFunc.<wbr>getNumOccurrences() &&<br>
- CombinerAAOnlyFunc != DAG.getMachineFunction().<wbr>getName())<br>
- UseAA = false;<br>
-#endif<br>
- if (UseAA && ST->isUnindexed()) {<br>
- // FIXME: We should do this even without AA enabled. AA will just allow<br>
- // FindBetterChain to work in more situations. The problem with this is that<br>
- // any combine that expects memory operations to be on consecutive chains<br>
- // first needs to be updated to look for users of the same chain.<br>
-<br>
+ if (ST->isUnindexed()) {<br>
// Walk up chain skipping non-aliasing memory nodes, on this store and any<br>
// adjacent stores.<br>
if (findBetterNeighborChains(ST)) {<br>
@@ -12888,8 +12854,15 @@ SDValue DAGCombiner::visitSTORE(SDNode *<br>
if (SimplifyDemandedBits(<br>
Value,<br>
APInt::getLowBitsSet(Value.<wbr>getScalarValueSizeInBits(),<br>
- ST->getMemoryVT().<wbr>getScalarSizeInBits())))<br>
+ ST->getMemoryVT().<wbr>getScalarSizeInBits()))) {<br>
+ // Re-visit the store if anything changed and the store hasn't been merged<br>
+ // with another node (N is deleted) SimplifyDemandedBits will add Value's<br>
+ // node back to the worklist if necessary, but we also need to re-visit<br>
+ // the Store node itself.<br>
+ if (N->getOpcode() != ISD::DELETED_NODE)<br>
+ AddToWorklist(N);<br>
return SDValue(N, 0);<br>
+ }<br>
}<br>
<br>
// If this is a load followed by a store to the same location, then the store<br>
@@ -12933,15 +12906,12 @@ SDValue DAGCombiner::visitSTORE(SDNode *<br>
// There can be multiple store sequences on the same chain.<br>
// Keep trying to merge store sequences until we are unable to do so<br>
// or until we merge the last store on the chain.<br>
- SmallVector<MemOpLink, 8> StoreNodes;<br>
- bool Changed = MergeConsecutiveStores(ST, StoreNodes);<br>
+ bool Changed = MergeConsecutiveStores(ST);<br>
if (!Changed) break;<br>
-<br>
- if (any_of(StoreNodes,<br>
- [ST](const MemOpLink &Link) { return Link.MemNode == ST; })) {<br>
- // ST has been merged and no longer exists.<br>
+ // Return N as merge only uses CombineTo and no worklist clean<br>
+ // up is necessary.<br>
+ if (N->getOpcode() == ISD::DELETED_NODE || !isa<StoreSDNode>(N))<br>
return SDValue(N, 0);<br>
- }<br>
}<br>
}<br>
<br>
@@ -12950,7 +12920,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *<br>
// Make sure to do this only after attempting to merge stores in order to<br>
// avoid changing the types of some subset of stores due to visit order,<br>
// preventing their merging.<br>
- if (isa<ConstantFPSDNode>(Value)) {<br>
+ if (isa<ConstantFPSDNode>(ST-><wbr>getValue())) {<br>
if (SDValue NewSt = replaceStoreOfFPConstant(ST))<br>
return NewSt;<br>
}<br>
@@ -13887,6 +13857,35 @@ SDValue DAGCombiner::visitBUILD_<wbr>VECTOR(S<br>
if (ISD::allOperandsUndef(N))<br>
return DAG.getUNDEF(VT);<br>
<br>
+ // Check if we can express BUILD VECTOR via subvector extract.<br>
+ if (!LegalTypes && (N->getNumOperands() > 1)) {<br>
+ SDValue Op0 = N->getOperand(0);<br>
+ auto checkElem = [&](SDValue Op) -> uint64_t {<br>
+ if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) &&<br>
+ (Op0.getOperand(0) == Op.getOperand(0)))<br>
+ if (auto CNode = dyn_cast<ConstantSDNode>(Op.<wbr>getOperand(1)))<br>
+ return CNode->getZExtValue();<br>
+ return -1;<br>
+ };<br>
+<br>
+ int Offset = checkElem(Op0);<br>
+ for (unsigned i = 0; i < N->getNumOperands(); ++i) {<br>
+ if (Offset + i != checkElem(N->getOperand(i))) {<br>
+ Offset = -1;<br>
+ break;<br>
+ }<br>
+ }<br>
+<br>
+ if ((Offset == 0) &&<br>
+ (Op0.getOperand(0).<wbr>getValueType() == N->getValueType(0)))<br>
+ return Op0.getOperand(0);<br>
+ if ((Offset != -1) &&<br>
+ ((Offset % N->getValueType(0).<wbr>getVectorNumElements()) ==<br>
+ 0)) // IDX must be multiple of output size.<br>
+ return DAG.getNode(ISD::EXTRACT_<wbr>SUBVECTOR, SDLoc(N), N->getValueType(0),<br>
+ Op0.getOperand(0), Op0.getOperand(1));<br>
+ }<br>
+<br>
if (SDValue V = reduceBuildVecExtToExtBuildVec<wbr>(N))<br>
return V;<br>
<br>
@@ -15983,7 +15982,7 @@ static bool FindBaseOffset(SDValue Ptr,<br>
if (Base.getOpcode() == ISD::ADD) {<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.<wbr>getOperand(1))) {<br>
Base = Base.getOperand(0);<br>
- Offset += C->getZExtValue();<br>
+ Offset += C->getSExtValue();<br>
}<br>
}<br>
<br>
@@ -16180,6 +16179,12 @@ void DAGCombiner::GatherAllAliases(<wbr>SDNod<br>
++Depth;<br>
break;<br>
<br>
+ case ISD::CopyFromReg:<br>
+ // Forward past CopyFromReg.<br>
+ Chains.push_back(Chain.<wbr>getOperand(0));<br>
+ ++Depth;<br>
+ break;<br>
+<br>
default:<br>
// For all other instructions we will just have to take what we can get.<br>
Aliases.push_back(Chain);<br>
@@ -16208,6 +16213,18 @@ SDValue DAGCombiner::FindBetterChain(<wbr>SDN<br>
return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);<br>
}<br>
<br>
+// This function tries to collect a bunch of potentially interesting<br>
+// nodes to improve the chains of, all at once. This might seem<br>
+// redundant, as this function gets called when visiting every store<br>
+// node, so why not let the work be done on each store as it's visited?<br>
+//<br>
+// I believe this is mainly important because MergeConsecutiveStores<br>
+// is unable to deal with merging stores of different sizes, so unless<br>
+// we improve the chains of all the potential candidates up-front<br>
+// before running MergeConsecutiveStores, it might only see some of<br>
+// the nodes that will eventually be candidates, and then not be able<br>
+// to go from a partially-merged state to the desired final<br>
+// fully-merged state.<br>
bool DAGCombiner::<wbr>findBetterNeighborChains(<wbr>StoreSDNode *St) {<br>
// This holds the base pointer, index, and the offset in bytes from the base<br>
// pointer.<br>
@@ -16243,10 +16260,8 @@ bool DAGCombiner::<wbr>findBetterNeighborChai<br>
if (!Ptr.equalBaseIndex(BasePtr))<br>
break;<br>
<br>
- // Find the next memory operand in the chain. If the next operand in the<br>
- // chain is a store then move up and continue the scan with the next<br>
- // memory operand. If the next operand is a load save it and use alias<br>
- // information to check if it interferes with anything.<br>
+ // Walk up the chain to find the next store node, ignoring any<br>
+ // intermediate loads. Any other kind of node will halt the loop.<br>
SDNode *NextInChain = Index->getChain().getNode();<br>
while (true) {<br>
if (StoreSDNode *STn = dyn_cast<StoreSDNode>(<wbr>NextInChain)) {<br>
@@ -16265,9 +16280,14 @@ bool DAGCombiner::<wbr>findBetterNeighborChai<br>
Index = nullptr;<br>
break;<br>
}<br>
- }<br>
+ } // end while<br>
}<br>
<br>
+ // At this point, ChainedStores lists all of the Store nodes<br>
+ // reachable by iterating up through chain nodes matching the above<br>
+ // conditions. For each such store identified, try to find an<br>
+ // earlier chain to attach the store to which won't violate the<br>
+ // required ordering.<br>
bool MadeChangeToSt = false;<br>
SmallVector<std::pair<<wbr>StoreSDNode *, SDValue>, 8> BetterChains;<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>TargetLoweringBase.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/TargetLoweringBase.<wbr>cpp?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>TargetLoweringBase.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>TargetLoweringBase.cpp Mon Mar 13 19:34:14 2017<br>
@@ -850,7 +850,7 @@ TargetLoweringBase::<wbr>TargetLoweringBase(c<br>
MinFunctionAlignment = 0;<br>
PrefFunctionAlignment = 0;<br>
PrefLoopAlignment = 0;<br>
- GatherAllAliasesMaxDepth = 6;<br>
+ GatherAllAliasesMaxDepth = 18;<br>
MinStackArgumentAlignment = 1;<br>
// TODO: the default will be switched to 0 in the next commit, along<br>
// with the Target-specific changes necessary.<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64ISelLowering.<wbr>cpp?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64ISelLowering.cpp Mon Mar 13 19:34:14 2017<br>
@@ -9338,7 +9338,7 @@ static SDValue performSTORECombine(SDNod<br>
return SDValue();<br>
}<br>
<br>
- /// This function handles the log2-shuffle pattern produced by the<br>
+/// This function handles the log2-shuffle pattern produced by the<br>
/// LoopVectorizer for the across vector reduction. It consists of<br>
/// log2(NumVectorElements) steps and, in each step, 2^(s) elements<br>
/// are reduced, where s is an induction variable from 0 to<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/<wbr>ARMISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>ARM/ARMISelLowering.h?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/<wbr>ARMISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/<wbr>ARMISelLowering.h Mon Mar 13 19:34:14 2017<br>
@@ -500,6 +500,11 @@ class InstrItineraryData;<br>
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,<br>
unsigned &Cost) const override;<br>
<br>
+ bool canMergeStoresTo(EVT MemVT) const override {<br>
+ // Do not merge to larger than i32.<br>
+ return (MemVT.getSizeInBits() <= 32);<br>
+ }<br>
+<br>
bool isCheapToSpeculateCttz() const override;<br>
bool isCheapToSpeculateCtlz() const override;<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/argument-blocks.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/argument-blocks.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/argument-<wbr>blocks.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/argument-blocks.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/argument-blocks.ll Mon Mar 13 19:34:14 2017<br>
@@ -59,10 +59,10 @@ define i64 @test_hfa_ignores_gprs([7 x f<br>
}<br>
<br>
; [2 x float] should not be promoted to double by the Darwin varargs handling,<br>
-; but should go in an 8-byte aligned slot.<br>
+; but should go in an 8-byte aligned slot and can be merged as integer stores.<br>
define void @test_varargs_stackalign() {<br>
; CHECK-LABEL: test_varargs_stackalign:<br>
-; CHECK-DARWINPCS: stp {{w[0-9]+}}, {{w[0-9]+}}, [sp, #16]<br>
+; CHECK-DARWINPCS: str {{x[0-9]+}}, [sp, #16]<br>
<br>
call void(...) @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0])<br>
ret void<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-abi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-abi.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-abi.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-abi.ll Mon Mar 13 19:34:14 2017<br>
@@ -205,10 +205,7 @@ declare i32 @args_i32(i32, i32, i32, i32<br>
define i32 @test8(i32 %argc, i8** nocapture %argv) nounwind {<br>
entry:<br>
; CHECK-LABEL: test8<br>
-; CHECK: strb {{w[0-9]+}}, [sp, #3]<br>
-; CHECK: strb wzr, [sp, #2]<br>
-; CHECK: strb {{w[0-9]+}}, [sp, #1]<br>
-; CHECK: strb wzr, [sp]<br>
+; CHECK: str w8, [sp]<br>
; CHECK: bl<br>
; FAST-LABEL: test8<br>
; FAST: strb {{w[0-9]+}}, [sp]<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-memset-inline.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-memset-inline.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-memset-<wbr>inline.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-memset-inline.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-memset-inline.ll Mon Mar 13 19:34:14 2017<br>
@@ -13,8 +13,8 @@ define void @t2() nounwind ssp {<br>
entry:<br>
; CHECK-LABEL: t2:<br>
; CHECK: strh wzr, [sp, #32]<br>
-; CHECK: stp xzr, xzr, [sp, #16]<br>
-; CHECK: str xzr, [sp, #8]<br>
+; CHECK: stp xzr, xzr, [sp, #8]<br>
+; CHECK: str xzr, [sp, #24]<br>
%buf = alloca [26 x i8], align 1<br>
%0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0<br>
call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-variadic-aapcs.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-variadic-aapcs.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-<wbr>variadic-aapcs.ll?rev=297695&<wbr>r1=297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-variadic-aapcs.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-variadic-aapcs.<wbr>ll Mon Mar 13 19:34:14 2017<br>
@@ -99,7 +99,7 @@ define void @test_nospare([8 x i64], [8<br>
; __stack field should point just past them.<br>
define void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) {<br>
; CHECK-LABEL: test_offsetstack:<br>
-; CHECK: sub sp, sp, #80<br>
+; CHECK: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #-80]!<br>
; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #96<br>
; CHECK: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var<br>
; CHECK: str [[STACK_TOP]], [x[[VAR]]]<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/merge-store.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/merge-store.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/merge-store.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/merge-store.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/merge-store.ll Mon Mar 13 19:34:14 2017<br>
@@ -4,8 +4,7 @@<br>
@g0 = external global <3 x float>, align 16<br>
@g1 = external global <3 x float>, align 4<br>
<br>
-; CHECK: ldr s[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]]{{\]}}, #4<br>
-; CHECK: ld1{{\.?s?}} { v[[R0]]{{\.?s?}} }[1], {{\[}}[[R1]]{{\]}}<br>
+; CHECK: ldr q[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]], :lo12:g0<br>
; CHECK: str d[[R0]]<br>
<br>
define void @blam() {<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/vector_merge_dep_<wbr>check.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/vector_merge_dep_check.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/vector_merge_<wbr>dep_check.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/vector_merge_dep_<wbr>check.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/vector_merge_dep_<wbr>check.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,5 +1,4 @@<br>
-; RUN: llc --combiner-alias-analysis=<wbr>false < %s | FileCheck %s<br>
-; RUN: llc --combiner-alias-analysis=true < %s | FileCheck %s<br>
+; RUN: llc < %s | FileCheck %s<br>
<br>
; This test checks that we do not merge stores together which have<br>
; dependencies through their non-chain operands (e.g. one store is the<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/debugger-insert-nops.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/debugger-insert-nops.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/debugger-<wbr>insert-nops.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/debugger-insert-nops.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/debugger-insert-nops.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,13 +1,21 @@<br>
-; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-<wbr>insert-nops -verify-machineinstrs < %s | FileCheck %s<br>
+; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-<wbr>insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK<br>
+; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-<wbr>insert-nops -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECKNOP<br>
<br>
-; CHECK: test01.cl:2:{{[0-9]+}}<br>
-; CHECK-NEXT: s_nop 0<br>
+; This test expects that we have one instance for each line in some order with "s_nop 0" instances after each.<br>
<br>
-; CHECK: test01.cl:3:{{[0-9]+}}<br>
-; CHECK-NEXT: s_nop 0<br>
+; Check that each line appears at least once<br>
+; CHECK-DAG: test01.cl:2:3<br>
+; CHECK-DAG: test01.cl:3:3<br>
+; CHECK-DAG: test01.cl:4:3<br>
<br>
-; CHECK: test01.cl:4:{{[0-9]+}}<br>
-; CHECK-NEXT: s_nop 0<br>
+<br>
+; Check that each of each of the lines consists of the line output, followed by "s_nop 0"<br>
+; CHECKNOP: test01.cl:{{[234]}}:3<br>
+; CHECKNOP-NEXT: s_nop 0<br>
+; CHECKNOP: test01.cl:{{[234]}}:3<br>
+; CHECKNOP-NEXT: s_nop 0<br>
+; CHECKNOP: test01.cl:{{[234]}}:3<br>
+; CHECKNOP-NEXT: s_nop 0<br>
<br>
; CHECK: test01.cl:5:{{[0-9]+}}<br>
; CHECK-NEXT: s_nop 0<br>
@@ -21,7 +29,7 @@ entry:<br>
call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !17, metadata !18), !dbg !19<br>
%0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !20<br>
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 0, !dbg !20<br>
- store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !21<br>
+ store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !20<br>
%1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !22<br>
%arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i32 1, !dbg !22<br>
store i32 2, i32 addrspace(1)* %arrayidx1, align 4, !dbg !23<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/insert_vector_elt.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/insert_vector_<wbr>elt.ll?rev=297695&r1=297694&<wbr>r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/insert_vector_elt.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/insert_vector_elt.ll Mon Mar 13 19:34:14 2017<br>
@@ -253,11 +253,9 @@ define void @dynamic_insertelement_v2i8(<br>
; GCN: buffer_load_ubyte v{{[0-9]+}}, off<br>
; GCN: buffer_load_ubyte v{{[0-9]+}}, off<br>
<br>
-; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:6<br>
-; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:5<br>
; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4<br>
-<br>
-; GCN: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}<br>
+; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:5<br>
+; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:6<br>
<br>
; GCN-NO-TONGA: buffer_load_ubyte<br>
; GCN-NO-TONGA: buffer_load_ubyte<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/merge-stores.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/merge-stores.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/merge-stores.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/merge-stores.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/merge-stores.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,8 +1,5 @@<br>
-; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-load-store-vectorizer=<wbr>0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-NOAA %s<br>
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=<wbr>0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-NOAA %s<br>
-<br>
-; RUN: llc -march=amdgcn -verify-machineinstrs -combiner-alias-analysis -amdgpu-load-store-vectorizer=<wbr>0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s<br>
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -combiner-alias-analysis -amdgpu-load-store-vectorizer=<wbr>0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s<br>
+; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-load-store-vectorizer=<wbr>0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s<br>
+; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -amdgpu-load-store-vectorizer=<wbr>0 < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=GCN-AA %s<br>
<br>
; This test is mostly to test DAG store merging, so disable the vectorizer.<br>
; Run with devices with different unaligned load restrictions.<br>
@@ -150,12 +147,7 @@ define void @merge_global_store_4_consta<br>
}<br>
<br>
; GCN-LABEL: {{^}}merge_global_store_4_<wbr>constants_mixed_i32_f32:<br>
-; GCN-NOAA: buffer_store_dwordx4 v<br>
-<br>
-; GCN-AA: buffer_store_dwordx2<br>
-; GCN-AA: buffer_store_dword v<br>
-; GCN-AA: buffer_store_dword v<br>
-<br>
+; GCN-AA: buffer_store_dwordx4 v<br>
; GCN: s_endpgm<br>
define void @merge_global_store_4_<wbr>constants_mixed_i32_f32(float addrspace(1)* %out) #0 {<br>
%out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1<br>
@@ -474,17 +466,9 @@ define void @merge_global_store_4_adjace<br>
ret void<br>
}<br>
<br>
-; This works once AA is enabled on the subtarget<br>
; GCN-LABEL: {{^}}merge_global_store_4_<wbr>vector_elts_loads_v4i32:<br>
; GCN: buffer_load_dwordx4 [[LOAD:v\[[0-9]+:[0-9]+\]]]<br>
-<br>
-; GCN-NOAA: buffer_store_dword v<br>
-; GCN-NOAA: buffer_store_dword v<br>
-; GCN-NOAA: buffer_store_dword v<br>
-; GCN-NOAA: buffer_store_dword v<br>
-<br>
-; GCN-AA: buffer_store_dwordx4 [[LOAD]]<br>
-<br>
+; GCN: buffer_store_dwordx4 [[LOAD]]<br>
; GCN: s_endpgm<br>
define void @merge_global_store_4_vector_<wbr>elts_loads_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 {<br>
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i32 1<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/private-element-size.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/private-element-size.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/private-<wbr>element-size.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/private-element-size.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/private-element-size.ll Mon Mar 13 19:34:14 2017<br>
@@ -32,10 +32,10 @@<br>
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], s9 offset:40{{$}}<br>
; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, off, s[0:3], s9 offset:44{{$}}<br>
<br>
-; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}<br>
-; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}}<br>
-; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}}<br>
-; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}}<br>
+; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}}<br>
+; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}}<br>
+; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}}<br>
+; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}}<br>
define void @private_elt_size_v4i32(<4 x i32> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {<br>
entry:<br>
%tid = call i32 @llvm.amdgcn.workitem.id.x()<br>
@@ -130,8 +130,8 @@ entry:<br>
; HSA-ELT8: private_element_size = 2<br>
; HSA-ELT4: private_element_size = 1<br>
<br>
-; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:16<br>
-; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], s9 offset:24<br>
+; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, {{off|v[0-9]}}, s[0:3], s9 offset:1<br>
+; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, {{off|v[0-9]}}, s[0:3], s9 offset:2<br>
<br>
; HSA-ELTGE8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/si-triv-disjoint-mem-<wbr>access.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/si-triv-<wbr>disjoint-mem-access.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/si-triv-disjoint-mem-<wbr>access.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/si-triv-disjoint-mem-<wbr>access.ll Mon Mar 13 19:34:14 2017<br>
@@ -157,9 +157,8 @@ define void @reorder_global_load_local_s<br>
<br>
; FUNC-LABEL: @reorder_local_offsets<br>
; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:100 offset1:102<br>
-; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:3 offset1:100<br>
-; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12<br>
-; CI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:408<br>
+; CI-DAG: ds_write2_b32 {{v[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:3 offset1:100<br>
+; CI-DAG: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:408<br>
; CI: buffer_store_dword<br>
; CI: s_endpgm<br>
define void @reorder_local_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(3)* noalias nocapture %ptr0) #0 {<br>
@@ -181,12 +180,12 @@ define void @reorder_local_offsets(i32 a<br>
}<br>
<br>
; FUNC-LABEL: @reorder_global_offsets<br>
-; CI: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400<br>
-; CI: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408<br>
-; CI: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12<br>
-; CI: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400<br>
-; CI: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408<br>
-; CI: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12<br>
+; CI-DAG: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400<br>
+; CI-DAG: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408<br>
+; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12<br>
+; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400<br>
+; CI-DAG: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408<br>
+; CI: buffer_store_dword<br>
; CI: s_endpgm<br>
define void @reorder_global_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(1)* noalias nocapture %ptr0) #0 {<br>
%ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 3<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>2012-10-04-AAPCS-byval-align8.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/2012-10-04-AAPCS-<wbr>byval-align8.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>2012-10-04-AAPCS-byval-align8.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>2012-10-04-AAPCS-byval-align8.<wbr>ll Mon Mar 13 19:34:14 2017<br>
@@ -12,7 +12,8 @@ define void @test_byval_8_bytes_alignmen<br>
entry:<br>
; CHECK: sub sp, sp, #12<br>
; CHECK: sub sp, sp, #4<br>
-; CHECK: stmib sp, {r1, r2, r3}<br>
+; CHECK: add r0, sp, #4<br>
+; CHECK: stm sp, {r0, r1, r2, r3}<br>
%g = alloca i8*<br>
%g1 = bitcast i8** %g to i8*<br>
call void @llvm.va_start(i8* %g1)<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>alloc-no-stack-realign.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/alloc-no-stack-realign.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/alloc-no-stack-<wbr>realign.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>alloc-no-stack-realign.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>alloc-no-stack-realign.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,5 +1,4 @@<br>
-; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=NO-REALIGN<br>
-; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=REALIGN<br>
+; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s<br>
<br>
; rdar://12713765<br>
; When realign-stack is set to false, make sure we are not creating stack<br>
@@ -8,29 +7,31 @@<br>
<br>
define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {<br>
entry:<br>
-; NO-REALIGN-LABEL: test1<br>
-; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]<br>
-; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!<br>
-; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32<br>
-; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48<br>
-; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-<br>
-; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48<br>
-; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32<br>
-; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; NO-REALIGN: mov r[[R3:[0-9]+]], r[[R1]]<br>
-; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R3]]:128]!<br>
-; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R3]]:128]<br>
-<br>
-; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48<br>
-; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32<br>
-; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!<br>
-; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]<br>
+; CHECK-LABEL: test1<br>
+; CHECK: ldr r[[R1:[0-9]+]], [pc, r1]<br>
+; CHECK: add r[[R2:[0-9]+]], r1, #48<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: mov r[[R2:[0-9]+]], r[[R1]]<br>
+; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: add r[[R1:[0-9]+]], r[[R1]], #32<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: mov r[[R1:[0-9]+]], sp<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: add r[[R2:[0-9]+]], r[[R1]], #32<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: add r[[R1:[0-9]+]], r0, #48<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: add r[[R1:[0-9]+]], r0, #32<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r0:128]!<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r0:128]<br>
%retval = alloca <16 x float>, align 16<br>
%0 = load <16 x float>, <16 x float>* @T3_retval, align 16<br>
store <16 x float> %0, <16 x float>* %retval<br>
@@ -41,32 +42,33 @@ entry:<br>
<br>
define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {<br>
entry:<br>
-; REALIGN-LABEL: test2<br>
-; REALIGN: bfc sp, #0, #6<br>
-; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]]<br>
-; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!<br>
-; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32<br>
-; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48<br>
-; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: ldr r[[R1:[0-9]+]], [pc, r1]<br>
+; CHECK: add r[[R2:[0-9]+]], r[[R1]], #48<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: mov r[[R2:[0-9]+]], r[[R1]]<br>
+; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: add r[[R1:[0-9]+]], r[[R1]], #32<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: mov r[[R1:[0-9]+]], sp<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: orr r[[R2:[0-9]+]], r[[R1]], #32<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]!<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]!<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
+; CHECK: add r[[R1:[0-9]+]], r0, #48<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: add r[[R1:[0-9]+]], r0, #32<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
+; CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r0:128]!<br>
+; CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r0:128]<br>
<br>
<br>
-; REALIGN: orr r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48<br>
-; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #32<br>
-; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #16<br>
-; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]<br>
-; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
-<br>
-; REALIGN: add r[[R1:[0-9]+]], r[[R0:0]], #48<br>
-; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
-; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32<br>
-; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]<br>
-; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]!<br>
-; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]<br>
- %retval = alloca <16 x float>, align 16<br>
+%retval = alloca <16 x float>, align 16<br>
%0 = load <16 x float>, <16 x float>* @T3_retval, align 16<br>
store <16 x float> %0, <16 x float>* %retval<br>
%1 = load <16 x float>, <16 x float>* %retval<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>gpr-paired-spill.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/gpr-paired-spill.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/gpr-paired-spill.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>gpr-paired-spill.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>gpr-paired-spill.ll Mon Mar 13 19:34:14 2017<br>
@@ -16,22 +16,22 @@ define void @foo(i64* %addr) {<br>
; an LDMIA was created with both a FrameIndex and an offset, which<br>
; is not allowed.<br>
<br>
-; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]<br>
-; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp]<br>
+; CHECK-WITH-LDRD-DAG: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]<br>
+; CHECK-WITH-LDRD-DAG: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp]<br>
<br>
-; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]<br>
-; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp]<br>
+; CHECK-WITH-LDRD-DAG: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8]<br>
+; CHECK-WITH-LDRD-DAG: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp]<br>
<br>
; We also want to ensure the register scavenger is working (i.e. an<br>
; offset from sp can be generated), so we need two spills.<br>
-; CHECK-WITHOUT-LDRD: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}}<br>
-; CHECK-WITHOUT-LDRD: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}<br>
-; CHECK-WITHOUT-LDRD: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}<br>
+; CHECK-WITHOUT-LDRD-DAG: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}}<br>
+; CHECK-WITHOUT-LDRD-DAG: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}<br>
+; CHECK-WITHOUT-LDRD-DAG: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}<br>
<br>
; In principle LLVM may have to recalculate the offset. At the moment<br>
; it reuses the original though.<br>
-; CHECK-WITHOUT-LDRD: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}<br>
-; CHECK-WITHOUT-LDRD: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}}<br>
+; CHECK-WITHOUT-LDRD-DAG: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}<br>
+; CHECK-WITHOUT-LDRD-DAG: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}}<br>
<br>
store volatile i64 %val1, i64* %addr<br>
store volatile i64 %val2, i64* %addr<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>ifcvt10.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt10.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/ifcvt10.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>ifcvt10.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>ifcvt10.ll Mon Mar 13 19:34:14 2017<br>
@@ -10,8 +10,6 @@ entry:<br>
; CHECK: vpop {d8}<br>
; CHECK-NOT: vpopne<br>
; CHECK: pop {r7, pc}<br>
-; CHECK: vpop {d8}<br>
-; CHECK: pop {r7, pc}<br>
br i1 undef, label %if.else, label %if.then<br>
<br>
if.then: ; preds = %entry<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>illegal-bitfield-loadstore.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/illegal-bitfield-loadstore.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/illegal-bitfield-<wbr>loadstore.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>illegal-bitfield-loadstore.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>illegal-bitfield-loadstore.ll Mon Mar 13 19:34:14 2017<br>
@@ -6,9 +6,7 @@ define void @i24_or(i24* %a) {<br>
; LE-LABEL: i24_or:<br>
; LE: @ BB#0:<br>
; LE-NEXT: ldrh r1, [r0]<br>
-; LE-NEXT: ldrb r2, [r0, #2]<br>
; LE-NEXT: orr r1, r1, #384<br>
-; LE-NEXT: strb r2, [r0, #2]<br>
; LE-NEXT: strh r1, [r0]<br>
; LE-NEXT: mov pc, lr<br>
;<br>
@@ -31,21 +29,19 @@ define void @i24_or(i24* %a) {<br>
define void @i24_and_or(i24* %a) {<br>
; LE-LABEL: i24_and_or:<br>
; LE: @ BB#0:<br>
-; LE-NEXT: ldrb r2, [r0, #2]<br>
; LE-NEXT: ldrh r1, [r0]<br>
-; LE-NEXT: strb r2, [r0, #2]<br>
; LE-NEXT: mov r2, #16256<br>
-; LE-NEXT: orr r1, r1, #384<br>
; LE-NEXT: orr r2, r2, #49152<br>
+; LE-NEXT: orr r1, r1, #384<br>
; LE-NEXT: and r1, r1, r2<br>
; LE-NEXT: strh r1, [r0]<br>
; LE-NEXT: mov pc, lr<br>
;<br>
; BE-LABEL: i24_and_or:<br>
; BE: @ BB#0:<br>
+; BE-NEXT: mov r1, #128<br>
+; BE-NEXT: strb r1, [r0, #2]<br>
; BE-NEXT: ldrh r1, [r0]<br>
-; BE-NEXT: mov r2, #128<br>
-; BE-NEXT: strb r2, [r0, #2]<br>
; BE-NEXT: orr r1, r1, #1<br>
; BE-NEXT: strh r1, [r0]<br>
; BE-NEXT: mov pc, lr<br>
@@ -59,9 +55,7 @@ define void @i24_and_or(i24* %a) {<br>
define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {<br>
; LE-LABEL: i24_insert_bit:<br>
; LE: @ BB#0:<br>
-; LE-NEXT: ldrb r3, [r0, #2]<br>
; LE-NEXT: ldrh r2, [r0]<br>
-; LE-NEXT: strb r3, [r0, #2]<br>
; LE-NEXT: mov r3, #255<br>
; LE-NEXT: orr r3, r3, #57088<br>
; LE-NEXT: and r2, r2, r3<br>
@@ -71,9 +65,7 @@ define void @i24_insert_bit(i24* %a, i1<br>
;<br>
; BE-LABEL: i24_insert_bit:<br>
; BE: @ BB#0:<br>
-; BE-NEXT: ldrb r3, [r0, #2]<br>
; BE-NEXT: ldrh r2, [r0]<br>
-; BE-NEXT: strb r3, [r0, #2]<br>
; BE-NEXT: mov r3, #57088<br>
; BE-NEXT: orr r3, r3, #16711680<br>
; BE-NEXT: and r2, r3, r2, lsl #8<br>
@@ -93,14 +85,9 @@ define void @i24_insert_bit(i24* %a, i1<br>
define void @i56_or(i56* %a) {<br>
; LE-LABEL: i56_or:<br>
; LE: @ BB#0:<br>
-; LE-NEXT: mov r2, r0<br>
-; LE-NEXT: ldr r12, [r0]<br>
-; LE-NEXT: ldrh r3, [r2, #4]!<br>
-; LE-NEXT: ldrb r1, [r2, #2]<br>
-; LE-NEXT: strb r1, [r2, #2]<br>
-; LE-NEXT: orr r1, r12, #384<br>
+; LE-NEXT: ldr r1, [r0]<br>
+; LE-NEXT: orr r1, r1, #384<br>
; LE-NEXT: str r1, [r0]<br>
-; LE-NEXT: strh r3, [r2]<br>
; LE-NEXT: mov pc, lr<br>
;<br>
; BE-LABEL: i56_or:<br>
@@ -128,36 +115,29 @@ define void @i56_or(i56* %a) {<br>
define void @i56_and_or(i56* %a) {<br>
; LE-LABEL: i56_and_or:<br>
; LE: @ BB#0:<br>
-; LE-NEXT: mov r2, r0<br>
; LE-NEXT: ldr r1, [r0]<br>
-; LE-NEXT: ldrh r12, [r2, #4]!<br>
; LE-NEXT: orr r1, r1, #384<br>
-; LE-NEXT: ldrb r3, [r2, #2]<br>
; LE-NEXT: bic r1, r1, #127<br>
-; LE-NEXT: strb r3, [r2, #2]<br>
; LE-NEXT: str r1, [r0]<br>
-; LE-NEXT: strh r12, [r2]<br>
; LE-NEXT: mov pc, lr<br>
;<br>
; BE-LABEL: i56_and_or:<br>
; BE: @ BB#0:<br>
-; BE-NEXT: .save {r11, lr}<br>
-; BE-NEXT: push {r11, lr}<br>
-; BE-NEXT: mov r2, r0<br>
-; BE-NEXT: ldr lr, [r0]<br>
+; BE-NEXT: mov r1, r0<br>
; BE-NEXT: mov r3, #128<br>
-; BE-NEXT: ldrh r12, [r2, #4]!<br>
-; BE-NEXT: strb r3, [r2, #2]<br>
-; BE-NEXT: lsl r3, r12, #8<br>
-; BE-NEXT: orr r3, r3, lr, lsl #24<br>
-; BE-NEXT: orr r3, r3, #384<br>
-; BE-NEXT: lsr r1, r3, #8<br>
-; BE-NEXT: strh r1, [r2]<br>
-; BE-NEXT: bic r1, lr, #255<br>
-; BE-NEXT: orr r1, r1, r3, lsr #24<br>
+; BE-NEXT: ldrh r2, [r1, #4]!<br>
+; BE-NEXT: strb r3, [r1, #2]<br>
+; BE-NEXT: lsl r2, r2, #8<br>
+; BE-NEXT: ldr r12, [r0]<br>
+; BE-NEXT: orr r2, r2, r12, lsl #24<br>
+; BE-NEXT: orr r2, r2, #384<br>
+; BE-NEXT: lsr r3, r2, #8<br>
+; BE-NEXT: strh r3, [r1]<br>
+; BE-NEXT: bic r1, r12, #255<br>
+; BE-NEXT: orr r1, r1, r2, lsr #24<br>
; BE-NEXT: str r1, [r0]<br>
-; BE-NEXT: pop {r11, lr}<br>
; BE-NEXT: mov pc, lr<br>
+<br>
%b = load i56, i56* %a, align 1<br>
%c = and i56 %b, -128<br>
%d = or i56 %c, 384<br>
@@ -168,35 +148,27 @@ define void @i56_and_or(i56* %a) {<br>
define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {<br>
; LE-LABEL: i56_insert_bit:<br>
; LE: @ BB#0:<br>
-; LE-NEXT: .save {r11, lr}<br>
-; LE-NEXT: push {r11, lr}<br>
-; LE-NEXT: mov r3, r0<br>
-; LE-NEXT: ldr lr, [r0]<br>
-; LE-NEXT: ldrh r12, [r3, #4]!<br>
-; LE-NEXT: ldrb r2, [r3, #2]<br>
-; LE-NEXT: strb r2, [r3, #2]<br>
-; LE-NEXT: bic r2, lr, #8192<br>
+; LE-NEXT: ldr r2, [r0]<br>
+; LE-NEXT: bic r2, r2, #8192<br>
; LE-NEXT: orr r1, r2, r1, lsl #13<br>
; LE-NEXT: str r1, [r0]<br>
-; LE-NEXT: strh r12, [r3]<br>
-; LE-NEXT: pop {r11, lr}<br>
; LE-NEXT: mov pc, lr<br>
;<br>
; BE-LABEL: i56_insert_bit:<br>
; BE: @ BB#0:<br>
; BE-NEXT: .save {r11, lr}<br>
; BE-NEXT: push {r11, lr}<br>
-; BE-NEXT: mov r3, r0<br>
+; BE-NEXT: mov r2, r0<br>
+; BE-NEXT: ldrh r12, [r2, #4]!<br>
+; BE-NEXT: ldrb r3, [r2, #2]<br>
+; BE-NEXT: strb r3, [r2, #2]<br>
+; BE-NEXT: orr r12, r3, r12, lsl #8<br>
; BE-NEXT: ldr lr, [r0]<br>
-; BE-NEXT: ldrh r12, [r3, #4]!<br>
-; BE-NEXT: ldrb r2, [r3, #2]<br>
-; BE-NEXT: strb r2, [r3, #2]<br>
-; BE-NEXT: orr r2, r2, r12, lsl #8<br>
-; BE-NEXT: orr r2, r2, lr, lsl #24<br>
-; BE-NEXT: bic r2, r2, #8192<br>
-; BE-NEXT: orr r1, r2, r1, lsl #13<br>
-; BE-NEXT: lsr r2, r1, #8<br>
-; BE-NEXT: strh r2, [r3]<br>
+; BE-NEXT: orr r3, r12, lr, lsl #24<br>
+; BE-NEXT: bic r3, r3, #8192<br>
+; BE-NEXT: orr r1, r3, r1, lsl #13<br>
+; BE-NEXT: lsr r3, r1, #8<br>
+; BE-NEXT: strh r3, [r2]<br>
; BE-NEXT: bic r2, lr, #255<br>
; BE-NEXT: orr r1, r2, r1, lsr #24<br>
; BE-NEXT: str r1, [r0]<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>static-addr-hoisting.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/static-addr-hoisting.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/static-addr-<wbr>hoisting.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>static-addr-hoisting.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>static-addr-hoisting.ll Mon Mar 13 19:34:14 2017<br>
@@ -6,9 +6,9 @@ define void @multiple_store() {<br>
; CHECK: movs [[VAL:r[0-9]+]], #42<br>
; CHECK: movt r[[BASE1]], #15<br>
<br>
-; CHECK: str [[VAL]], [r[[BASE1]]]<br>
-; CHECK: str [[VAL]], [r[[BASE1]], #24]<br>
-; CHECK: str.w [[VAL]], [r[[BASE1]], #42]<br>
+; CHECK-DAG: str [[VAL]], [r[[BASE1]]]<br>
+; CHECK-DAG: str [[VAL]], [r[[BASE1]], #24]<br>
+; CHECK-DAG: str.w [[VAL]], [r[[BASE1]], #42]<br>
<br>
; CHECK: movw r[[BASE2:[0-9]+]], #20394<br>
; CHECK: movt r[[BASE2]], #18<br>
<br>
Modified: llvm/trunk/test/CodeGen/BPF/<wbr>undef.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/BPF/undef.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/BPF/undef.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/BPF/<wbr>undef.ll (original)<br>
+++ llvm/trunk/test/CodeGen/BPF/<wbr>undef.ll Mon Mar 13 19:34:14 2017<br>
@@ -13,50 +13,55 @@<br>
<br>
; Function Attrs: nounwind uwtable<br>
define i32 @ebpf_filter(%struct.__sk_<wbr>buff* nocapture readnone %ebpf_packet) #0 section "socket1" {<br>
+; CHECK: r2 = r10<br>
+; CHECK: r2 += -2<br>
+; CHECK: r1 = 0<br>
+; CHECK: *(u16 *)(r2 + 6) = r1<br>
+; CHECK: *(u16 *)(r2 + 4) = r1<br>
+; CHECK: *(u16 *)(r2 + 2) = r1<br>
+; CHECK: r2 = 6<br>
+; CHECK: *(u8 *)(r10 - 7) = r2<br>
+; CHECK: r2 = 5<br>
+; CHECK: *(u8 *)(r10 - 8) = r2<br>
+; CHECK: r2 = 7<br>
+; CHECK: *(u8 *)(r10 - 6) = r2<br>
+; CHECK: r2 = 8<br>
+; CHECK: *(u8 *)(r10 - 5) = r2<br>
+; CHECK: r2 = 9<br>
+; CHECK: *(u8 *)(r10 - 4) = r2<br>
+; CHECK: r2 = 10<br>
+; CHECK: *(u8 *)(r10 - 3) = r2<br>
+; CHECK: *(u16 *)(r10 + 24) = r1<br>
+; CHECK: *(u16 *)(r10 + 22) = r1<br>
+; CHECK: *(u16 *)(r10 + 20) = r1<br>
+; CHECK: *(u16 *)(r10 + 18) = r1<br>
+; CHECK: *(u16 *)(r10 + 16) = r1<br>
+; CHECK: *(u16 *)(r10 + 14) = r1<br>
+; CHECK: *(u16 *)(r10 + 12) = r1<br>
+; CHECK: *(u16 *)(r10 + 10) = r1<br>
+; CHECK: *(u16 *)(r10 + 8) = r1<br>
+; CHECK: *(u16 *)(r10 + 6) = r1<br>
+; CHECK: *(u16 *)(r10 - 2) = r1<br>
+; CHECK: *(u16 *)(r10 + 26) = r1<br>
+; CHECK: r2 = r10<br>
+; CHECK: r2 += -8<br>
+; CHECK: r1 = <MCOperand Expr:(routing)>ll<br>
+; CHECK: call bpf_map_lookup_elem<br>
+; CHECK: exit<br>
%key = alloca %struct.routing_key_2, align 1<br>
%1 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 0<br>
-; CHECK: r1 = 5<br>
-; CHECK: *(u8 *)(r10 - 8) = r1<br>
store i8 5, i8* %1, align 1<br>
%2 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 1<br>
-; CHECK: r1 = 6<br>
-; CHECK: *(u8 *)(r10 - 7) = r1<br>
store i8 6, i8* %2, align 1<br>
%3 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 2<br>
-; CHECK: r1 = 7<br>
-; CHECK: *(u8 *)(r10 - 6) = r1<br>
store i8 7, i8* %3, align 1<br>
%4 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 3<br>
-; CHECK: r1 = 8<br>
-; CHECK: *(u8 *)(r10 - 5) = r1<br>
store i8 8, i8* %4, align 1<br>
%5 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 4<br>
-; CHECK: r1 = 9<br>
-; CHECK: *(u8 *)(r10 - 4) = r1<br>
store i8 9, i8* %5, align 1<br>
%6 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 0, i32 0, i64 5<br>
-; CHECK: r1 = 10<br>
-; CHECK: *(u8 *)(r10 - 3) = r1<br>
store i8 10, i8* %6, align 1<br>
%7 = getelementptr inbounds %struct.routing_key_2, %struct.routing_key_2* %key, i64 1, i32 0, i64 0<br>
-; CHECK: r1 = r10<br>
-; CHECK: r1 += -2<br>
-; CHECK: r2 = 0<br>
-; CHECK: *(u16 *)(r1 + 6) = r2<br>
-; CHECK: *(u16 *)(r1 + 4) = r2<br>
-; CHECK: *(u16 *)(r1 + 2) = r2<br>
-; CHECK: *(u16 *)(r10 + 24) = r2<br>
-; CHECK: *(u16 *)(r10 + 22) = r2<br>
-; CHECK: *(u16 *)(r10 + 20) = r2<br>
-; CHECK: *(u16 *)(r10 + 18) = r2<br>
-; CHECK: *(u16 *)(r10 + 16) = r2<br>
-; CHECK: *(u16 *)(r10 + 14) = r2<br>
-; CHECK: *(u16 *)(r10 + 12) = r2<br>
-; CHECK: *(u16 *)(r10 + 10) = r2<br>
-; CHECK: *(u16 *)(r10 + 8) = r2<br>
-; CHECK: *(u16 *)(r10 + 6) = r2<br>
-; CHECK: *(u16 *)(r10 - 2) = r2<br>
-; CHECK: *(u16 *)(r10 + 26) = r2<br>
call void @llvm.memset.p0i8.i64(i8* %7, i8 0, i64 30, i32 1, i1 false)<br>
%8 = call i32 (%struct.bpf_map_def*, %struct.routing_key_2*, ...) bitcast (i32 (...)* @bpf_map_lookup_elem to i32 (%struct.bpf_map_def*, %struct.routing_key_2*, ...)*)(%struct.bpf_map_def* nonnull @routing, %struct.routing_key_2* nonnull %key) #3<br>
ret i32 undef<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>MSP430/Inst16mm.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MSP430/Inst16mm.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/MSP430/Inst16mm.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>MSP430/Inst16mm.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>MSP430/Inst16mm.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc -march=msp430 -combiner-alias-analysis < %s | FileCheck %s<br>
+; RUN: llc -march=msp430 < %s | FileCheck %s<br>
target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-<wbr>i32:8:8"<br>
target triple = "msp430-generic-generic"<br>
@foo = common global i16 0, align 2<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>cconv/arguments-float.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/arguments-float.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/cconv/arguments-<wbr>float.ll?rev=297695&r1=297694&<wbr>r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>cconv/arguments-float.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>cconv/arguments-float.ll Mon Mar 13 19:34:14 2017<br>
@@ -63,39 +63,39 @@ entry:<br>
; NEW-DAG: sd $5, 16([[R2]])<br>
<br>
; O32 has run out of argument registers and starts using the stack<br>
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp)<br>
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp)<br>
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 16($sp)<br>
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 20($sp)<br>
; O32-DAG: sw [[R3]], 24([[R2]])<br>
; O32-DAG: sw [[R4]], 28([[R2]])<br>
; NEW-DAG: sd $6, 24([[R2]])<br>
<br>
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp)<br>
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)<br>
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp)<br>
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp)<br>
; O32-DAG: sw [[R3]], 32([[R2]])<br>
; O32-DAG: sw [[R4]], 36([[R2]])<br>
; NEW-DAG: sd $7, 32([[R2]])<br>
<br>
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp)<br>
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)<br>
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp)<br>
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)<br>
; O32-DAG: sw [[R3]], 40([[R2]])<br>
; O32-DAG: sw [[R4]], 44([[R2]])<br>
; NEW-DAG: sd $8, 40([[R2]])<br>
<br>
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp)<br>
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp)<br>
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp)<br>
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)<br>
; O32-DAG: sw [[R3]], 48([[R2]])<br>
; O32-DAG: sw [[R4]], 52([[R2]])<br>
; NEW-DAG: sd $9, 48([[R2]])<br>
<br>
-; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 56($sp)<br>
-; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 60($sp)<br>
+; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp)<br>
+; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp)<br>
; O32-DAG: sw [[R3]], 56([[R2]])<br>
; O32-DAG: sw [[R4]], 60([[R2]])<br>
; NEW-DAG: sd $10, 56([[R2]])<br>
<br>
; N32/N64 have run out of registers and starts using the stack too<br>
-; O32-DAG: lw [[R3:\$[0-9]+]], 64($sp)<br>
-; O32-DAG: lw [[R4:\$[0-9]+]], 68($sp)<br>
+; O32-DAG: lw [[R3:\$[0-9]+]], 56($sp)<br>
+; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp)<br>
; O32-DAG: sw [[R3]], 64([[R2]])<br>
; O32-DAG: sw [[R4]], 68([[R2]])<br>
; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>cconv/arguments-varargs.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/arguments-varargs.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/cconv/arguments-<wbr>varargs.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>cconv/arguments-varargs.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>cconv/arguments-varargs.ll Mon Mar 13 19:34:14 2017<br>
@@ -315,12 +315,11 @@ entry:<br>
; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte<br>
; order.<br>
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)<br>
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])<br>
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA_TMP2]])<br>
; O32-DAG: sw [[ARG1]], 8([[GV]])<br>
-; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])<br>
-; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4<br>
-; O32-DAG: sw [[VA2]], 0([[SP]])<br>
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])<br>
+; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4<br>
+; O32-DAG: sw [[VA3]], 0([[SP]])<br>
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 4([[VA_TMP2]])<br>
; O32-DAG: sw [[ARG1]], 12([[GV]])<br>
<br>
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)<br>
@@ -349,10 +348,9 @@ entry:<br>
; Load the second argument from the variable portion and copy it to the global.<br>
; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])<br>
; O32-DAG: sw [[ARG2]], 16([[GV]])<br>
-; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])<br>
-; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4<br>
-; O32-DAG: sw [[VA2]], 0([[SP]])<br>
-; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])<br>
+; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4<br>
+; O32-DAG: sw [[VA3]], 0([[SP]])<br>
+; O32-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA_TMP2]])<br>
; O32-DAG: sw [[ARG2]], 20([[GV]])<br>
<br>
; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]])<br>
@@ -678,12 +676,11 @@ entry:<br>
; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte<br>
; order.<br>
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)<br>
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])<br>
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA_TMP2]])<br>
; O32-DAG: sw [[ARG1]], 8([[GV]])<br>
-; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])<br>
-; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4<br>
-; O32-DAG: sw [[VA2]], 0([[SP]])<br>
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])<br>
+; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4<br>
+; O32-DAG: sw [[VA3]], 0([[SP]])<br>
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 4([[VA_TMP2]])<br>
; O32-DAG: sw [[ARG1]], 12([[GV]])<br>
<br>
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)<br>
@@ -712,10 +709,9 @@ entry:<br>
; Load the second argument from the variable portion and copy it to the global.<br>
; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])<br>
; O32-DAG: sw [[ARG2]], 16([[GV]])<br>
-; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])<br>
-; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4<br>
+; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4<br>
; O32-DAG: sw [[VA2]], 0([[SP]])<br>
-; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])<br>
+; O32-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA_TMP2]])<br>
; O32-DAG: sw [[ARG2]], 20([[GV]])<br>
<br>
; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]])<br>
@@ -1040,10 +1036,9 @@ entry:<br>
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)<br>
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])<br>
; O32-DAG: sw [[ARG1]], 8([[GV]])<br>
-; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])<br>
-; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4<br>
-; O32-DAG: sw [[VA2]], 0([[SP]])<br>
-; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])<br>
+; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4<br>
+; O32-DAG: sw [[VA3]], 0([[SP]])<br>
+; O32-DAG: lw [[ARG1:\$[0-9]+]], 4([[VA_TMP2]])<br>
; O32-DAG: sw [[ARG1]], 12([[GV]])<br>
<br>
; N32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)<br>
@@ -1072,10 +1067,9 @@ entry:<br>
; Load the second argument from the variable portion and copy it to the global.<br>
; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])<br>
; O32-DAG: sw [[ARG2]], 16([[GV]])<br>
-; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]])<br>
-; O32-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 4<br>
-; O32-DAG: sw [[VA2]], 0([[SP]])<br>
-; O32-DAG: lw [[ARG2:\$[0-9]+]], 0([[VA]])<br>
+; O32-DAG: addiu [[VA3:\$[0-9]+]], [[VA2]], 4<br>
+; O32-DAG: sw [[VA3]], 0([[SP]])<br>
+; O32-DAG: lw [[ARG2:\$[0-9]+]], 4([[VA_TMP2]])<br>
; O32-DAG: sw [[ARG2]], 20([[GV]])<br>
<br>
; NEW-DAG: ld [[ARG2:\$[0-9]+]], 0([[VA2]])<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>fastcc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fastcc.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/fastcc.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>fastcc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>fastcc.ll Mon Mar 13 19:34:14 2017<br>
@@ -132,20 +132,19 @@ entry:<br>
define internal fastcc void @callee0(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15, i32 %a16) nounwind noinline {<br>
entry:<br>
; CHECK: callee0<br>
-; CHECK: sw $4<br>
-; CHECK: sw $5<br>
-; CHECK: sw $6<br>
-; CHECK: sw $7<br>
-; CHECK: sw $8<br>
-; CHECK: sw $9<br>
-; CHECK: sw $10<br>
-; CHECK: sw $11<br>
-; CHECK: sw $12<br>
-; CHECK: sw $13<br>
-; CHECK: sw $14<br>
-; CHECK: sw $15<br>
-; CHECK: sw $24<br>
-; CHECK: sw $3<br>
+; CHECK-DAG: sw $4<br>
+; CHECK-DAG: sw $5<br>
+; CHECK-DAG: sw $7<br>
+; CHECK-DAG: sw $8<br>
+; CHECK-DAG: sw $9<br>
+; CHECK-DAG: sw $10<br>
+; CHECK-DAG: sw $11<br>
+; CHECK-DAG: sw $12<br>
+; CHECK-DAG: sw $13<br>
+; CHECK-DAG: sw $14<br>
+; CHECK-DAG: sw $15<br>
+; CHECK-DAG: sw $24<br>
+; CHECK-DAG: sw $3<br>
<br>
; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc.<br>
; CHECK-NACL-NOT: sw $14<br>
@@ -223,27 +222,27 @@ entry:<br>
<br>
define internal fastcc void @callee1(float %a0, float %a1, float %a2, float %a3, float %a4, float %a5, float %a6, float %a7, float %a8, float %a9, float %a10, float %a11, float %a12, float %a13, float %a14, float %a15, float %a16, float %a17, float %a18, float %a19, float %a20) nounwind noinline {<br>
entry:<br>
-; CHECK: callee1<br>
-; CHECK: swc1 $f0<br>
-; CHECK: swc1 $f1<br>
-; CHECK: swc1 $f2<br>
-; CHECK: swc1 $f3<br>
-; CHECK: swc1 $f4<br>
-; CHECK: swc1 $f5<br>
-; CHECK: swc1 $f6<br>
-; CHECK: swc1 $f7<br>
-; CHECK: swc1 $f8<br>
-; CHECK: swc1 $f9<br>
-; CHECK: swc1 $f10<br>
-; CHECK: swc1 $f11<br>
-; CHECK: swc1 $f12<br>
-; CHECK: swc1 $f13<br>
-; CHECK: swc1 $f14<br>
-; CHECK: swc1 $f15<br>
-; CHECK: swc1 $f16<br>
-; CHECK: swc1 $f17<br>
-; CHECK: swc1 $f18<br>
-; CHECK: swc1 $f19<br>
+; CHECK-LABEL: callee1:<br>
+; CHECK-DAG: swc1 $f0<br>
+; CHECK-DAG: swc1 $f1<br>
+; CHECK-DAG: swc1 $f2<br>
+; CHECK-DAG: swc1 $f3<br>
+; CHECK-DAG: swc1 $f4<br>
+; CHECK-DAG: swc1 $f5<br>
+; CHECK-DAG: swc1 $f6<br>
+; CHECK-DAG: swc1 $f7<br>
+; CHECK-DAG: swc1 $f8<br>
+; CHECK-DAG: swc1 $f9<br>
+; CHECK-DAG: swc1 $f10<br>
+; CHECK-DAG: swc1 $f11<br>
+; CHECK-DAG: swc1 $f12<br>
+; CHECK-DAG: swc1 $f13<br>
+; CHECK-DAG: swc1 $f14<br>
+; CHECK-DAG: swc1 $f15<br>
+; CHECK-DAG: swc1 $f16<br>
+; CHECK-DAG: swc1 $f17<br>
+; CHECK-DAG: swc1 $f18<br>
+; CHECK-DAG: swc1 $f19<br>
<br>
store float %a0, float* @gf0, align 4<br>
store float %a1, float* @gf1, align 4<br>
@@ -316,8 +315,6 @@ entry:<br>
<br>
; NOODDSPREG-LABEL: callee2:<br>
<br>
-; NOODDSPREG: addiu $sp, $sp, -[[OFFSET:[0-9]+]]<br>
-<br>
; Check that first 10 arguments are received in even float registers<br>
; f0, f2, ... , f18. Check that 11th argument is received on stack.<br>
<br>
@@ -333,7 +330,7 @@ entry:<br>
; NOODDSPREG-DAG: swc1 $f16, 32($[[R0]])<br>
; NOODDSPREG-DAG: swc1 $f18, 36($[[R0]])<br>
<br>
-; NOODDSPREG-DAG: lwc1 $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp)<br>
+; NOODDSPREG-DAG: lwc1 $[[F0:f[0-9]*[02468]]], 0($sp)<br>
; NOODDSPREG-DAG: swc1 $[[F0]], 40($[[R0]])<br>
<br>
store float %a0, float* getelementptr ([11 x float], [11 x float]* @fa, i32 0, i32 0), align 4<br>
@@ -397,7 +394,6 @@ entry:<br>
<br>
; FP64-NOODDSPREG-LABEL: callee3:<br>
<br>
-; FP64-NOODDSPREG: addiu $sp, $sp, -[[OFFSET:[0-9]+]]<br>
<br>
; Check that first 10 arguments are received in even float registers<br>
; f0, f2, ... , f18. Check that 11th argument is received on stack.<br>
@@ -414,7 +410,7 @@ entry:<br>
; FP64-NOODDSPREG-DAG: sdc1 $f16, 64($[[R0]])<br>
; FP64-NOODDSPREG-DAG: sdc1 $f18, 72($[[R0]])<br>
<br>
-; FP64-NOODDSPREG-DAG: ldc1 $[[F0:f[0-9]*[02468]]], [[OFFSET]]($sp)<br>
+; FP64-NOODDSPREG-DAG: ldc1 $[[F0:f[0-9]*[02468]]], 0($sp)<br>
; FP64-NOODDSPREG-DAG: sdc1 $[[F0]], 80($[[R0]])<br>
<br>
store double %a0, double* getelementptr ([11 x double], [11 x double]* @da, i32 0, i32 0), align 8<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>load-store-left-right.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/load-store-left-right.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/load-store-left-<wbr>right.ll?rev=297695&r1=297694&<wbr>r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>load-store-left-right.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>load-store-left-right.ll Mon Mar 13 19:34:14 2017<br>
@@ -250,12 +250,18 @@ entry:<br>
; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(<br>
; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s0)(<br>
<br>
-; FIXME: We should be able to do better than this on MIPS32r6/MIPS64r6 since<br>
-; we have unaligned halfword load/store available<br>
-; ALL-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])<br>
-; ALL-DAG: sb $[[R1]], 2($[[PTR]])<br>
-; ALL-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])<br>
-; ALL-DAG: sb $[[R1]], 3($[[PTR]])<br>
+; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS32-DAG: sb $[[R1]], 2($[[PTR]])<br>
+; MIPS32-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]])<br>
+; MIPS32-DAG: sb $[[R2]], 3($[[PTR]])<br>
+<br>
+; MIPS32R6: lhu $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS32R6: sh $[[R1]], 2($[[PTR]])<br>
+<br>
+; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS64-DAG: sb $[[R1]], 2($[[PTR]])<br>
+; MIPS64-DAG: lbu $[[R2:[0-9]+]], 1($[[PTR]])<br>
+; MIPS64-DAG: sb $[[R2]], 3($[[PTR]])<br>
<br>
%0 = load %struct.S0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 0), align 1<br>
store %struct.S0 %0, %struct.S0* getelementptr inbounds (%struct.S0, %struct.S0* @struct_s0, i32 1), align 1<br>
@@ -268,37 +274,54 @@ entry:<br>
<br>
; MIPS32-EL: lw $[[PTR:[0-9]+]], %got(struct_s1)(<br>
; MIPS32-EB: lw $[[PTR:[0-9]+]], %got(struct_s1)(<br>
-; MIPS32-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])<br>
-; MIPS32-DAG: sb $[[R1]], 4($[[PTR]])<br>
-; MIPS32-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])<br>
-; MIPS32-DAG: sb $[[R1]], 5($[[PTR]])<br>
-; MIPS32-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])<br>
-; MIPS32-DAG: sb $[[R1]], 6($[[PTR]])<br>
-; MIPS32-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])<br>
-; MIPS32-DAG: sb $[[R1]], 7($[[PTR]])<br>
+; MIPS32-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])<br>
+; MIPS32-EL-DAG: lwr $[[R1]], 0($[[PTR]])<br>
+; MIPS32-EL-DAG: swl $[[R1]], 7($[[PTR]])<br>
+; MIPS32-EL-DAG: swr $[[R1]], 4($[[PTR]])<br>
+; MIPS32-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS32-EB-DAG: lwr $[[R1]], 3($[[PTR]])<br>
+; MIPS32-EB-DAG: swl $[[R1]], 4($[[PTR]])<br>
+; MIPS32-EB-DAG: swr $[[R1]], 7($[[PTR]])<br>
+<br>
+; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 4($[[PTR]])<br>
+; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])<br>
+; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 5($[[PTR]])<br>
+; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])<br>
+; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 6($[[PTR]])<br>
+; MIPS32-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])<br>
+; MIPS32-NOLEFTRIGHT-DAG: sb $[[R1]], 7($[[PTR]])<br>
<br>
; MIPS32R6: lw $[[PTR:[0-9]+]], %got(struct_s1)(<br>
-; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]])<br>
-; MIPS32R6-DAG: sh $[[R1]], 4($[[PTR]])<br>
-; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]])<br>
-; MIPS32R6-DAG: sh $[[R1]], 6($[[PTR]])<br>
+; MIPS32R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS32R6-DAG: sw $[[R1]], 4($[[PTR]])<br>
<br>
; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(<br>
; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(<br>
-; MIPS64-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])<br>
-; MIPS64-DAG: sb $[[R1]], 4($[[PTR]])<br>
-; MIPS64-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])<br>
-; MIPS64-DAG: sb $[[R1]], 5($[[PTR]])<br>
-; MIPS64-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])<br>
-; MIPS64-DAG: sb $[[R1]], 6($[[PTR]])<br>
-; MIPS64-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])<br>
-; MIPS64-DAG: sb $[[R1]], 7($[[PTR]])<br>
+<br>
+; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])<br>
+; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]])<br>
+; MIPS64-EL-DAG: swl $[[R1]], 7($[[PTR]])<br>
+; MIPS64-EL-DAG: swr $[[R1]], 4($[[PTR]])<br>
+<br>
+; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])<br>
+; MIPS64-EB-DAG: swl $[[R1]], 4($[[PTR]])<br>
+; MIPS64-EB-DAG: swr $[[R1]], 7($[[PTR]])<br>
+<br>
+<br>
+; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 4($[[PTR]])<br>
+; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 1($[[PTR]])<br>
+; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 5($[[PTR]])<br>
+; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 2($[[PTR]])<br>
+; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 6($[[PTR]])<br>
+; MIPS64-NOLEFTRIGHT-DAG: lbu $[[R1:[0-9]+]], 3($[[PTR]])<br>
+; MIPS64-NOLEFTRIGHT-DAG: sb $[[R1]], 7($[[PTR]])<br>
<br>
; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s1)(<br>
-; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]])<br>
-; MIPS64R6-DAG: sh $[[R1]], 4($[[PTR]])<br>
-; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]])<br>
-; MIPS64R6-DAG: sh $[[R1]], 6($[[PTR]])<br>
+; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS64R6-DAG: sw $[[R1]], 4($[[PTR]])<br>
<br>
%0 = load %struct.S1, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 0), align 1<br>
store %struct.S1 %0, %struct.S1* getelementptr inbounds (%struct.S1, %struct.S1* @struct_s1, i32 1), align 1<br>
@@ -336,30 +359,21 @@ entry:<br>
; MIPS32R6-DAG: sw $[[R1]], 12($[[PTR]])<br>
<br>
; MIPS64-EL: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(<br>
-; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])<br>
-; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]])<br>
-; MIPS64-EL-DAG: swl $[[R1]], 11($[[PTR]])<br>
-; MIPS64-EL-DAG: swr $[[R1]], 8($[[PTR]])<br>
-; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 7($[[PTR]])<br>
-; MIPS64-EL-DAG: lwr $[[R1]], 4($[[PTR]])<br>
-; MIPS64-EL-DAG: swl $[[R1]], 15($[[PTR]])<br>
-; MIPS64-EL-DAG: swr $[[R1]], 12($[[PTR]])<br>
+<br>
+; MIPS64-EL-DAG: ldl $[[R1:[0-9]+]], 7($[[PTR]])<br>
+; MIPS64-EL-DAG: ldr $[[R1]], 0($[[PTR]])<br>
+; MIPS64-EL-DAG: sdl $[[R1]], 15($[[PTR]])<br>
+; MIPS64-EL-DAG: sdr $[[R1]], 8($[[PTR]])<br>
<br>
; MIPS64-EB: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(<br>
-; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])<br>
-; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])<br>
-; MIPS64-EB-DAG: swl $[[R1]], 8($[[PTR]])<br>
-; MIPS64-EB-DAG: swr $[[R1]], 11($[[PTR]])<br>
-; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 4($[[PTR]])<br>
-; MIPS64-EB-DAG: lwr $[[R1]], 7($[[PTR]])<br>
-; MIPS64-EB-DAG: swl $[[R1]], 12($[[PTR]])<br>
-; MIPS64-EB-DAG: swr $[[R1]], 15($[[PTR]])<br>
+; MIPS64-EB-DAG: ldl $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS64-EB-DAG: ldr $[[R1]], 7($[[PTR]])<br>
+; MIPS64-EB-DAG: sdl $[[R1]], 8($[[PTR]])<br>
+; MIPS64-EB-DAG: sdr $[[R1]], 15($[[PTR]])<br>
<br>
; MIPS64R6: ld $[[PTR:[0-9]+]], %got_disp(struct_s2)(<br>
-; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 0($[[PTR]])<br>
-; MIPS64R6-DAG: sw $[[R1]], 8($[[PTR]])<br>
-; MIPS64R6-DAG: lw $[[R1:[0-9]+]], 4($[[PTR]])<br>
-; MIPS64R6-DAG: sw $[[R1]], 12($[[PTR]])<br>
+; MIPS64R6-DAG: ld $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS64R6-DAG: sd $[[R1]], 8($[[PTR]])<br>
<br>
%0 = load %struct.S2, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 0), align 1<br>
store %struct.S2 %0, %struct.S2* getelementptr inbounds (%struct.S2, %struct.S2* @struct_s2, i32 1), align 1<br>
@@ -416,17 +430,17 @@ entry:<br>
; MIPS64-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[PTR]])<br>
; MIPS64-EL-DAG: lwr $[[R1]], 0($[[PTR]])<br>
<br>
-; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)(<br>
-; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])<br>
-; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])<br>
-; MIPS64-EB-DAG: dsll $[[R1]], $[[R1]], 32<br>
+; MIPS64-EB: ld $[[SPTR:[0-9]+]], %got_disp(arr)(<br>
; MIPS64-EB-DAG: lbu $[[R2:[0-9]+]], 5($[[PTR]])<br>
; MIPS64-EB-DAG: lbu $[[R3:[0-9]+]], 4($[[PTR]])<br>
; MIPS64-EB-DAG: dsll $[[T0:[0-9]+]], $[[R3]], 8<br>
; MIPS64-EB-DAG: or $[[T1:[0-9]+]], $[[T0]], $[[R2]]<br>
-; MIPS64-EB-DAG: dsll $[[T1]], $[[T1]], 16<br>
-; MIPS64-EB-DAG: or $[[T3:[0-9]+]], $[[R1]], $[[T1]]<br>
; MIPS64-EB-DAG: lbu $[[R4:[0-9]+]], 6($[[PTR]])<br>
+; MIPS64-EB-DAG: dsll $[[T1]], $[[T1]], 16<br>
+; MIPS64-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[PTR]])<br>
+; MIPS64-EB-DAG: lwr $[[R1]], 3($[[PTR]])<br>
+; MIPS64-EB-DAG: dsll $[[R5:[0-9]+]], $[[R1]], 32<br>
+; MIPS64-EB-DAG: or $[[T3:[0-9]+]], $[[R5]], $[[T1]]<br>
; MIPS64-EB-DAG: dsll $[[T4:[0-9]+]], $[[R4]], 8<br>
; MIPS64-EB-DAG: or $4, $[[T3]], $[[T4]]<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>micromips-li.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-li.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/micromips-li.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>micromips-li.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>micromips-li.ll Mon Mar 13 19:34:14 2017<br>
@@ -13,6 +13,6 @@ entry:<br>
ret i32 0<br>
}<br>
<br>
-; CHECK: li16 ${{[2-7]|16|17}}, 1<br>
; CHECK: addiu ${{[0-9]+}}, $zero, 2148<br>
+; CHECK: li16 ${{[2-7]|16|17}}, 1<br>
; CHECK: ori ${{[0-9]+}}, $zero, 33332<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>mips64-f128-call.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64-f128-call.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/mips64-f128-call.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>mips64-f128-call.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>mips64-f128-call.ll Mon Mar 13 19:34:14 2017<br>
@@ -4,8 +4,8 @@<br>
@gld1 = external global fp128<br>
<br>
; CHECK: foo0<br>
-; CHECK: sdc1 $f12, %lo(gld0)(${{[0-9]+}})<br>
-; CHECK: sdc1 $f13, 8(${{[0-9]+}})<br>
+; CHECK-DAG: sdc1 $f12, %lo(gld0)(${{[0-9]+}})<br>
+; CHECK-DAG: sdc1 $f13, 8(${{[0-9]+}})<br>
<br>
define void @foo0(fp128 %a0) {<br>
entry:<br>
@@ -14,8 +14,8 @@ entry:<br>
}<br>
<br>
; CHECK: foo1<br>
-; CHECK: ldc1 $f12, %lo(gld0)(${{[0-9]+}})<br>
-; CHECK: ldc1 $f13, 8(${{[0-9]+}})<br>
+; CHECK-DAG: ldc1 $f12, %lo(gld0)(${{[0-9]+}})<br>
+; CHECK-DAG: ldc1 $f13, 8(${{[0-9]+}})<br>
<br>
define void @foo1() {<br>
entry:<br>
@@ -26,11 +26,11 @@ entry:<br>
<br>
declare void @foo2(fp128)<br>
<br>
+<br>
; CHECK: foo3:<br>
-; CHECK: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %hi(gld0)<br>
-; CHECK: dsll $[[R1:[0-9]+]], $[[R0]], 16<br>
+<br>
+; CHECK: daddiu $[[R2:[0-9]+]], $[[R1:[0-9]+]], %lo(gld0)<br>
; CHECK: sdc1 $f0, %lo(gld0)($[[R1]])<br>
-; CHECK: daddiu $[[R2:[0-9]]], $[[R1]], %lo(gld0)<br>
; CHECK: sdc1 $f2, 8($[[R2]])<br>
; CHECK: daddiu $[[R3:[0-9]+]], ${{[0-9]+}}, %hi(gld1)<br>
; CHECK: dsll $[[R4:[0-9]+]], $[[R3]], 16<br>
@@ -39,7 +39,6 @@ declare void @foo2(fp128)<br>
; CHECK: ldc1 $f2, 8($[[R5]])<br>
<br>
<br>
-<br>
define fp128 @foo3() {<br>
entry:<br>
%call = tail call fp128 @foo4()<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>mips64-f128.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64-f128.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/mips64-f128.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>mips64-f128.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>mips64-f128.ll Mon Mar 13 19:34:14 2017<br>
@@ -577,10 +577,10 @@ entry:<br>
<br>
; ALL-LABEL: store_LD_LD:<br>
; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1)<br>
-; ALL: ld $[[R1:[0-9]+]], 0($[[R0]])<br>
; ALL: ld $[[R2:[0-9]+]], 8($[[R0]])<br>
; ALL: ld $[[R3:[0-9]+]], %got_disp(gld0)<br>
; ALL: sd $[[R2]], 8($[[R3]])<br>
+; ALL: ld $[[R1:[0-9]+]], 0($[[R0]])<br>
; ALL: sd $[[R1]], 0($[[R3]])<br>
<br>
define void @store_LD_LD() {<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>mno-ldc1-sdc1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mno-ldc1-sdc1.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/mno-ldc1-sdc1.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>mno-ldc1-sdc1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>mno-ldc1-sdc1.ll Mon Mar 13 19:34:14 2017<br>
@@ -130,12 +130,12 @@<br>
; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)<br>
; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25<br>
; MM-MNO-PIC: lw $[[R3:[0-9]+]], %got(g0)($[[R2]])<br>
-; MM-MNO-PIC: lw16 $[[R4:[0-9]+]], 0($[[R3]])<br>
-; MM-MNO-PIC: lw16 $[[R5:[0-9]+]], 4($[[R3]])<br>
-; MM-MNO-LE-PIC: mtc1 $[[R4]], $f0<br>
-; MM-MNO-LE-PIC: mthc1 $[[R5]], $f0<br>
-; MM-MNO-BE-PIC: mtc1 $[[R5]], $f0<br>
-; MM-MNO-BE-PIC: mthc1 $[[R4]], $f0<br>
+; MM-MNO-PIC-DAG: lw16 $[[R4:[0-9]+]], 0($[[R3]])<br>
+; MM-MNO-PIC-DAG: lw16 $[[R5:[0-9]+]], 4($[[R3]])<br>
+; MM-MNO-LE-PIC-DAG: mtc1 $[[R4]], $f0<br>
+; MM-MNO-LE-PIC-DAG: mthc1 $[[R5]], $f0<br>
+; MM-MNO-BE-PIC-DAG: mtc1 $[[R5]], $f0<br>
+; MM-MNO-BE-PIC-DAG: mthc1 $[[R4]], $f0<br>
<br>
; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0)<br>
; MM-STATIC-PIC: ldc1 $f0, %lo(g0)($[[R0]])<br>
@@ -214,13 +214,13 @@ entry:<br>
; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp)<br>
; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp)<br>
; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25<br>
-; MM-MNO-LE-PIC: mfc1 $[[R3:[0-9]+]], $f12<br>
-; MM-MNO-BE-PIC: mfhc1 $[[R3:[0-9]+]], $f12<br>
-; MM-MNO-PIC: lw $[[R4:[0-9]+]], %got(g0)($[[R2]])<br>
-; MM-MNO-PIC: sw16 $[[R3]], 0($[[R4]])<br>
-; MM-MNO-LE-PIC: mfhc1 $[[R5:[0-9]+]], $f12<br>
-; MM-MNO-BE-PIC: mfc1 $[[R5:[0-9]+]], $f12<br>
-; MM-MNO-PIC: sw16 $[[R5]], 4($[[R4]])<br>
+; MM-MNO-LE-PIC-DAG: mfc1 $[[R3:[0-9]+]], $f12<br>
+; MM-MNO-BE-PIC-DAG: mfhc1 $[[R3:[0-9]+]], $f12<br>
+; MM-MNO-PIC-DAG: lw $[[R4:[0-9]+]], %got(g0)($[[R2]])<br>
+; MM-MNO-PIC-DAG: sw16 $[[R3]], 0($[[R4]])<br>
+; MM-MNO-LE-PIC-DAG: mfhc1 $[[R5:[0-9]+]], $f12<br>
+; MM-MNO-BE-PIC-DAG: mfc1 $[[R5:[0-9]+]], $f12<br>
+; MM-MNO-PIC-DAG: sw16 $[[R5]], 4($[[R4]])<br>
<br>
; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0)<br>
; MM-STATIC-PIC: sdc1 $f12, %lo(g0)($[[R0]])<br>
@@ -267,8 +267,8 @@ entry:<br>
<br>
; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $5, 3<br>
; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]]<br>
-; MM-MNO-PIC: lw16 $[[R2:[0-9]+]], 0($[[R1]])<br>
-; MM-MNO-PIC: lw16 $[[R3:[0-9]+]], 4($[[R1]])<br>
+; MM-MNO-PIC-DAG: lw16 $[[R2:[0-9]+]], 0($[[R1]])<br>
+; MM-MNO-PIC-DAG: lw16 $[[R3:[0-9]+]], 4($[[R1]])<br>
; MM-MNO-LE-PIC: mtc1 $[[R2]], $f0<br>
; MM-MNO-LE-PIC: mthc1 $[[R3]], $f0<br>
; MM-MNO-BE-PIC: mtc1 $[[R3]], $f0<br>
@@ -313,14 +313,14 @@ entry:<br>
; MM: addu16 $[[R1:[0-9]+]], $6, $[[R0]]<br>
; MM: sdc1 $f12, 0($[[R1]])<br>
<br>
-; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3<br>
-; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]]<br>
-; MM-MNO-LE-PIC: mfc1 $[[R2:[0-9]+]], $f12<br>
-; MM-MNO-BE-PIC: mfhc1 $[[R2:[0-9]+]], $f12<br>
-; MM-MNO-PIC: sw16 $[[R2]], 0($[[R1]])<br>
-; MM-MNO-LE-PIC: mfhc1 $[[R3:[0-9]+]], $f12<br>
-; MM-MNO-BE-PIC: mfc1 $[[R3:[0-9]+]], $f12<br>
-; MM-MNO-PIC: sw16 $[[R3]], 4($[[R1]])<br>
+; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3<br>
+; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]]<br>
+; MM-MNO-LE-PIC-DAG: mfc1 $[[R2:[0-9]+]], $f12<br>
+; MM-MNO-BE-PIC-DAG: mfhc1 $[[R2:[0-9]+]], $f12<br>
+; MM-MNO-PIC-DAG: sw16 $[[R2]], 0($[[R1]])<br>
+; MM-MNO-LE-PIC-DAG: mfhc1 $[[R3:[0-9]+]], $f12<br>
+; MM-MNO-BE-PIC-DAG: mfc1 $[[R3:[0-9]+]], $f12<br>
+; MM-MNO-PIC-DAG: sw16 $[[R3]], 4($[[R1]])<br>
<br>
; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $7, 3<br>
; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]]<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>msa/f16-llvm-ir.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/f16-llvm-ir.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/msa/f16-llvm-ir.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>msa/f16-llvm-ir.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>msa/f16-llvm-ir.ll Mon Mar 13 19:34:14 2017<br>
@@ -234,15 +234,15 @@ entry:<br>
; MIPS32: insert.w $w[[W0]][1], $[[R1]]<br>
; MIPS32: insert.w $w[[W0]][3], $[[R1]]<br>
<br>
-; MIPS64-N64: ld $[[R3:[0-9]+]], %got_disp(h)<br>
-; MIPS64-N32: lw $[[R3:[0-9]+]], %got_disp(h)<br>
-; MIPS64: dmfc1 $[[R1:[0-9]+]], $f[[F2]]<br>
-; MIPS64: fill.d $w[[W0:[0-9]+]], $[[R1]]<br>
+; MIPS64-N64-DAG: ld $[[R3:[0-9]+]], %got_disp(h)<br>
+; MIPS64-N32-DAG: lw $[[R3:[0-9]+]], %got_disp(h)<br>
+; MIPS64-DAG: dmfc1 $[[R1:[0-9]+]], $f[[F2]]<br>
+; MIPS64-DAG: fill.d $w[[W0:[0-9]+]], $[[R1]]<br>
<br>
-; ALL: fexdo.w $w[[W1:[0-9]+]], $w[[W0]], $w[[W0]]<br>
-; ALL: fexdo.h $w[[W2:[0-9]+]], $w[[W1]], $w[[W1]]<br>
+; ALL-DAG: fexdo.w $w[[W1:[0-9]+]], $w[[W0]], $w[[W0]]<br>
+; ALL-DAG: fexdo.h $w[[W2:[0-9]+]], $w[[W1]], $w[[W1]]<br>
<br>
-; MIPS32: lw $[[R3:[0-9]+]], %got(h)<br>
+; MIPS32-DAG: lw $[[R3:[0-9]+]], %got(h)<br>
<br>
; ALL: copy_u.h $[[R2:[0-9]+]], $w[[W2]]<br>
; ALL: sh $[[R2]], 0($[[R3]])<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>msa/i5_ld_st.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/msa/i5_ld_st.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/msa/i5_ld_st.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>msa/i5_ld_st.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>msa/i5_ld_st.ll Mon Mar 13 19:34:14 2017<br>
@@ -336,8 +336,8 @@ entry:<br>
<br>
; CHECK: llvm_mips_st_b_valid_range_<wbr>tests:<br>
; CHECK: ld.b<br>
-; CHECK: st.b [[R1:\$w[0-9]+]], -512(<br>
-; CHECK: st.b [[R1:\$w[0-9]+]], 511(<br>
+; CHECK-DAG: st.b [[R1:\$w[0-9]+]], -512(<br>
+; CHECK-DAG: st.b [[R1:\$w[0-9]+]], 511(<br>
; CHECK: .size llvm_mips_st_b_valid_range_<wbr>tests<br>
;<br>
<br>
@@ -351,10 +351,10 @@ entry:<br>
}<br>
<br>
; CHECK: llvm_mips_st_b_invalid_range_<wbr>tests:<br>
-; CHECK: addiu $2, $1, -513<br>
+; CHECK: addiu $2, $1, 512<br>
; CHECK: ld.b<br>
; CHECK: st.b [[R1:\$w[0-9]+]], 0(<br>
-; CHECK: addiu $1, $1, 512<br>
+; CHECK: addiu $1, $1, -513<br>
; CHECK: st.b [[R1:\$w[0-9]+]], 0(<br>
; CHECK: .size llvm_mips_st_b_invalid_range_<wbr>tests<br>
;<br>
@@ -404,8 +404,8 @@ entry:<br>
<br>
; CHECK: llvm_mips_st_h_valid_range_<wbr>tests:<br>
; CHECK: ld.h<br>
-; CHECK: st.h [[R1:\$w[0-9]+]], -1024(<br>
-; CHECK: st.h [[R1:\$w[0-9]+]], 1022(<br>
+; CHECK-DAG: st.h [[R1:\$w[0-9]+]], -1024(<br>
+; CHECK-DAG: st.h [[R1:\$w[0-9]+]], 1022(<br>
; CHECK: .size llvm_mips_st_h_valid_range_<wbr>tests<br>
;<br>
<br>
@@ -419,10 +419,10 @@ entry:<br>
}<br>
<br>
; CHECK: llvm_mips_st_h_invalid_range_<wbr>tests:<br>
-; CHECK: addiu $2, $1, -1026<br>
+; CHECK: addiu $2, $1, 1024<br>
; CHECK: ld.h<br>
; CHECK: st.h [[R1:\$w[0-9]+]], 0(<br>
-; CHECK: addiu $1, $1, 1024<br>
+; CHECK: addiu $1, $1, -1026<br>
; CHECK: st.h [[R1:\$w[0-9]+]], 0(<br>
; CHECK: .size llvm_mips_st_h_invalid_range_<wbr>tests<br>
;<br>
@@ -472,8 +472,8 @@ entry:<br>
<br>
; CHECK: llvm_mips_st_w_valid_range_<wbr>tests:<br>
; CHECK: ld.w<br>
-; CHECK: st.w [[R1:\$w[0-9]+]], -2048(<br>
-; CHECK: st.w [[R1:\$w[0-9]+]], 2044(<br>
+; CHECK-DAG: st.w [[R1:\$w[0-9]+]], -2048(<br>
+; CHECK-DAG: st.w [[R1:\$w[0-9]+]], 2044(<br>
; CHECK: .size llvm_mips_st_w_valid_range_<wbr>tests<br>
;<br>
<br>
@@ -487,10 +487,10 @@ entry:<br>
}<br>
<br>
; CHECK: llvm_mips_st_w_invalid_range_<wbr>tests:<br>
-; CHECK: addiu $2, $1, -2052<br>
+; CHECK: addiu $2, $1, 2048<br>
; CHECK: ld.w<br>
; CHECK: st.w [[R1:\$w[0-9]+]], 0(<br>
-; CHECK: addiu $1, $1, 2048<br>
+; CHECK: addiu $1, $1, -2052<br>
; CHECK: st.w [[R1:\$w[0-9]+]], 0(<br>
; CHECK: .size llvm_mips_st_w_invalid_range_<wbr>tests<br>
;<br>
@@ -540,8 +540,8 @@ entry:<br>
<br>
; CHECK: llvm_mips_st_d_valid_range_<wbr>tests:<br>
; CHECK: ld.d<br>
-; CHECK: st.d [[R1:\$w[0-9]+]], -4096(<br>
-; CHECK: st.d [[R1:\$w[0-9]+]], 4088(<br>
+; CHECK-DAG: st.d [[R1:\$w[0-9]+]], -4096(<br>
+; CHECK-DAG: st.d [[R1:\$w[0-9]+]], 4088(<br>
; CHECK: .size llvm_mips_st_d_valid_range_<wbr>tests<br>
;<br>
<br>
@@ -555,10 +555,10 @@ entry:<br>
}<br>
<br>
; CHECK: llvm_mips_st_d_invalid_range_<wbr>tests:<br>
-; CHECK: addiu $2, $1, -4104<br>
+; CHECK: addiu $2, $1, 4096<br>
; CHECK: ld.d<br>
; CHECK: st.d [[R1:\$w[0-9]+]], 0(<br>
-; CHECK: addiu $1, $1, 4096<br>
+; CHECK: addiu $1, $1, -4104<br>
; CHECK: st.d [[R1:\$w[0-9]+]], 0(<br>
; CHECK: .size llvm_mips_st_d_invalid_range_<wbr>tests<br>
;<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_byval.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/o32_cc_byval.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_byval.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_byval.ll Mon Mar 13 19:34:14 2017<br>
@@ -45,20 +45,18 @@ declare void @callee3(float, %struct.S3*<br>
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {<br>
entry:<br>
; CHECK: addiu $sp, $sp, -48<br>
-; CHECK: sw $7, 60($sp)<br>
-; CHECK: sw $6, 56($sp)<br>
-; CHECK: lw $4, 80($sp)<br>
-; CHECK: ldc1 $f[[F0:[0-9]+]], 72($sp)<br>
-; CHECK: lw $[[R3:[0-9]+]], 64($sp)<br>
-; CHECK: lw $[[R4:[0-9]+]], 68($sp)<br>
-; CHECK: lw $[[R2:[0-9]+]], 60($sp)<br>
-; CHECK: lh $[[R1:[0-9]+]], 58($sp)<br>
-; CHECK: lb $[[R0:[0-9]+]], 56($sp)<br>
-; CHECK: sw $[[R0]], 32($sp)<br>
-; CHECK: sw $[[R1]], 28($sp)<br>
-; CHECK: sw $[[R2]], 24($sp)<br>
-; CHECK: sw $[[R4]], 20($sp)<br>
-; CHECK: sw $[[R3]], 16($sp)<br>
+; CHECK-DAG: sw $7, 60($sp)<br>
+; CHECK-DAG: sw $6, 56($sp)<br>
+; CHECK-DAG: ldc1 $f[[F0:[0-9]+]], 72($sp)<br>
+; CHECK-DAG: lw $[[R3:[0-9]+]], 64($sp)<br>
+; CHECK-DAG: lw $[[R4:[0-9]+]], 68($sp)<br>
+; CHECK-DAG: lh $[[R1:[0-9]+]], 58($sp)<br>
+; CHECK-DAG: lb $[[R0:[0-9]+]], 56($sp)<br>
+; CHECK-DAG: sw $[[R0]], 32($sp)<br>
+; CHECK-DAG: sw $[[R1]], 28($sp)<br>
+; CHECK-DAG: sw $[[R4]], 20($sp)<br>
+; CHECK-DAG: sw $[[R3]], 16($sp)<br>
+; CHECK-DAG: sw $7, 24($sp)<br>
; CHECK: mfc1 $6, $f[[F0]]<br>
<br>
%i2 = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 5<br>
@@ -82,13 +80,11 @@ declare void @callee4(i32, double, i64,<br>
define void @f3(%struct.S2* nocapture byval %s2) nounwind {<br>
entry:<br>
; CHECK: addiu $sp, $sp, -48<br>
-; CHECK: sw $7, 60($sp)<br>
-; CHECK: sw $6, 56($sp)<br>
-; CHECK: sw $5, 52($sp)<br>
-; CHECK: sw $4, 48($sp)<br>
-; CHECK: lw $4, 48($sp)<br>
-; CHECK: lw $[[R0:[0-9]+]], 60($sp)<br>
-; CHECK: sw $[[R0]], 24($sp)<br>
+; CHECK-DAG: sw $7, 60($sp)<br>
+; CHECK-DAG: sw $6, 56($sp)<br>
+; CHECK-DAG: sw $5, 52($sp)<br>
+; CHECK-DAG: sw $4, 48($sp)<br>
+; CHECK-DAG: sw $7, 24($sp)<br>
<br>
%arrayidx = getelementptr inbounds %struct.S2, %struct.S2* %s2, i32 0, i32 0, i32 0<br>
%tmp = load i32, i32* %arrayidx, align 4<br>
@@ -101,14 +97,14 @@ entry:<br>
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {<br>
entry:<br>
; CHECK: addiu $sp, $sp, -48<br>
-; CHECK: sw $7, 60($sp)<br>
-; CHECK: sw $6, 56($sp)<br>
-; CHECK: sw $5, 52($sp)<br>
-; CHECK: lw $4, 60($sp)<br>
-; CHECK: lw $[[R1:[0-9]+]], 80($sp)<br>
-; CHECK: lb $[[R0:[0-9]+]], 52($sp)<br>
-; CHECK: sw $[[R0]], 32($sp)<br>
-; CHECK: sw $[[R1]], 24($sp)<br>
+; CHECK-DAG: sw $7, 60($sp)<br>
+; CHECK-DAG: sw $6, 56($sp)<br>
+; CHECK-DAG: sw $5, 52($sp)<br>
+; CHECK-DAG: lw $[[R1:[0-9]+]], 80($sp)<br>
+; CHECK-DAG: lb $[[R0:[0-9]+]], 52($sp)<br>
+; CHECK-DAG: sw $[[R0]], 32($sp)<br>
+; CHECK-DAG: sw $[[R1]], 24($sp)<br>
+; CHECK: move $4, $7<br>
<br>
%i = getelementptr inbounds %struct.S1, %struct.S1* %s1, i32 0, i32 2<br>
%tmp = load i32, i32* %i, align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_vararg.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Mips/o32_cc_vararg.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_vararg.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/<wbr>o32_cc_vararg.ll Mon Mar 13 19:34:14 2017<br>
@@ -29,9 +29,9 @@ entry:<br>
<br>
; CHECK-LABEL: va1:<br>
; CHECK: addiu $sp, $sp, -16<br>
+; CHECK: sw $5, 20($sp)<br>
; CHECK: sw $7, 28($sp)<br>
; CHECK: sw $6, 24($sp)<br>
-; CHECK: sw $5, 20($sp)<br>
; CHECK: lw $2, 20($sp)<br>
}<br>
<br>
@@ -83,8 +83,8 @@ entry:<br>
<br>
; CHECK-LABEL: va3:<br>
; CHECK: addiu $sp, $sp, -16<br>
-; CHECK: sw $7, 28($sp)<br>
; CHECK: sw $6, 24($sp)<br>
+; CHECK: sw $7, 28($sp)<br>
; CHECK: lw $2, 24($sp)<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/anon_aggr.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/anon_aggr.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/anon_aggr.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/anon_aggr.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/anon_aggr.ll Mon Mar 13 19:34:14 2017<br>
@@ -60,33 +60,34 @@ equal:<br>
unequal:<br>
ret i8* %array2_ptr<br>
}<br>
-<br>
; CHECK-LABEL: func2:<br>
-; CHECK: ld [[REG2:[0-9]+]], 72(1)<br>
-; CHECK: cmpld {{([0-9]+,)?}}4, [[REG2]]<br>
-; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]<br>
+; CHECK: cmpld {{([0-9]+,)?}}4, 6<br>
+; CHECK-DAG: std 6, 72(1)<br>
+; CHECK-DAG: std 5, 64(1)<br>
+; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]]<br>
; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]<br>
; CHECK: ld 3, -[[OFFSET2]](1)<br>
; CHECK: ld 3, -[[OFFSET1]](1)<br>
<br>
-; DARWIN32: _func2:<br>
-; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36<br>
-; DARWIN32: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])<br>
+; DARWIN32-LABEL: _func2<br>
+; DARWIN32-DAG: addi r[[REG8:[0-9]+]], r[[REGSP:[0-9]+]], 36<br>
+; DARWIN32-DAG: lwz r[[REG2:[0-9]+]], 44(r[[REGSP]])<br>
; DARWIN32: mr<br>
-; DARWIN32: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]<br>
-; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]<br>
-; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]<br>
-; DARWIN32: stw r[[REG2]], -[[OFFSET2:[0-9]+]]<br>
-; DARWIN32: lwz r3, -[[OFFSET1]]<br>
-; DARWIN32: lwz r3, -[[OFFSET2]]<br>
+; DARWIN32: mr r[[REG7:[0-9]+]], r5<br>
+; DARWIN32-DAG: cmplw {{(cr[0-9]+,)?}}r5, r[[REG2]]<br>
+; DARWIN32-DAG: stw r[[REG7]], -[[OFFSET1:[0-9]+]]<br>
+; DARWIN32-DAG: stw r[[REG2]], -[[OFFSET2:[0-9]+]]<br>
+; DARWIN32-DAG: lwz r3, -[[OFFSET1]]<br>
+; DARWIN32-DAG: lwz r3, -[[OFFSET2]]<br>
+<br>
<br>
; DARWIN64: _func2:<br>
; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)<br>
; DARWIN64: mr<br>
; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]<br>
; DARWIN64: cmpld {{(cr[0-9]+,)?}}r[[REGA]], r[[REG2]]<br>
-; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]<br>
; DARWIN64: std r[[REG2]], -[[OFFSET2:[0-9]+]]<br>
+; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]<br>
; DARWIN64: ld r3, -[[OFFSET1]]<br>
; DARWIN64: ld r3, -[[OFFSET2]]<br>
<br>
@@ -106,24 +107,24 @@ unequal:<br>
}<br>
<br>
; CHECK-LABEL: func3:<br>
-; CHECK: ld [[REG3:[0-9]+]], 72(1)<br>
-; CHECK: ld [[REG4:[0-9]+]], 56(1)<br>
-; CHECK: cmpld {{([0-9]+,)?}}[[REG4]], [[REG3]]<br>
-; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1)<br>
-; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1)<br>
+; CHECK: cmpld {{([0-9]+,)?}}4, 6<br>
+; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]](1)<br>
+; CHECK-DAG: std 6, -[[OFFSET1:[0-9]+]](1)<br>
; CHECK: ld 3, -[[OFFSET2]](1)<br>
; CHECK: ld 3, -[[OFFSET1]](1)<br>
<br>
-; DARWIN32: _func3:<br>
-; DARWIN32: addi r[[REG1:[0-9]+]], r[[REGSP:[0-9]+]], 36<br>
-; DARWIN32: addi r[[REG2:[0-9]+]], r[[REGSP]], 24<br>
-; DARWIN32: lwz r[[REG3:[0-9]+]], 44(r[[REGSP]])<br>
-; DARWIN32: lwz r[[REG4:[0-9]+]], 32(r[[REGSP]])<br>
-; DARWIN32: cmplw {{(cr[0-9]+,)?}}r[[REG4]], r[[REG3]]<br>
-; DARWIN32: stw r[[REG3]], -[[OFFSET1:[0-9]+]]<br>
-; DARWIN32: stw r[[REG4]], -[[OFFSET2:[0-9]+]]<br>
-; DARWIN32: lwz r3, -[[OFFSET2]]<br>
-; DARWIN32: lwz r3, -[[OFFSET1]]<br>
+; DARWIN32-LABEL: _func3:<br>
+; DARWIN32-DAG: stw r[[REG8:[0-9]+]], 44(r[[REGSP:[0-9]+]])<br>
+; DARWIN32-DAG: stw r[[REG5:[0-9]+]], 32(r[[REGSP]])<br>
+; DARWIN32-DAG: addi r[[REG5a:[0-9]+]], r[[REGSP:[0-9]+]], 36<br>
+; DARWIN32-DAG: addi r[[REG8a:[0-9]+]], r[[REGSP]], 24<br>
+; DARWIN32-DAG: lwz r[[REG5a:[0-9]+]], 44(r[[REGSP]])<br>
+; DARWIN32-DAG: lwz r[[REG8a:[0-9]+]], 32(r[[REGSP]])<br>
+; DARWIN32-DAG: cmplw {{(cr[0-9]+,)?}}r[[REG8a]], r[[REG5a]]<br>
+; DARWIN32-DAG: stw r[[REG5a]], -[[OFFSET1:[0-9]+]]<br>
+; DARWIN32-DAG: stw r[[REG8a]], -[[OFFSET2:[0-9]+]]<br>
+; DARWIN32-DAG: lwz r3, -[[OFFSET1:[0-9]+]]<br>
+; DARWIN32-DAG: lwz r3, -[[OFFSET2:[0-9]+]]<br>
<br>
; DARWIN64: _func3:<br>
; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1)<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/complex-return.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/complex-return.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/complex-<wbr>return.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/complex-return.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/complex-return.ll Mon Mar 13 19:34:14 2017<br>
@@ -24,10 +24,10 @@ entry:<br>
}<br>
<br>
; CHECK-LABEL: foo:<br>
-; CHECK: lfd 1<br>
-; CHECK: lfd 2<br>
-; CHECK: lfd 3<br>
-; CHECK: lfd 4<br>
+; CHECK-DAG: lfd 1<br>
+; CHECK-DAG: lfd 2<br>
+; CHECK-DAG: lfd 3<br>
+; CHECK_DAG: lfd 4<br>
<br>
define { float, float } @oof() nounwind {<br>
entry:<br>
@@ -50,6 +50,6 @@ entry:<br>
}<br>
<br>
; CHECK-LABEL: oof:<br>
-; CHECK: lfs 2<br>
-; CHECK: lfs 1<br>
+; CHECK-DAG: lfs 2<br>
+; CHECK-DAG: lfs 1<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/jaggedstructs.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/jaggedstructs.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/jaggedstructs.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/jaggedstructs.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/jaggedstructs.ll Mon Mar 13 19:34:14 2017<br>
@@ -18,31 +18,31 @@ entry:<br>
ret void<br>
}<br>
<br>
-; CHECK: std 6, 184(1)<br>
-; CHECK: std 5, 176(1)<br>
-; CHECK: std 4, 168(1)<br>
-; CHECK: std 3, 160(1)<br>
-; CHECK: lbz {{[0-9]+}}, 167(1)<br>
-; CHECK: lhz {{[0-9]+}}, 165(1)<br>
-; CHECK: stb {{[0-9]+}}, 55(1)<br>
-; CHECK: sth {{[0-9]+}}, 53(1)<br>
-; CHECK: lbz {{[0-9]+}}, 175(1)<br>
-; CHECK: lwz {{[0-9]+}}, 171(1)<br>
-; CHECK: stb {{[0-9]+}}, 63(1)<br>
-; CHECK: stw {{[0-9]+}}, 59(1)<br>
-; CHECK: lhz {{[0-9]+}}, 182(1)<br>
-; CHECK: lwz {{[0-9]+}}, 178(1)<br>
-; CHECK: sth {{[0-9]+}}, 70(1)<br>
-; CHECK: stw {{[0-9]+}}, 66(1)<br>
-; CHECK: lbz {{[0-9]+}}, 191(1)<br>
-; CHECK: lhz {{[0-9]+}}, 189(1)<br>
-; CHECK: lwz {{[0-9]+}}, 185(1)<br>
-; CHECK: stb {{[0-9]+}}, 79(1)<br>
-; CHECK: sth {{[0-9]+}}, 77(1)<br>
-; CHECK: stw {{[0-9]+}}, 73(1)<br>
-; CHECK: ld 6, 72(1)<br>
-; CHECK: ld 5, 64(1)<br>
-; CHECK: ld 4, 56(1)<br>
-; CHECK: ld 3, 48(1)<br>
+; CHECK-DAG: std 3, 160(1)<br>
+; CHECK-DAG: std 6, 184(1)<br>
+; CHECK-DAG: std 5, 176(1)<br>
+; CHECK-DAG: std 4, 168(1)<br>
+; CHECK-DAG: lbz {{[0-9]+}}, 167(1)<br>
+; CHECK-DAG: lhz {{[0-9]+}}, 165(1)<br>
+; CHECK-DAG: stb {{[0-9]+}}, 55(1)<br>
+; CHECK-DAG-DAG: sth {{[0-9]+}}, 53(1)<br>
+; CHECK-DAG: lbz {{[0-9]+}}, 175(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 171(1)<br>
+; CHECK-DAG: stb {{[0-9]+}}, 63(1)<br>
+; CHECK-DAG: stw {{[0-9]+}}, 59(1)<br>
+; CHECK-DAG: lhz {{[0-9]+}}, 182(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 178(1)<br>
+; CHECK-DAG: sth {{[0-9]+}}, 70(1)<br>
+; CHECK-DAG: stw {{[0-9]+}}, 66(1)<br>
+; CHECK-DAG: lbz {{[0-9]+}}, 191(1)<br>
+; CHECK-DAG: lhz {{[0-9]+}}, 189(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 185(1)<br>
+; CHECK-DAG: stb {{[0-9]+}}, 79(1)<br>
+; CHECK-DAG: sth {{[0-9]+}}, 77(1)<br>
+; CHECK-DAG: stw {{[0-9]+}}, 73(1)<br>
+; CHECK-DAG: ld 6, 72(1)<br>
+; CHECK-DAG: ld 5, 64(1)<br>
+; CHECK-DAG: ld 4, 56(1)<br>
+; CHECK-DAG: ld 3, 48(1)<br>
<br>
declare void @check(%struct.S3* byval, %struct.S5* byval, %struct.S6* byval, %struct.S7* byval)<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/ppc64-align-long-<wbr>double.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64-align-long-double.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/ppc64-align-<wbr>long-double.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/ppc64-align-long-<wbr>double.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/ppc64-align-long-<wbr>double.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,6 +1,6 @@<br>
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=-vsx < %s | FileCheck %s<br>
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s<br>
-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck %s<br>
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-P9 %s<br>
<br>
; Verify internal alignment of long double in a struct. The double<br>
; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain<br>
@@ -19,19 +19,44 @@ entry:<br>
ret ppc_fp128 %0<br>
}<br>
<br>
+; The additional stores are caused because we forward the value in the<br>
+; store->load->bitcast path to make a store and bitcast of the same<br>
+; value. Since the target does bitcast through memory and we no longer<br>
+; remember the address we need to do the store in a fresh local<br>
+; address.<br>
+<br>
; CHECK-DAG: std 6, 72(1)<br>
; CHECK-DAG: std 5, 64(1)<br>
; CHECK-DAG: std 4, 56(1)<br>
; CHECK-DAG: std 3, 48(1)<br>
-; CHECK: lfd 1, 64(1)<br>
-; CHECK: lfd 2, 72(1)<br>
+<br>
+; CHECK-DAG: std 5, -16(1)<br>
+; CHECK-DAG: std 6, -8(1)<br>
+; CHECK-DAG: lfd 1, -16(1)<br>
+; CHECK-DAG: lfd 2, -8(1)<br>
+<br>
+; FIXMECHECK: lfd 1, 64(1)<br>
+; FIXMECHECK: lfd 2, 72(1)<br>
<br>
; CHECK-VSX-DAG: std 6, 72(1)<br>
; CHECK-VSX-DAG: std 5, 64(1)<br>
; CHECK-VSX-DAG: std 4, 56(1)<br>
; CHECK-VSX-DAG: std 3, 48(1)<br>
-; CHECK-VSX: li 3, 16<br>
-; CHECK-VSX: addi 4, 1, 48<br>
-; CHECK-VSX: lxsdx 1, 4, 3<br>
-; CHECK-VSX: li 3, 24<br>
-; CHECK-VSX: lxsdx 2, 4, 3<br>
+; CHECK-VSX-DAG: std 5, -16(1)<br>
+; CHECK-VSX-DAG: std 6, -8(1)<br>
+; CHECK-VSX: addi 3, 1, -16<br>
+; CHECK-VSX: lxsdx 1, 0, 3<br>
+; CHECK-VSX: addi 3, 1, -8<br>
+; CHECK-VSX: lxsdx 2, 0, 3<br>
+<br>
+; FIXME-VSX: addi 4, 1, 48<br>
+; FIXME-VSX: lxsdx 1, 4, 3<br>
+; FIXME-VSX: li 3, 24<br>
+; FIXME-VSX: lxsdx 2, 4, 3<br>
+<br>
+; CHECK-P9: std 6, 72(1)<br>
+; CHECK-P9: std 5, 64(1)<br>
+; CHECK-P9: std 4, 56(1)<br>
+; CHECK-P9: std 3, 48(1)<br>
+; CHECK-P9: mtvsrd 1, 5<br>
+; CHECK-P9: mtvsrd 2, 6<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/structsinmem.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/structsinmem.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/structsinmem.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/structsinmem.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/structsinmem.ll Mon Mar 13 19:34:14 2017<br>
@@ -113,13 +113,13 @@ entry:<br>
%add13 = add nsw i32 %add11, %6<br>
ret i32 %add13<br>
<br>
-; CHECK: lha {{[0-9]+}}, 126(1)<br>
-; CHECK: lha {{[0-9]+}}, 132(1)<br>
-; CHECK: lbz {{[0-9]+}}, 119(1)<br>
-; CHECK: lwz {{[0-9]+}}, 140(1)<br>
-; CHECK: lwz {{[0-9]+}}, 144(1)<br>
-; CHECK: lwz {{[0-9]+}}, 152(1)<br>
-; CHECK: lwz {{[0-9]+}}, 160(1)<br>
+; CHECK-DAG: lha {{[0-9]+}}, 126(1)<br>
+; CHECK-DAG: lha {{[0-9]+}}, 132(1)<br>
+; CHECK-DAG: lbz {{[0-9]+}}, 119(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 140(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 144(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 152(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 160(1)<br>
}<br>
<br>
define i32 @caller2() nounwind {<br>
@@ -205,11 +205,11 @@ entry:<br>
%add13 = add nsw i32 %add11, %6<br>
ret i32 %add13<br>
<br>
-; CHECK: lha {{[0-9]+}}, 126(1)<br>
-; CHECK: lha {{[0-9]+}}, 133(1)<br>
-; CHECK: lbz {{[0-9]+}}, 119(1)<br>
-; CHECK: lwz {{[0-9]+}}, 140(1)<br>
-; CHECK: lwz {{[0-9]+}}, 147(1)<br>
-; CHECK: lwz {{[0-9]+}}, 154(1)<br>
-; CHECK: lwz {{[0-9]+}}, 161(1)<br>
+; CHECK-DAG: lha {{[0-9]+}}, 126(1)<br>
+; CHECK-DAG: lha {{[0-9]+}}, 133(1)<br>
+; CHECK-DAG: lbz {{[0-9]+}}, 119(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 140(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 147(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 154(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 161(1)<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>PowerPC/structsinregs.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/structsinregs.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/PowerPC/structsinregs.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>PowerPC/structsinregs.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>PowerPC/structsinregs.ll Mon Mar 13 19:34:14 2017<br>
@@ -59,6 +59,7 @@ entry:<br>
%call = call i32 @callee1(%struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7)<br>
ret i32 %call<br>
<br>
+; CHECK-LABEL: caller1<br>
; CHECK: ld 9, 112(31)<br>
; CHECK: ld 8, 120(31)<br>
; CHECK: ld 7, 128(31)<br>
@@ -97,20 +98,21 @@ entry:<br>
%add13 = add nsw i32 %add11, %6<br>
ret i32 %add13<br>
<br>
-; CHECK: std 9, 96(1)<br>
-; CHECK: std 8, 88(1)<br>
-; CHECK: std 7, 80(1)<br>
-; CHECK: stw 6, 76(1)<br>
-; CHECK: stw 5, 68(1)<br>
-; CHECK: sth 4, 62(1)<br>
-; CHECK: stb 3, 55(1)<br>
-; CHECK: lha {{[0-9]+}}, 62(1)<br>
-; CHECK: lha {{[0-9]+}}, 68(1)<br>
-; CHECK: lbz {{[0-9]+}}, 55(1)<br>
-; CHECK: lwz {{[0-9]+}}, 76(1)<br>
-; CHECK: lwz {{[0-9]+}}, 80(1)<br>
-; CHECK: lwz {{[0-9]+}}, 88(1)<br>
-; CHECK: lwz {{[0-9]+}}, 96(1)<br>
+; CHECK-LABEL: callee1<br>
+; CHECK-DAG: std 9, 96(1)<br>
+; CHECK-DAG: std 8, 88(1)<br>
+; CHECK-DAG: std 7, 80(1)<br>
+; CHECK-DAG: stw 6, 76(1)<br>
+; CHECK-DAG: stw 5, 68(1)<br>
+; CHECK-DAG: sth 4, 62(1)<br>
+; CHECK-DAG: stb 3, 55(1)<br>
+; CHECK-DAG: lha {{[0-9]+}}, 62(1)<br>
+; CHECK-DAG: lha {{[0-9]+}}, 68(1)<br>
+; CHECK-DAG: lbz {{[0-9]+}}, 55(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 76(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 80(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 88(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 96(1)<br>
}<br>
<br>
define i32 @caller2() nounwind {<br>
@@ -139,6 +141,7 @@ entry:<br>
%call = call i32 @callee2(%struct.t1* byval %p1, %struct.t2* byval %p2, %struct.t3* byval %p3, %struct.t4* byval %p4, %struct.t5* byval %p5, %struct.t6* byval %p6, %struct.t7* byval %p7)<br>
ret i32 %call<br>
<br>
+; CHECK-LABEL: caller2<br>
; CHECK: stb {{[0-9]+}}, 71(1)<br>
; CHECK: sth {{[0-9]+}}, 69(1)<br>
; CHECK: stb {{[0-9]+}}, 87(1)<br>
@@ -184,18 +187,19 @@ entry:<br>
%add13 = add nsw i32 %add11, %6<br>
ret i32 %add13<br>
<br>
-; CHECK: std 9, 96(1)<br>
-; CHECK: std 8, 88(1)<br>
-; CHECK: std 7, 80(1)<br>
-; CHECK: stw 6, 76(1)<br>
-; CHECK: std 5, 64(1)<br>
-; CHECK: sth 4, 62(1)<br>
-; CHECK: stb 3, 55(1)<br>
-; CHECK: lha {{[0-9]+}}, 62(1)<br>
-; CHECK: lha {{[0-9]+}}, 69(1)<br>
-; CHECK: lbz {{[0-9]+}}, 55(1)<br>
-; CHECK: lwz {{[0-9]+}}, 76(1)<br>
-; CHECK: lwz {{[0-9]+}}, 83(1)<br>
-; CHECK: lwz {{[0-9]+}}, 90(1)<br>
-; CHECK: lwz {{[0-9]+}}, 97(1)<br>
+; CHECK-LABEL: callee2<br>
+; CHECK-DAG: std 9, 96(1)<br>
+; CHECK-DAG: std 8, 88(1)<br>
+; CHECK-DAG: std 7, 80(1)<br>
+; CHECK-DAG: stw 6, 76(1)<br>
+; CHECK-DAG: std 5, 64(1)<br>
+; CHECK-DAG: sth 4, 62(1)<br>
+; CHECK-DAG: stb 3, 55(1)<br>
+; CHECK-DAG: lha {{[0-9]+}}, 62(1)<br>
+; CHECK-DAG: lha {{[0-9]+}}, 69(1)<br>
+; CHECK-DAG: lbz {{[0-9]+}}, 55(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 76(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 83(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 90(1)<br>
+; CHECK-DAG: lwz {{[0-9]+}}, 97(1)<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>SystemZ/unaligned-01.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/unaligned-01.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/SystemZ/unaligned-01.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>SystemZ/unaligned-01.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>SystemZ/unaligned-01.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,10 +1,7 @@<br>
; Check that unaligned accesses are allowed in general. We check the<br>
; few exceptions (like CRL) in their respective test files.<br>
;<br>
-; FIXME: -combiner-alias-analysis (the default for SystemZ) stops<br>
-; f1 from being optimized.<br>
-; RUN: llc < %s -mtriple=s390x-linux-gnu -combiner-alias-analysis=false \<br>
-; RUN: | FileCheck %s<br>
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s<br>
<br>
; Check that these four byte stores become a single word store.<br>
define void @f1(i8 *%ptr) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb/<wbr>2010-07-15-debugOrdering.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Thumb/2010-07-15-<wbr>debugOrdering.ll?rev=297695&<wbr>r1=297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Thumb/<wbr>2010-07-15-debugOrdering.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb/<wbr>2010-07-15-debugOrdering.ll Mon Mar 13 19:34:14 2017<br>
@@ -9,9 +9,9 @@<br>
<br>
define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind {<br>
; CHECK: bl ___muldf3<br>
-; CHECK: bl ___muldf3<br>
; CHECK: beq LBB0<br>
; CHECK: bl ___muldf3<br>
+; CHECK: bl ___muldf3<br>
; <label>:3<br>
switch i32 %1, label %4 [<br>
i32 0, label %5<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb/<wbr>stack-access.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/stack-access.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Thumb/stack-access.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Thumb/<wbr>stack-access.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb/<wbr>stack-access.ll Mon Mar 13 19:34:14 2017<br>
@@ -74,15 +74,17 @@ define zeroext i16 @test6() {<br>
}<br>
<br>
; Accessing the bottom of a large array shouldn't require materializing a base<br>
+;<br>
+; CHECK: movs [[REG:r[0-9]+]], #1<br>
+; CHECK: str [[REG]], [sp, #16]<br>
+; CHECK: str [[REG]], [sp, #4]<br>
+<br>
define void @test7() {<br>
%arr = alloca [200 x i32], align 4<br>
<br>
- ; CHECK: movs [[REG:r[0-9]+]], #1<br>
- ; CHECK: str [[REG]], [sp, #4]<br>
%arrayidx = getelementptr inbounds [200 x i32], [200 x i32]* %arr, i32 0, i32 1<br>
store i32 1, i32* %arrayidx, align 4<br>
<br>
- ; CHECK: str [[REG]], [sp, #16]<br>
%arrayidx1 = getelementptr inbounds [200 x i32], [200 x i32]* %arr, i32 0, i32 4<br>
store i32 1, i32* %arrayidx1, align 4<br>
<br>
@@ -96,30 +98,36 @@ define void @test8() {<br>
%arr1 = alloca [224 x i32], align 4<br>
<br>
; CHECK: movs [[REG:r[0-9]+]], #1<br>
-; CHECK: str [[REG]], [sp]<br>
+; CHECK-DAG: str [[REG]], [sp]<br>
%arr1idx1 = getelementptr inbounds [224 x i32], [224 x i32]* %arr1, i32 0, i32 0<br>
store i32 1, i32* %arr1idx1, align 4<br>
<br>
; Offset in range for sp-based store, but not for non-sp-based store<br>
-; CHECK: str [[REG]], [sp, #128]<br>
+; CHECK-DAG: str [[REG]], [sp, #128]<br>
%arr1idx2 = getelementptr inbounds [224 x i32], [224 x i32]* %arr1, i32 0, i32 32<br>
store i32 1, i32* %arr1idx2, align 4<br>
<br>
-; CHECK: str [[REG]], [sp, #896]<br>
+; CHECK-DAG: str [[REG]], [sp, #896]<br>
%arr2idx1 = getelementptr inbounds [224 x i32], [224 x i32]* %arr2, i32 0, i32 0<br>
store i32 1, i32* %arr2idx1, align 4<br>
<br>
; %arr2 is in range, but this element of it is not<br>
-; CHECK: str [[REG]], [{{r[0-9]+}}]<br>
+; CHECK-DAG: ldr [[RA:r[0-9]+]], .LCPI7_2<br>
+; CHECK-DAG: add [[RA]], sp<br>
+; CHECK-DAG: str [[REG]], [{{r[0-9]+}}]<br>
%arr2idx2 = getelementptr inbounds [224 x i32], [224 x i32]* %arr2, i32 0, i32 32<br>
store i32 1, i32* %arr2idx2, align 4<br>
<br>
; %arr3 is not in range<br>
-; CHECK: str [[REG]], [{{r[0-9]+}}]<br>
+; CHECK-DAG: ldr [[RB:r[0-9]+]], .LCPI7_3<br>
+; CHECK-DAG: add [[RB]], sp<br>
+; CHECK-DAG: str [[REG]], [{{r[0-9]+}}]<br>
%arr3idx1 = getelementptr inbounds [224 x i32], [224 x i32]* %arr3, i32 0, i32 0<br>
store i32 1, i32* %arr3idx1, align 4<br>
<br>
-; CHECK: str [[REG]], [{{r[0-9]+}}]<br>
+; CHECK-DAG: ldr [[RC:r[0-9]+]], .LCPI7_4<br>
+; CHECK-DAG: add [[RC]], sp<br>
+; CHECK-DAG: str [[REG]], [{{r[0-9]+}}]<br>
%arr3idx2 = getelementptr inbounds [224 x i32], [224 x i32]* %arr3, i32 0, i32 32<br>
store i32 1, i32* %arr3idx2, align 4<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>2010-09-17-SideEffectsInChain.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/2010-09-17-<wbr>SideEffectsInChain.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>2010-09-17-SideEffectsInChain.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>2010-09-17-SideEffectsInChain.<wbr>ll Mon Mar 13 19:34:14 2017<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc < %s -combiner-alias-analysis -march=x86-64 -mcpu=core2 | FileCheck %s<br>
+; RUN: llc < %s -march=x86-64 -mcpu=core2 | FileCheck %s<br>
<br>
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-<wbr>i16:16:16-i32:32:32-i64:64:64-<wbr>f32:32:32-f64:64:64-v64:64:64-<wbr>v128:128:128-a0:0:64-s0:64:64-<wbr>f80:128:128-n8:16:32:64"<br>
target triple = "x86_64-apple-darwin10.4"<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>2012-11-28-merge-store-alias.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-11-28-merge-store-alias.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/2012-11-28-merge-<wbr>store-alias.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>2012-11-28-merge-store-alias.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>2012-11-28-merge-store-alias.<wbr>ll Mon Mar 13 19:34:14 2017<br>
@@ -3,8 +3,8 @@<br>
; CHECK: merge_stores_can<br>
; CHECK: callq foo<br>
; CHECK: xorps %xmm0, %xmm0<br>
-; CHECK-NEXT: movl 36(%rsp), %ebp<br>
; CHECK-NEXT: movups %xmm0<br>
+; CHECK-NEXT: movl 36(%rsp), %ebp<br>
; CHECK: callq foo<br>
; CHECK: ret<br>
declare i32 @foo([10 x i32]* )<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>MergeConsecutiveStores.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/MergeConsecutiveStores.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/<wbr>MergeConsecutiveStores.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>MergeConsecutiveStores.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>MergeConsecutiveStores.ll Mon Mar 13 19:34:14 2017<br>
@@ -111,8 +111,7 @@ define void @merge_const_store_vec(i32 %<br>
; CHECK-LABEL: merge_nonconst_store:<br>
; CHECK: movl $67305985<br>
; CHECK: movb<br>
-; CHECK: movb<br>
-; CHECK: movb<br>
+; CHECK: movw<br>
; CHECK: movb<br>
; CHECK: ret<br>
define void @merge_nonconst_store(i32 %count, i8 %zz, %struct.A* nocapture %p) nounwind uwtable noinline ssp {<br>
@@ -292,16 +291,12 @@ block4:<br>
ret void<br>
}<br>
<br>
-;; On x86, even unaligned copies should be merged to vector ops.<br>
-;; TODO: however, this cannot happen at the moment, due to brokenness<br>
-;; in MergeConsecutiveStores. See UseAA FIXME in DAGCombiner.cpp<br>
-;; visitSTORE.<br>
-<br>
+;; On x86, even unaligned copies can be merged to vector ops.<br>
; CHECK-LABEL: merge_loads_no_align:<br>
; load:<br>
-; CHECK-NOT: vmovups ;; TODO<br>
+; CHECK: vmovups<br>
; store:<br>
-; CHECK-NOT: vmovups ;; TODO<br>
+; CHECK: vmovups<br>
; CHECK: ret<br>
define void @merge_loads_no_align(i32 %count, %struct.B* noalias nocapture %q, %struct.B* noalias nocapture %p) nounwind uwtable noinline ssp {<br>
%a1 = icmp sgt i32 %count, 0<br>
@@ -583,8 +578,8 @@ define void @merge_vec_element_and_scala<br>
<br>
; CHECK-LABEL: merge_vec_element_and_scalar_<wbr>load<br>
; CHECK: movq (%rdi), %rax<br>
+; CHECK-NEXT: movq 8(%rdi), %rcx<br>
; CHECK-NEXT: movq %rax, 32(%rdi)<br>
-; CHECK-NEXT: movq 8(%rdi), %rax<br>
-; CHECK-NEXT: movq %rax, 40(%rdi)<br>
+; CHECK-NEXT: movq %rcx, 40(%rdi)<br>
; CHECK-NEXT: retq<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>avx-vbroadcast.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-vbroadcast.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/avx-vbroadcast.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>avx-vbroadcast.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>avx-vbroadcast.ll Mon Mar 13 19:34:14 2017<br>
@@ -842,12 +842,15 @@ define float @broadcast_lifetime() nounw<br>
; X32-NEXT: leal {{[0-9]+}}(%esp), %esi<br>
; X32-NEXT: movl %esi, (%esp)<br>
; X32-NEXT: calll _gfunc<br>
-; X32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm0<br>
+; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp) ## 16-byte Spill<br>
; X32-NEXT: movl %esi, (%esp)<br>
; X32-NEXT: calll _gfunc<br>
-; X32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm0<br>
-; X32-NEXT: vsubss {{[0-9]+}}(%esp), %xmm0, %xmm0 ## 16-byte Folded Reload<br>
+; X32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
+; X32-NEXT: vpermilps $0, {{[0-9]+}}(%esp), %xmm1 ## 16-byte Folded Reload<br>
+; X32-NEXT: ## xmm1 = mem[0,0,0,0]<br>
+; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]<br>
+; X32-NEXT: vsubss %xmm1, %xmm0, %xmm0<br>
; X32-NEXT: vmovss %xmm0, {{[0-9]+}}(%esp)<br>
; X32-NEXT: flds {{[0-9]+}}(%esp)<br>
; X32-NEXT: addl $56, %esp<br>
@@ -859,12 +862,15 @@ define float @broadcast_lifetime() nounw<br>
; X64-NEXT: subq $40, %rsp<br>
; X64-NEXT: movq %rsp, %rdi<br>
; X64-NEXT: callq _gfunc<br>
-; X64-NEXT: vbroadcastss {{[0-9]+}}(%rsp), %xmm0<br>
+; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; X64-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp) ## 16-byte Spill<br>
; X64-NEXT: movq %rsp, %rdi<br>
; X64-NEXT: callq _gfunc<br>
-; X64-NEXT: vbroadcastss {{[0-9]+}}(%rsp), %xmm0<br>
-; X64-NEXT: vsubss {{[0-9]+}}(%rsp), %xmm0, %xmm0 ## 16-byte Folded Reload<br>
+; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
+; X64-NEXT: vpermilps $0, {{[0-9]+}}(%rsp), %xmm1 ## 16-byte Folded Reload<br>
+; X64-NEXT: ## xmm1 = mem[0,0,0,0]<br>
+; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]<br>
+; X64-NEXT: vsubss %xmm1, %xmm0, %xmm0<br>
; X64-NEXT: addq $40, %rsp<br>
; X64-NEXT: retq<br>
%1 = alloca <4 x float>, align 16<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>avx512-mask-op.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/avx512-mask-op.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>avx512-mask-op.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>avx512-mask-op.ll Mon Mar 13 19:34:14 2017<br>
@@ -1197,10 +1197,6 @@ define void @ktest_2(<32 x float> %in, f<br>
; KNL-NEXT: kmovw %k0, %eax<br>
; KNL-NEXT: vpinsrb $15, %eax, %xmm2, %xmm2<br>
; KNL-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2<br>
-; KNL-NEXT: vpsllw $7, %ymm2, %ymm2<br>
-; KNL-NEXT: vpand {{.*}}(%rip), %ymm2, %ymm2<br>
-; KNL-NEXT: vpxor %ymm3, %ymm3, %ymm3<br>
-; KNL-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm2<br>
; KNL-NEXT: vmovups 4(%rdi), %zmm3 {%k2} {z}<br>
; KNL-NEXT: vmovups 68(%rdi), %zmm4 {%k1} {z}<br>
; KNL-NEXT: vcmpltps %zmm4, %zmm1, %k0<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>chain_order.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/chain_order.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/chain_order.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>chain_order.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>chain_order.ll Mon Mar 13 19:34:14 2017<br>
@@ -11,9 +11,9 @@ define void @cftx020(double* nocapture %<br>
; CHECK-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0]<br>
; CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0<br>
; CHECK-NEXT: vmovupd (%rdi), %xmm1<br>
-; CHECK-NEXT: vsubpd 16(%rdi), %xmm1, %xmm1<br>
; CHECK-NEXT: vmovupd %xmm0, (%rdi)<br>
-; CHECK-NEXT: vmovupd %xmm1, 16(%rdi)<br>
+; CHECK-NEXT: vsubpd 16(%rdi), %xmm1, %xmm0<br>
+; CHECK-NEXT: vmovupd %xmm0, 16(%rdi)<br>
; CHECK-NEXT: retq<br>
entry:<br>
%0 = load double, double* %a, align 8<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/clear_upper_vector_element_bits.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/clear_upper_<wbr>vector_element_bits.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll Mon Mar 13 19:34:14 2017<br>
@@ -360,47 +360,47 @@ define <16 x i8> @_clearupper16xi8a(<16<br>
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
; SSE-NEXT: movd %eax, %xmm0<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi<br>
; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
; SSE-NEXT: movd %eax, %xmm1<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3],xmm1[4],xmm0[4],xmm1[<wbr>5],xmm0[5],xmm1[6],xmm0[6],<wbr>xmm1[7],xmm0[7]<br>
-; SSE-NEXT: movd %esi, %xmm0<br>
; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx<br>
-; SSE-NEXT: movd %ecx, %xmm2<br>
+; SSE-NEXT: movd %eax, %xmm0<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm2<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3],xmm2[4],xmm0[4],xmm2[<wbr>5],xmm0[5],xmm2[6],xmm0[6],<wbr>xmm2[7],xmm0[7]<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3],xmm2[4],xmm1[4],xmm2[<wbr>5],xmm1[5],xmm2[6],xmm1[6],<wbr>xmm2[7],xmm1[7]<br>
-; SSE-NEXT: movd %edx, %xmm0<br>
-; SSE-NEXT: movd %esi, %xmm1<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3],xmm1[4],xmm0[4],xmm1[<wbr>5],xmm0[5],xmm1[6],xmm0[6],<wbr>xmm1[7],xmm0[7]<br>
-; SSE-NEXT: movd %edi, %xmm0<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx<br>
-; SSE-NEXT: movd %edx, %xmm3<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm0<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm3<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[<wbr>1],xmm3[2],xmm0[2],xmm3[3],<wbr>xmm0[3],xmm3[4],xmm0[4],xmm3[<wbr>5],xmm0[5],xmm3[6],xmm0[6],<wbr>xmm3[7],xmm0[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1],xmm3[2],xmm1[2],xmm3[3],<wbr>xmm1[3],xmm3[4],xmm1[4],xmm3[<wbr>5],xmm1[5],xmm3[6],xmm1[6],<wbr>xmm3[7],xmm1[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[<wbr>1],xmm3[2],xmm2[2],xmm3[3],<wbr>xmm2[3],xmm3[4],xmm2[4],xmm3[<wbr>5],xmm2[5],xmm3[6],xmm2[6],<wbr>xmm3[7],xmm2[7]<br>
-; SSE-NEXT: movd %r9d, %xmm0<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm0<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
; SSE-NEXT: movd %eax, %xmm1<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3],xmm1[4],xmm0[4],xmm1[<wbr>5],xmm0[5],xmm1[6],xmm0[6],<wbr>xmm1[7],xmm0[7]<br>
-; SSE-NEXT: movd %r8d, %xmm0<br>
-; SSE-NEXT: movd %ecx, %xmm2<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3],xmm2[4],xmm0[4],xmm2[<wbr>5],xmm0[5],xmm2[6],xmm0[6],<wbr>xmm2[7],xmm0[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3],xmm2[4],xmm1[4],xmm2[<wbr>5],xmm1[5],xmm2[6],xmm1[6],<wbr>xmm2[7],xmm1[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[<wbr>1],xmm1[2],xmm3[2],xmm1[3],<wbr>xmm3[3],xmm1[4],xmm3[4],xmm1[<wbr>5],xmm3[5],xmm1[6],xmm3[6],<wbr>xmm1[7],xmm3[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1],xmm1[2],xmm2[2],xmm1[3],<wbr>xmm2[3],xmm1[4],xmm2[4],xmm1[<wbr>5],xmm2[5],xmm1[6],xmm2[6],<wbr>xmm1[7],xmm2[7]<br>
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
-; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3],xmm1[4],xmm0[4],xmm1[<wbr>5],xmm0[5],xmm1[6],xmm0[6],<wbr>xmm1[7],xmm0[7]<br>
-; SSE-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero<br>
+; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3],xmm2[4],xmm0[4],xmm2[<wbr>5],xmm0[5],xmm2[6],xmm0[6],<wbr>xmm2[7],xmm0[7]<br>
+; SSE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero<br>
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3],xmm0[4],xmm3[4],xmm0[<wbr>5],xmm3[5],xmm0[6],xmm3[6],<wbr>xmm0[7],xmm3[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3],xmm0[4],xmm2[4],xmm0[<wbr>5],xmm2[5],xmm0[6],xmm2[6],<wbr>xmm0[7],xmm2[7]<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm2<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm3<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[<wbr>1],xmm3[2],xmm2[2],xmm3[3],<wbr>xmm2[3],xmm3[4],xmm2[4],xmm3[<wbr>5],xmm2[5],xmm3[6],xmm2[6],<wbr>xmm3[7],xmm2[7]<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm2<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm4<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[<wbr>1],xmm4[2],xmm2[2],xmm4[3],<wbr>xmm2[3],xmm4[4],xmm2[4],xmm4[<wbr>5],xmm2[5],xmm4[6],xmm2[6],<wbr>xmm4[7],xmm2[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[<wbr>1],xmm4[2],xmm3[2],xmm4[3],<wbr>xmm3[3],xmm4[4],xmm3[4],xmm4[<wbr>5],xmm3[5],xmm4[6],xmm3[6],<wbr>xmm4[7],xmm3[7]<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[<wbr>1],xmm0[2],xmm4[2],xmm0[3],<wbr>xmm4[3],xmm0[4],xmm4[4],xmm0[<wbr>5],xmm4[5],xmm0[6],xmm4[6],<wbr>xmm0[7],xmm4[7]<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3],xmm0[4],xmm1[4],xmm0[<wbr>5],xmm1[5],xmm0[6],xmm1[6],<wbr>xmm0[7],xmm1[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3],xmm0[4],xmm2[4],xmm0[<wbr>5],xmm2[5],xmm0[6],xmm2[6],<wbr>xmm0[7],xmm2[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3],xmm0[4],xmm3[4],xmm0[<wbr>5],xmm3[5],xmm0[6],xmm3[6],<wbr>xmm0[7],xmm3[7]<br>
; SSE-NEXT: pand {{.*}}(%rip), %xmm0<br>
; SSE-NEXT: retq<br>
;<br>
@@ -487,92 +487,92 @@ define <32 x i8> @_clearupper32xi8a(<32<br>
; SSE-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)<br>
; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
; SSE-NEXT: movd %eax, %xmm0<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi<br>
; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
; SSE-NEXT: movd %eax, %xmm1<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3],xmm1[4],xmm0[4],xmm1[<wbr>5],xmm0[5],xmm1[6],xmm0[6],<wbr>xmm1[7],xmm0[7]<br>
-; SSE-NEXT: movd %esi, %xmm0<br>
; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx<br>
-; SSE-NEXT: movd %ecx, %xmm2<br>
+; SSE-NEXT: movd %eax, %xmm0<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm2<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3],xmm2[4],xmm0[4],xmm2[<wbr>5],xmm0[5],xmm2[6],xmm0[6],<wbr>xmm2[7],xmm0[7]<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3],xmm2[4],xmm1[4],xmm2[<wbr>5],xmm1[5],xmm2[6],xmm1[6],<wbr>xmm2[7],xmm1[7]<br>
-; SSE-NEXT: movd %edx, %xmm0<br>
-; SSE-NEXT: movd %esi, %xmm1<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3],xmm1[4],xmm0[4],xmm1[<wbr>5],xmm0[5],xmm1[6],xmm0[6],<wbr>xmm1[7],xmm0[7]<br>
-; SSE-NEXT: movd %edi, %xmm0<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx<br>
-; SSE-NEXT: movd %edx, %xmm3<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm0<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm3<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[<wbr>1],xmm3[2],xmm0[2],xmm3[3],<wbr>xmm0[3],xmm3[4],xmm0[4],xmm3[<wbr>5],xmm0[5],xmm3[6],xmm0[6],<wbr>xmm3[7],xmm0[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1],xmm3[2],xmm1[2],xmm3[3],<wbr>xmm1[3],xmm3[4],xmm1[4],xmm3[<wbr>5],xmm1[5],xmm3[6],xmm1[6],<wbr>xmm3[7],xmm1[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[<wbr>1],xmm3[2],xmm2[2],xmm3[3],<wbr>xmm2[3],xmm3[4],xmm2[4],xmm3[<wbr>5],xmm2[5],xmm3[6],xmm2[6],<wbr>xmm3[7],xmm2[7]<br>
-; SSE-NEXT: movd %r9d, %xmm0<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm0<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
; SSE-NEXT: movd %eax, %xmm1<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3],xmm1[4],xmm0[4],xmm1[<wbr>5],xmm0[5],xmm1[6],xmm0[6],<wbr>xmm1[7],xmm0[7]<br>
-; SSE-NEXT: movd %r8d, %xmm0<br>
-; SSE-NEXT: movd %ecx, %xmm2<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3],xmm2[4],xmm0[4],xmm2[<wbr>5],xmm0[5],xmm2[6],xmm0[6],<wbr>xmm2[7],xmm0[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3],xmm2[4],xmm1[4],xmm2[<wbr>5],xmm1[5],xmm2[6],xmm1[6],<wbr>xmm2[7],xmm1[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[<wbr>1],xmm1[2],xmm3[2],xmm1[3],<wbr>xmm3[3],xmm1[4],xmm3[4],xmm1[<wbr>5],xmm3[5],xmm1[6],xmm3[6],<wbr>xmm1[7],xmm3[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1],xmm1[2],xmm2[2],xmm1[3],<wbr>xmm2[3],xmm1[4],xmm2[4],xmm1[<wbr>5],xmm2[5],xmm1[6],xmm2[6],<wbr>xmm1[7],xmm2[7]<br>
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
-; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3],xmm1[4],xmm0[4],xmm1[<wbr>5],xmm0[5],xmm1[6],xmm0[6],<wbr>xmm1[7],xmm0[7]<br>
-; SSE-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero<br>
+; SSE-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3],xmm2[4],xmm0[4],xmm2[<wbr>5],xmm0[5],xmm2[6],xmm0[6],<wbr>xmm2[7],xmm0[7]<br>
+; SSE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero<br>
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3],xmm0[4],xmm3[4],xmm0[<wbr>5],xmm3[5],xmm0[6],xmm3[6],<wbr>xmm0[7],xmm3[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3],xmm0[4],xmm2[4],xmm0[<wbr>5],xmm2[5],xmm0[6],xmm2[6],<wbr>xmm0[7],xmm2[7]<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm2<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm3<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[<wbr>1],xmm3[2],xmm2[2],xmm3[3],<wbr>xmm2[3],xmm3[4],xmm2[4],xmm3[<wbr>5],xmm2[5],xmm3[6],xmm2[6],<wbr>xmm3[7],xmm2[7]<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm2<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm4<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[<wbr>1],xmm4[2],xmm2[2],xmm4[3],<wbr>xmm2[3],xmm4[4],xmm2[4],xmm4[<wbr>5],xmm2[5],xmm4[6],xmm2[6],<wbr>xmm4[7],xmm2[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[<wbr>1],xmm4[2],xmm3[2],xmm4[3],<wbr>xmm3[3],xmm4[4],xmm3[4],xmm4[<wbr>5],xmm3[5],xmm4[6],xmm3[6],<wbr>xmm4[7],xmm3[7]<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[<wbr>1],xmm0[2],xmm4[2],xmm0[3],<wbr>xmm4[3],xmm0[4],xmm4[4],xmm0[<wbr>5],xmm4[5],xmm0[6],xmm4[6],<wbr>xmm0[7],xmm4[7]<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3],xmm0[4],xmm1[4],xmm0[<wbr>5],xmm1[5],xmm0[6],xmm1[6],<wbr>xmm0[7],xmm1[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3],xmm0[4],xmm2[4],xmm0[<wbr>5],xmm2[5],xmm0[6],xmm2[6],<wbr>xmm0[7],xmm2[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3],xmm0[4],xmm3[4],xmm0[<wbr>5],xmm3[5],xmm0[6],xmm3[6],<wbr>xmm0[7],xmm3[7]<br>
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,<wbr>15,15,15,15,15,15,15]<br>
; SSE-NEXT: pand %xmm2, %xmm0<br>
; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
; SSE-NEXT: movd %eax, %xmm1<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r9d<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %r8d<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edi<br>
; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
; SSE-NEXT: movd %eax, %xmm3<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1],xmm3[2],xmm1[2],xmm3[3],<wbr>xmm1[3],xmm3[4],xmm1[4],xmm3[<wbr>5],xmm1[5],xmm3[6],xmm1[6],<wbr>xmm3[7],xmm1[7]<br>
-; SSE-NEXT: movd %esi, %xmm1<br>
; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %esi<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx<br>
-; SSE-NEXT: movd %ecx, %xmm4<br>
+; SSE-NEXT: movd %eax, %xmm1<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm4<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[<wbr>1],xmm4[2],xmm1[2],xmm4[3],<wbr>xmm1[3],xmm4[4],xmm1[4],xmm4[<wbr>5],xmm1[5],xmm4[6],xmm1[6],<wbr>xmm4[7],xmm1[7]<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[<wbr>1],xmm4[2],xmm3[2],xmm4[3],<wbr>xmm3[3],xmm4[4],xmm3[4],xmm4[<wbr>5],xmm3[5],xmm4[6],xmm3[6],<wbr>xmm4[7],xmm3[7]<br>
-; SSE-NEXT: movd %edx, %xmm1<br>
-; SSE-NEXT: movd %esi, %xmm3<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1],xmm3[2],xmm1[2],xmm3[3],<wbr>xmm1[3],xmm3[4],xmm1[4],xmm3[<wbr>5],xmm1[5],xmm3[6],xmm1[6],<wbr>xmm3[7],xmm1[7]<br>
-; SSE-NEXT: movd %edi, %xmm1<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx<br>
-; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %edx<br>
-; SSE-NEXT: movd %edx, %xmm5<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm1<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm5<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[<wbr>1],xmm5[2],xmm1[2],xmm5[3],<wbr>xmm1[3],xmm5[4],xmm1[4],xmm5[<wbr>5],xmm1[5],xmm5[6],xmm1[6],<wbr>xmm5[7],xmm1[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm3[0],xmm5[1],xmm3[<wbr>1],xmm5[2],xmm3[2],xmm5[3],<wbr>xmm3[3],xmm5[4],xmm3[4],xmm5[<wbr>5],xmm3[5],xmm5[6],xmm3[6],<wbr>xmm5[7],xmm3[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[<wbr>1],xmm5[2],xmm4[2],xmm5[3],<wbr>xmm4[3],xmm5[4],xmm4[4],xmm5[<wbr>5],xmm4[5],xmm5[6],xmm4[6],<wbr>xmm5[7],xmm4[7]<br>
-; SSE-NEXT: movd %r9d, %xmm1<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm1<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
; SSE-NEXT: movd %eax, %xmm3<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1],xmm3[2],xmm1[2],xmm3[3],<wbr>xmm1[3],xmm3[4],xmm1[4],xmm3[<wbr>5],xmm1[5],xmm3[6],xmm1[6],<wbr>xmm3[7],xmm1[7]<br>
-; SSE-NEXT: movd %r8d, %xmm1<br>
-; SSE-NEXT: movd %ecx, %xmm4<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[<wbr>1],xmm4[2],xmm1[2],xmm4[3],<wbr>xmm1[3],xmm4[4],xmm1[4],xmm4[<wbr>5],xmm1[5],xmm4[6],xmm1[6],<wbr>xmm4[7],xmm1[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[<wbr>1],xmm4[2],xmm3[2],xmm4[3],<wbr>xmm3[3],xmm4[4],xmm3[4],xmm4[<wbr>5],xmm3[5],xmm4[6],xmm3[6],<wbr>xmm4[7],xmm3[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[<wbr>1],xmm3[2],xmm5[2],xmm3[3],<wbr>xmm5[3],xmm3[4],xmm5[4],xmm3[<wbr>5],xmm5[5],xmm3[6],xmm5[6],<wbr>xmm3[7],xmm5[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[<wbr>1],xmm3[2],xmm4[2],xmm3[3],<wbr>xmm4[3],xmm3[4],xmm4[4],xmm3[<wbr>5],xmm4[5],xmm3[6],xmm4[6],<wbr>xmm3[7],xmm4[7]<br>
; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
-; SSE-NEXT: movd {{.*#+}} xmm3 = mem[0],zero,zero,zero<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1],xmm3[2],xmm1[2],xmm3[3],<wbr>xmm1[3],xmm3[4],xmm1[4],xmm3[<wbr>5],xmm1[5],xmm3[6],xmm1[6],<wbr>xmm3[7],xmm1[7]<br>
-; SSE-NEXT: movd {{.*#+}} xmm6 = mem[0],zero,zero,zero<br>
+; SSE-NEXT: movd {{.*#+}} xmm4 = mem[0],zero,zero,zero<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[<wbr>1],xmm4[2],xmm1[2],xmm4[3],<wbr>xmm1[3],xmm4[4],xmm1[4],xmm4[<wbr>5],xmm1[5],xmm4[6],xmm1[6],<wbr>xmm4[7],xmm1[7]<br>
+; SSE-NEXT: movd {{.*#+}} xmm5 = mem[0],zero,zero,zero<br>
; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[<wbr>1],xmm1[2],xmm5[2],xmm1[3],<wbr>xmm5[3],xmm1[4],xmm5[4],xmm1[<wbr>5],xmm5[5],xmm1[6],xmm5[6],<wbr>xmm1[7],xmm5[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[<wbr>1],xmm1[2],xmm4[2],xmm1[3],<wbr>xmm4[3],xmm1[4],xmm4[4],xmm1[<wbr>5],xmm4[5],xmm1[6],xmm4[6],<wbr>xmm1[7],xmm4[7]<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm4<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm5<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[<wbr>1],xmm5[2],xmm4[2],xmm5[3],<wbr>xmm4[3],xmm5[4],xmm4[4],xmm5[<wbr>5],xmm4[5],xmm5[6],xmm4[6],<wbr>xmm5[7],xmm4[7]<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm4<br>
+; SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax<br>
+; SSE-NEXT: movd %eax, %xmm6<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm4[0],xmm6[1],xmm4[<wbr>1],xmm6[2],xmm4[2],xmm6[3],<wbr>xmm4[3],xmm6[4],xmm4[4],xmm6[<wbr>5],xmm4[5],xmm6[6],xmm4[6],<wbr>xmm6[7],xmm4[7]<br>
+; SSE-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[<wbr>1],xmm6[2],xmm5[2],xmm6[3],<wbr>xmm5[3],xmm6[4],xmm5[4],xmm6[<wbr>5],xmm5[5],xmm6[6],xmm5[6],<wbr>xmm6[7],xmm5[7]<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[<wbr>1],xmm1[2],xmm6[2],xmm1[3],<wbr>xmm6[3],xmm1[4],xmm6[4],xmm1[<wbr>5],xmm6[5],xmm1[6],xmm6[6],<wbr>xmm1[7],xmm6[7]<br>
; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[<wbr>1],xmm1[2],xmm3[2],xmm1[3],<wbr>xmm3[3],xmm1[4],xmm3[4],xmm1[<wbr>5],xmm3[5],xmm1[6],xmm3[6],<wbr>xmm1[7],xmm3[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[<wbr>1],xmm1[2],xmm4[2],xmm1[3],<wbr>xmm4[3],xmm1[4],xmm4[4],xmm1[<wbr>5],xmm4[5],xmm1[6],xmm4[6],<wbr>xmm1[7],xmm4[7]<br>
-; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm5[0],xmm1[1],xmm5[<wbr>1],xmm1[2],xmm5[2],xmm1[3],<wbr>xmm5[3],xmm1[4],xmm5[4],xmm1[<wbr>5],xmm5[5],xmm1[6],xmm5[6],<wbr>xmm1[7],xmm5[7]<br>
; SSE-NEXT: pand %xmm2, %xmm1<br>
; SSE-NEXT: retq<br>
;<br>
@@ -1180,91 +1180,87 @@ define <32 x i8> @_clearupper32xi8b(<32<br>
;<br>
; AVX1-LABEL: _clearupper32xi8b:<br>
; AVX1: # BB#0:<br>
-; AVX1-NEXT: pushq %rbp<br>
-; AVX1-NEXT: pushq %r15<br>
; AVX1-NEXT: pushq %r14<br>
-; AVX1-NEXT: pushq %r13<br>
-; AVX1-NEXT: pushq %r12<br>
; AVX1-NEXT: pushq %rbx<br>
; AVX1-NEXT: vpextrq $1, %xmm0, -{{[0-9]+}}(%rsp)<br>
; AVX1-NEXT: vmovq %xmm0, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: movq -{{[0-9]+}}(%rsp), %rcx<br>
-; AVX1-NEXT: movq -{{[0-9]+}}(%rsp), %rdx<br>
-; AVX1-NEXT: movq %rcx, %r8<br>
-; AVX1-NEXT: movq %rcx, %r9<br>
-; AVX1-NEXT: movq %rcx, %r10<br>
-; AVX1-NEXT: movq %rcx, %r11<br>
-; AVX1-NEXT: movq %rcx, %r14<br>
-; AVX1-NEXT: movq %rcx, %r15<br>
-; AVX1-NEXT: movq %rdx, %r12<br>
-; AVX1-NEXT: movq %rdx, %r13<br>
+; AVX1-NEXT: movq -{{[0-9]+}}(%rsp), %r14<br>
+; AVX1-NEXT: vpextrq $1, %xmm0, %rdx<br>
+; AVX1-NEXT: movq %rdx, %r8<br>
+; AVX1-NEXT: movq %rdx, %r9<br>
+; AVX1-NEXT: movq %rdx, %r11<br>
+; AVX1-NEXT: movq %rdx, %rsi<br>
; AVX1-NEXT: movq %rdx, %rdi<br>
+; AVX1-NEXT: movq %rdx, %rcx<br>
; AVX1-NEXT: movq %rdx, %rax<br>
-; AVX1-NEXT: movq %rdx, %rsi<br>
-; AVX1-NEXT: movq %rdx, %rbx<br>
-; AVX1-NEXT: movq %rdx, %rbp<br>
; AVX1-NEXT: andb $15, %dl<br>
; AVX1-NEXT: movb %dl, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: movq %rcx, %rdx<br>
+; AVX1-NEXT: shrq $56, %rax<br>
+; AVX1-NEXT: andb $15, %al<br>
+; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp)<br>
+; AVX1-NEXT: movq %r14, %r10<br>
+; AVX1-NEXT: shrq $48, %rcx<br>
; AVX1-NEXT: andb $15, %cl<br>
; AVX1-NEXT: movb %cl, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: shrq $56, %rbp<br>
-; AVX1-NEXT: andb $15, %bpl<br>
-; AVX1-NEXT: movb %bpl, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: shrq $48, %rbx<br>
+; AVX1-NEXT: movq %r14, %rdx<br>
+; AVX1-NEXT: shrq $40, %rdi<br>
+; AVX1-NEXT: andb $15, %dil<br>
+; AVX1-NEXT: movb %dil, -{{[0-9]+}}(%rsp)<br>
+; AVX1-NEXT: movq %r14, %rax<br>
+; AVX1-NEXT: shrq $32, %rsi<br>
+; AVX1-NEXT: andb $15, %sil<br>
+; AVX1-NEXT: movb %sil, -{{[0-9]+}}(%rsp)<br>
+; AVX1-NEXT: movq %r14, %rcx<br>
+; AVX1-NEXT: shrq $24, %r11<br>
+; AVX1-NEXT: andb $15, %r11b<br>
+; AVX1-NEXT: movb %r11b, -{{[0-9]+}}(%rsp)<br>
+; AVX1-NEXT: movq %r14, %rsi<br>
+; AVX1-NEXT: shrq $16, %r9<br>
+; AVX1-NEXT: andb $15, %r9b<br>
+; AVX1-NEXT: movb %r9b, -{{[0-9]+}}(%rsp)<br>
+; AVX1-NEXT: movq %r14, %rdi<br>
+; AVX1-NEXT: shrq $8, %r8<br>
+; AVX1-NEXT: andb $15, %r8b<br>
+; AVX1-NEXT: movb %r8b, -{{[0-9]+}}(%rsp)<br>
+; AVX1-NEXT: movq %r14, %rbx<br>
+; AVX1-NEXT: andb $15, %r14b<br>
+; AVX1-NEXT: movb %r14b, -{{[0-9]+}}(%rsp)<br>
+; AVX1-NEXT: shrq $8, %r10<br>
+; AVX1-NEXT: shrq $16, %rdx<br>
+; AVX1-NEXT: shrq $24, %rax<br>
+; AVX1-NEXT: shrq $32, %rcx<br>
+; AVX1-NEXT: shrq $40, %rsi<br>
+; AVX1-NEXT: shrq $48, %rdi<br>
+; AVX1-NEXT: shrq $56, %rbx<br>
; AVX1-NEXT: andb $15, %bl<br>
; AVX1-NEXT: movb %bl, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: shrq $40, %rsi<br>
+; AVX1-NEXT: andb $15, %dil<br>
+; AVX1-NEXT: movb %dil, -{{[0-9]+}}(%rsp)<br>
; AVX1-NEXT: andb $15, %sil<br>
; AVX1-NEXT: movb %sil, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: shrq $32, %rax<br>
+; AVX1-NEXT: andb $15, %cl<br>
+; AVX1-NEXT: movb %cl, -{{[0-9]+}}(%rsp)<br>
; AVX1-NEXT: andb $15, %al<br>
; AVX1-NEXT: movb %al, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: shrq $24, %rdi<br>
-; AVX1-NEXT: andb $15, %dil<br>
-; AVX1-NEXT: movb %dil, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: shrq $16, %r13<br>
-; AVX1-NEXT: andb $15, %r13b<br>
-; AVX1-NEXT: movb %r13b, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: shrq $8, %r12<br>
-; AVX1-NEXT: andb $15, %r12b<br>
-; AVX1-NEXT: movb %r12b, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: shrq $8, %r8<br>
-; AVX1-NEXT: shrq $16, %r9<br>
-; AVX1-NEXT: shrq $24, %r10<br>
-; AVX1-NEXT: shrq $32, %r11<br>
-; AVX1-NEXT: shrq $40, %r14<br>
-; AVX1-NEXT: shrq $48, %r15<br>
-; AVX1-NEXT: shrq $56, %rdx<br>
; AVX1-NEXT: andb $15, %dl<br>
; AVX1-NEXT: movb %dl, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: andb $15, %r15b<br>
-; AVX1-NEXT: movb %r15b, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: andb $15, %r14b<br>
-; AVX1-NEXT: movb %r14b, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: andb $15, %r11b<br>
-; AVX1-NEXT: movb %r11b, -{{[0-9]+}}(%rsp)<br>
; AVX1-NEXT: andb $15, %r10b<br>
; AVX1-NEXT: movb %r10b, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: andb $15, %r9b<br>
-; AVX1-NEXT: movb %r9b, -{{[0-9]+}}(%rsp)<br>
-; AVX1-NEXT: andb $15, %r8b<br>
-; AVX1-NEXT: movb %r8b, -{{[0-9]+}}(%rsp)<br>
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0<br>
; AVX1-NEXT: vmovq %xmm0, %rax<br>
-; AVX1-NEXT: movq %rax, %rcx<br>
+; AVX1-NEXT: movq %rax, %r8<br>
; AVX1-NEXT: movq %rax, %rdx<br>
; AVX1-NEXT: movq %rax, %rsi<br>
; AVX1-NEXT: movq %rax, %rdi<br>
-; AVX1-NEXT: movl %eax, %ebp<br>
; AVX1-NEXT: movl %eax, %ebx<br>
+; AVX1-NEXT: movl %eax, %ecx<br>
; AVX1-NEXT: vmovd %eax, %xmm1<br>
; AVX1-NEXT: shrl $8, %eax<br>
; AVX1-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1<br>
-; AVX1-NEXT: shrl $16, %ebx<br>
-; AVX1-NEXT: vpinsrb $2, %ebx, %xmm1, %xmm1<br>
-; AVX1-NEXT: shrl $24, %ebp<br>
-; AVX1-NEXT: vpinsrb $3, %ebp, %xmm1, %xmm1<br>
+; AVX1-NEXT: shrl $16, %ecx<br>
+; AVX1-NEXT: vpinsrb $2, %ecx, %xmm1, %xmm1<br>
+; AVX1-NEXT: shrl $24, %ebx<br>
+; AVX1-NEXT: vpinsrb $3, %ebx, %xmm1, %xmm1<br>
; AVX1-NEXT: shrq $32, %rdi<br>
; AVX1-NEXT: vpinsrb $4, %edi, %xmm1, %xmm1<br>
; AVX1-NEXT: shrq $40, %rsi<br>
@@ -1274,8 +1270,8 @@ define <32 x i8> @_clearupper32xi8b(<32<br>
; AVX1-NEXT: shrq $48, %rdx<br>
; AVX1-NEXT: vpinsrb $6, %edx, %xmm1, %xmm1<br>
; AVX1-NEXT: vpextrq $1, %xmm0, %rax<br>
-; AVX1-NEXT: shrq $56, %rcx<br>
-; AVX1-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm0<br>
+; AVX1-NEXT: shrq $56, %r8<br>
+; AVX1-NEXT: vpinsrb $7, %r8d, %xmm1, %xmm0<br>
; AVX1-NEXT: movl %eax, %ecx<br>
; AVX1-NEXT: shrl $8, %ecx<br>
; AVX1-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0<br>
@@ -1343,100 +1339,92 @@ define <32 x i8> @_clearupper32xi8b(<32<br>
; AVX1-NEXT: vpinsrb $15, %eax, %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX1-NEXT: popq %rbx<br>
-; AVX1-NEXT: popq %r12<br>
-; AVX1-NEXT: popq %r13<br>
; AVX1-NEXT: popq %r14<br>
-; AVX1-NEXT: popq %r15<br>
-; AVX1-NEXT: popq %rbp<br>
; AVX1-NEXT: retq<br>
;<br>
; AVX2-LABEL: _clearupper32xi8b:<br>
; AVX2: # BB#0:<br>
-; AVX2-NEXT: pushq %rbp<br>
-; AVX2-NEXT: pushq %r15<br>
; AVX2-NEXT: pushq %r14<br>
-; AVX2-NEXT: pushq %r13<br>
-; AVX2-NEXT: pushq %r12<br>
; AVX2-NEXT: pushq %rbx<br>
; AVX2-NEXT: vpextrq $1, %xmm0, -{{[0-9]+}}(%rsp)<br>
; AVX2-NEXT: vmovq %xmm0, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: movq -{{[0-9]+}}(%rsp), %rcx<br>
-; AVX2-NEXT: movq -{{[0-9]+}}(%rsp), %rdx<br>
-; AVX2-NEXT: movq %rcx, %r8<br>
-; AVX2-NEXT: movq %rcx, %r9<br>
-; AVX2-NEXT: movq %rcx, %r10<br>
-; AVX2-NEXT: movq %rcx, %r11<br>
-; AVX2-NEXT: movq %rcx, %r14<br>
-; AVX2-NEXT: movq %rcx, %r15<br>
-; AVX2-NEXT: movq %rdx, %r12<br>
-; AVX2-NEXT: movq %rdx, %r13<br>
+; AVX2-NEXT: movq -{{[0-9]+}}(%rsp), %r14<br>
+; AVX2-NEXT: vpextrq $1, %xmm0, %rdx<br>
+; AVX2-NEXT: movq %rdx, %r8<br>
+; AVX2-NEXT: movq %rdx, %r9<br>
+; AVX2-NEXT: movq %rdx, %r11<br>
+; AVX2-NEXT: movq %rdx, %rsi<br>
; AVX2-NEXT: movq %rdx, %rdi<br>
+; AVX2-NEXT: movq %rdx, %rcx<br>
; AVX2-NEXT: movq %rdx, %rax<br>
-; AVX2-NEXT: movq %rdx, %rsi<br>
-; AVX2-NEXT: movq %rdx, %rbx<br>
-; AVX2-NEXT: movq %rdx, %rbp<br>
; AVX2-NEXT: andb $15, %dl<br>
; AVX2-NEXT: movb %dl, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: movq %rcx, %rdx<br>
+; AVX2-NEXT: shrq $56, %rax<br>
+; AVX2-NEXT: andb $15, %al<br>
+; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp)<br>
+; AVX2-NEXT: movq %r14, %r10<br>
+; AVX2-NEXT: shrq $48, %rcx<br>
; AVX2-NEXT: andb $15, %cl<br>
; AVX2-NEXT: movb %cl, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: shrq $56, %rbp<br>
-; AVX2-NEXT: andb $15, %bpl<br>
-; AVX2-NEXT: movb %bpl, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: shrq $48, %rbx<br>
+; AVX2-NEXT: movq %r14, %rdx<br>
+; AVX2-NEXT: shrq $40, %rdi<br>
+; AVX2-NEXT: andb $15, %dil<br>
+; AVX2-NEXT: movb %dil, -{{[0-9]+}}(%rsp)<br>
+; AVX2-NEXT: movq %r14, %rax<br>
+; AVX2-NEXT: shrq $32, %rsi<br>
+; AVX2-NEXT: andb $15, %sil<br>
+; AVX2-NEXT: movb %sil, -{{[0-9]+}}(%rsp)<br>
+; AVX2-NEXT: movq %r14, %rcx<br>
+; AVX2-NEXT: shrq $24, %r11<br>
+; AVX2-NEXT: andb $15, %r11b<br>
+; AVX2-NEXT: movb %r11b, -{{[0-9]+}}(%rsp)<br>
+; AVX2-NEXT: movq %r14, %rsi<br>
+; AVX2-NEXT: shrq $16, %r9<br>
+; AVX2-NEXT: andb $15, %r9b<br>
+; AVX2-NEXT: movb %r9b, -{{[0-9]+}}(%rsp)<br>
+; AVX2-NEXT: movq %r14, %rdi<br>
+; AVX2-NEXT: shrq $8, %r8<br>
+; AVX2-NEXT: andb $15, %r8b<br>
+; AVX2-NEXT: movb %r8b, -{{[0-9]+}}(%rsp)<br>
+; AVX2-NEXT: movq %r14, %rbx<br>
+; AVX2-NEXT: andb $15, %r14b<br>
+; AVX2-NEXT: movb %r14b, -{{[0-9]+}}(%rsp)<br>
+; AVX2-NEXT: shrq $8, %r10<br>
+; AVX2-NEXT: shrq $16, %rdx<br>
+; AVX2-NEXT: shrq $24, %rax<br>
+; AVX2-NEXT: shrq $32, %rcx<br>
+; AVX2-NEXT: shrq $40, %rsi<br>
+; AVX2-NEXT: shrq $48, %rdi<br>
+; AVX2-NEXT: shrq $56, %rbx<br>
; AVX2-NEXT: andb $15, %bl<br>
; AVX2-NEXT: movb %bl, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: shrq $40, %rsi<br>
+; AVX2-NEXT: andb $15, %dil<br>
+; AVX2-NEXT: movb %dil, -{{[0-9]+}}(%rsp)<br>
; AVX2-NEXT: andb $15, %sil<br>
; AVX2-NEXT: movb %sil, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: shrq $32, %rax<br>
+; AVX2-NEXT: andb $15, %cl<br>
+; AVX2-NEXT: movb %cl, -{{[0-9]+}}(%rsp)<br>
; AVX2-NEXT: andb $15, %al<br>
; AVX2-NEXT: movb %al, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: shrq $24, %rdi<br>
-; AVX2-NEXT: andb $15, %dil<br>
-; AVX2-NEXT: movb %dil, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: shrq $16, %r13<br>
-; AVX2-NEXT: andb $15, %r13b<br>
-; AVX2-NEXT: movb %r13b, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: shrq $8, %r12<br>
-; AVX2-NEXT: andb $15, %r12b<br>
-; AVX2-NEXT: movb %r12b, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: shrq $8, %r8<br>
-; AVX2-NEXT: shrq $16, %r9<br>
-; AVX2-NEXT: shrq $24, %r10<br>
-; AVX2-NEXT: shrq $32, %r11<br>
-; AVX2-NEXT: shrq $40, %r14<br>
-; AVX2-NEXT: shrq $48, %r15<br>
-; AVX2-NEXT: shrq $56, %rdx<br>
; AVX2-NEXT: andb $15, %dl<br>
; AVX2-NEXT: movb %dl, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: andb $15, %r15b<br>
-; AVX2-NEXT: movb %r15b, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: andb $15, %r14b<br>
-; AVX2-NEXT: movb %r14b, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: andb $15, %r11b<br>
-; AVX2-NEXT: movb %r11b, -{{[0-9]+}}(%rsp)<br>
; AVX2-NEXT: andb $15, %r10b<br>
; AVX2-NEXT: movb %r10b, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: andb $15, %r9b<br>
-; AVX2-NEXT: movb %r9b, -{{[0-9]+}}(%rsp)<br>
-; AVX2-NEXT: andb $15, %r8b<br>
-; AVX2-NEXT: movb %r8b, -{{[0-9]+}}(%rsp)<br>
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0<br>
; AVX2-NEXT: vmovq %xmm0, %rax<br>
-; AVX2-NEXT: movq %rax, %rcx<br>
+; AVX2-NEXT: movq %rax, %r8<br>
; AVX2-NEXT: movq %rax, %rdx<br>
; AVX2-NEXT: movq %rax, %rsi<br>
; AVX2-NEXT: movq %rax, %rdi<br>
-; AVX2-NEXT: movl %eax, %ebp<br>
; AVX2-NEXT: movl %eax, %ebx<br>
+; AVX2-NEXT: movl %eax, %ecx<br>
; AVX2-NEXT: vmovd %eax, %xmm1<br>
; AVX2-NEXT: shrl $8, %eax<br>
; AVX2-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1<br>
-; AVX2-NEXT: shrl $16, %ebx<br>
-; AVX2-NEXT: vpinsrb $2, %ebx, %xmm1, %xmm1<br>
-; AVX2-NEXT: shrl $24, %ebp<br>
-; AVX2-NEXT: vpinsrb $3, %ebp, %xmm1, %xmm1<br>
+; AVX2-NEXT: shrl $16, %ecx<br>
+; AVX2-NEXT: vpinsrb $2, %ecx, %xmm1, %xmm1<br>
+; AVX2-NEXT: shrl $24, %ebx<br>
+; AVX2-NEXT: vpinsrb $3, %ebx, %xmm1, %xmm1<br>
; AVX2-NEXT: shrq $32, %rdi<br>
; AVX2-NEXT: vpinsrb $4, %edi, %xmm1, %xmm1<br>
; AVX2-NEXT: shrq $40, %rsi<br>
@@ -1446,8 +1434,8 @@ define <32 x i8> @_clearupper32xi8b(<32<br>
; AVX2-NEXT: shrq $48, %rdx<br>
; AVX2-NEXT: vpinsrb $6, %edx, %xmm1, %xmm1<br>
; AVX2-NEXT: vpextrq $1, %xmm0, %rax<br>
-; AVX2-NEXT: shrq $56, %rcx<br>
-; AVX2-NEXT: vpinsrb $7, %ecx, %xmm1, %xmm0<br>
+; AVX2-NEXT: shrq $56, %r8<br>
+; AVX2-NEXT: vpinsrb $7, %r8d, %xmm1, %xmm0<br>
; AVX2-NEXT: movl %eax, %ecx<br>
; AVX2-NEXT: shrl $8, %ecx<br>
; AVX2-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0<br>
@@ -1515,11 +1503,7 @@ define <32 x i8> @_clearupper32xi8b(<32<br>
; AVX2-NEXT: vpinsrb $15, %eax, %xmm1, %xmm1<br>
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX2-NEXT: popq %rbx<br>
-; AVX2-NEXT: popq %r12<br>
-; AVX2-NEXT: popq %r13<br>
; AVX2-NEXT: popq %r14<br>
-; AVX2-NEXT: popq %r15<br>
-; AVX2-NEXT: popq %rbp<br>
; AVX2-NEXT: retq<br>
%x4 = bitcast <32 x i8> %0 to <64 x i4><br>
%r0 = insertelement <64 x i4> %x4, i4 zeroinitializer, i32 1<br>
<br>
Removed: llvm/trunk/test/CodeGen/X86/<wbr>combiner-aa-0.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combiner-aa-0.ll?rev=297694&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/combiner-aa-0.ll?<wbr>rev=297694&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>combiner-aa-0.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>combiner-aa-0.ll (removed)<br>
@@ -1,20 +0,0 @@<br>
-; RUN: llc < %s -march=x86-64 -combiner-global-alias-<wbr>analysis -combiner-alias-analysis<br>
-<br>
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-<wbr>i16:16:16-i32:32:32-i64:64:64-<wbr>f32:32:32-f64:64:64-v64:64:64-<wbr>v128:128:128-a0:0:64-s0:64:64-<wbr>f80:128:128"<br>
- %struct.Hash_Key = type { [4 x i32], i32 }<br>
-@g_flipV_hashkey = external global %struct.Hash_Key, align 16 ; <%struct.Hash_Key*> [#uses=1]<br>
-<br>
-define void @foo() nounwind {<br>
- %t0 = load i32, i32* undef, align 16 ; <i32> [#uses=1]<br>
- %t1 = load i32, i32* null, align 4 ; <i32> [#uses=1]<br>
- %t2 = srem i32 %t0, 32 ; <i32> [#uses=1]<br>
- %t3 = shl i32 1, %t2 ; <i32> [#uses=1]<br>
- %t4 = xor i32 %t3, %t1 ; <i32> [#uses=1]<br>
- store i32 %t4, i32* null, align 4<br>
- %t5 = getelementptr %struct.Hash_Key, %struct.Hash_Key* @g_flipV_hashkey, i64 0, i32 0, i64 0 ; <i32*> [#uses=2]<br>
- %t6 = load i32, i32* %t5, align 4 ; <i32> [#uses=1]<br>
- %t7 = shl i32 1, undef ; <i32> [#uses=1]<br>
- %t8 = xor i32 %t7, %t6 ; <i32> [#uses=1]<br>
- store i32 %t8, i32* %t5, align 4<br>
- unreachable<br>
-}<br>
<br>
Removed: llvm/trunk/test/CodeGen/X86/<wbr>combiner-aa-1.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combiner-aa-1.ll?rev=297694&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/combiner-aa-1.ll?<wbr>rev=297694&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>combiner-aa-1.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>combiner-aa-1.ll (removed)<br>
@@ -1,23 +0,0 @@<br>
-; RUN: llc < %s --combiner-alias-analysis --combiner-global-alias-<wbr>analysis<br>
-; PR4880<br>
-<br>
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-<wbr>i16:16:16-i32:32:32-i64:32:64-<wbr>f32:32:32-f64:32:64-v64:64:64-<wbr>v128:128:128-a0:0:64-f80:32:<wbr>32"<br>
-target triple = "i386-pc-linux-gnu"<br>
-<br>
-%struct.alst_node = type { %struct.node }<br>
-%struct.arg_node = type { %struct.node, i8*, %struct.alst_node* }<br>
-%struct.arglst_node = type { %struct.alst_node, %struct.arg_node*, %struct.arglst_node* }<br>
-%struct.lam_node = type { %struct.alst_node, %struct.arg_node*, %struct.alst_node* }<br>
-%struct.node = type { i32 (...)**, %struct.node* }<br>
-<br>
-define i32 @._ZN8lam_node18resolve_name_<wbr>clashEP8arg_nodeP9alst_node._<wbr>ZNK8lam_nodeeqERK8exp_node._<wbr>ZN11arglst_nodeD0Ev(%struct.<wbr>lam_node* %this.this, %struct.arg_node* %outer_arg, %struct.alst_node* %env.cmp, %struct.arglst_node* %this, i32 %functionID) {<br>
-comb_entry:<br>
- %.SV59 = alloca %struct.node* ; <%struct.node**> [#uses=1]<br>
- %0 = load i32 (...)**, i32 (...)*** null, align 4 ; <i32 (...)**> [#uses=1]<br>
- %1 = getelementptr inbounds i32 (...)*, i32 (...)** %0, i32 3 ; <i32 (...)**> [#uses=1]<br>
- %2 = load i32 (...)*, i32 (...)** %1, align 4 ; <i32 (...)*> [#uses=1]<br>
- store %struct.node* undef, %struct.node** %.SV59<br>
- %3 = bitcast i32 (...)* %2 to i32 (%struct.node*)* ; <i32 (%struct.node*)*> [#uses=1]<br>
- %4 = tail call i32 %3(%struct.node* undef) ; <i32> [#uses=0]<br>
- unreachable<br>
-}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>copy-eflags.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/copy-eflags.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/copy-eflags.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>copy-eflags.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>copy-eflags.ll Mon Mar 13 19:34:14 2017<br>
@@ -9,19 +9,22 @@ target triple = "i686-unknown-linux-gnu"<br>
@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1<br>
<br>
; CHECK-LABEL: func:<br>
-; This tests whether eax is properly saved/restored around the lahf/sahf<br>
-; instruction sequences.<br>
+; This tests whether eax is properly saved/restored around the<br>
+; lahf/sahf instruction sequences. We make mem op volatile to prevent<br>
+; their reordering to avoid spills.<br>
+<br>
+<br>
define i32 @func() {<br>
entry:<br>
%bval = load i8, i8* @b<br>
%inc = add i8 %bval, 1<br>
- store i8 %inc, i8* @b<br>
- %cval = load i32, i32* @c<br>
+ store volatile i8 %inc, i8* @b<br>
+ %cval = load volatile i32, i32* @c<br>
%inc1 = add nsw i32 %cval, 1<br>
- store i32 %inc1, i32* @c<br>
- %aval = load i8, i8* @a<br>
+ store volatile i32 %inc1, i32* @c<br>
+ %aval = load volatile i8, i8* @a<br>
%inc2 = add i8 %aval, 1<br>
- store i8 %inc2, i8* @a<br>
+ store volatile i8 %inc2, i8* @a<br>
; Copy flags produced by the incb of %inc1 to a register, need to save+restore<br>
; eax around it. The flags will be reused by %tobool.<br>
; CHECK: pushl %eax<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>dag-merge-fast-accesses.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dag-merge-fast-accesses.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/dag-merge-fast-<wbr>accesses.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>dag-merge-fast-accesses.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>dag-merge-fast-accesses.ll Mon Mar 13 19:34:14 2017<br>
@@ -51,19 +51,11 @@ define void @merge_vec_element_store(<4<br>
}<br>
<br>
<br>
-;; TODO: FAST *should* be:<br>
-;; movups (%rdi), %xmm0<br>
-;; movups %xmm0, 40(%rdi)<br>
-;; ..but is not currently. See the UseAA FIXME in DAGCombiner.cpp<br>
-;; visitSTORE.<br>
-<br>
define void @merge_vec_load_and_stores(i64 *%ptr) {<br>
; FAST-LABEL: merge_vec_load_and_stores:<br>
; FAST: # BB#0:<br>
-; FAST-NEXT: movq (%rdi), %rax<br>
-; FAST-NEXT: movq 8(%rdi), %rcx<br>
-; FAST-NEXT: movq %rax, 40(%rdi)<br>
-; FAST-NEXT: movq %rcx, 48(%rdi)<br>
+; FAST-NEXT: movups (%rdi), %xmm0<br>
+; FAST-NEXT: movups %xmm0, 40(%rdi)<br>
; FAST-NEXT: retq<br>
;<br>
; SLOW-LABEL: merge_vec_load_and_stores:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>dont-trunc-store-double-to-<wbr>float.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dont-trunc-store-double-to-float.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/dont-trunc-store-<wbr>double-to-float.ll?rev=297695&<wbr>r1=297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>dont-trunc-store-double-to-<wbr>float.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>dont-trunc-store-double-to-<wbr>float.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,9 +1,9 @@<br>
; RUN: llc -march=x86 < %s | FileCheck %s<br>
<br>
; CHECK-LABEL: @bar<br>
-; CHECK: movl $1074339512,<br>
-; CHECK: movl $1374389535,<br>
-; CHECK: movl $1078523331,<br>
+; CHECK-DAG: movl $1074339512,<br>
+; CHECK-DAG: movl $1374389535,<br>
+; CHECK-DAG: movl $1078523331,<br>
define void @bar() unnamed_addr {<br>
entry-block:<br>
%a = alloca double<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>extractelement-legalization-<wbr>store-ordering.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/extractelement-legalization-store-ordering.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/extractelement-<wbr>legalization-store-ordering.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>extractelement-legalization-<wbr>store-ordering.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>extractelement-legalization-<wbr>store-ordering.ll Mon Mar 13 19:34:14 2017<br>
@@ -16,19 +16,20 @@ target datalayout = "e-m:o-p:32:32-f64:3<br>
; CHECK-NEXT: movl 20(%esp), %edx<br>
; CHECK-NEXT: paddd (%edx), %xmm0<br>
; CHECK-NEXT: movdqa %xmm0, (%edx)<br>
-; CHECK-NEXT: movl (%edx), %esi<br>
-; CHECK-NEXT: movl 12(%edx), %edi<br>
-; CHECK-NEXT: movl 8(%edx), %ebx<br>
-; CHECK-NEXT: movl 4(%edx), %edx<br>
-; CHECK-NEXT: shll $4, %ecx<br>
+; CHECK-NEXT: movl (%edx), %esi<br>
+; CHECK-NEXT: movl 4(%edx), %edi<br>
+; CHECK-NEXT: shll $4, %ecx<br>
+; CHECK-NEXT: movl 8(%edx), %ebx<br>
+; CHECK-NEXT: movl 12(%edx), %edx<br>
; CHECK-NEXT: movl %esi, 12(%eax,%ecx)<br>
-; CHECK-NEXT: movl %edx, (%eax,%ecx)<br>
+; CHECK-NEXT: movl %edi, (%eax,%ecx)<br>
; CHECK-NEXT: movl %ebx, 8(%eax,%ecx)<br>
-; CHECK-NEXT: movl %edi, 4(%eax,%ecx)<br>
+; CHECK-NEXT: movl %edx, 4(%eax,%ecx)<br>
; CHECK-NEXT: popl %esi<br>
; CHECK-NEXT: popl %edi<br>
; CHECK-NEXT: popl %ebx<br>
; CHECK-NEXT: retl<br>
+<br>
define void @test_extractelement_<wbr>legalization_storereuse(<4 x i32> %a, i32* nocapture %x, i32* nocapture readonly %y, i32 %i) #0 {<br>
entry:<br>
%0 = bitcast i32* %y to <4 x i32>*<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>i256-add.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i256-add.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/i256-add.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>i256-add.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>i256-add.ll Mon Mar 13 19:34:14 2017<br>
@@ -6,45 +6,122 @@ define void @add(i256* %p, i256* %q) nou<br>
; X32-LABEL: add:<br>
; X32: # BB#0:<br>
; X32-NEXT: pushl %ebp<br>
+; X32-NEXT: movl %esp, %ebp<br>
; X32-NEXT: pushl %ebx<br>
; X32-NEXT: pushl %edi<br>
; X32-NEXT: pushl %esi<br>
-; X32-NEXT: subl $16, %esp<br>
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx<br>
-; X32-NEXT: movl 8(%ecx), %edi<br>
-; X32-NEXT: movl (%ecx), %esi<br>
-; X32-NEXT: movl 4(%ecx), %ebx<br>
-; X32-NEXT: movl 28(%eax), %edx<br>
-; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill<br>
-; X32-NEXT: movl 24(%eax), %edx<br>
-; X32-NEXT: addl (%eax), %esi<br>
-; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill<br>
-; X32-NEXT: adcl 4(%eax), %ebx<br>
-; X32-NEXT: movl %ebx, (%esp) # 4-byte Spill<br>
-; X32-NEXT: adcl 8(%eax), %edi<br>
-; X32-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill<br>
-; X32-NEXT: movl 20(%eax), %ebx<br>
-; X32-NEXT: movl 12(%eax), %esi<br>
-; X32-NEXT: movl 16(%eax), %edi<br>
-; X32-NEXT: adcl 12(%ecx), %esi<br>
-; X32-NEXT: adcl 16(%ecx), %edi<br>
-; X32-NEXT: adcl 20(%ecx), %ebx<br>
-; X32-NEXT: adcl 24(%ecx), %edx<br>
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax # 4-byte Reload<br>
-; X32-NEXT: adcl 28(%ecx), %eax<br>
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp # 4-byte Reload<br>
-; X32-NEXT: movl %ebp, 8(%ecx)<br>
-; X32-NEXT: movl (%esp), %ebp # 4-byte Reload<br>
-; X32-NEXT: movl %ebp, 4(%ecx)<br>
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp # 4-byte Reload<br>
-; X32-NEXT: movl %ebp, (%ecx)<br>
-; X32-NEXT: movl %esi, 12(%ecx)<br>
-; X32-NEXT: movl %edi, 16(%ecx)<br>
-; X32-NEXT: movl %ebx, 20(%ecx)<br>
-; X32-NEXT: movl %edx, 24(%ecx)<br>
-; X32-NEXT: movl %eax, 28(%ecx)<br>
-; X32-NEXT: addl $16, %esp<br>
+; X32-NEXT: subl $28, %esp<br>
+; X32-NEXT: movl 12(%ebp), %edi<br>
+; X32-NEXT: movl 8(%ebp), %eax<br>
+; X32-NEXT: movl (%eax), %ecx<br>
+; X32-NEXT: movl (%edi), %edx<br>
+; X32-NEXT: movl %ecx, %esi<br>
+; X32-NEXT: addl %edx, %esi<br>
+; X32-NEXT: movl 4(%edi), %ebx<br>
+; X32-NEXT: movl 4(%eax), %esi<br>
+; X32-NEXT: adcl %ebx, %esi<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %esi<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: movl %esi, -32(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl %esi, -16(%ebp) # 4-byte Spill<br>
+; X32-NEXT: addl %edx, %ecx<br>
+; X32-NEXT: movl %ecx, -40(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl 8(%edi), %edx<br>
+; X32-NEXT: movl %edx, -28(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl 28(%edi), %ecx<br>
+; X32-NEXT: movl %ecx, -36(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl 24(%edi), %ecx<br>
+; X32-NEXT: movl %ecx, -20(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl 20(%edi), %ecx<br>
+; X32-NEXT: movl 16(%edi), %esi<br>
+; X32-NEXT: movl %esi, -24(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl 12(%edi), %edi<br>
+; X32-NEXT: adcl %ebx, 4(%eax)<br>
+; X32-NEXT: movl 8(%eax), %ebx<br>
+; X32-NEXT: movl -16(%ebp), %esi # 4-byte Reload<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %esi, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: adcl %edx, %ebx<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %ebx<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: adcl %edi, 12(%eax)<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %ebx, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: adcl 12(%eax), %edi<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %esi<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: movl 16(%eax), %ebx<br>
+; X32-NEXT: movl -24(%ebp), %edx # 4-byte Reload<br>
+; X32-NEXT: adcl %edx, %ebx<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %ebx<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %edi<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %esi, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: adcl %edx, 16(%eax)<br>
+; X32-NEXT: movl -32(%ebp), %edx # 4-byte Reload<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %edx, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: movl -28(%ebp), %edx # 4-byte Reload<br>
+; X32-NEXT: adcl %edx, 8(%eax)<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %edi, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: adcl %ecx, 20(%eax)<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %ebx, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: adcl 20(%eax), %ecx<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %ecx<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: movl -20(%ebp), %edx # 4-byte Reload<br>
+; X32-NEXT: adcl %edx, 24(%eax)<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %ecx, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: adcl 24(%eax), %edx<br>
+; X32-NEXT: movl -36(%ebp), %ecx # 4-byte Reload<br>
+; X32-NEXT: adcl %ecx, 28(%eax)<br>
+; X32-NEXT: movl -40(%ebp), %ecx # 4-byte Reload<br>
+; X32-NEXT: movl %ecx, (%eax)<br>
+; X32-NEXT: addl $28, %esp<br>
; X32-NEXT: popl %esi<br>
; X32-NEXT: popl %edi<br>
; X32-NEXT: popl %ebx<br>
@@ -53,18 +130,28 @@ define void @add(i256* %p, i256* %q) nou<br>
;<br>
; X64-LABEL: add:<br>
; X64: # BB#0:<br>
-; X64-NEXT: movq 16(%rdi), %rax<br>
-; X64-NEXT: movq (%rdi), %r8<br>
-; X64-NEXT: movq 8(%rdi), %rdx<br>
-; X64-NEXT: movq 24(%rsi), %rcx<br>
-; X64-NEXT: addq (%rsi), %r8<br>
-; X64-NEXT: adcq 8(%rsi), %rdx<br>
-; X64-NEXT: adcq 16(%rsi), %rax<br>
-; X64-NEXT: adcq 24(%rdi), %rcx<br>
-; X64-NEXT: movq %rax, 16(%rdi)<br>
-; X64-NEXT: movq %rdx, 8(%rdi)<br>
-; X64-NEXT: movq %r8, (%rdi)<br>
-; X64-NEXT: movq %rcx, 24(%rdi)<br>
+; X64-NEXT: pushq %rbp<br>
+; X64-NEXT: movq %rsp, %rbp<br>
+; X64-NEXT: movq (%rdi), %rdx<br>
+; X64-NEXT: movq 8(%rdi), %r9<br>
+; X64-NEXT: movq 24(%rsi), %r8<br>
+; X64-NEXT: movq 8(%rsi), %r10<br>
+; X64-NEXT: movq 16(%rsi), %rcx<br>
+; X64-NEXT: movq (%rsi), %rsi<br>
+; X64-NEXT: movq %rdx, %rax<br>
+; X64-NEXT: addq %rsi, %rax<br>
+; X64-NEXT: adcq %r10, 8(%rdi)<br>
+; X64-NEXT: addq %rsi, %rdx<br>
+; X64-NEXT: adcq %r10, %r9<br>
+; X64-NEXT: pushfq<br>
+; X64-NEXT: popq %rax<br>
+; X64-NEXT: adcq %rcx, 16(%rdi)<br>
+; X64-NEXT: pushq %rax<br>
+; X64-NEXT: popfq<br>
+; X64-NEXT: adcq 16(%rdi), %rcx<br>
+; X64-NEXT: adcq %r8, 24(%rdi)<br>
+; X64-NEXT: movq %rdx, (%rdi)<br>
+; X64-NEXT: popq %rbp<br>
; X64-NEXT: retq<br>
%a = load i256, i256* %p<br>
%b = load i256, i256* %q<br>
@@ -76,43 +163,110 @@ define void @sub(i256* %p, i256* %q) nou<br>
; X32-LABEL: sub:<br>
; X32: # BB#0:<br>
; X32-NEXT: pushl %ebp<br>
+; X32-NEXT: movl %esp, %ebp<br>
; X32-NEXT: pushl %ebx<br>
; X32-NEXT: pushl %edi<br>
; X32-NEXT: pushl %esi<br>
-; X32-NEXT: subl $12, %esp<br>
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx<br>
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx<br>
-; X32-NEXT: movl 16(%ecx), %eax<br>
-; X32-NEXT: movl 12(%ecx), %edx<br>
-; X32-NEXT: movl 8(%ecx), %edi<br>
-; X32-NEXT: movl (%ecx), %esi<br>
-; X32-NEXT: movl 4(%ecx), %ebp<br>
-; X32-NEXT: subl (%ebx), %esi<br>
-; X32-NEXT: movl %esi, {{[0-9]+}}(%esp) # 4-byte Spill<br>
-; X32-NEXT: sbbl 4(%ebx), %ebp<br>
-; X32-NEXT: sbbl 8(%ebx), %edi<br>
-; X32-NEXT: sbbl 12(%ebx), %edx<br>
-; X32-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill<br>
-; X32-NEXT: sbbl 16(%ebx), %eax<br>
-; X32-NEXT: movl %eax, (%esp) # 4-byte Spill<br>
-; X32-NEXT: movl 20(%ecx), %esi<br>
-; X32-NEXT: sbbl 20(%ebx), %esi<br>
+; X32-NEXT: subl $24, %esp<br>
+; X32-NEXT: movl 12(%ebp), %edi<br>
+; X32-NEXT: movl 8(%ebp), %ecx<br>
+; X32-NEXT: movl (%ecx), %eax<br>
+; X32-NEXT: movl 4(%ecx), %edx<br>
+; X32-NEXT: movl (%edi), %esi<br>
+; X32-NEXT: cmpl %esi, %eax<br>
+; X32-NEXT: movl 4(%edi), %ebx<br>
+; X32-NEXT: sbbl %ebx, %edx<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %edx<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: movl %edx, -24(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl %edx, -16(%ebp) # 4-byte Spill<br>
+; X32-NEXT: subl %esi, %eax<br>
+; X32-NEXT: movl %eax, -36(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl 8(%edi), %esi<br>
+; X32-NEXT: movl 28(%edi), %eax<br>
+; X32-NEXT: movl %eax, -32(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl 24(%edi), %eax<br>
+; X32-NEXT: movl %eax, -28(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl 20(%edi), %eax<br>
+; X32-NEXT: movl %eax, -20(%ebp) # 4-byte Spill<br>
+; X32-NEXT: movl 16(%edi), %edx<br>
+; X32-NEXT: movl 12(%edi), %edi<br>
+; X32-NEXT: sbbl %ebx, 4(%ecx)<br>
+; X32-NEXT: movl 8(%ecx), %ebx<br>
+; X32-NEXT: movl -16(%ebp), %eax # 4-byte Reload<br>
+; X32-NEXT: movl %eax, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: sbbl %esi, %ebx<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %ebx<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: sbbl %edi, 12(%ecx)<br>
+; X32-NEXT: movl 12(%ecx), %eax<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %ebx, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: sbbl %edi, %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %eax<br>
+; X32-NEXT: movl 16(%ecx), %edi<br>
+; X32-NEXT: sbbl %edx, %edi<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %edi<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %ebx<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: movl %eax, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: sbbl %edx, 16(%ecx)<br>
+; X32-NEXT: movl -24(%ebp), %eax # 4-byte Reload<br>
+; X32-NEXT: movl %eax, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: sbbl %esi, 8(%ecx)<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %ebx, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: movl -20(%ebp), %edx # 4-byte Reload<br>
+; X32-NEXT: sbbl %edx, 20(%ecx)<br>
+; X32-NEXT: movl 20(%ecx), %eax<br>
+; X32-NEXT: pushl %eax<br>
+; X32-NEXT: movl %edi, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: popl %eax<br>
+; X32-NEXT: sbbl %edx, %eax<br>
+; X32-NEXT: seto %al<br>
+; X32-NEXT: lahf<br>
+; X32-NEXT: movl %eax, %eax<br>
+; X32-NEXT: movl -28(%ebp), %esi # 4-byte Reload<br>
+; X32-NEXT: sbbl %esi, 24(%ecx)<br>
; X32-NEXT: movl 24(%ecx), %edx<br>
-; X32-NEXT: sbbl 24(%ebx), %edx<br>
-; X32-NEXT: movl 28(%ecx), %eax<br>
-; X32-NEXT: sbbl 28(%ebx), %eax<br>
-; X32-NEXT: movl %edi, 8(%ecx)<br>
-; X32-NEXT: movl %ebp, 4(%ecx)<br>
-; X32-NEXT: movl {{[0-9]+}}(%esp), %edi # 4-byte Reload<br>
-; X32-NEXT: movl %edi, (%ecx)<br>
-; X32-NEXT: movl {{[0-9]+}}(%esp), %edi # 4-byte Reload<br>
-; X32-NEXT: movl %edi, 12(%ecx)<br>
-; X32-NEXT: movl (%esp), %edi # 4-byte Reload<br>
-; X32-NEXT: movl %edi, 16(%ecx)<br>
-; X32-NEXT: movl %esi, 20(%ecx)<br>
-; X32-NEXT: movl %edx, 24(%ecx)<br>
-; X32-NEXT: movl %eax, 28(%ecx)<br>
-; X32-NEXT: addl $12, %esp<br>
+; X32-NEXT: movl %eax, %eax<br>
+; X32-NEXT: addb $127, %al<br>
+; X32-NEXT: sahf<br>
+; X32-NEXT: sbbl %esi, %edx<br>
+; X32-NEXT: movl -32(%ebp), %eax # 4-byte Reload<br>
+; X32-NEXT: sbbl %eax, 28(%ecx)<br>
+; X32-NEXT: movl -36(%ebp), %eax # 4-byte Reload<br>
+; X32-NEXT: movl %eax, (%ecx)<br>
+; X32-NEXT: addl $24, %esp<br>
; X32-NEXT: popl %esi<br>
; X32-NEXT: popl %edi<br>
; X32-NEXT: popl %ebx<br>
@@ -121,18 +275,28 @@ define void @sub(i256* %p, i256* %q) nou<br>
;<br>
; X64-LABEL: sub:<br>
; X64: # BB#0:<br>
-; X64-NEXT: movq 24(%rdi), %r8<br>
-; X64-NEXT: movq 16(%rdi), %rcx<br>
-; X64-NEXT: movq (%rdi), %rdx<br>
-; X64-NEXT: movq 8(%rdi), %rax<br>
-; X64-NEXT: subq (%rsi), %rdx<br>
-; X64-NEXT: sbbq 8(%rsi), %rax<br>
-; X64-NEXT: sbbq 16(%rsi), %rcx<br>
-; X64-NEXT: sbbq 24(%rsi), %r8<br>
-; X64-NEXT: movq %rcx, 16(%rdi)<br>
-; X64-NEXT: movq %rax, 8(%rdi)<br>
-; X64-NEXT: movq %rdx, (%rdi)<br>
-; X64-NEXT: movq %r8, 24(%rdi)<br>
+; X64-NEXT: pushq %rbp<br>
+; X64-NEXT: movq %rsp, %rbp<br>
+; X64-NEXT: movq (%rdi), %rax<br>
+; X64-NEXT: movq 8(%rdi), %rcx<br>
+; X64-NEXT: movq 24(%rsi), %r8<br>
+; X64-NEXT: movq 8(%rsi), %rdx<br>
+; X64-NEXT: movq 16(%rsi), %r9<br>
+; X64-NEXT: movq (%rsi), %rsi<br>
+; X64-NEXT: cmpq %rsi, %rax<br>
+; X64-NEXT: sbbq %rdx, 8(%rdi)<br>
+; X64-NEXT: subq %rsi, %rax<br>
+; X64-NEXT: sbbq %rdx, %rcx<br>
+; X64-NEXT: pushfq<br>
+; X64-NEXT: popq %rcx<br>
+; X64-NEXT: sbbq %r9, 16(%rdi)<br>
+; X64-NEXT: movq 16(%rdi), %rdx<br>
+; X64-NEXT: pushq %rcx<br>
+; X64-NEXT: popfq<br>
+; X64-NEXT: sbbq %r9, %rdx<br>
+; X64-NEXT: sbbq %r8, 24(%rdi)<br>
+; X64-NEXT: movq %rax, (%rdi)<br>
+; X64-NEXT: popq %rbp<br>
; X64-NEXT: retq<br>
%a = load i256, i256* %p<br>
%b = load i256, i256* %q<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>i386-shrink-wrapping.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/i386-shrink-wrapping.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/i386-shrink-<wbr>wrapping.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>i386-shrink-wrapping.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>i386-shrink-wrapping.ll Mon Mar 13 19:34:14 2017<br>
@@ -55,8 +55,7 @@ target triple = "i386-apple-macosx10.5"<br>
;<br>
; CHECK-NEXT: L_e$non_lazy_ptr, [[E:%[a-z]+]]<br>
; CHECK-NEXT: movb [[D]], ([[E]])<br>
-; CHECK-NEXT: L_f$non_lazy_ptr, [[F:%[a-z]+]]<br>
-; CHECK-NEXT: movsbl ([[F]]), [[CONV:%[a-z]+]]<br>
+; CHECK-NEXT: movsbl ([[E]]), [[CONV:%[a-z]+]]<br>
; CHECK-NEXT: movl $6, [[CONV:%[a-z]+]]<br>
; The eflags is used in the next instruction.<br>
; If that instruction disappear, we are not exercising the bug<br>
@@ -96,7 +95,7 @@ for.end:<br>
%.b3 = load i1, i1* @d, align 1<br>
%tmp2 = select i1 %.b3, i8 0, i8 6<br>
store i8 %tmp2, i8* @e, align 1<br>
- %tmp3 = load i8, i8* @f, align 1<br>
+ %tmp3 = load i8, i8* @e, align 1<br>
%conv = sext i8 %tmp3 to i32<br>
%add = add nsw i32 %conv, 1<br>
%rem = srem i32 %tmp1, %add<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>live-range-nosubreg.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/live-range-nosubreg.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/live-range-<wbr>nosubreg.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>live-range-nosubreg.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>live-range-nosubreg.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,7 +1,6 @@<br>
-; RUN: llc -march=x86-64 < %s | FileCheck %s<br>
+; RUN: llc -march=x86-64 < %s<br>
<br>
-; Check for a sane output. This testcase used to crash. See PR29132.<br>
-; CHECK: leal -1<br>
+; This testcase used to crash. See PR29132.<br>
<br>
target triple = "x86_64-unknown-linux-gnu"<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>longlong-deadload.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/longlong-deadload.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/longlong-deadload.<wbr>ll?rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>longlong-deadload.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>longlong-deadload.ll Mon Mar 13 19:34:14 2017<br>
@@ -7,10 +7,8 @@ define void @test(i64* %P) nounwind {<br>
; CHECK: # BB#0:<br>
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; CHECK-NEXT: movl (%eax), %ecx<br>
-; CHECK-NEXT: movl 4(%eax), %edx<br>
; CHECK-NEXT: xorl $1, %ecx<br>
; CHECK-NEXT: orl $2, %ecx<br>
-; CHECK-NEXT: movl %edx, 4(%eax)<br>
; CHECK-NEXT: movl %ecx, (%eax)<br>
; CHECK-NEXT: retl<br>
%tmp1 = load i64, i64* %P, align 8<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>merge-consecutive-loads-128.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/merge-consecutive-<wbr>loads-128.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>merge-consecutive-loads-128.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>merge-consecutive-loads-128.ll Mon Mar 13 19:34:14 2017<br>
@@ -1037,12 +1037,12 @@ define <2 x i64> @merge_2i64_i64_12_vola<br>
define <4 x float> @merge_4f32_f32_2345_volatile(<wbr>float* %ptr) nounwind uwtable noinline ssp {<br>
; SSE2-LABEL: merge_4f32_f32_2345_volatile:<br>
; SSE2: # BB#0:<br>
-; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
+; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; SSE2-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero<br>
; SSE2-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1]<br>
-; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1]<br>
+; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
+; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
; SSE2-NEXT: retq<br>
;<br>
@@ -1065,13 +1065,13 @@ define <4 x float> @merge_4f32_f32_2345_<br>
; X32-SSE1-LABEL: merge_4f32_f32_2345_volatile:<br>
; X32-SSE1: # BB#0:<br>
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
-; X32-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
-; X32-SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
-; X32-SSE1-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; X32-SSE1-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero<br>
-; X32-SSE1-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1]<br>
-; X32-SSE1-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1]<br>
-; X32-SSE1-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
+; X32-SSE1-DAG: movss 8(%eax), %[[R0:xmm[0-3]]] # [[R0]] = mem[0],zero,zero,zero<br>
+; X32-SSE1-DAG: movss 12(%eax), %[[R1:xmm[0-3]]] # [[R1]] = mem[0],zero,zero,zero<br>
+; X32-SSE1-DAG: movss 16(%eax), %[[R2:xmm[0-3]]] # [[R2]] = mem[0],zero,zero,zero<br>
+; X32-SSE1-DAG: movss 20(%eax), %[[R3:xmm[0-3]]] # [[R3]] = mem[0],zero,zero,zero<br>
+; X32-SSE1-DAG: unpcklps %[[R2]], %[[R0]] # [[R0]] = [[R0]][0],[[R2]][0],[[R0]][1],<wbr>[[R2]][1]<br>
+; X32-SSE1-DAG: unpcklps %[[R3]], %[[R1]] # [[R1]] = [[R1]][0],[[R3]][0],[[R1]][1],<wbr>[[R3]][1]<br>
+; X32-SSE1-DAG: unpcklps %[[R1]], %[[R0]] # [[R0]] = [[R0]][0],[[R1]][0],[[R0]][1],<wbr>[[R1]][1]<br>
; X32-SSE1-NEXT: retl<br>
;<br>
; X32-SSE41-LABEL: merge_4f32_f32_2345_volatile:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>merge-consecutive-loads-256.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/merge-consecutive-<wbr>loads-256.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>merge-consecutive-loads-256.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>merge-consecutive-loads-256.ll Mon Mar 13 19:34:14 2017<br>
@@ -668,10 +668,10 @@ define <16 x i16> @merge_16i16_i16_0uu3z<br>
; AVX1: # BB#0:<br>
; AVX1-NEXT: vpxor %xmm0, %xmm0, %xmm0<br>
; AVX1-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm1<br>
-; AVX1-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm1<br>
; AVX1-NEXT: vpinsrw $4, 24(%rdi), %xmm0, %xmm0<br>
; AVX1-NEXT: vpinsrw $6, 28(%rdi), %xmm0, %xmm0<br>
; AVX1-NEXT: vpinsrw $7, 30(%rdi), %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX1-NEXT: retq<br>
;<br>
@@ -679,10 +679,10 @@ define <16 x i16> @merge_16i16_i16_0uu3z<br>
; AVX2: # BB#0:<br>
; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0<br>
; AVX2-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm1<br>
-; AVX2-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm1<br>
; AVX2-NEXT: vpinsrw $4, 24(%rdi), %xmm0, %xmm0<br>
; AVX2-NEXT: vpinsrw $6, 28(%rdi), %xmm0, %xmm0<br>
; AVX2-NEXT: vpinsrw $7, 30(%rdi), %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm1<br>
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX2-NEXT: retq<br>
;<br>
@@ -690,10 +690,10 @@ define <16 x i16> @merge_16i16_i16_0uu3z<br>
; AVX512F: # BB#0:<br>
; AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0<br>
; AVX512F-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm1<br>
-; AVX512F-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm1<br>
; AVX512F-NEXT: vpinsrw $4, 24(%rdi), %xmm0, %xmm0<br>
; AVX512F-NEXT: vpinsrw $6, 28(%rdi), %xmm0, %xmm0<br>
; AVX512F-NEXT: vpinsrw $7, 30(%rdi), %xmm0, %xmm0<br>
+; AVX512F-NEXT: vpinsrw $3, 6(%rdi), %xmm1, %xmm1<br>
; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX512F-NEXT: retq<br>
;<br>
@@ -702,10 +702,10 @@ define <16 x i16> @merge_16i16_i16_0uu3z<br>
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
; X32-AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0<br>
; X32-AVX-NEXT: vpinsrw $0, (%eax), %xmm0, %xmm1<br>
-; X32-AVX-NEXT: vpinsrw $3, 6(%eax), %xmm1, %xmm1<br>
; X32-AVX-NEXT: vpinsrw $4, 24(%eax), %xmm0, %xmm0<br>
; X32-AVX-NEXT: vpinsrw $6, 28(%eax), %xmm0, %xmm0<br>
; X32-AVX-NEXT: vpinsrw $7, 30(%eax), %xmm0, %xmm0<br>
+; X32-AVX-NEXT: vpinsrw $3, 6(%eax), %xmm1, %xmm1<br>
; X32-AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; X32-AVX-NEXT: retl<br>
%ptr0 = getelementptr inbounds i16, i16* %ptr, i64 0<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>merge-store-partially-alias-<wbr>loads.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-store-partially-alias-loads.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/merge-store-<wbr>partially-alias-loads.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>merge-store-partially-alias-<wbr>loads.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>merge-store-partially-alias-<wbr>loads.ll Mon Mar 13 19:34:14 2017<br>
@@ -21,11 +21,11 @@<br>
; DBGDAG-DAG: [[LD2:t[0-9]+]]: i16,ch = load<LD2[%tmp81](align=1)> [[ENTRYTOKEN]], [[BASEPTR]], undef:i64<br>
; DBGDAG-DAG: [[LD1:t[0-9]+]]: i8,ch = load<LD1[%tmp12]> [[ENTRYTOKEN]], [[ADDPTR]], undef:i64<br>
<br>
-; DBGDAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1<br>
-<br>
+; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<ST1[%tmp14]> [[ENTRYTOKEN]], [[LD1]], t{{[0-9]+}}, undef:i64<br>
+; DBGDAG-DAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1<br>
; DBGDAG-DAG: [[ST2:t[0-9]+]]: ch = store<ST2[%tmp10](align=1)> [[LOADTOKEN]], [[LD2]], t{{[0-9]+}}, undef:i64<br>
-; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<ST1[%tmp14]> [[ST2]], [[LD1]], t{{[0-9]+}}, undef:i64<br>
-; DBGDAG: X86ISD::RET_FLAG [[ST1]],<br>
+<br>
+; DBGDAG: X86ISD::RET_FLAG t{{[0-9]+}},<br>
<br>
; DBGDAG: Type-legalized selection DAG: BB#0 'merge_store_partial_overlap_<wbr>load:'<br>
define void @merge_store_partial_overlap_<wbr>load([4 x i8]* %tmp) {<br>
<br>
Removed: llvm/trunk/test/CodeGen/X86/<wbr>pr18023.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr18023.ll?rev=297694&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/pr18023.ll?rev=<wbr>297694&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>pr18023.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>pr18023.ll (removed)<br>
@@ -1,31 +0,0 @@<br>
-; RUN: llc < %s -mtriple x86_64-apple-macosx10.9.0 | FileCheck %s<br>
-; PR18023<br>
-<br>
-; CHECK: movabsq $4294967296, %rcx<br>
-; CHECK: movq %rcx, (%rax)<br>
-; CHECK: movl $1, 4(%rax)<br>
-; CHECK: movl $0, 4(%rax)<br>
-; CHECK: movq $1, 4(%rax)<br>
-<br>
-@c = common global i32 0, align 4<br>
-@a = common global [3 x i32] zeroinitializer, align 4<br>
-@b = common global i32 0, align 4<br>
-@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1<br>
-<br>
-define void @func() {<br>
- store i32 1, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4<br>
- store i32 0, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 0), align 4<br>
- %1 = load volatile i32, i32* @b, align 4<br>
- store i32 1, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4<br>
- store i32 0, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4<br>
- %2 = load volatile i32, i32* @b, align 4<br>
- store i32 1, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4<br>
- store i32 0, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 2), align 4<br>
- %3 = load volatile i32, i32* @b, align 4<br>
- store i32 3, i32* @c, align 4<br>
- %4 = load i32, i32* getelementptr inbounds ([3 x i32], [3 x i32]* @a, i64 0, i64 1), align 4<br>
- %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %4)<br>
- ret void<br>
-}<br>
-<br>
-declare i32 @printf(i8*, ...)<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/<wbr>pr32108.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32108.ll?rev=297695&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/pr32108.ll?rev=<wbr>297695&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>pr32108.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>pr32108.ll Mon Mar 13 19:34:14 2017<br>
@@ -0,0 +1,20 @@<br>
+; RUN: llc -march=x86-64 %s -o -<br>
+<br>
+target triple = "x86_64-unknown-linux-gnu"<br>
+<br>
+define void @autogen_SD1794() {<br>
+BB:<br>
+ %Cmp45 = icmp slt <4 x i32> undef, undef<br>
+ br label %CF243<br>
+<br>
+CF243: ; preds = %CF243, %BB<br>
+ br i1 undef, label %CF243, label %CF257<br>
+<br>
+CF257: ; preds = %CF243<br>
+ %Shuff144 = shufflevector <4 x i1> undef, <4 x i1> %Cmp45, <4 x i32> <i32 undef, i32 undef, i32 5, i32 undef><br>
+ br label %CF244<br>
+<br>
+CF244: ; preds = %CF244, %CF257<br>
+ %Shuff182 = shufflevector <4 x i1> %Shuff144, <4 x i1> zeroinitializer, <4 x i32> <i32 3, i32 5, i32 7, i32 undef><br>
+ br label %CF244<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>split-store.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/split-store.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/split-store.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>split-store.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>split-store.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,8 +1,8 @@<br>
; RUN: llc -mtriple=x86_64-unknown-<wbr>unknown -force-split-store < %s | FileCheck %s<br>
<br>
; CHECK-LABEL: int32_float_pair<br>
-; CHECK: movl %edi, (%rsi)<br>
-; CHECK: movss %xmm0, 4(%rsi)<br>
+; CHECK-DAG: movl %edi, (%rsi)<br>
+; CHECK-DAG: movss %xmm0, 4(%rsi)<br>
define void @int32_float_pair(i32 %tmp1, float %tmp2, i64* %ref.tmp) {<br>
entry:<br>
%t0 = bitcast float %tmp2 to i32<br>
@@ -15,8 +15,8 @@ entry:<br>
}<br>
<br>
; CHECK-LABEL: float_int32_pair<br>
-; CHECK: movss %xmm0, (%rsi)<br>
-; CHECK: movl %edi, 4(%rsi)<br>
+; CHECK-DAG: movss %xmm0, (%rsi)<br>
+; CHECK-DAG: movl %edi, 4(%rsi)<br>
define void @float_int32_pair(float %tmp1, i32 %tmp2, i64* %ref.tmp) {<br>
entry:<br>
%t0 = bitcast float %tmp1 to i32<br>
@@ -29,9 +29,9 @@ entry:<br>
}<br>
<br>
; CHECK-LABEL: int16_float_pair<br>
-; CHECK: movzwl %di, %eax<br>
-; CHECK: movl %eax, (%rsi)<br>
-; CHECK: movss %xmm0, 4(%rsi)<br>
+; CHECK-DAG: movzwl %di, %eax<br>
+; CHECK-DAG: movl %eax, (%rsi)<br>
+; CHECK-DAG: movss %xmm0, 4(%rsi)<br>
define void @int16_float_pair(i16 signext %tmp1, float %tmp2, i64* %ref.tmp) {<br>
entry:<br>
%t0 = bitcast float %tmp2 to i32<br>
@@ -44,9 +44,9 @@ entry:<br>
}<br>
<br>
; CHECK-LABEL: int8_float_pair<br>
-; CHECK: movzbl %dil, %eax<br>
-; CHECK: movl %eax, (%rsi)<br>
-; CHECK: movss %xmm0, 4(%rsi)<br>
+; CHECK-DAG: movzbl %dil, %eax<br>
+; CHECK-DAG: movl %eax, (%rsi)<br>
+; CHECK-DAG: movss %xmm0, 4(%rsi)<br>
define void @int8_float_pair(i8 signext %tmp1, float %tmp2, i64* %ref.tmp) {<br>
entry:<br>
%t0 = bitcast float %tmp2 to i32<br>
@@ -146,10 +146,9 @@ entry:<br>
; CHECK: movw %di, (%rdx)<br>
; CHECK: shrl $16, %edi<br>
; CHECK: movb %dil, 2(%rdx)<br>
-; CHECK: movl %esi, %eax<br>
-; CHECK: shrl $16, %eax<br>
-; CHECK: movb %al, 6(%rdx)<br>
-; CHECK: movw %si, 4(%rdx)<br>
+; CHECK: movw %si, 4(%rdx)<br>
+; CHECK: shrl $16, %esi<br>
+; CHECK: movb %sil, 6(%rdx)<br>
define void @int24_int24_pair(i24 signext %tmp1, i24 signext %tmp2, i48* %ref.tmp) {<br>
entry:<br>
%t1 = zext i24 %tmp2 to i48<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>stores-merging.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stores-merging.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/stores-merging.ll?<wbr>rev=297695&r1=297694&r2=<wbr>297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>stores-merging.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>stores-merging.ll Mon Mar 13 19:34:14 2017<br>
@@ -13,9 +13,9 @@ target triple = "x86_64-unknown-linux-gn<br>
;; the same result in memory in the end.<br>
<br>
; CHECK-LABEL: redundant_stores_merging:<br>
-; CHECK: movl $123, e+8(%rip)<br>
-; CHECK: movabsq $1958505086977, %rax<br>
+; CHECK: movabsq $528280977409, %rax<br>
; CHECK: movq %rax, e+4(%rip)<br>
+; CHECK: movl $456, e+8(%rip)<br>
define void @redundant_stores_merging() {<br>
entry:<br>
store i32 1, i32* getelementptr inbounds (%structTy, %structTy* @e, i64 0, i32 1), align 4<br>
@@ -26,9 +26,9 @@ entry:<br>
<br>
;; This variant tests PR25154.<br>
; CHECK-LABEL: redundant_stores_merging_<wbr>reverse:<br>
-; CHECK: movl $123, e+8(%rip)<br>
-; CHECK: movabsq $1958505086977, %rax<br>
+; CHECK: movabsq $528280977409, %rax<br>
; CHECK: movq %rax, e+4(%rip)<br>
+; CHECK: movl $456, e+8(%rip)<br>
define void @redundant_stores_merging_<wbr>reverse() {<br>
entry:<br>
store i32 123, i32* getelementptr inbounds (%structTy, %structTy* @e, i64 0, i32 2), align 4<br>
@@ -45,9 +45,8 @@ entry:<br>
;; a movl, after the store to 3).<br>
<br>
;; CHECK-LABEL: overlapping_stores_merging:<br>
-;; CHECK: movw $0, b+2(%rip)<br>
+;; CHECK: movl $1, b(%rip)<br>
;; CHECK: movw $2, b+3(%rip)<br>
-;; CHECK: movw $1, b(%rip)<br>
define void @overlapping_stores_merging() {<br>
entry:<br>
store i16 0, i16* bitcast (i8* getelementptr inbounds ([8 x i8], [8 x i8]* @b, i64 0, i64 2) to i16*), align 2<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>vector-compare-results.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-compare-results.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/vector-compare-<wbr>results.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>vector-compare-results.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>vector-compare-results.ll Mon Mar 13 19:34:14 2017<br>
@@ -350,98 +350,98 @@ define <32 x i1> @test_cmp_v32i8(<32 x i<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 2(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, (%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movq %rdi, %rax<br>
@@ -900,98 +900,98 @@ define <32 x i1> @test_cmp_v32i16(<32 x<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 2(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, (%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movq %rdi, %rax<br>
@@ -1169,196 +1169,196 @@ define <64 x i1> @test_cmp_v64i8(<64 x i<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 6(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 4(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 2(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, (%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movq %rdi, %rax<br>
@@ -2491,98 +2491,98 @@ define <32 x i1> @test_cmp_v32f32(<32 x<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 2(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, (%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movq %rdi, %rax<br>
@@ -3990,98 +3990,98 @@ define <32 x i1> @test_cmp_v32i32(<32 x<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 2(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, (%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movq %rdi, %rax<br>
@@ -4944,196 +4944,196 @@ define <64 x i1> @test_cmp_v64i16(<64 x<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 6(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 4(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 2(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, (%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movq %rdi, %rax<br>
@@ -6775,392 +6775,392 @@ define <128 x i1> @test_cmp_v128i8(<128<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 14(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm6, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm5, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm3, -{{[0-9]+}}(%rsp)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 14(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 14(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm6, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 12(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 12(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm5, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 10(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 10(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, 8(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 8(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm3, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 6(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 4(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 2(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 14(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 12(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 10(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 8(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 6(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 4(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, (%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movq %rdi, %rax<br>
@@ -8581,98 +8581,98 @@ define <32 x i1> @test_cmp_v32f64(<32 x<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 2(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, (%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movq %rdi, %rax<br>
@@ -9897,98 +9897,98 @@ define <32 x i1> @test_cmp_v32i64(<32 x<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
-; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
-; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
-; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, (%rdi)<br>
+; SSE2-NEXT: movb %al, 2(%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, 2(%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
; SSE2-NEXT: andb $1, %al<br>
-; SSE2-NEXT: movb %al, 2(%rdi)<br>
+; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al<br>
+; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %cl<br>
+; SSE2-NEXT: andb $1, %cl<br>
+; SSE2-NEXT: movb %cl, (%rdi)<br>
; SSE2-NEXT: andb $1, %al<br>
; SSE2-NEXT: movb %al, (%rdi)<br>
; SSE2-NEXT: movq %rdi, %rax<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-variable-128.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-variable-128.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/vector-shuffle-<wbr>variable-128.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-variable-128.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-variable-128.ll Mon Mar 13 19:34:14 2017<br>
@@ -42,8 +42,8 @@ define <2 x i64> @var_shuffle_v2i64_v2i6<br>
; SSE-NEXT: andl $1, %edi<br>
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; SSE-NEXT: andl $1, %esi<br>
-; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero<br>
; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero<br>
+; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero<br>
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
; SSE-NEXT: retq<br>
;<br>
@@ -56,7 +56,7 @@ define <2 x i64> @var_shuffle_v2i64_v2i6<br>
; AVX-NEXT: andl $1, %esi<br>
; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
; AVX-NEXT: retq<br>
%x0 = extractelement <2 x i64> %x, i32 %i0<br>
%x1 = extractelement <2 x i64> %x, i32 %i1<br>
@@ -79,10 +79,10 @@ define <4 x float> @var_shuffle_v4f32_v4<br>
; SSE2-NEXT: andl $3, %ecx<br>
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
+; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1]<br>
; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
+; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
-; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1]<br>
; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
; SSE2-NEXT: retq<br>
;<br>
@@ -99,10 +99,10 @@ define <4 x float> @var_shuffle_v4f32_v4<br>
; SSSE3-NEXT: andl $3, %ecx<br>
; SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
+; SSSE3-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1]<br>
; SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
+; SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
-; SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; SSSE3-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1]<br>
; SSSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
; SSSE3-NEXT: retq<br>
;<br>
@@ -164,10 +164,10 @@ define <4 x i32> @var_shuffle_v4i32_v4i3<br>
; SSE2-NEXT: andl $3, %ecx<br>
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
+; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1]<br>
; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
+; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
-; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1]<br>
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
; SSE2-NEXT: retq<br>
;<br>
@@ -184,10 +184,10 @@ define <4 x i32> @var_shuffle_v4i32_v4i3<br>
; SSSE3-NEXT: andl $3, %ecx<br>
; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
+; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1]<br>
; SSSE3-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
+; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
-; SSSE3-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1]<br>
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
; SSSE3-NEXT: retq<br>
;<br>
@@ -255,29 +255,29 @@ define <8 x i16> @var_shuffle_v8i16_v8i1<br>
; SSE2-NEXT: andl $7, %r10d<br>
; SSE2-NEXT: movzwl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $7, %eax<br>
-; SSE2-NEXT: movzwl -24(%rsp,%r10,2), %r10d<br>
; SSE2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; SSE2-NEXT: movzwl -24(%rsp,%rdi,2), %edi<br>
-; SSE2-NEXT: movzwl -24(%rsp,%rsi,2), %esi<br>
-; SSE2-NEXT: movd %r10d, %xmm0<br>
-; SSE2-NEXT: movzwl -24(%rsp,%rdx,2), %edx<br>
-; SSE2-NEXT: movd %edx, %xmm1<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3]<br>
-; SSE2-NEXT: movzwl -24(%rsp,%rcx,2), %ecx<br>
-; SSE2-NEXT: movd %edi, %xmm0<br>
-; SSE2-NEXT: movzwl -24(%rsp,%r8,2), %edx<br>
-; SSE2-NEXT: movd %edx, %xmm2<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3]<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3]<br>
+; SSE2-NEXT: movd %eax, %xmm0<br>
+; SSE2-NEXT: movzwl -24(%rsp,%rcx,2), %eax<br>
; SSE2-NEXT: movd %eax, %xmm1<br>
-; SSE2-NEXT: movd %ecx, %xmm2<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3]<br>
-; SSE2-NEXT: movd %esi, %xmm1<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3]<br>
; SSE2-NEXT: movzwl -24(%rsp,%r9,2), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm0<br>
+; SSE2-NEXT: movzwl -24(%rsp,%rsi,2), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm2<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3]<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3]<br>
+; SSE2-NEXT: movzwl -24(%rsp,%r10,2), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm0<br>
+; SSE2-NEXT: movzwl -24(%rsp,%rdx,2), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm1<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3]<br>
+; SSE2-NEXT: movzwl -24(%rsp,%r8,2), %eax<br>
; SSE2-NEXT: movd %eax, %xmm3<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[<wbr>1],xmm1[2],xmm3[2],xmm1[3],<wbr>xmm3[3]<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1],xmm1[2],xmm2[2],xmm1[3],<wbr>xmm2[3]<br>
+; SSE2-NEXT: movzwl -24(%rsp,%rdi,2), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm0<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3]<br>
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3]<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3]<br>
; SSE2-NEXT: retq<br>
;<br>
; SSSE3-LABEL: var_shuffle_v8i16_v8i16_<wbr>xxxxxxxx_i16:<br>
@@ -299,29 +299,29 @@ define <8 x i16> @var_shuffle_v8i16_v8i1<br>
; SSSE3-NEXT: andl $7, %r10d<br>
; SSSE3-NEXT: movzwl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $7, %eax<br>
-; SSSE3-NEXT: movzwl -24(%rsp,%r10,2), %r10d<br>
; SSSE3-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; SSSE3-NEXT: movzwl -24(%rsp,%rdi,2), %edi<br>
-; SSSE3-NEXT: movzwl -24(%rsp,%rsi,2), %esi<br>
-; SSSE3-NEXT: movd %r10d, %xmm0<br>
-; SSSE3-NEXT: movzwl -24(%rsp,%rdx,2), %edx<br>
-; SSSE3-NEXT: movd %edx, %xmm1<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3]<br>
-; SSSE3-NEXT: movzwl -24(%rsp,%rcx,2), %ecx<br>
-; SSSE3-NEXT: movd %edi, %xmm0<br>
-; SSSE3-NEXT: movzwl -24(%rsp,%r8,2), %edx<br>
-; SSSE3-NEXT: movd %edx, %xmm2<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3]<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3]<br>
+; SSSE3-NEXT: movd %eax, %xmm0<br>
+; SSSE3-NEXT: movzwl -24(%rsp,%rcx,2), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm1<br>
-; SSSE3-NEXT: movd %ecx, %xmm2<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3]<br>
-; SSSE3-NEXT: movd %esi, %xmm1<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3]<br>
; SSSE3-NEXT: movzwl -24(%rsp,%r9,2), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm0<br>
+; SSSE3-NEXT: movzwl -24(%rsp,%rsi,2), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm2<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3]<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3]<br>
+; SSSE3-NEXT: movzwl -24(%rsp,%r10,2), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm0<br>
+; SSSE3-NEXT: movzwl -24(%rsp,%rdx,2), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm1<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1],xmm1[2],xmm0[2],xmm1[3],<wbr>xmm0[3]<br>
+; SSSE3-NEXT: movzwl -24(%rsp,%r8,2), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm3<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[<wbr>1],xmm1[2],xmm3[2],xmm1[3],<wbr>xmm3[3]<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[<wbr>1],xmm1[2],xmm2[2],xmm1[3],<wbr>xmm2[3]<br>
+; SSSE3-NEXT: movzwl -24(%rsp,%rdi,2), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm0<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3]<br>
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3]<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3]<br>
; SSSE3-NEXT: retq<br>
;<br>
; SSE41-LABEL: var_shuffle_v8i16_v8i16_<wbr>xxxxxxxx_i16:<br>
@@ -343,8 +343,6 @@ define <8 x i16> @var_shuffle_v8i16_v8i1<br>
; SSE41-NEXT: andl $7, %r10d<br>
; SSE41-NEXT: movzwl {{[0-9]+}}(%rsp), %eax<br>
; SSE41-NEXT: andl $7, %eax<br>
-; SSE41-NEXT: movzwl -24(%rsp,%r10,2), %r10d<br>
-; SSE41-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
; SSE41-NEXT: movzwl -24(%rsp,%rdi,2), %edi<br>
; SSE41-NEXT: movd %edi, %xmm0<br>
; SSE41-NEXT: pinsrw $1, -24(%rsp,%rsi,2), %xmm0<br>
@@ -352,8 +350,8 @@ define <8 x i16> @var_shuffle_v8i16_v8i1<br>
; SSE41-NEXT: pinsrw $3, -24(%rsp,%rcx,2), %xmm0<br>
; SSE41-NEXT: pinsrw $4, -24(%rsp,%r8,2), %xmm0<br>
; SSE41-NEXT: pinsrw $5, -24(%rsp,%r9,2), %xmm0<br>
-; SSE41-NEXT: pinsrw $6, %r10d, %xmm0<br>
-; SSE41-NEXT: pinsrw $7, %eax, %xmm0<br>
+; SSE41-NEXT: pinsrw $6, -24(%rsp,%r10,2), %xmm0<br>
+; SSE41-NEXT: pinsrw $7, -24(%rsp,%rax,2), %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: var_shuffle_v8i16_v8i16_<wbr>xxxxxxxx_i16:<br>
@@ -375,8 +373,6 @@ define <8 x i16> @var_shuffle_v8i16_v8i1<br>
; AVX-NEXT: andl $7, %r10d<br>
; AVX-NEXT: movzwl {{[0-9]+}}(%rsp), %eax<br>
; AVX-NEXT: andl $7, %eax<br>
-; AVX-NEXT: movzwl -24(%rsp,%r10,2), %r10d<br>
-; AVX-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
; AVX-NEXT: movzwl -24(%rsp,%rdi,2), %edi<br>
; AVX-NEXT: vmovd %edi, %xmm0<br>
; AVX-NEXT: vpinsrw $1, -24(%rsp,%rsi,2), %xmm0, %xmm0<br>
@@ -384,8 +380,8 @@ define <8 x i16> @var_shuffle_v8i16_v8i1<br>
; AVX-NEXT: vpinsrw $3, -24(%rsp,%rcx,2), %xmm0, %xmm0<br>
; AVX-NEXT: vpinsrw $4, -24(%rsp,%r8,2), %xmm0, %xmm0<br>
; AVX-NEXT: vpinsrw $5, -24(%rsp,%r9,2), %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrw $6, %r10d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0<br>
+; AVX-NEXT: vpinsrw $6, -24(%rsp,%r10,2), %xmm0, %xmm0<br>
+; AVX-NEXT: vpinsrw $7, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX-NEXT: retq<br>
%x0 = extractelement <8 x i16> %x, i16 %i0<br>
%x1 = extractelement <8 x i16> %x, i16 %i1<br>
@@ -416,80 +412,80 @@ define <16 x i8> @var_shuffle_v16i8_v16i<br>
; SSE2-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def><br>
; SSE2-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d<br>
-; SSE2-NEXT: andl $15, %r10d<br>
-; SSE2-NEXT: leaq -{{[0-9]+}}(%rsp), %r11<br>
-; SSE2-NEXT: movzbl (%r10,%r11), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm15<br>
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSE2-NEXT: leaq -{{[0-9]+}}(%rsp), %r10<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
; SSE2-NEXT: movd %eax, %xmm8<br>
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm15<br>
+; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
+; SSE2-NEXT: andl $15, %eax<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
; SSE2-NEXT: movd %eax, %xmm9<br>
-; SSE2-NEXT: andl $15, %edx<br>
-; SSE2-NEXT: movzbl (%rdx,%r11), %eax<br>
+; SSE2-NEXT: andl $15, %ecx<br>
+; SSE2-NEXT: movzbl (%rcx,%r10), %eax<br>
; SSE2-NEXT: movd %eax, %xmm3<br>
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
; SSE2-NEXT: movd %eax, %xmm10<br>
-; SSE2-NEXT: andl $15, %edi<br>
-; SSE2-NEXT: movzbl (%rdi,%r11), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm0<br>
+; SSE2-NEXT: andl $15, %r9d<br>
+; SSE2-NEXT: movzbl (%r9,%r10), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm7<br>
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
; SSE2-NEXT: movd %eax, %xmm11<br>
-; SSE2-NEXT: andl $15, %r8d<br>
-; SSE2-NEXT: movzbl (%r8,%r11), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm7<br>
+; SSE2-NEXT: andl $15, %esi<br>
+; SSE2-NEXT: movzbl (%rsi,%r10), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm6<br>
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%r11), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm2<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm12<br>
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%r11), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm12<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm5<br>
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
; SSE2-NEXT: movd %eax, %xmm13<br>
-; SSE2-NEXT: andl $15, %ecx<br>
-; SSE2-NEXT: movzbl (%rcx,%r11), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm6<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%r10), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm4<br>
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
; SSE2-NEXT: movd %eax, %xmm14<br>
-; SSE2-NEXT: andl $15, %esi<br>
-; SSE2-NEXT: movzbl (%rsi,%r11), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm5<br>
+; SSE2-NEXT: andl $15, %r8d<br>
+; SSE2-NEXT: movzbl (%r8,%r10), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm1<br>
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%r11), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm4<br>
-; SSE2-NEXT: andl $15, %r9d<br>
-; SSE2-NEXT: movzbl (%r9,%r11), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm1<br>
+; SSE2-NEXT: movzbl (%rax,%r10), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm2<br>
+; SSE2-NEXT: andl $15, %edi<br>
+; SSE2-NEXT: movzbl (%rdi,%r10), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm0<br>
; SSE2-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],<wbr>xmm8[1],xmm15[2],xmm8[2],<wbr>xmm15[3],xmm8[3],xmm15[4],<wbr>xmm8[4],xmm15[5],xmm8[5],<wbr>xmm15[6],xmm8[6],xmm15[7],<wbr>xmm8[7]<br>
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[<wbr>1],xmm3[2],xmm9[2],xmm3[3],<wbr>xmm9[3],xmm3[4],xmm9[4],xmm3[<wbr>5],xmm9[5],xmm3[6],xmm9[6],<wbr>xmm3[7],xmm9[7]<br>
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],<wbr>xmm15[1],xmm3[2],xmm15[2],<wbr>xmm3[3],xmm15[3],xmm3[4],<wbr>xmm15[4],xmm3[5],xmm15[5],<wbr>xmm3[6],xmm15[6],xmm3[7],<wbr>xmm15[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm10[0],xmm0[1],<wbr>xmm10[1],xmm0[2],xmm10[2],<wbr>xmm0[3],xmm10[3],xmm0[4],<wbr>xmm10[4],xmm0[5],xmm10[5],<wbr>xmm0[6],xmm10[6],xmm0[7],<wbr>xmm10[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],<wbr>xmm11[1],xmm7[2],xmm11[2],<wbr>xmm7[3],xmm11[3],xmm7[4],<wbr>xmm11[4],xmm7[5],xmm11[5],<wbr>xmm7[6],xmm11[6],xmm7[7],<wbr>xmm11[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[<wbr>1],xmm0[2],xmm7[2],xmm0[3],<wbr>xmm7[3],xmm0[4],xmm7[4],xmm0[<wbr>5],xmm7[5],xmm0[6],xmm7[6],<wbr>xmm0[7],xmm7[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3],xmm0[4],xmm3[4],xmm0[<wbr>5],xmm3[5],xmm0[6],xmm3[6],<wbr>xmm0[7],xmm3[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm12[0],xmm2[1],<wbr>xmm12[1],xmm2[2],xmm12[2],<wbr>xmm2[3],xmm12[3],xmm2[4],<wbr>xmm12[4],xmm2[5],xmm12[5],<wbr>xmm2[6],xmm12[6],xmm2[7],<wbr>xmm12[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],<wbr>xmm13[1],xmm6[2],xmm13[2],<wbr>xmm6[3],xmm13[3],xmm6[4],<wbr>xmm13[4],xmm6[5],xmm13[5],<wbr>xmm6[6],xmm13[6],xmm6[7],<wbr>xmm13[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[<wbr>1],xmm6[2],xmm2[2],xmm6[3],<wbr>xmm2[3],xmm6[4],xmm2[4],xmm6[<wbr>5],xmm2[5],xmm6[6],xmm2[6],<wbr>xmm6[7],xmm2[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm14[0],xmm5[1],<wbr>xmm14[1],xmm5[2],xmm14[2],<wbr>xmm5[3],xmm14[3],xmm5[4],<wbr>xmm14[4],xmm5[5],xmm14[5],<wbr>xmm5[6],xmm14[6],xmm5[7],<wbr>xmm14[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[<wbr>1],xmm1[2],xmm4[2],xmm1[3],<wbr>xmm4[3],xmm1[4],xmm4[4],xmm1[<wbr>5],xmm4[5],xmm1[6],xmm4[6],<wbr>xmm1[7],xmm4[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[<wbr>1],xmm5[2],xmm1[2],xmm5[3],<wbr>xmm1[3],xmm5[4],xmm1[4],xmm5[<wbr>5],xmm1[5],xmm5[6],xmm1[6],<wbr>xmm5[7],xmm1[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[<wbr>1],xmm5[2],xmm6[2],xmm5[3],<wbr>xmm6[3],xmm5[4],xmm6[4],xmm5[<wbr>5],xmm6[5],xmm5[6],xmm6[6],<wbr>xmm5[7],xmm6[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[<wbr>1],xmm0[2],xmm5[2],xmm0[3],<wbr>xmm5[3],xmm0[4],xmm5[4],xmm0[<wbr>5],xmm5[5],xmm0[6],xmm5[6],<wbr>xmm0[7],xmm5[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm10[0],xmm7[1],<wbr>xmm10[1],xmm7[2],xmm10[2],<wbr>xmm7[3],xmm10[3],xmm7[4],<wbr>xmm10[4],xmm7[5],xmm10[5],<wbr>xmm7[6],xmm10[6],xmm7[7],<wbr>xmm10[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm11[0],xmm6[1],<wbr>xmm11[1],xmm6[2],xmm11[2],<wbr>xmm6[3],xmm11[3],xmm6[4],<wbr>xmm11[4],xmm6[5],xmm11[5],<wbr>xmm6[6],xmm11[6],xmm6[7],<wbr>xmm11[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[<wbr>1],xmm6[2],xmm7[2],xmm6[3],<wbr>xmm7[3],xmm6[4],xmm7[4],xmm6[<wbr>5],xmm7[5],xmm6[6],xmm7[6],<wbr>xmm6[7],xmm7[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[<wbr>1],xmm6[2],xmm3[2],xmm6[3],<wbr>xmm3[3],xmm6[4],xmm3[4],xmm6[<wbr>5],xmm3[5],xmm6[6],xmm3[6],<wbr>xmm6[7],xmm3[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm12[0],xmm5[1],<wbr>xmm12[1],xmm5[2],xmm12[2],<wbr>xmm5[3],xmm12[3],xmm5[4],<wbr>xmm12[4],xmm5[5],xmm12[5],<wbr>xmm5[6],xmm12[6],xmm5[7],<wbr>xmm12[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm13[0],xmm4[1],<wbr>xmm13[1],xmm4[2],xmm13[2],<wbr>xmm4[3],xmm13[3],xmm4[4],<wbr>xmm13[4],xmm4[5],xmm13[5],<wbr>xmm4[6],xmm13[6],xmm4[7],<wbr>xmm13[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[<wbr>1],xmm4[2],xmm5[2],xmm4[3],<wbr>xmm5[3],xmm4[4],xmm5[4],xmm4[<wbr>5],xmm5[5],xmm4[6],xmm5[6],<wbr>xmm4[7],xmm5[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],<wbr>xmm14[1],xmm1[2],xmm14[2],<wbr>xmm1[3],xmm14[3],xmm1[4],<wbr>xmm14[4],xmm1[5],xmm14[5],<wbr>xmm1[6],xmm14[6],xmm1[7],<wbr>xmm14[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3],xmm0[4],xmm2[4],xmm0[<wbr>5],xmm2[5],xmm0[6],xmm2[6],<wbr>xmm0[7],xmm2[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3],xmm0[4],xmm1[4],xmm0[<wbr>5],xmm1[5],xmm0[6],xmm1[6],<wbr>xmm0[7],xmm1[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[<wbr>1],xmm0[2],xmm4[2],xmm0[3],<wbr>xmm4[3],xmm0[4],xmm4[4],xmm0[<wbr>5],xmm4[5],xmm0[6],xmm4[6],<wbr>xmm0[7],xmm4[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[<wbr>1],xmm0[2],xmm6[2],xmm0[3],<wbr>xmm6[3],xmm0[4],xmm6[4],xmm0[<wbr>5],xmm6[5],xmm0[6],xmm6[6],<wbr>xmm0[7],xmm6[7]<br>
; SSE2-NEXT: retq<br>
;<br>
; SSSE3-LABEL: var_shuffle_v16i8_v16i8_<wbr>xxxxxxxxxxxxxxxx_i8:<br>
@@ -501,89 +497,84 @@ define <16 x i8> @var_shuffle_v16i8_v16i<br>
; SSSE3-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def><br>
; SSSE3-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d<br>
-; SSSE3-NEXT: andl $15, %r10d<br>
-; SSSE3-NEXT: leaq -{{[0-9]+}}(%rsp), %r11<br>
-; SSSE3-NEXT: movzbl (%r10,%r11), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm15<br>
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSSE3-NEXT: leaq -{{[0-9]+}}(%rsp), %r10<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm8<br>
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm15<br>
+; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
+; SSSE3-NEXT: andl $15, %eax<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm9<br>
-; SSSE3-NEXT: andl $15, %edx<br>
-; SSSE3-NEXT: movzbl (%rdx,%r11), %eax<br>
+; SSSE3-NEXT: andl $15, %ecx<br>
+; SSSE3-NEXT: movzbl (%rcx,%r10), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm3<br>
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm10<br>
-; SSSE3-NEXT: andl $15, %edi<br>
-; SSSE3-NEXT: movzbl (%rdi,%r11), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm0<br>
+; SSSE3-NEXT: andl $15, %r9d<br>
+; SSSE3-NEXT: movzbl (%r9,%r10), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm7<br>
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm11<br>
-; SSSE3-NEXT: andl $15, %r8d<br>
-; SSSE3-NEXT: movzbl (%r8,%r11), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm7<br>
+; SSSE3-NEXT: andl $15, %esi<br>
+; SSSE3-NEXT: movzbl (%rsi,%r10), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm6<br>
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%r11), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm2<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm12<br>
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%r11), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm12<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm5<br>
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm13<br>
-; SSSE3-NEXT: andl $15, %ecx<br>
-; SSSE3-NEXT: movzbl (%rcx,%r11), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm6<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%r10), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm4<br>
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%r11), %eax<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm14<br>
-; SSSE3-NEXT: andl $15, %esi<br>
-; SSSE3-NEXT: movzbl (%rsi,%r11), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm5<br>
+; SSSE3-NEXT: andl $15, %r8d<br>
+; SSSE3-NEXT: movzbl (%r8,%r10), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm1<br>
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax<br>
; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%r11), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm4<br>
-; SSSE3-NEXT: andl $15, %r9d<br>
-; SSSE3-NEXT: movzbl (%r9,%r11), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm1<br>
+; SSSE3-NEXT: movzbl (%rax,%r10), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm2<br>
+; SSSE3-NEXT: andl $15, %edi<br>
+; SSSE3-NEXT: movzbl (%rdi,%r10), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm0<br>
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],<wbr>xmm8[1],xmm15[2],xmm8[2],<wbr>xmm15[3],xmm8[3],xmm15[4],<wbr>xmm8[4],xmm15[5],xmm8[5],<wbr>xmm15[6],xmm8[6],xmm15[7],<wbr>xmm8[7]<br>
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[<wbr>1],xmm3[2],xmm9[2],xmm3[3],<wbr>xmm9[3],xmm3[4],xmm9[4],xmm3[<wbr>5],xmm9[5],xmm3[6],xmm9[6],<wbr>xmm3[7],xmm9[7]<br>
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],<wbr>xmm15[1],xmm3[2],xmm15[2],<wbr>xmm3[3],xmm15[3],xmm3[4],<wbr>xmm15[4],xmm3[5],xmm15[5],<wbr>xmm3[6],xmm15[6],xmm3[7],<wbr>xmm15[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm10[0],xmm0[1],<wbr>xmm10[1],xmm0[2],xmm10[2],<wbr>xmm0[3],xmm10[3],xmm0[4],<wbr>xmm10[4],xmm0[5],xmm10[5],<wbr>xmm0[6],xmm10[6],xmm0[7],<wbr>xmm10[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],<wbr>xmm11[1],xmm7[2],xmm11[2],<wbr>xmm7[3],xmm11[3],xmm7[4],<wbr>xmm11[4],xmm7[5],xmm11[5],<wbr>xmm7[6],xmm11[6],xmm7[7],<wbr>xmm11[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[<wbr>1],xmm0[2],xmm7[2],xmm0[3],<wbr>xmm7[3],xmm0[4],xmm7[4],xmm0[<wbr>5],xmm7[5],xmm0[6],xmm7[6],<wbr>xmm0[7],xmm7[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3],xmm0[4],xmm3[4],xmm0[<wbr>5],xmm3[5],xmm0[6],xmm3[6],<wbr>xmm0[7],xmm3[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm12[0],xmm2[1],<wbr>xmm12[1],xmm2[2],xmm12[2],<wbr>xmm2[3],xmm12[3],xmm2[4],<wbr>xmm12[4],xmm2[5],xmm12[5],<wbr>xmm2[6],xmm12[6],xmm2[7],<wbr>xmm12[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],<wbr>xmm13[1],xmm6[2],xmm13[2],<wbr>xmm6[3],xmm13[3],xmm6[4],<wbr>xmm13[4],xmm6[5],xmm13[5],<wbr>xmm6[6],xmm13[6],xmm6[7],<wbr>xmm13[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[<wbr>1],xmm6[2],xmm2[2],xmm6[3],<wbr>xmm2[3],xmm6[4],xmm2[4],xmm6[<wbr>5],xmm2[5],xmm6[6],xmm2[6],<wbr>xmm6[7],xmm2[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm14[0],xmm5[1],<wbr>xmm14[1],xmm5[2],xmm14[2],<wbr>xmm5[3],xmm14[3],xmm5[4],<wbr>xmm14[4],xmm5[5],xmm14[5],<wbr>xmm5[6],xmm14[6],xmm5[7],<wbr>xmm14[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[<wbr>1],xmm1[2],xmm4[2],xmm1[3],<wbr>xmm4[3],xmm1[4],xmm4[4],xmm1[<wbr>5],xmm4[5],xmm1[6],xmm4[6],<wbr>xmm1[7],xmm4[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[<wbr>1],xmm5[2],xmm1[2],xmm5[3],<wbr>xmm1[3],xmm5[4],xmm1[4],xmm5[<wbr>5],xmm1[5],xmm5[6],xmm1[6],<wbr>xmm5[7],xmm1[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[<wbr>1],xmm5[2],xmm6[2],xmm5[3],<wbr>xmm6[3],xmm5[4],xmm6[4],xmm5[<wbr>5],xmm6[5],xmm5[6],xmm6[6],<wbr>xmm5[7],xmm6[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[<wbr>1],xmm0[2],xmm5[2],xmm0[3],<wbr>xmm5[3],xmm0[4],xmm5[4],xmm0[<wbr>5],xmm5[5],xmm0[6],xmm5[6],<wbr>xmm0[7],xmm5[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm10[0],xmm7[1],<wbr>xmm10[1],xmm7[2],xmm10[2],<wbr>xmm7[3],xmm10[3],xmm7[4],<wbr>xmm10[4],xmm7[5],xmm10[5],<wbr>xmm7[6],xmm10[6],xmm7[7],<wbr>xmm10[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm11[0],xmm6[1],<wbr>xmm11[1],xmm6[2],xmm11[2],<wbr>xmm6[3],xmm11[3],xmm6[4],<wbr>xmm11[4],xmm6[5],xmm11[5],<wbr>xmm6[6],xmm11[6],xmm6[7],<wbr>xmm11[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[<wbr>1],xmm6[2],xmm7[2],xmm6[3],<wbr>xmm7[3],xmm6[4],xmm7[4],xmm6[<wbr>5],xmm7[5],xmm6[6],xmm7[6],<wbr>xmm6[7],xmm7[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[<wbr>1],xmm6[2],xmm3[2],xmm6[3],<wbr>xmm3[3],xmm6[4],xmm3[4],xmm6[<wbr>5],xmm3[5],xmm6[6],xmm3[6],<wbr>xmm6[7],xmm3[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm12[0],xmm5[1],<wbr>xmm12[1],xmm5[2],xmm12[2],<wbr>xmm5[3],xmm12[3],xmm5[4],<wbr>xmm12[4],xmm5[5],xmm12[5],<wbr>xmm5[6],xmm12[6],xmm5[7],<wbr>xmm12[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm13[0],xmm4[1],<wbr>xmm13[1],xmm4[2],xmm13[2],<wbr>xmm4[3],xmm13[3],xmm4[4],<wbr>xmm13[4],xmm4[5],xmm13[5],<wbr>xmm4[6],xmm13[6],xmm4[7],<wbr>xmm13[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[<wbr>1],xmm4[2],xmm5[2],xmm4[3],<wbr>xmm5[3],xmm4[4],xmm5[4],xmm4[<wbr>5],xmm5[5],xmm4[6],xmm5[6],<wbr>xmm4[7],xmm5[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],<wbr>xmm14[1],xmm1[2],xmm14[2],<wbr>xmm1[3],xmm14[3],xmm1[4],<wbr>xmm14[4],xmm1[5],xmm14[5],<wbr>xmm1[6],xmm14[6],xmm1[7],<wbr>xmm14[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3],xmm0[4],xmm2[4],xmm0[<wbr>5],xmm2[5],xmm0[6],xmm2[6],<wbr>xmm0[7],xmm2[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3],xmm0[4],xmm1[4],xmm0[<wbr>5],xmm1[5],xmm0[6],xmm1[6],<wbr>xmm0[7],xmm1[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[<wbr>1],xmm0[2],xmm4[2],xmm0[3],<wbr>xmm4[3],xmm0[4],xmm4[4],xmm0[<wbr>5],xmm4[5],xmm0[6],xmm4[6],<wbr>xmm0[7],xmm4[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[<wbr>1],xmm0[2],xmm6[2],xmm0[3],<wbr>xmm6[3],xmm0[4],xmm6[4],xmm0[<wbr>5],xmm6[5],xmm0[6],xmm6[6],<wbr>xmm0[7],xmm6[7]<br>
; SSSE3-NEXT: retq<br>
;<br>
; SSE41-LABEL: var_shuffle_v16i8_v16i8_<wbr>xxxxxxxxxxxxxxxx_i8:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: pushq %rbp<br>
-; SSE41-NEXT: pushq %r15<br>
-; SSE41-NEXT: pushq %r14<br>
-; SSE41-NEXT: pushq %r12<br>
-; SSE41-NEXT: pushq %rbx<br>
; SSE41-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def><br>
; SSE41-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def><br>
; SSE41-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def><br>
@@ -591,74 +582,54 @@ define <16 x i8> @var_shuffle_v16i8_v16i<br>
; SSE41-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def><br>
; SSE41-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; SSE41-NEXT: andl $15, %edi<br>
-; SSE41-NEXT: andl $15, %esi<br>
-; SSE41-NEXT: andl $15, %edx<br>
-; SSE41-NEXT: andl $15, %ecx<br>
-; SSE41-NEXT: andl $15, %r8d<br>
; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSE41-NEXT: andl $15, %r9d<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d<br>
-; SSE41-NEXT: andl $15, %r10d<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d<br>
-; SSE41-NEXT: andl $15, %r11d<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %r14d<br>
-; SSE41-NEXT: andl $15, %r14d<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %r15d<br>
-; SSE41-NEXT: andl $15, %r15d<br>
; SSE41-NEXT: leaq -{{[0-9]+}}(%rsp), %rax<br>
; SSE41-NEXT: movzbl (%rdi,%rax), %edi<br>
; SSE41-NEXT: movd %edi, %xmm0<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %r12d<br>
-; SSE41-NEXT: andl $15, %r12d<br>
-; SSE41-NEXT: pinsrb $1, (%rsi,%rax), %xmm0<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %esi<br>
; SSE41-NEXT: andl $15, %esi<br>
-; SSE41-NEXT: pinsrb $2, (%rdx,%rax), %xmm0<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %edx<br>
+; SSE41-NEXT: pinsrb $1, (%rsi,%rax), %xmm0<br>
; SSE41-NEXT: andl $15, %edx<br>
-; SSE41-NEXT: pinsrb $3, (%rcx,%rax), %xmm0<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: pinsrb $2, (%rdx,%rax), %xmm0<br>
; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $3, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: andl $15, %r8d<br>
; SSE41-NEXT: pinsrb $4, (%r8,%rax), %xmm0<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ebx<br>
-; SSE41-NEXT: andl $15, %ebx<br>
+; SSE41-NEXT: andl $15, %r9d<br>
; SSE41-NEXT: pinsrb $5, (%r9,%rax), %xmm0<br>
-; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %edi<br>
-; SSE41-NEXT: andl $15, %edi<br>
-; SSE41-NEXT: movzbl (%r10,%rax), %r8d<br>
-; SSE41-NEXT: movzbl (%r11,%rax), %r9d<br>
-; SSE41-NEXT: movzbl (%r14,%rax), %r10d<br>
-; SSE41-NEXT: movzbl (%r15,%rax), %r11d<br>
-; SSE41-NEXT: movzbl (%r12,%rax), %ebp<br>
-; SSE41-NEXT: movzbl (%rsi,%rax), %esi<br>
-; SSE41-NEXT: movzbl (%rdx,%rax), %edx<br>
-; SSE41-NEXT: movzbl (%rcx,%rax), %ecx<br>
-; SSE41-NEXT: movzbl (%rbx,%rax), %ebx<br>
-; SSE41-NEXT: movzbl (%rdi,%rax), %eax<br>
-; SSE41-NEXT: pinsrb $6, %r8d, %xmm0<br>
-; SSE41-NEXT: pinsrb $7, %r9d, %xmm0<br>
-; SSE41-NEXT: pinsrb $8, %r10d, %xmm0<br>
-; SSE41-NEXT: pinsrb $9, %r11d, %xmm0<br>
-; SSE41-NEXT: pinsrb $10, %ebp, %xmm0<br>
-; SSE41-NEXT: pinsrb $11, %esi, %xmm0<br>
-; SSE41-NEXT: pinsrb $12, %edx, %xmm0<br>
-; SSE41-NEXT: pinsrb $13, %ecx, %xmm0<br>
-; SSE41-NEXT: pinsrb $14, %ebx, %xmm0<br>
-; SSE41-NEXT: pinsrb $15, %eax, %xmm0<br>
-; SSE41-NEXT: popq %rbx<br>
-; SSE41-NEXT: popq %r12<br>
-; SSE41-NEXT: popq %r14<br>
-; SSE41-NEXT: popq %r15<br>
-; SSE41-NEXT: popq %rbp<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $6, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $7, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $8, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $9, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $10, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $11, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $12, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $13, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $14, (%rcx,%rax), %xmm0<br>
+; SSE41-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; SSE41-NEXT: andl $15, %ecx<br>
+; SSE41-NEXT: pinsrb $15, (%rcx,%rax), %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: var_shuffle_v16i8_v16i8_<wbr>xxxxxxxxxxxxxxxx_i8:<br>
; AVX: # BB#0:<br>
-; AVX-NEXT: pushq %rbp<br>
-; AVX-NEXT: pushq %r15<br>
-; AVX-NEXT: pushq %r14<br>
-; AVX-NEXT: pushq %r12<br>
-; AVX-NEXT: pushq %rbx<br>
; AVX-NEXT: # kill: %R9D<def> %R9D<kill> %R9<def><br>
; AVX-NEXT: # kill: %R8D<def> %R8D<kill> %R8<def><br>
; AVX-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<def><br>
@@ -666,65 +637,50 @@ define <16 x i8> @var_shuffle_v16i8_v16i<br>
; AVX-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def><br>
; AVX-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def><br>
; AVX-NEXT: andl $15, %edi<br>
-; AVX-NEXT: andl $15, %esi<br>
-; AVX-NEXT: andl $15, %edx<br>
-; AVX-NEXT: andl $15, %ecx<br>
-; AVX-NEXT: andl $15, %r8d<br>
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)<br>
-; AVX-NEXT: andl $15, %r9d<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %r10d<br>
-; AVX-NEXT: andl $15, %r10d<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %r11d<br>
-; AVX-NEXT: andl $15, %r11d<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %r14d<br>
-; AVX-NEXT: andl $15, %r14d<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %r15d<br>
-; AVX-NEXT: andl $15, %r15d<br>
; AVX-NEXT: leaq -{{[0-9]+}}(%rsp), %rax<br>
; AVX-NEXT: movzbl (%rdi,%rax), %edi<br>
; AVX-NEXT: vmovd %edi, %xmm0<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %r12d<br>
-; AVX-NEXT: andl $15, %r12d<br>
-; AVX-NEXT: vpinsrb $1, (%rsi,%rax), %xmm0, %xmm0<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %esi<br>
; AVX-NEXT: andl $15, %esi<br>
-; AVX-NEXT: vpinsrb $2, (%rdx,%rax), %xmm0, %xmm0<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %edx<br>
+; AVX-NEXT: vpinsrb $1, (%rsi,%rax), %xmm0, %xmm0<br>
; AVX-NEXT: andl $15, %edx<br>
-; AVX-NEXT: vpinsrb $3, (%rcx,%rax), %xmm0, %xmm0<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: vpinsrb $2, (%rdx,%rax), %xmm0, %xmm0<br>
; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $3, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: andl $15, %r8d<br>
; AVX-NEXT: vpinsrb $4, (%r8,%rax), %xmm0, %xmm0<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ebx<br>
-; AVX-NEXT: andl $15, %ebx<br>
+; AVX-NEXT: andl $15, %r9d<br>
; AVX-NEXT: vpinsrb $5, (%r9,%rax), %xmm0, %xmm0<br>
-; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %edi<br>
-; AVX-NEXT: andl $15, %edi<br>
-; AVX-NEXT: movzbl (%r10,%rax), %r8d<br>
-; AVX-NEXT: movzbl (%r11,%rax), %r9d<br>
-; AVX-NEXT: movzbl (%r14,%rax), %r10d<br>
-; AVX-NEXT: movzbl (%r15,%rax), %r11d<br>
-; AVX-NEXT: movzbl (%r12,%rax), %ebp<br>
-; AVX-NEXT: movzbl (%rsi,%rax), %esi<br>
-; AVX-NEXT: movzbl (%rdx,%rax), %edx<br>
-; AVX-NEXT: movzbl (%rcx,%rax), %ecx<br>
-; AVX-NEXT: movzbl (%rbx,%rax), %ebx<br>
-; AVX-NEXT: movzbl (%rdi,%rax), %eax<br>
-; AVX-NEXT: vpinsrb $6, %r8d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $7, %r9d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $9, %r11d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $10, %ebp, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $11, %esi, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $12, %edx, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $14, %ebx, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0<br>
-; AVX-NEXT: popq %rbx<br>
-; AVX-NEXT: popq %r12<br>
-; AVX-NEXT: popq %r14<br>
-; AVX-NEXT: popq %r15<br>
-; AVX-NEXT: popq %rbp<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $6, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $7, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $8, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $9, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $10, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $11, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $12, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $13, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $14, (%rcx,%rax), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl {{[0-9]+}}(%rsp), %ecx<br>
+; AVX-NEXT: andl $15, %ecx<br>
+; AVX-NEXT: vpinsrb $15, (%rcx,%rax), %xmm0, %xmm0<br>
; AVX-NEXT: retq<br>
%x0 = extractelement <16 x i8> %x, i8 %i0<br>
%x1 = extractelement <16 x i8> %x, i8 %i1<br>
@@ -779,11 +735,11 @@ define <4 x i32> @mem_shuffle_v4i32_v4i3<br>
; SSE2-NEXT: andl $3, %esi<br>
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
+; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1]<br>
; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
+; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
-; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1]<br>
-; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
; SSE2-NEXT: retq<br>
;<br>
; SSSE3-LABEL: mem_shuffle_v4i32_v4i32_xxxx_<wbr>i32:<br>
@@ -799,11 +755,11 @@ define <4 x i32> @mem_shuffle_v4i32_v4i3<br>
; SSSE3-NEXT: andl $3, %esi<br>
; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
+; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[<wbr>1]<br>
; SSSE3-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
+; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
-; SSSE3-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1]<br>
-; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1]<br>
+; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1]<br>
; SSSE3-NEXT: retq<br>
;<br>
; SSE41-LABEL: mem_shuffle_v4i32_v4i32_xxxx_<wbr>i32:<br>
@@ -862,341 +818,281 @@ define <16 x i8> @mem_shuffle_v16i8_v16i<br>
; SSE2-LABEL: mem_shuffle_v16i8_v16i8_<wbr>xxxxxxxxxxxxxxxx_i8:<br>
; SSE2: # BB#0:<br>
; SSE2-NEXT: movzbl (%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
+; SSE2-NEXT: movzbl 15(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
; SSE2-NEXT: leaq -{{[0-9]+}}(%rsp), %rcx<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm0<br>
-; SSE2-NEXT: movzbl 8(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm8<br>
-; SSE2-NEXT: movzbl 12(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm9<br>
-; SSE2-NEXT: movzbl 4(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm3<br>
-; SSE2-NEXT: movzbl 14(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm10<br>
-; SSE2-NEXT: movzbl 6(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm5<br>
-; SSE2-NEXT: movzbl 10(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm11<br>
-; SSE2-NEXT: movzbl 2(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm7<br>
-; SSE2-NEXT: movzbl 15(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm12<br>
-; SSE2-NEXT: movzbl 7(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm2<br>
-; SSE2-NEXT: movzbl 11(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm13<br>
-; SSE2-NEXT: movzbl 3(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm6<br>
-; SSE2-NEXT: movzbl 13(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm14<br>
-; SSE2-NEXT: movzbl 5(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm4<br>
-; SSE2-NEXT: movzbl 9(%rdi), %eax<br>
-; SSE2-NEXT: andl $15, %eax<br>
-; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm15<br>
-; SSE2-NEXT: movzbl 1(%rdi), %eax<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm8<br>
+; SSE2-NEXT: movzbl 7(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm15<br>
+; SSE2-NEXT: movzbl 11(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm9<br>
+; SSE2-NEXT: movzbl 3(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm3<br>
+; SSE2-NEXT: movzbl 13(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm10<br>
+; SSE2-NEXT: movzbl 5(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm7<br>
+; SSE2-NEXT: movzbl 9(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm11<br>
+; SSE2-NEXT: movzbl 1(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm6<br>
+; SSE2-NEXT: movzbl 14(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm12<br>
+; SSE2-NEXT: movzbl 6(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm5<br>
+; SSE2-NEXT: movzbl 10(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm13<br>
+; SSE2-NEXT: movzbl 2(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm4<br>
+; SSE2-NEXT: movzbl 12(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm14<br>
+; SSE2-NEXT: movzbl 4(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm1<br>
+; SSE2-NEXT: movzbl 8(%rdi), %edx<br>
+; SSE2-NEXT: andl $15, %edx<br>
+; SSE2-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSE2-NEXT: movd %edx, %xmm2<br>
; SSE2-NEXT: andl $15, %eax<br>
; SSE2-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSE2-NEXT: movd %eax, %xmm1<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm8[0],xmm0[1],xmm8[<wbr>1],xmm0[2],xmm8[2],xmm0[3],<wbr>xmm8[3],xmm0[4],xmm8[4],xmm0[<wbr>5],xmm8[5],xmm0[6],xmm8[6],<wbr>xmm0[7],xmm8[7]<br>
+; SSE2-NEXT: movd %eax, %xmm0<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],<wbr>xmm8[1],xmm15[2],xmm8[2],<wbr>xmm15[3],xmm8[3],xmm15[4],<wbr>xmm8[4],xmm15[5],xmm8[5],<wbr>xmm15[6],xmm8[6],xmm15[7],<wbr>xmm8[7]<br>
; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[<wbr>1],xmm3[2],xmm9[2],xmm3[3],<wbr>xmm9[3],xmm3[4],xmm9[4],xmm3[<wbr>5],xmm9[5],xmm3[6],xmm9[6],<wbr>xmm3[7],xmm9[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3],xmm0[4],xmm3[4],xmm0[<wbr>5],xmm3[5],xmm0[6],xmm3[6],<wbr>xmm0[7],xmm3[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm10[0],xmm5[1],<wbr>xmm10[1],xmm5[2],xmm10[2],<wbr>xmm5[3],xmm10[3],xmm5[4],<wbr>xmm10[4],xmm5[5],xmm10[5],<wbr>xmm5[6],xmm10[6],xmm5[7],<wbr>xmm10[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],<wbr>xmm11[1],xmm7[2],xmm11[2],<wbr>xmm7[3],xmm11[3],xmm7[4],<wbr>xmm11[4],xmm7[5],xmm11[5],<wbr>xmm7[6],xmm11[6],xmm7[7],<wbr>xmm11[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[<wbr>1],xmm7[2],xmm5[2],xmm7[3],<wbr>xmm5[3],xmm7[4],xmm5[4],xmm7[<wbr>5],xmm5[5],xmm7[6],xmm5[6],<wbr>xmm7[7],xmm5[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[<wbr>1],xmm0[2],xmm7[2],xmm0[3],<wbr>xmm7[3],xmm0[4],xmm7[4],xmm0[<wbr>5],xmm7[5],xmm0[6],xmm7[6],<wbr>xmm0[7],xmm7[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm12[0],xmm2[1],<wbr>xmm12[1],xmm2[2],xmm12[2],<wbr>xmm2[3],xmm12[3],xmm2[4],<wbr>xmm12[4],xmm2[5],xmm12[5],<wbr>xmm2[6],xmm12[6],xmm2[7],<wbr>xmm12[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],<wbr>xmm13[1],xmm6[2],xmm13[2],<wbr>xmm6[3],xmm13[3],xmm6[4],<wbr>xmm13[4],xmm6[5],xmm13[5],<wbr>xmm6[6],xmm13[6],xmm6[7],<wbr>xmm13[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[<wbr>1],xmm6[2],xmm2[2],xmm6[3],<wbr>xmm2[3],xmm6[4],xmm2[4],xmm6[<wbr>5],xmm2[5],xmm6[6],xmm2[6],<wbr>xmm6[7],xmm2[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm14[0],xmm4[1],<wbr>xmm14[1],xmm4[2],xmm14[2],<wbr>xmm4[3],xmm14[3],xmm4[4],<wbr>xmm14[4],xmm4[5],xmm14[5],<wbr>xmm4[6],xmm14[6],xmm4[7],<wbr>xmm14[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm15[0],xmm1[1],<wbr>xmm15[1],xmm1[2],xmm15[2],<wbr>xmm1[3],xmm15[3],xmm1[4],<wbr>xmm15[4],xmm1[5],xmm15[5],<wbr>xmm1[6],xmm15[6],xmm1[7],<wbr>xmm15[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[<wbr>1],xmm1[2],xmm4[2],xmm1[3],<wbr>xmm4[3],xmm1[4],xmm4[4],xmm1[<wbr>5],xmm4[5],xmm1[6],xmm4[6],<wbr>xmm1[7],xmm4[7]<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[<wbr>1],xmm1[2],xmm6[2],xmm1[3],<wbr>xmm6[3],xmm1[4],xmm6[4],xmm1[<wbr>5],xmm6[5],xmm1[6],xmm6[6],<wbr>xmm1[7],xmm6[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],<wbr>xmm15[1],xmm3[2],xmm15[2],<wbr>xmm3[3],xmm15[3],xmm3[4],<wbr>xmm15[4],xmm3[5],xmm15[5],<wbr>xmm3[6],xmm15[6],xmm3[7],<wbr>xmm15[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm10[0],xmm7[1],<wbr>xmm10[1],xmm7[2],xmm10[2],<wbr>xmm7[3],xmm10[3],xmm7[4],<wbr>xmm10[4],xmm7[5],xmm10[5],<wbr>xmm7[6],xmm10[6],xmm7[7],<wbr>xmm10[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm11[0],xmm6[1],<wbr>xmm11[1],xmm6[2],xmm11[2],<wbr>xmm6[3],xmm11[3],xmm6[4],<wbr>xmm11[4],xmm6[5],xmm11[5],<wbr>xmm6[6],xmm11[6],xmm6[7],<wbr>xmm11[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[<wbr>1],xmm6[2],xmm7[2],xmm6[3],<wbr>xmm7[3],xmm6[4],xmm7[4],xmm6[<wbr>5],xmm7[5],xmm6[6],xmm7[6],<wbr>xmm6[7],xmm7[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[<wbr>1],xmm6[2],xmm3[2],xmm6[3],<wbr>xmm3[3],xmm6[4],xmm3[4],xmm6[<wbr>5],xmm3[5],xmm6[6],xmm3[6],<wbr>xmm6[7],xmm3[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm12[0],xmm5[1],<wbr>xmm12[1],xmm5[2],xmm12[2],<wbr>xmm5[3],xmm12[3],xmm5[4],<wbr>xmm12[4],xmm5[5],xmm12[5],<wbr>xmm5[6],xmm12[6],xmm5[7],<wbr>xmm12[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm13[0],xmm4[1],<wbr>xmm13[1],xmm4[2],xmm13[2],<wbr>xmm4[3],xmm13[3],xmm4[4],<wbr>xmm13[4],xmm4[5],xmm13[5],<wbr>xmm4[6],xmm13[6],xmm4[7],<wbr>xmm13[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[<wbr>1],xmm4[2],xmm5[2],xmm4[3],<wbr>xmm5[3],xmm4[4],xmm5[4],xmm4[<wbr>5],xmm5[5],xmm4[6],xmm5[6],<wbr>xmm4[7],xmm5[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],<wbr>xmm14[1],xmm1[2],xmm14[2],<wbr>xmm1[3],xmm14[3],xmm1[4],<wbr>xmm14[4],xmm1[5],xmm14[5],<wbr>xmm1[6],xmm14[6],xmm1[7],<wbr>xmm14[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3],xmm0[4],xmm2[4],xmm0[<wbr>5],xmm2[5],xmm0[6],xmm2[6],<wbr>xmm0[7],xmm2[7]<br>
; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3],xmm0[4],xmm1[4],xmm0[<wbr>5],xmm1[5],xmm0[6],xmm1[6],<wbr>xmm0[7],xmm1[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[<wbr>1],xmm0[2],xmm4[2],xmm0[3],<wbr>xmm4[3],xmm0[4],xmm4[4],xmm0[<wbr>5],xmm4[5],xmm0[6],xmm4[6],<wbr>xmm0[7],xmm4[7]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[<wbr>1],xmm0[2],xmm6[2],xmm0[3],<wbr>xmm6[3],xmm0[4],xmm6[4],xmm0[<wbr>5],xmm6[5],xmm0[6],xmm6[6],<wbr>xmm0[7],xmm6[7]<br>
; SSE2-NEXT: retq<br>
;<br>
; SSSE3-LABEL: mem_shuffle_v16i8_v16i8_<wbr>xxxxxxxxxxxxxxxx_i8:<br>
; SSSE3: # BB#0:<br>
; SSSE3-NEXT: movzbl (%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
+; SSSE3-NEXT: movzbl 15(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
; SSSE3-NEXT: leaq -{{[0-9]+}}(%rsp), %rcx<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm0<br>
-; SSSE3-NEXT: movzbl 8(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm8<br>
-; SSSE3-NEXT: movzbl 12(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm9<br>
-; SSSE3-NEXT: movzbl 4(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm3<br>
-; SSSE3-NEXT: movzbl 14(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm10<br>
-; SSSE3-NEXT: movzbl 6(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm5<br>
-; SSSE3-NEXT: movzbl 10(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm11<br>
-; SSSE3-NEXT: movzbl 2(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm7<br>
-; SSSE3-NEXT: movzbl 15(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm12<br>
-; SSSE3-NEXT: movzbl 7(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm2<br>
-; SSSE3-NEXT: movzbl 11(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm13<br>
-; SSSE3-NEXT: movzbl 3(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm6<br>
-; SSSE3-NEXT: movzbl 13(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm14<br>
-; SSSE3-NEXT: movzbl 5(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm4<br>
-; SSSE3-NEXT: movzbl 9(%rdi), %eax<br>
-; SSSE3-NEXT: andl $15, %eax<br>
-; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm15<br>
-; SSSE3-NEXT: movzbl 1(%rdi), %eax<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm8<br>
+; SSSE3-NEXT: movzbl 7(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm15<br>
+; SSSE3-NEXT: movzbl 11(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm9<br>
+; SSSE3-NEXT: movzbl 3(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm3<br>
+; SSSE3-NEXT: movzbl 13(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm10<br>
+; SSSE3-NEXT: movzbl 5(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm7<br>
+; SSSE3-NEXT: movzbl 9(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm11<br>
+; SSSE3-NEXT: movzbl 1(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm6<br>
+; SSSE3-NEXT: movzbl 14(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm12<br>
+; SSSE3-NEXT: movzbl 6(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm5<br>
+; SSSE3-NEXT: movzbl 10(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm13<br>
+; SSSE3-NEXT: movzbl 2(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm4<br>
+; SSSE3-NEXT: movzbl 12(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm14<br>
+; SSSE3-NEXT: movzbl 4(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm1<br>
+; SSSE3-NEXT: movzbl 8(%rdi), %edx<br>
+; SSSE3-NEXT: andl $15, %edx<br>
+; SSSE3-NEXT: movzbl (%rdx,%rcx), %edx<br>
+; SSSE3-NEXT: movd %edx, %xmm2<br>
; SSSE3-NEXT: andl $15, %eax<br>
; SSSE3-NEXT: movzbl (%rax,%rcx), %eax<br>
-; SSSE3-NEXT: movd %eax, %xmm1<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm8[0],xmm0[1],xmm8[<wbr>1],xmm0[2],xmm8[2],xmm0[3],<wbr>xmm8[3],xmm0[4],xmm8[4],xmm0[<wbr>5],xmm8[5],xmm0[6],xmm8[6],<wbr>xmm0[7],xmm8[7]<br>
+; SSSE3-NEXT: movd %eax, %xmm0<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],<wbr>xmm8[1],xmm15[2],xmm8[2],<wbr>xmm15[3],xmm8[3],xmm15[4],<wbr>xmm8[4],xmm15[5],xmm8[5],<wbr>xmm15[6],xmm8[6],xmm15[7],<wbr>xmm8[7]<br>
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[<wbr>1],xmm3[2],xmm9[2],xmm3[3],<wbr>xmm9[3],xmm3[4],xmm9[4],xmm3[<wbr>5],xmm9[5],xmm3[6],xmm9[6],<wbr>xmm3[7],xmm9[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3],xmm0[4],xmm3[4],xmm0[<wbr>5],xmm3[5],xmm0[6],xmm3[6],<wbr>xmm0[7],xmm3[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm10[0],xmm5[1],<wbr>xmm10[1],xmm5[2],xmm10[2],<wbr>xmm5[3],xmm10[3],xmm5[4],<wbr>xmm10[4],xmm5[5],xmm10[5],<wbr>xmm5[6],xmm10[6],xmm5[7],<wbr>xmm10[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],<wbr>xmm11[1],xmm7[2],xmm11[2],<wbr>xmm7[3],xmm11[3],xmm7[4],<wbr>xmm11[4],xmm7[5],xmm11[5],<wbr>xmm7[6],xmm11[6],xmm7[7],<wbr>xmm11[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[<wbr>1],xmm7[2],xmm5[2],xmm7[3],<wbr>xmm5[3],xmm7[4],xmm5[4],xmm7[<wbr>5],xmm5[5],xmm7[6],xmm5[6],<wbr>xmm7[7],xmm5[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[<wbr>1],xmm0[2],xmm7[2],xmm0[3],<wbr>xmm7[3],xmm0[4],xmm7[4],xmm0[<wbr>5],xmm7[5],xmm0[6],xmm7[6],<wbr>xmm0[7],xmm7[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm12[0],xmm2[1],<wbr>xmm12[1],xmm2[2],xmm12[2],<wbr>xmm2[3],xmm12[3],xmm2[4],<wbr>xmm12[4],xmm2[5],xmm12[5],<wbr>xmm2[6],xmm12[6],xmm2[7],<wbr>xmm12[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],<wbr>xmm13[1],xmm6[2],xmm13[2],<wbr>xmm6[3],xmm13[3],xmm6[4],<wbr>xmm13[4],xmm6[5],xmm13[5],<wbr>xmm6[6],xmm13[6],xmm6[7],<wbr>xmm13[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[<wbr>1],xmm6[2],xmm2[2],xmm6[3],<wbr>xmm2[3],xmm6[4],xmm2[4],xmm6[<wbr>5],xmm2[5],xmm6[6],xmm2[6],<wbr>xmm6[7],xmm2[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm14[0],xmm4[1],<wbr>xmm14[1],xmm4[2],xmm14[2],<wbr>xmm4[3],xmm14[3],xmm4[4],<wbr>xmm14[4],xmm4[5],xmm14[5],<wbr>xmm4[6],xmm14[6],xmm4[7],<wbr>xmm14[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm15[0],xmm1[1],<wbr>xmm15[1],xmm1[2],xmm15[2],<wbr>xmm1[3],xmm15[3],xmm1[4],<wbr>xmm15[4],xmm1[5],xmm15[5],<wbr>xmm1[6],xmm15[6],xmm1[7],<wbr>xmm15[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[<wbr>1],xmm1[2],xmm4[2],xmm1[3],<wbr>xmm4[3],xmm1[4],xmm4[4],xmm1[<wbr>5],xmm4[5],xmm1[6],xmm4[6],<wbr>xmm1[7],xmm4[7]<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[<wbr>1],xmm1[2],xmm6[2],xmm1[3],<wbr>xmm6[3],xmm1[4],xmm6[4],xmm1[<wbr>5],xmm6[5],xmm1[6],xmm6[6],<wbr>xmm1[7],xmm6[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],<wbr>xmm15[1],xmm3[2],xmm15[2],<wbr>xmm3[3],xmm15[3],xmm3[4],<wbr>xmm15[4],xmm3[5],xmm15[5],<wbr>xmm3[6],xmm15[6],xmm3[7],<wbr>xmm15[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm10[0],xmm7[1],<wbr>xmm10[1],xmm7[2],xmm10[2],<wbr>xmm7[3],xmm10[3],xmm7[4],<wbr>xmm10[4],xmm7[5],xmm10[5],<wbr>xmm7[6],xmm10[6],xmm7[7],<wbr>xmm10[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm11[0],xmm6[1],<wbr>xmm11[1],xmm6[2],xmm11[2],<wbr>xmm6[3],xmm11[3],xmm6[4],<wbr>xmm11[4],xmm6[5],xmm11[5],<wbr>xmm6[6],xmm11[6],xmm6[7],<wbr>xmm11[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm7[0],xmm6[1],xmm7[<wbr>1],xmm6[2],xmm7[2],xmm6[3],<wbr>xmm7[3],xmm6[4],xmm7[4],xmm6[<wbr>5],xmm7[5],xmm6[6],xmm7[6],<wbr>xmm6[7],xmm7[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm3[0],xmm6[1],xmm3[<wbr>1],xmm6[2],xmm3[2],xmm6[3],<wbr>xmm3[3],xmm6[4],xmm3[4],xmm6[<wbr>5],xmm3[5],xmm6[6],xmm3[6],<wbr>xmm6[7],xmm3[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm12[0],xmm5[1],<wbr>xmm12[1],xmm5[2],xmm12[2],<wbr>xmm5[3],xmm12[3],xmm5[4],<wbr>xmm12[4],xmm5[5],xmm12[5],<wbr>xmm5[6],xmm12[6],xmm5[7],<wbr>xmm12[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm13[0],xmm4[1],<wbr>xmm13[1],xmm4[2],xmm13[2],<wbr>xmm4[3],xmm13[3],xmm4[4],<wbr>xmm13[4],xmm4[5],xmm13[5],<wbr>xmm4[6],xmm13[6],xmm4[7],<wbr>xmm13[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[<wbr>1],xmm4[2],xmm5[2],xmm4[3],<wbr>xmm5[3],xmm4[4],xmm5[4],xmm4[<wbr>5],xmm5[5],xmm4[6],xmm5[6],<wbr>xmm4[7],xmm5[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm14[0],xmm1[1],<wbr>xmm14[1],xmm1[2],xmm14[2],<wbr>xmm1[3],xmm14[3],xmm1[4],<wbr>xmm14[4],xmm1[5],xmm14[5],<wbr>xmm1[6],xmm14[6],xmm1[7],<wbr>xmm14[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3],xmm0[4],xmm2[4],xmm0[<wbr>5],xmm2[5],xmm0[6],xmm2[6],<wbr>xmm0[7],xmm2[7]<br>
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3],xmm0[4],xmm1[4],xmm0[<wbr>5],xmm1[5],xmm0[6],xmm1[6],<wbr>xmm0[7],xmm1[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[<wbr>1],xmm0[2],xmm4[2],xmm0[3],<wbr>xmm4[3],xmm0[4],xmm4[4],xmm0[<wbr>5],xmm4[5],xmm0[6],xmm4[6],<wbr>xmm0[7],xmm4[7]<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm6[0],xmm0[1],xmm6[<wbr>1],xmm0[2],xmm6[2],xmm0[3],<wbr>xmm6[3],xmm0[4],xmm6[4],xmm0[<wbr>5],xmm6[5],xmm0[6],xmm6[6],<wbr>xmm0[7],xmm6[7]<br>
; SSSE3-NEXT: retq<br>
;<br>
; SSE41-LABEL: mem_shuffle_v16i8_v16i8_<wbr>xxxxxxxxxxxxxxxx_i8:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: pushq %rbp<br>
-; SSE41-NEXT: pushq %r15<br>
-; SSE41-NEXT: pushq %r14<br>
-; SSE41-NEXT: pushq %r13<br>
-; SSE41-NEXT: pushq %r12<br>
-; SSE41-NEXT: pushq %rbx<br>
-; SSE41-NEXT: movzbl (%rdi), %r11d<br>
-; SSE41-NEXT: andl $15, %r11d<br>
+; SSE41-NEXT: movzbl (%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)<br>
-; SSE41-NEXT: movzbl 1(%rdi), %r9d<br>
-; SSE41-NEXT: andl $15, %r9d<br>
+; SSE41-NEXT: leaq -{{[0-9]+}}(%rsp), %rcx<br>
+; SSE41-NEXT: movzbl (%rax,%rcx), %eax<br>
+; SSE41-NEXT: movd %eax, %xmm0<br>
+; SSE41-NEXT: movzbl 1(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $1, (%rax,%rcx), %xmm0<br>
; SSE41-NEXT: movzbl 2(%rdi), %eax<br>
; SSE41-NEXT: andl $15, %eax<br>
-; SSE41-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>
+; SSE41-NEXT: pinsrb $2, (%rax,%rcx), %xmm0<br>
; SSE41-NEXT: movzbl 3(%rdi), %eax<br>
; SSE41-NEXT: andl $15, %eax<br>
-; SSE41-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>
-; SSE41-NEXT: movzbl 4(%rdi), %r14d<br>
-; SSE41-NEXT: andl $15, %r14d<br>
-; SSE41-NEXT: movzbl 5(%rdi), %r15d<br>
-; SSE41-NEXT: andl $15, %r15d<br>
-; SSE41-NEXT: movzbl 6(%rdi), %r12d<br>
-; SSE41-NEXT: andl $15, %r12d<br>
-; SSE41-NEXT: movzbl 7(%rdi), %r13d<br>
-; SSE41-NEXT: andl $15, %r13d<br>
-; SSE41-NEXT: movzbl 8(%rdi), %r8d<br>
-; SSE41-NEXT: andl $15, %r8d<br>
+; SSE41-NEXT: pinsrb $3, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 4(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $4, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 5(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $5, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 6(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $6, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 7(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $7, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 8(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $8, (%rax,%rcx), %xmm0<br>
; SSE41-NEXT: movzbl 9(%rdi), %eax<br>
; SSE41-NEXT: andl $15, %eax<br>
-; SSE41-NEXT: movzbl 10(%rdi), %ecx<br>
-; SSE41-NEXT: andl $15, %ecx<br>
-; SSE41-NEXT: movzbl 11(%rdi), %edx<br>
-; SSE41-NEXT: andl $15, %edx<br>
-; SSE41-NEXT: movzbl 12(%rdi), %esi<br>
-; SSE41-NEXT: andl $15, %esi<br>
-; SSE41-NEXT: leaq -{{[0-9]+}}(%rsp), %rbp<br>
-; SSE41-NEXT: movzbl (%r11,%rbp), %ebx<br>
-; SSE41-NEXT: movd %ebx, %xmm0<br>
-; SSE41-NEXT: movzbl 13(%rdi), %r11d<br>
-; SSE41-NEXT: andl $15, %r11d<br>
-; SSE41-NEXT: pinsrb $1, (%r9,%rbp), %xmm0<br>
-; SSE41-NEXT: movzbl 14(%rdi), %ebx<br>
-; SSE41-NEXT: andl $15, %ebx<br>
-; SSE41-NEXT: movzbl 15(%rdi), %edi<br>
-; SSE41-NEXT: andl $15, %edi<br>
-; SSE41-NEXT: movzbl (%rdi,%rbp), %r10d<br>
-; SSE41-NEXT: movzbl (%rbx,%rbp), %r9d<br>
-; SSE41-NEXT: movzbl (%r11,%rbp), %r11d<br>
-; SSE41-NEXT: movzbl (%rsi,%rbp), %esi<br>
-; SSE41-NEXT: movzbl (%rdx,%rbp), %edx<br>
-; SSE41-NEXT: movzbl (%rcx,%rbp), %ecx<br>
-; SSE41-NEXT: movzbl (%rax,%rbp), %eax<br>
-; SSE41-NEXT: movzbl (%r8,%rbp), %r8d<br>
-; SSE41-NEXT: movzbl (%r13,%rbp), %r13d<br>
-; SSE41-NEXT: movzbl (%r12,%rbp), %r12d<br>
-; SSE41-NEXT: movzbl (%r15,%rbp), %r15d<br>
-; SSE41-NEXT: movzbl (%r14,%rbp), %r14d<br>
-; SSE41-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload<br>
-; SSE41-NEXT: movzbl (%rdi,%rbp), %edi<br>
-; SSE41-NEXT: movq -{{[0-9]+}}(%rsp), %rbx # 8-byte Reload<br>
-; SSE41-NEXT: movzbl (%rbx,%rbp), %ebp<br>
-; SSE41-NEXT: pinsrb $2, %ebp, %xmm0<br>
-; SSE41-NEXT: pinsrb $3, %edi, %xmm0<br>
-; SSE41-NEXT: pinsrb $4, %r14d, %xmm0<br>
-; SSE41-NEXT: pinsrb $5, %r15d, %xmm0<br>
-; SSE41-NEXT: pinsrb $6, %r12d, %xmm0<br>
-; SSE41-NEXT: pinsrb $7, %r13d, %xmm0<br>
-; SSE41-NEXT: pinsrb $8, %r8d, %xmm0<br>
-; SSE41-NEXT: pinsrb $9, %eax, %xmm0<br>
-; SSE41-NEXT: pinsrb $10, %ecx, %xmm0<br>
-; SSE41-NEXT: pinsrb $11, %edx, %xmm0<br>
-; SSE41-NEXT: pinsrb $12, %esi, %xmm0<br>
-; SSE41-NEXT: pinsrb $13, %r11d, %xmm0<br>
-; SSE41-NEXT: pinsrb $14, %r9d, %xmm0<br>
-; SSE41-NEXT: pinsrb $15, %r10d, %xmm0<br>
-; SSE41-NEXT: popq %rbx<br>
-; SSE41-NEXT: popq %r12<br>
-; SSE41-NEXT: popq %r13<br>
-; SSE41-NEXT: popq %r14<br>
-; SSE41-NEXT: popq %r15<br>
-; SSE41-NEXT: popq %rbp<br>
+; SSE41-NEXT: pinsrb $9, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 10(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $10, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 11(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $11, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 12(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $12, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 13(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $13, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 14(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $14, (%rax,%rcx), %xmm0<br>
+; SSE41-NEXT: movzbl 15(%rdi), %eax<br>
+; SSE41-NEXT: andl $15, %eax<br>
+; SSE41-NEXT: pinsrb $15, (%rax,%rcx), %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: mem_shuffle_v16i8_v16i8_<wbr>xxxxxxxxxxxxxxxx_i8:<br>
; AVX: # BB#0:<br>
-; AVX-NEXT: pushq %rbp<br>
-; AVX-NEXT: pushq %r15<br>
-; AVX-NEXT: pushq %r14<br>
-; AVX-NEXT: pushq %r13<br>
-; AVX-NEXT: pushq %r12<br>
-; AVX-NEXT: pushq %rbx<br>
-; AVX-NEXT: movzbl (%rdi), %r11d<br>
-; AVX-NEXT: andl $15, %r11d<br>
+; AVX-NEXT: movzbl (%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)<br>
-; AVX-NEXT: movzbl 1(%rdi), %r9d<br>
-; AVX-NEXT: andl $15, %r9d<br>
+; AVX-NEXT: leaq -{{[0-9]+}}(%rsp), %rcx<br>
+; AVX-NEXT: movzbl (%rax,%rcx), %eax<br>
+; AVX-NEXT: vmovd %eax, %xmm0<br>
+; AVX-NEXT: movzbl 1(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $1, (%rax,%rcx), %xmm0, %xmm0<br>
; AVX-NEXT: movzbl 2(%rdi), %eax<br>
; AVX-NEXT: andl $15, %eax<br>
-; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>
+; AVX-NEXT: vpinsrb $2, (%rax,%rcx), %xmm0, %xmm0<br>
; AVX-NEXT: movzbl 3(%rdi), %eax<br>
; AVX-NEXT: andl $15, %eax<br>
-; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill<br>
-; AVX-NEXT: movzbl 4(%rdi), %r14d<br>
-; AVX-NEXT: andl $15, %r14d<br>
-; AVX-NEXT: movzbl 5(%rdi), %r15d<br>
-; AVX-NEXT: andl $15, %r15d<br>
-; AVX-NEXT: movzbl 6(%rdi), %r12d<br>
-; AVX-NEXT: andl $15, %r12d<br>
-; AVX-NEXT: movzbl 7(%rdi), %r13d<br>
-; AVX-NEXT: andl $15, %r13d<br>
-; AVX-NEXT: movzbl 8(%rdi), %r8d<br>
-; AVX-NEXT: andl $15, %r8d<br>
+; AVX-NEXT: vpinsrb $3, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 4(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $4, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 5(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $5, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 6(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $6, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 7(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $7, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 8(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $8, (%rax,%rcx), %xmm0, %xmm0<br>
; AVX-NEXT: movzbl 9(%rdi), %eax<br>
; AVX-NEXT: andl $15, %eax<br>
-; AVX-NEXT: movzbl 10(%rdi), %ecx<br>
-; AVX-NEXT: andl $15, %ecx<br>
-; AVX-NEXT: movzbl 11(%rdi), %edx<br>
-; AVX-NEXT: andl $15, %edx<br>
-; AVX-NEXT: movzbl 12(%rdi), %esi<br>
-; AVX-NEXT: andl $15, %esi<br>
-; AVX-NEXT: leaq -{{[0-9]+}}(%rsp), %rbp<br>
-; AVX-NEXT: movzbl (%r11,%rbp), %ebx<br>
-; AVX-NEXT: vmovd %ebx, %xmm0<br>
-; AVX-NEXT: movzbl 13(%rdi), %r11d<br>
-; AVX-NEXT: andl $15, %r11d<br>
-; AVX-NEXT: vpinsrb $1, (%r9,%rbp), %xmm0, %xmm0<br>
-; AVX-NEXT: movzbl 14(%rdi), %ebx<br>
-; AVX-NEXT: andl $15, %ebx<br>
-; AVX-NEXT: movzbl 15(%rdi), %edi<br>
-; AVX-NEXT: andl $15, %edi<br>
-; AVX-NEXT: movzbl (%rdi,%rbp), %r10d<br>
-; AVX-NEXT: movzbl (%rbx,%rbp), %r9d<br>
-; AVX-NEXT: movzbl (%r11,%rbp), %r11d<br>
-; AVX-NEXT: movzbl (%rsi,%rbp), %esi<br>
-; AVX-NEXT: movzbl (%rdx,%rbp), %edx<br>
-; AVX-NEXT: movzbl (%rcx,%rbp), %ecx<br>
-; AVX-NEXT: movzbl (%rax,%rbp), %eax<br>
-; AVX-NEXT: movzbl (%r8,%rbp), %r8d<br>
-; AVX-NEXT: movzbl (%r13,%rbp), %r13d<br>
-; AVX-NEXT: movzbl (%r12,%rbp), %r12d<br>
-; AVX-NEXT: movzbl (%r15,%rbp), %r15d<br>
-; AVX-NEXT: movzbl (%r14,%rbp), %r14d<br>
-; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rdi # 8-byte Reload<br>
-; AVX-NEXT: movzbl (%rdi,%rbp), %edi<br>
-; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rbx # 8-byte Reload<br>
-; AVX-NEXT: movzbl (%rbx,%rbp), %ebp<br>
-; AVX-NEXT: vpinsrb $2, %ebp, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $3, %edi, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $5, %r15d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $6, %r12d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $7, %r13d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $8, %r8d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $9, %eax, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $11, %edx, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $13, %r11d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $14, %r9d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrb $15, %r10d, %xmm0, %xmm0<br>
-; AVX-NEXT: popq %rbx<br>
-; AVX-NEXT: popq %r12<br>
-; AVX-NEXT: popq %r13<br>
-; AVX-NEXT: popq %r14<br>
-; AVX-NEXT: popq %r15<br>
-; AVX-NEXT: popq %rbp<br>
+; AVX-NEXT: vpinsrb $9, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 10(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $10, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 11(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $11, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 12(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $12, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 13(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $13, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 14(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $14, (%rax,%rcx), %xmm0, %xmm0<br>
+; AVX-NEXT: movzbl 15(%rdi), %eax<br>
+; AVX-NEXT: andl $15, %eax<br>
+; AVX-NEXT: vpinsrb $15, (%rax,%rcx), %xmm0, %xmm0<br>
; AVX-NEXT: retq<br>
%p0 = getelementptr inbounds i8, i8* %i, i64 0<br>
%p1 = getelementptr inbounds i8, i8* %i, i64 1<br>
@@ -1331,26 +1227,26 @@ define <8 x i16> @var_shuffle_v8i16_v8i1<br>
; SSE2-NEXT: andl $7, %r8d<br>
; SSE2-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)<br>
; SSE2-NEXT: andl $7, %r9d<br>
-; SSE2-NEXT: movzwl -24(%rsp,%rsi,2), %eax<br>
-; SSE2-NEXT: movzwl -24(%rsp,%rcx,2), %ecx<br>
-; SSE2-NEXT: movd %ecx, %xmm0<br>
+; SSE2-NEXT: movzwl -24(%rsp,%rcx,2), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm0<br>
; SSE2-NEXT: pxor %xmm1, %xmm1<br>
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3]<br>
-; SSE2-NEXT: movd %eax, %xmm2<br>
; SSE2-NEXT: movzwl -24(%rsp,%r9,2), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm2<br>
+; SSE2-NEXT: movzwl -24(%rsp,%rsi,2), %eax<br>
; SSE2-NEXT: movd %eax, %xmm3<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[<wbr>1],xmm2[2],xmm3[2],xmm2[3],<wbr>xmm3[3]<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3]<br>
-; SSE2-NEXT: movzwl -40(%rsp,%rdi,2), %eax<br>
-; SSE2-NEXT: movzwl -40(%rsp,%rdx,2), %ecx<br>
-; SSE2-NEXT: movd %ecx, %xmm3<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1],xmm3[2],xmm1[2],xmm3[3],<wbr>xmm1[3]<br>
-; SSE2-NEXT: movd %eax, %xmm0<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[<wbr>1],xmm3[2],xmm2[2],xmm3[3],<wbr>xmm2[3]<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[<wbr>1],xmm3[2],xmm0[2],xmm3[3],<wbr>xmm0[3]<br>
+; SSE2-NEXT: movzwl -40(%rsp,%rdx,2), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm2<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3]<br>
; SSE2-NEXT: movzwl -40(%rsp,%r8,2), %eax<br>
; SSE2-NEXT: movd %eax, %xmm1<br>
+; SSE2-NEXT: movzwl -40(%rsp,%rdi,2), %eax<br>
+; SSE2-NEXT: movd %eax, %xmm0<br>
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3]<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3]<br>
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3]<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3]<br>
; SSE2-NEXT: retq<br>
;<br>
; SSSE3-LABEL: var_shuffle_v8i16_v8i16_<wbr>xyxyxy00_i16:<br>
@@ -1369,26 +1265,26 @@ define <8 x i16> @var_shuffle_v8i16_v8i1<br>
; SSSE3-NEXT: andl $7, %r8d<br>
; SSSE3-NEXT: movdqa %xmm1, -{{[0-9]+}}(%rsp)<br>
; SSSE3-NEXT: andl $7, %r9d<br>
-; SSSE3-NEXT: movzwl -24(%rsp,%rsi,2), %eax<br>
-; SSSE3-NEXT: movzwl -24(%rsp,%rcx,2), %ecx<br>
-; SSSE3-NEXT: movd %ecx, %xmm0<br>
+; SSSE3-NEXT: movzwl -24(%rsp,%rcx,2), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm0<br>
; SSSE3-NEXT: pxor %xmm1, %xmm1<br>
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3]<br>
-; SSSE3-NEXT: movd %eax, %xmm2<br>
; SSSE3-NEXT: movzwl -24(%rsp,%r9,2), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm2<br>
+; SSSE3-NEXT: movzwl -24(%rsp,%rsi,2), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm3<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[<wbr>1],xmm2[2],xmm3[2],xmm2[3],<wbr>xmm3[3]<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[<wbr>1],xmm2[2],xmm0[2],xmm2[3],<wbr>xmm0[3]<br>
-; SSSE3-NEXT: movzwl -40(%rsp,%rdi,2), %eax<br>
-; SSSE3-NEXT: movzwl -40(%rsp,%rdx,2), %ecx<br>
-; SSSE3-NEXT: movd %ecx, %xmm3<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[<wbr>1],xmm3[2],xmm1[2],xmm3[3],<wbr>xmm1[3]<br>
-; SSSE3-NEXT: movd %eax, %xmm0<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[<wbr>1],xmm3[2],xmm2[2],xmm3[3],<wbr>xmm2[3]<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[<wbr>1],xmm3[2],xmm0[2],xmm3[3],<wbr>xmm0[3]<br>
+; SSSE3-NEXT: movzwl -40(%rsp,%rdx,2), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm2<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[<wbr>1],xmm2[2],xmm1[2],xmm2[3],<wbr>xmm1[3]<br>
; SSSE3-NEXT: movzwl -40(%rsp,%r8,2), %eax<br>
; SSSE3-NEXT: movd %eax, %xmm1<br>
+; SSSE3-NEXT: movzwl -40(%rsp,%rdi,2), %eax<br>
+; SSSE3-NEXT: movd %eax, %xmm0<br>
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[<wbr>1],xmm0[2],xmm1[2],xmm0[3],<wbr>xmm1[3]<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3]<br>
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[<wbr>1],xmm0[2],xmm2[2],xmm0[3],<wbr>xmm2[3]<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[<wbr>1],xmm0[2],xmm3[2],xmm0[3],<wbr>xmm3[3]<br>
; SSSE3-NEXT: retq<br>
;<br>
; SSE41-LABEL: var_shuffle_v8i16_v8i16_<wbr>xyxyxy00_i16:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-variable-256.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-variable-256.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/vector-shuffle-<wbr>variable-256.ll?rev=297695&r1=<wbr>297694&r2=297695&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-variable-256.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>vector-shuffle-variable-256.ll Mon Mar 13 19:34:14 2017<br>
@@ -1,4 +1,5 @@<br>
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.<wbr>py<br>
+; NOTE: Assertions have been autogenerated by update_llc_test_checks.py<br>
; RUN: llc < %s -mtriple=x86_64-unknown-<wbr>unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1<br>
; RUN: llc < %s -mtriple=x86_64-unknown-<wbr>unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2<br>
<br>
@@ -13,16 +14,16 @@ define <4 x double> @var_shuffle_v4f64_v<br>
; ALL-NEXT: movq %rsp, %rbp<br>
; ALL-NEXT: andq $-32, %rsp<br>
; ALL-NEXT: subq $64, %rsp<br>
-; ALL-NEXT: andl $3, %ecx<br>
-; ALL-NEXT: andl $3, %edx<br>
; ALL-NEXT: andl $3, %esi<br>
; ALL-NEXT: andl $3, %edi<br>
+; ALL-NEXT: andl $3, %ecx<br>
+; ALL-NEXT: andl $3, %edx<br>
; ALL-NEXT: vmovaps %ymm0, (%rsp)<br>
; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero<br>
; ALL-NEXT: vmovhpd {{.*#+}} xmm0 = xmm0[0],mem[0]<br>
; ALL-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero<br>
; ALL-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0]<br>
-; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
+; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; ALL-NEXT: movq %rbp, %rsp<br>
; ALL-NEXT: popq %rbp<br>
; ALL-NEXT: retq<br>
@@ -68,16 +69,16 @@ define <4 x double> @var_shuffle_v4f64_v<br>
define <4 x double> @var_shuffle_v4f64_v2f64_xxxx_<wbr>i64(<2 x double> %x, i64 %i0, i64 %i1, i64 %i2, i64 %i3) nounwind {<br>
; ALL-LABEL: var_shuffle_v4f64_v2f64_xxxx_<wbr>i64:<br>
; ALL: # BB#0:<br>
-; ALL-NEXT: andl $1, %ecx<br>
-; ALL-NEXT: andl $1, %edx<br>
; ALL-NEXT: andl $1, %esi<br>
; ALL-NEXT: andl $1, %edi<br>
+; ALL-NEXT: andl $1, %ecx<br>
+; ALL-NEXT: andl $1, %edx<br>
; ALL-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero<br>
; ALL-NEXT: vmovhpd {{.*#+}} xmm0 = xmm0[0],mem[0]<br>
; ALL-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero<br>
; ALL-NEXT: vmovhpd {{.*#+}} xmm1 = xmm1[0],mem[0]<br>
-; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
+; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; ALL-NEXT: retq<br>
%x0 = extractelement <2 x double> %x, i64 %i0<br>
%x1 = extractelement <2 x double> %x, i64 %i1<br>
@@ -97,18 +98,18 @@ define <4 x i64> @var_shuffle_v4i64_v4i6<br>
; AVX1-NEXT: movq %rsp, %rbp<br>
; AVX1-NEXT: andq $-32, %rsp<br>
; AVX1-NEXT: subq $64, %rsp<br>
-; AVX1-NEXT: andl $3, %ecx<br>
-; AVX1-NEXT: andl $3, %edx<br>
-; AVX1-NEXT: andl $3, %esi<br>
; AVX1-NEXT: andl $3, %edi<br>
+; AVX1-NEXT: andl $3, %esi<br>
+; AVX1-NEXT: andl $3, %edx<br>
+; AVX1-NEXT: andl $3, %ecx<br>
; AVX1-NEXT: vmovaps %ymm0, (%rsp)<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
+; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]<br>
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
+; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]<br>
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX1-NEXT: movq %rbp, %rsp<br>
; AVX1-NEXT: popq %rbp<br>
; AVX1-NEXT: retq<br>
@@ -119,18 +120,18 @@ define <4 x i64> @var_shuffle_v4i64_v4i6<br>
; AVX2-NEXT: movq %rsp, %rbp<br>
; AVX2-NEXT: andq $-32, %rsp<br>
; AVX2-NEXT: subq $64, %rsp<br>
-; AVX2-NEXT: andl $3, %ecx<br>
-; AVX2-NEXT: andl $3, %edx<br>
-; AVX2-NEXT: andl $3, %esi<br>
; AVX2-NEXT: andl $3, %edi<br>
+; AVX2-NEXT: andl $3, %esi<br>
+; AVX2-NEXT: andl $3, %edx<br>
+; AVX2-NEXT: andl $3, %ecx<br>
; AVX2-NEXT: vmovaps %ymm0, (%rsp)<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]<br>
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0<br>
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]<br>
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX2-NEXT: movq %rbp, %rsp<br>
; AVX2-NEXT: popq %rbp<br>
; AVX2-NEXT: retq<br>
@@ -152,12 +153,12 @@ define <4 x i64> @var_shuffle_v4i64_v4i6<br>
; AVX1-NEXT: movq %rsp, %rbp<br>
; AVX1-NEXT: andq $-32, %rsp<br>
; AVX1-NEXT: subq $64, %rsp<br>
-; AVX1-NEXT: andl $3, %esi<br>
; AVX1-NEXT: andl $3, %edi<br>
+; AVX1-NEXT: andl $3, %esi<br>
; AVX1-NEXT: vmovaps %ymm0, (%rsp)<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
+; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
; AVX1-NEXT: movq %rbp, %rsp<br>
@@ -170,12 +171,12 @@ define <4 x i64> @var_shuffle_v4i64_v4i6<br>
; AVX2-NEXT: movq %rsp, %rbp<br>
; AVX2-NEXT: andq $-32, %rsp<br>
; AVX2-NEXT: subq $64, %rsp<br>
-; AVX2-NEXT: andl $3, %esi<br>
; AVX2-NEXT: andl $3, %edi<br>
+; AVX2-NEXT: andl $3, %esi<br>
; AVX2-NEXT: vmovaps %ymm0, (%rsp)<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1<br>
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0<br>
; AVX2-NEXT: movq %rbp, %rsp<br>
@@ -195,34 +196,34 @@ define <4 x i64> @var_shuffle_v4i64_v4i6<br>
define <4 x i64> @var_shuffle_v4i64_v2i64_xxxx_<wbr>i64(<2 x i64> %x, i64 %i0, i64 %i1, i64 %i2, i64 %i3) nounwind {<br>
; AVX1-LABEL: var_shuffle_v4i64_v2i64_xxxx_<wbr>i64:<br>
; AVX1: # BB#0:<br>
-; AVX1-NEXT: andl $1, %ecx<br>
-; AVX1-NEXT: andl $1, %edx<br>
-; AVX1-NEXT: andl $1, %esi<br>
; AVX1-NEXT: andl $1, %edi<br>
+; AVX1-NEXT: andl $1, %esi<br>
+; AVX1-NEXT: andl $1, %edx<br>
+; AVX1-NEXT: andl $1, %ecx<br>
; AVX1-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
+; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]<br>
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
+; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]<br>
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX1-NEXT: retq<br>
;<br>
; AVX2-LABEL: var_shuffle_v4i64_v2i64_xxxx_<wbr>i64:<br>
; AVX2: # BB#0:<br>
-; AVX2-NEXT: andl $1, %ecx<br>
-; AVX2-NEXT: andl $1, %edx<br>
-; AVX2-NEXT: andl $1, %esi<br>
; AVX2-NEXT: andl $1, %edi<br>
+; AVX2-NEXT: andl $1, %esi<br>
+; AVX2-NEXT: andl $1, %edx<br>
+; AVX2-NEXT: andl $1, %ecx<br>
; AVX2-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]<br>
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]<br>
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0<br>
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]<br>
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX2-NEXT: retq<br>
%x0 = extractelement <2 x i64> %x, i64 %i0<br>
%x1 = extractelement <2 x i64> %x, i64 %i1<br>
@@ -260,16 +261,14 @@ define <8 x float> @var_shuffle_v8f32_v8<br>
; ALL-NEXT: movl 24(%rbp), %eax<br>
; ALL-NEXT: andl $7, %eax<br>
; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]<br>
; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
-; ALL-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]<br>
-; ALL-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],mem[0],xmm3[2,3]<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1],xmm0[0],xmm3[3]<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]<br>
-; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]<br>
+; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; ALL-NEXT: movq %rbp, %rsp<br>
; ALL-NEXT: popq %rbp<br>
; ALL-NEXT: retq<br>
@@ -313,16 +312,14 @@ define <8 x float> @var_shuffle_v8f32_v4<br>
; ALL-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; ALL-NEXT: andl $3, %eax<br>
; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]<br>
; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
-; ALL-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]<br>
-; ALL-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],mem[0],xmm3[2,3]<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm3[0,1],xmm0[0],xmm3[3]<br>
-; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]<br>
-; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]<br>
+; ALL-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]<br>
+; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; ALL-NEXT: retq<br>
%x0 = extractelement <4 x float> %x, i32 %i0<br>
%x1 = extractelement <4 x float> %x, i32 %i1<br>
@@ -363,32 +360,25 @@ define <16 x i16> @var_shuffle_v16i16_v1<br>
; AVX1-NEXT: vmovd %eax, %xmm0<br>
; AVX1-NEXT: movl 40(%rbp), %eax<br>
; AVX1-NEXT: andl $15, %eax<br>
-; AVX1-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $1, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl 48(%rbp), %eax<br>
; AVX1-NEXT: andl $15, %eax<br>
-; AVX1-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $2, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl 56(%rbp), %eax<br>
; AVX1-NEXT: andl $15, %eax<br>
-; AVX1-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $3, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl 64(%rbp), %eax<br>
; AVX1-NEXT: andl $15, %eax<br>
-; AVX1-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $4, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl 72(%rbp), %eax<br>
; AVX1-NEXT: andl $15, %eax<br>
-; AVX1-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $5, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl 80(%rbp), %eax<br>
; AVX1-NEXT: andl $15, %eax<br>
-; AVX1-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $6, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl 88(%rbp), %eax<br>
; AVX1-NEXT: andl $15, %eax<br>
-; AVX1-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $7, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: andl $15, %edi<br>
; AVX1-NEXT: movzwl (%rsp,%rdi,2), %eax<br>
; AVX1-NEXT: vmovd %eax, %xmm1<br>
@@ -404,12 +394,10 @@ define <16 x i16> @var_shuffle_v16i16_v1<br>
; AVX1-NEXT: vpinsrw $5, (%rsp,%r9,2), %xmm1, %xmm1<br>
; AVX1-NEXT: movl 16(%rbp), %eax<br>
; AVX1-NEXT: andl $15, %eax<br>
-; AVX1-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1<br>
+; AVX1-NEXT: vpinsrw $6, (%rsp,%rax,2), %xmm1, %xmm1<br>
; AVX1-NEXT: movl 24(%rbp), %eax<br>
; AVX1-NEXT: andl $15, %eax<br>
-; AVX1-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1<br>
+; AVX1-NEXT: vpinsrw $7, (%rsp,%rax,2), %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX1-NEXT: movq %rbp, %rsp<br>
; AVX1-NEXT: popq %rbp<br>
@@ -434,32 +422,25 @@ define <16 x i16> @var_shuffle_v16i16_v1<br>
; AVX2-NEXT: vmovd %eax, %xmm0<br>
; AVX2-NEXT: movl 40(%rbp), %eax<br>
; AVX2-NEXT: andl $15, %eax<br>
-; AVX2-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $1, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl 48(%rbp), %eax<br>
; AVX2-NEXT: andl $15, %eax<br>
-; AVX2-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $2, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl 56(%rbp), %eax<br>
; AVX2-NEXT: andl $15, %eax<br>
-; AVX2-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $3, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl 64(%rbp), %eax<br>
; AVX2-NEXT: andl $15, %eax<br>
-; AVX2-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $4, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl 72(%rbp), %eax<br>
; AVX2-NEXT: andl $15, %eax<br>
-; AVX2-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $5, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl 80(%rbp), %eax<br>
; AVX2-NEXT: andl $15, %eax<br>
-; AVX2-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $6, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl 88(%rbp), %eax<br>
; AVX2-NEXT: andl $15, %eax<br>
-; AVX2-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $7, (%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: andl $15, %edi<br>
; AVX2-NEXT: movzwl (%rsp,%rdi,2), %eax<br>
; AVX2-NEXT: vmovd %eax, %xmm1<br>
@@ -475,12 +456,10 @@ define <16 x i16> @var_shuffle_v16i16_v1<br>
; AVX2-NEXT: vpinsrw $5, (%rsp,%r9,2), %xmm1, %xmm1<br>
; AVX2-NEXT: movl 16(%rbp), %eax<br>
; AVX2-NEXT: andl $15, %eax<br>
-; AVX2-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1<br>
+; AVX2-NEXT: vpinsrw $6, (%rsp,%rax,2), %xmm1, %xmm1<br>
; AVX2-NEXT: movl 24(%rbp), %eax<br>
; AVX2-NEXT: andl $15, %eax<br>
-; AVX2-NEXT: movzwl (%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1<br>
+; AVX2-NEXT: vpinsrw $7, (%rsp,%rax,2), %xmm1, %xmm1<br>
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX2-NEXT: movq %rbp, %rsp<br>
; AVX2-NEXT: popq %rbp<br>
@@ -536,32 +515,25 @@ define <16 x i16> @var_shuffle_v16i16_v8<br>
; AVX1-NEXT: vmovd %eax, %xmm0<br>
; AVX1-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX1-NEXT: andl $7, %eax<br>
-; AVX1-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $1, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX1-NEXT: andl $7, %eax<br>
-; AVX1-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $2, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX1-NEXT: andl $7, %eax<br>
-; AVX1-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $3, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX1-NEXT: andl $7, %eax<br>
-; AVX1-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $4, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX1-NEXT: andl $7, %eax<br>
-; AVX1-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $5, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX1-NEXT: andl $7, %eax<br>
-; AVX1-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $6, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX1-NEXT: andl $7, %eax<br>
-; AVX1-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0<br>
+; AVX1-NEXT: vpinsrw $7, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX1-NEXT: andl $7, %edi<br>
; AVX1-NEXT: movzwl -24(%rsp,%rdi,2), %eax<br>
; AVX1-NEXT: vmovd %eax, %xmm1<br>
@@ -577,12 +549,10 @@ define <16 x i16> @var_shuffle_v16i16_v8<br>
; AVX1-NEXT: vpinsrw $5, -24(%rsp,%r9,2), %xmm1, %xmm1<br>
; AVX1-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX1-NEXT: andl $7, %eax<br>
-; AVX1-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1<br>
+; AVX1-NEXT: vpinsrw $6, -24(%rsp,%rax,2), %xmm1, %xmm1<br>
; AVX1-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX1-NEXT: andl $7, %eax<br>
-; AVX1-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX1-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1<br>
+; AVX1-NEXT: vpinsrw $7, -24(%rsp,%rax,2), %xmm1, %xmm1<br>
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX1-NEXT: retq<br>
;<br>
@@ -601,32 +571,25 @@ define <16 x i16> @var_shuffle_v16i16_v8<br>
; AVX2-NEXT: vmovd %eax, %xmm0<br>
; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX2-NEXT: andl $7, %eax<br>
-; AVX2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $1, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX2-NEXT: andl $7, %eax<br>
-; AVX2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $2, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX2-NEXT: andl $7, %eax<br>
-; AVX2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $3, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX2-NEXT: andl $7, %eax<br>
-; AVX2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $4, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX2-NEXT: andl $7, %eax<br>
-; AVX2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $5, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX2-NEXT: andl $7, %eax<br>
-; AVX2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $6, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX2-NEXT: andl $7, %eax<br>
-; AVX2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0<br>
+; AVX2-NEXT: vpinsrw $7, -24(%rsp,%rax,2), %xmm0, %xmm0<br>
; AVX2-NEXT: andl $7, %edi<br>
; AVX2-NEXT: movzwl -24(%rsp,%rdi,2), %eax<br>
; AVX2-NEXT: vmovd %eax, %xmm1<br>
@@ -642,12 +605,10 @@ define <16 x i16> @var_shuffle_v16i16_v8<br>
; AVX2-NEXT: vpinsrw $5, -24(%rsp,%r9,2), %xmm1, %xmm1<br>
; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX2-NEXT: andl $7, %eax<br>
-; AVX2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1<br>
+; AVX2-NEXT: vpinsrw $6, -24(%rsp,%rax,2), %xmm1, %xmm1<br>
; AVX2-NEXT: movl {{[0-9]+}}(%rsp), %eax<br>
; AVX2-NEXT: andl $7, %eax<br>
-; AVX2-NEXT: movzwl -24(%rsp,%rax,2), %eax<br>
-; AVX2-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1<br>
+; AVX2-NEXT: vpinsrw $7, -24(%rsp,%rax,2), %xmm1, %xmm1<br>
; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX2-NEXT: retq<br>
%x0 = extractelement <8 x i16> %x, i32 %i0<br>
@@ -707,11 +668,11 @@ define <4 x i64> @mem_shuffle_v4i64_v4i6<br>
; AVX1-NEXT: vmovaps %ymm0, (%rsp)<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
+; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
+; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]<br>
-; AVX1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]<br>
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX1-NEXT: movq %rbp, %rsp<br>
; AVX1-NEXT: popq %rbp<br>
; AVX1-NEXT: retq<br>
@@ -733,11 +694,11 @@ define <4 x i64> @mem_shuffle_v4i64_v4i6<br>
; AVX2-NEXT: vmovaps %ymm0, (%rsp)<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
+; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]<br>
-; AVX2-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]<br>
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0<br>
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX2-NEXT: movq %rbp, %rsp<br>
; AVX2-NEXT: popq %rbp<br>
; AVX2-NEXT: retq<br>
@@ -774,11 +735,11 @@ define <4 x i64> @mem_shuffle_v4i64_v2i6<br>
; AVX1-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
+; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
+; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
; AVX1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]<br>
-; AVX1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
-; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]<br>
-; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0<br>
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX1-NEXT: retq<br>
;<br>
; AVX2-LABEL: mem_shuffle_v4i64_v2i64_xxxx_<wbr>i64:<br>
@@ -794,11 +755,11 @@ define <4 x i64> @mem_shuffle_v4i64_v2i6<br>
; AVX2-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]<br>
+; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero<br>
; AVX2-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]<br>
-; AVX2-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero<br>
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]<br>
-; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0<br>
+; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0<br>
; AVX2-NEXT: retq<br>
%p0 = getelementptr inbounds i64, i64* %i, i32 0<br>
%p1 = getelementptr inbounds i64, i64* %i, i32 1<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>vectorcall.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vectorcall.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/vectorcall.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>vectorcall.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>vectorcall.ll Mon Mar 13 19:34:14 2017<br>
@@ -103,7 +103,7 @@ entry:<br>
}<br>
; CHECK-LABEL: test_mixed_1<br>
; CHECK: movaps %xmm1, 16(%{{(e|r)}}sp)<br>
-; CHECK: movaps 16(%{{(e|r)}}sp), %xmm0<br>
+; CHECK: movaps %xmm1, %xmm0<br>
; CHECK: ret{{q|l}}<br>
<br>
define x86_vectorcallcc <4 x float> @test_mixed_2(%struct.HVA4 inreg %a, %struct.HVA4* %b, <4 x float> %c) {<br>
@@ -149,7 +149,7 @@ entry:<br>
}<br>
; CHECK-LABEL: test_mixed_5<br>
; CHECK: movaps %xmm5, 16(%{{(e|r)}}sp)<br>
-; CHECK: movaps 16(%{{(e|r)}}sp), %xmm0<br>
+; CHECK: movaps %xmm5, %xmm0<br>
; CHECK: ret{{[ql]}}<br>
<br>
define x86_vectorcallcc %struct.HVA4 @test_mixed_6(%struct.HVA4 inreg %a, %struct.HVA4* %b) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>win32-eh.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win32-eh.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/win32-eh.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>win32-eh.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>win32-eh.ll Mon Mar 13 19:34:14 2017<br>
@@ -27,23 +27,26 @@ catch:<br>
<br>
; CHECK-LABEL: _use_except_handler3:<br>
; CHECK: pushl %ebp<br>
-; CHECK: movl %esp, %ebp<br>
-; CHECK: pushl %ebx<br>
-; CHECK: pushl %edi<br>
-; CHECK: pushl %esi<br>
-; CHECK: subl ${{[0-9]+}}, %esp<br>
-; CHECK: movl $-1, -16(%ebp)<br>
-; CHECK: movl $L__ehtable$use_except_<wbr>handler3, -20(%ebp)<br>
-; CHECK: leal -28(%ebp), %[[node:[^ ,]*]]<br>
-; CHECK: movl $__except_handler3, -24(%ebp)<br>
-; CHECK: movl %fs:0, %[[next:[^ ,]*]]<br>
-; CHECK: movl %[[next]], -28(%ebp)<br>
-; CHECK: movl %[[node]], %fs:0<br>
-; CHECK: calll _may_throw_or_crash<br>
+; CHECK-NEXT: movl %esp, %ebp<br>
+; CHECK-NEXT: pushl %ebx<br>
+; CHECK-NEXT: pushl %edi<br>
+; CHECK-NEXT: pushl %esi<br>
+; CHECK-NEXT: subl ${{[0-9]+}}, %esp<br>
+; CHECK-NEXT: movl %esp, -36(%ebp)<br>
+; CHECK-NEXT: movl $-1, -16(%ebp)<br>
+; CHECK-NEXT: movl $L__ehtable$use_except_<wbr>handler3, -20(%ebp)<br>
+; CHECK-NEXT: leal -28(%ebp), %[[node:[^ ,]*]]<br>
+; CHECK-NEXT: movl $__except_handler3, -24(%ebp)<br>
+; CHECK-NEXT: movl %fs:0, %[[next:[^ ,]*]]<br>
+; CHECK-NEXT: movl %[[next]], -28(%ebp)<br>
+; CHECK-NEXT: movl %[[node]], %fs:0<br>
+; CHECK-NEXT: movl $0, -16(%ebp)<br>
+; CHECK-NEXT: calll _may_throw_or_crash<br>
+<br>
; CHECK: movl -28(%ebp), %[[next:[^ ,]*]]<br>
-; CHECK: movl %[[next]], %fs:0<br>
+; CHECK-NEXT: movl %[[next]], %fs:0<br>
; CHECK: retl<br>
-; CHECK: LBB1_2: # %catch{{$}}<br>
+; CHECK-NEXT: LBB1_2: # %catch{{$}}<br>
<br>
; CHECK: .section .xdata,"dr"<br>
; CHECK-LABEL: L__ehtable$use_except_<wbr>handler3:<br>
@@ -66,23 +69,37 @@ catch:<br>
<br>
; CHECK-LABEL: _use_except_handler4:<br>
; CHECK: pushl %ebp<br>
-; CHECK: movl %esp, %ebp<br>
-; CHECK: subl ${{[0-9]+}}, %esp<br>
-; CHECK: movl %esp, -36(%ebp)<br>
-; CHECK: movl $-2, -16(%ebp)<br>
-; CHECK: movl $L__ehtable$use_except_<wbr>handler4, %[[lsda:[^ ,]*]]<br>
-; CHECK: xorl ___security_cookie, %[[lsda]]<br>
-; CHECK: movl %[[lsda]], -20(%ebp)<br>
-; CHECK: leal -28(%ebp), %[[node:[^ ,]*]]<br>
-; CHECK: movl $__except_handler4, -24(%ebp)<br>
-; CHECK: movl %fs:0, %[[next:[^ ,]*]]<br>
-; CHECK: movl %[[next]], -28(%ebp)<br>
-; CHECK: movl %[[node]], %fs:0<br>
-; CHECK: calll _may_throw_or_crash<br>
+; CHECK-NEXT: movl %esp, %ebp<br>
+; CHECK-NEXT: pushl %ebx<br>
+; CHECK-NEXT: pushl %edi<br>
+; CHECK-NEXT: pushl %esi<br>
+; CHECK-NEXT: subl ${{[0-9]+}}, %esp<br>
+; CHECK-NEXT: movl %ebp, %eax<br>
+; CHECK-NEXT: movl %esp, -36(%ebp)<br>
+; CHECK-NEXT: movl $-2, -16(%ebp)<br>
+; CHECK-NEXT: movl $L__ehtable$use_except_<wbr>handler4, %[[lsda:[^ ,]*]]<br>
+; CHECK-NEXT: movl ___security_cookie, %[[seccookie:[^ ,]*]]<br>
+; CHECK-NEXT: xorl %[[seccookie]], %[[lsda]]<br>
+; CHECK-NEXT: movl %[[lsda]], -20(%ebp)<br>
+; CHECK-NEXT: xorl %[[seccookie]], %[[tmp1:[^ ,]*]]<br>
+; CHECK-NEXT: movl %[[tmp1]], -40(%ebp)<br>
+; CHECK-NEXT: leal -28(%ebp), %[[node:[^ ,]*]]<br>
+; CHECK-NEXT: movl $__except_handler4, -24(%ebp)<br>
+; CHECK-NEXT: movl %fs:0, %[[next:[^ ,]*]]<br>
+; CHECK-NEXT: movl %[[next]], -28(%ebp)<br>
+; CHECK-NEXT: movl %[[node]], %fs:0<br>
+; CHECK-NEXT: movl $0, -16(%ebp)<br>
+; CHECK-NEXT: calll _may_throw_or_crash<br>
+<br>
; CHECK: movl -28(%ebp), %[[next:[^ ,]*]]<br>
-; CHECK: movl %[[next]], %fs:0<br>
-; CHECK: retl<br>
-; CHECK: LBB2_2: # %catch{{$}}<br>
+; CHECK-NEXT: movl %[[next]], %fs:0<br>
+; CHECK-NEXT: addl $28, %esp<br>
+; CHECK-NEXT: popl %esi<br>
+; CHECK-NEXT: popl %edi<br>
+; CHECK-NEXT: popl %ebx<br>
+; CHECK-NEXT: popl %ebp<br>
+; CHECK-NEXT: retl<br>
+; CHECK-NEXT: LBB2_2: # %catch{{$}}<br>
<br>
; CHECK: .section .xdata,"dr"<br>
; CHECK-LABEL: L__ehtable$use_except_<wbr>handler4:<br>
@@ -109,26 +126,33 @@ catch:<br>
<br>
; CHECK-LABEL: _use_except_handler4_ssp:<br>
; CHECK: pushl %ebp<br>
-; CHECK: movl %esp, %ebp<br>
-; CHECK: subl ${{[0-9]+}}, %esp<br>
-; CHECK: movl %ebp, %[[ehguard:[^ ,]*]]<br>
-; CHECK: movl %esp, -36(%ebp)<br>
-; CHECK: movl $-2, -16(%ebp)<br>
-; CHECK: movl $L__ehtable$use_except_<wbr>handler4_ssp, %[[lsda:[^ ,]*]]<br>
-; CHECK: xorl ___security_cookie, %[[lsda]]<br>
-; CHECK: movl %[[lsda]], -20(%ebp)<br>
-; CHECK: xorl ___security_cookie, %[[ehguard]]<br>
-; CHECK: movl %[[ehguard]], -40(%ebp)<br>
-; CHECK: leal -28(%ebp), %[[node:[^ ,]*]]<br>
-; CHECK: movl $__except_handler4, -24(%ebp)<br>
-; CHECK: movl %fs:0, %[[next:[^ ,]*]]<br>
-; CHECK: movl %[[next]], -28(%ebp)<br>
-; CHECK: movl %[[node]], %fs:0<br>
-; CHECK: calll _may_throw_or_crash<br>
+; CHECK-NEXT: movl %esp, %ebp<br>
+; CHECK-NEXT: pushl %ebx<br>
+; CHECK-NEXT: pushl %edi<br>
+; CHECK-NEXT: pushl %esi<br>
+; CHECK-NEXT: subl ${{[0-9]+}}, %esp<br>
+; CHECK-NEXT: movl %ebp, %[[ehguard:[^ ,]*]]<br>
+; CHECK-NEXT: movl %esp, -36(%ebp)<br>
+; CHECK-NEXT: movl $-2, -16(%ebp)<br>
+; CHECK-NEXT: movl $L__ehtable$use_except_<wbr>handler4_ssp, %[[lsda:[^ ,]*]]<br>
+; CHECK-NEXT: movl ___security_cookie, %[[seccookie:[^ ,]*]]<br>
+; CHECK-NEXT: xorl %[[seccookie]], %[[lsda]]<br>
+; CHECK-NEXT: movl %[[lsda]], -20(%ebp)<br>
+; CHECK-NEXT: xorl %[[seccookie]], %[[ehguard]]<br>
+; CHECK-NEXT: movl %[[ehguard]], -40(%ebp)<br>
+; CHECK-NEXT: leal -28(%ebp), %[[node:[^ ,]*]]<br>
+; CHECK-NEXT: movl $__except_handler4, -24(%ebp)<br>
+; CHECK-NEXT: movl %fs:0, %[[next:[^ ,]*]]<br>
+; CHECK-NEXT: movl %[[next]], -28(%ebp)<br>
+; CHECK-NEXT: movl %[[node]], %fs:0<br>
+; CHECK-NEXT: movl $0, -16(%ebp)<br>
+; CHECK-NEXT: calll _may_throw_or_crash<br>
; CHECK: movl -28(%ebp), %[[next:[^ ,]*]]<br>
-; CHECK: movl %[[next]], %fs:0<br>
+; CHECK-NEXT: movl %[[next]], %fs:0<br>
; CHECK: retl<br>
-; CHECK: [[catch:[^ ,]*]]: # %catch{{$}}<br>
+; CHECK-NEXT: [[catch:[^ ,]*]]: # %catch{{$}}<br>
+<br>
+<br>
<br>
; CHECK: .section .xdata,"dr"<br>
; CHECK-LABEL: L__ehtable$use_except_<wbr>handler4_ssp:<br>
@@ -155,23 +179,26 @@ catch:<br>
<br>
; CHECK-LABEL: _use_CxxFrameHandler3:<br>
; CHECK: pushl %ebp<br>
-; CHECK: movl %esp, %ebp<br>
-; CHECK: subl ${{[0-9]+}}, %esp<br>
-; CHECK: movl %esp, -28(%ebp)<br>
-; CHECK: movl $-1, -16(%ebp)<br>
-; CHECK: leal -24(%ebp), %[[node:[^ ,]*]]<br>
-; CHECK: movl $___ehhandler$use_<wbr>CxxFrameHandler3, -20(%ebp)<br>
-; CHECK: movl %fs:0, %[[next:[^ ,]*]]<br>
-; CHECK: movl %[[next]], -24(%ebp)<br>
-; CHECK: movl %[[node]], %fs:0<br>
-; CHECK: movl $0, -16(%ebp)<br>
-; CHECK: calll _may_throw_or_crash<br>
+; CHECK-NEXT: movl %esp, %ebp<br>
+; CHECK-NEXT: pushl %ebx<br>
+; CHECK-NEXT: pushl %edi<br>
+; CHECK-NEXT: pushl %esi<br>
+; CHECK-NEXT: subl ${{[0-9]+}}, %esp<br>
+; CHECK-NEXT: movl %esp, -28(%ebp)<br>
+; CHECK-NEXT: movl $-1, -16(%ebp)<br>
+; CHECK-NEXT: leal -24(%ebp), %[[node:[^ ,]*]]<br>
+; CHECK-NEXT: movl $___ehhandler$use_<wbr>CxxFrameHandler3, -20(%ebp)<br>
+; CHECK-NEXT: movl %fs:0, %[[next:[^ ,]*]]<br>
+; CHECK-NEXT: movl %[[next]], -24(%ebp)<br>
+; CHECK-NEXT: movl %[[node]], %fs:0<br>
+; CHECK-NEXT: movl $0, -16(%ebp)<br>
+; CHECK-NEXT: calll _may_throw_or_crash<br>
; CHECK: movl -24(%ebp), %[[next:[^ ,]*]]<br>
-; CHECK: movl %[[next]], %fs:0<br>
+; CHECK-NEXT: movl %[[next]], %fs:0<br>
; CHECK: retl<br>
<br>
; CHECK: .section .xdata,"dr"<br>
-; CHECK: .p2align 2<br>
+; CHECK-NEXT: .p2align 2<br>
; CHECK-LABEL: L__ehtable$use_<wbr>CxxFrameHandler3:<br>
; CHECK-NEXT: .long 429065506<br>
; CHECK-NEXT: .long 2<br>
@@ -185,8 +212,8 @@ catch:<br>
<br>
; CHECK-LABEL: ___ehhandler$use_<wbr>CxxFrameHandler3:<br>
; CHECK: movl $L__ehtable$use_<wbr>CxxFrameHandler3, %eax<br>
-; CHECK: jmp ___CxxFrameHandler3 # TAILCALL<br>
+; CHECK-NEXT: jmp ___CxxFrameHandler3 # TAILCALL<br>
<br>
; CHECK: .safeseh __except_handler3<br>
-; CHECK: .safeseh __except_handler4<br>
-; CHECK: .safeseh ___ehhandler$use_<wbr>CxxFrameHandler3<br>
+; CHECK-NEXT: .safeseh __except_handler4<br>
+; CHECK-NEXT: .safeseh ___ehhandler$use_<wbr>CxxFrameHandler3<br>
<br>
Modified: llvm/trunk/test/CodeGen/XCore/<wbr>varargs.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/varargs.ll?rev=297695&r1=297694&r2=297695&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/XCore/varargs.ll?rev=<wbr>297695&r1=297694&r2=297695&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/XCore/<wbr>varargs.ll (original)<br>
+++ llvm/trunk/test/CodeGen/XCore/<wbr>varargs.ll Mon Mar 13 19:34:14 2017<br>
@@ -26,10 +26,10 @@ entry:<br>
; CHECK-LABEL: test_vararg<br>
; CHECK: extsp 6<br>
; CHECK: stw lr, sp[1]<br>
+; CHECK: stw r3, sp[6]<br>
; CHECK: stw r0, sp[3]<br>
; CHECK: stw r1, sp[4]<br>
; CHECK: stw r2, sp[5]<br>
-; CHECK: stw r3, sp[6]<br>
; CHECK: ldaw r0, sp[3]<br>
; CHECK: stw r0, sp[2]<br>
%list = alloca i8*, align 4<br>
<br>
<br>
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</blockquote></div><br></div>