<div dir="ltr">I enabled expensive checks and I'm still unable to reproduce this locally. Any chance you can get the errors from the test?</div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Mon, Mar 13, 2017 at 12:18 PM, Galina Kistanova <span dir="ltr"><<a href="mailto:gkistanova@gmail.com" target="_blank">gkistanova@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hello Craig,<br><br>It look like one your recent commits broke one of our builders:<br><br><a href="http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/61/steps/test-check-all/logs/stdio" target="_blank">http://lab.llvm.org:8011/<wbr>builders/llvm-clang-x86_64-<wbr>expensive-checks-win/builds/<wbr>61/steps/test-check-all/logs/<wbr>stdio</a><br><br>Failing Tests (1):<br> LLVM :: CodeGen/X86/evex-to-vex-<wbr>compress.mir<br><br>Please have a look at this?<br><br>Thanks<br><br>Galina<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Mar 12, 2017 at 10:47 PM, Craig Topper via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ctopper<br>
Date: Mon Mar 13 00:47:56 2017<br>
New Revision: 297603<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=297603&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=297603&view=rev</a><br>
Log:<br>
[AVX-512] Add EVEX2VEX test cases for the cvt instructions fixed in r297599 and r297600.<br>
<br>
Modified:<br>
llvm/trunk/test/CodeGen/X86/ev<wbr>ex-to-vex-compress.mir<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/ev<wbr>ex-to-vex-compress.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/evex-to-vex-compress.mir?rev=297603&r1=297602&r2=297603&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/evex-to-vex-compress.mir?<wbr>rev=297603&r1=297602&r2=<wbr>297603&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/ev<wbr>ex-to-vex-compress.mir (original)<br>
+++ llvm/trunk/test/CodeGen/X86/ev<wbr>ex-to-vex-compress.mir Mon Mar 13 00:47:56 2017<br>
@@ -2130,8 +2130,12 @@ body: |<br>
%edi = VCVTSD2SIZrr %xmm0<br>
; CHECK: %xmm0 = VCVTSD2SSrm %xmm0, %rdi, 1, _, 0, _<br>
%xmm0 = VCVTSD2SSZrm %xmm0, %rdi, 1, _, 0, _<br>
+ ; CHECK: %xmm0 = Int_VCVTSD2SSrm %xmm0, %rdi, 1, _, 0, _<br>
+ %xmm0 = VCVTSD2SSZrm_Int %xmm0, %rdi, 1, _, 0, _<br>
; CHECK: %xmm0 = VCVTSD2SSrr %xmm0, _<br>
%xmm0 = VCVTSD2SSZrr %xmm0, _<br>
+ ; CHECK: %xmm0 = Int_VCVTSD2SSrr %xmm0, _<br>
+ %xmm0 = VCVTSD2SSZrr_Int %xmm0, _<br>
; CHECK: %xmm0 = VCVTSI2SDrm %xmm0, %rdi, 1, _, 0, _<br>
%xmm0 = VCVTSI2SDZrm %xmm0, %rdi, 1, _, 0, _<br>
; CHECK: %xmm0 = Int_VCVTSI2SDrm %xmm0, %rdi, 1, _, 0, _<br>
@@ -2166,10 +2170,18 @@ body: |<br>
%xmm0 = VCVTSI642SSZrr_Int %xmm0, _<br>
; CHECK: %xmm0 = VCVTSS2SDrm %xmm0, %rdi, 1, _, 0, _<br>
%xmm0 = VCVTSS2SDZrm %xmm0, %rdi, 1, _, 0, _<br>
+ ; CHECK: %xmm0 = Int_VCVTSS2SDrm %xmm0, %rdi, 1, _, 0, _<br>
+ %xmm0 = VCVTSS2SDZrm_Int %xmm0, %rdi, 1, _, 0, _<br>
; CHECK: %xmm0 = VCVTSS2SDrr %xmm0, _<br>
%xmm0 = VCVTSS2SDZrr %xmm0, _<br>
+ ; CHECK: %xmm0 = Int_VCVTSS2SDrr %xmm0, _<br>
+ %xmm0 = VCVTSS2SDZrr_Int %xmm0, _<br>
+ ; CHECK: %rdi = VCVTSS2SI64rm %rdi, %xmm0, 1, _, 0<br>
+ %rdi = VCVTSS2SI64Zrm %rdi, %xmm0, 1, _, 0<br>
; CHECK: %rdi = VCVTSS2SI64rr %xmm0<br>
%rdi = VCVTSS2SI64Zrr %xmm0<br>
+ ; CHECK: %edi = VCVTSS2SIrm %rdi, %xmm0, 1, _, 0<br>
+ %edi = VCVTSS2SIZrm %rdi, %xmm0, 1, _, 0<br>
; CHECK: %edi = VCVTSS2SIrr %xmm0<br>
%edi = VCVTSS2SIZrr %xmm0<br>
; CHECK: %rdi = VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0<br>
@@ -4438,8 +4450,12 @@ body: |<br>
%edi = VCVTSD2SIZrr %xmm16<br>
; CHECK: %xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, _, 0, _<br>
%xmm16 = VCVTSD2SSZrm %xmm16, %rdi, 1, _, 0, _<br>
+ ; CHECK: %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, _, 0, _<br>
+ %xmm16 = VCVTSD2SSZrm_Int %xmm16, %rdi, 1, _, 0, _<br>
; CHECK: %xmm16 = VCVTSD2SSZrr %xmm16, _<br>
%xmm16 = VCVTSD2SSZrr %xmm16, _<br>
+ ; CHECK: %xmm16 = VCVTSD2SSZrr_Int %xmm16, _<br>
+ %xmm16 = VCVTSD2SSZrr_Int %xmm16, _<br>
; CHECK: %xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, _, 0, _<br>
%xmm16 = VCVTSI2SDZrm %xmm16, %rdi, 1, _, 0, _<br>
; CHECK: %xmm16 = VCVTSI2SDZrm_Int %xmm16, %rdi, 1, _, 0, _<br>
@@ -4474,8 +4490,12 @@ body: |<br>
%xmm16 = VCVTSI642SSZrr_Int %xmm16, _<br>
; CHECK: %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _<br>
%xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _<br>
+ ; CHECK: %xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, _, 0, _<br>
+ %xmm16 = VCVTSS2SDZrm_Int %xmm16, %rdi, 1, _, 0, _<br>
; CHECK: %xmm16 = VCVTSS2SDZrr %xmm16, _<br>
%xmm16 = VCVTSS2SDZrr %xmm16, _<br>
+ ; CHECK: %xmm16 = VCVTSS2SDZrr_Int %xmm16, _<br>
+ %xmm16 = VCVTSS2SDZrr_Int %xmm16, _<br>
; CHECK: %rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, _, 0<br>
%rdi = VCVTSS2SI64Zrm %rdi, %xmm16, 1, _, 0<br>
; CHECK: %rdi = VCVTSS2SI64Zrr %xmm16<br>
<br>
<br>
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</blockquote></div><br></div>
</blockquote></div><br></div>