<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Yes, it seems like for whatever reason the “svn rm” of AArch64SchedVulcan.td didn’t trigger a new cmake, The subsequent clang patch that fixed the errors from clang’s “Driver/aarch64-cpus.c, Frontend/aarch64-taget-cpu.c, and Preprocessor/aarch64-target-features.c”. should fix the pronblem, unless you are using ninja. For those systems, I think forcing a cmake would fix the problem.<div class=""><br class=""></div><div class="">Joel</div><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Mar 7, 2017, at 3:29 PM, Galina Kistanova <<a href="mailto:gkistanova@gmail.com" class="">gkistanova@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div class="">Hello Joel,<br class=""><br class="">It look like this commit broke one of our builders:<br class=""><br class=""><a href="http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/2169" class="">http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/2169</a><br class=""><br class="">Please have a look at this?<br class=""><br class="">Thanks<br class=""><br class=""></div>Galina<br class=""></div><div class="gmail_extra"><br class=""><div class="gmail_quote">On Tue, Mar 7, 2017 at 11:42 AM, Joel Jones via llvm-commits <span dir="ltr" class=""><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: joel_k_jones<br class="">
Date: Tue Mar 7 13:42:40 2017<br class="">
New Revision: 297190<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=297190&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project?rev=297190&view=rev</a><br class="">
Log:<br class="">
[AArch64] Vulcan is now ThunderXT99<br class="">
<br class="">
Broadcom Vulcan is now Cavium ThunderX2T99.<br class="">
<br class="">
LLVM Bugzilla: <a href="http://bugs.llvm.org/show_bug.cgi?id=32113" rel="noreferrer" target="_blank" class="">http://bugs.llvm.org/show_bug.<wbr class="">cgi?id=32113</a><br class="">
<br class="">
Minor fixes for the alignments of loops and functions for<br class="">
ThunderX T81/T83/T88 (better performance).<br class="">
<br class="">
Patch was tested with SpecCPU2006.<br class="">
<br class="">
Patch by Stefan Teleman<br class="">
<br class="">
Differential Revision: <a href="https://reviews.llvm.org/D30510" rel="noreferrer" target="_blank" class="">https://reviews.llvm.org/<wbr class="">D30510</a><br class="">
<br class="">
Added:<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedThunderX2T99.td<br class="">
Removed:<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedVulcan.td<br class="">
Modified:<br class="">
llvm/trunk/include/llvm/<wbr class="">Support/AArch64TargetParser.<wbr class="">def<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64.td<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedThunderX.td<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64Subtarget.cpp<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64Subtarget.h<br class="">
llvm/trunk/test/CodeGen/<wbr class="">AArch64/cpus.ll<br class="">
llvm/trunk/test/CodeGen/<wbr class="">AArch64/machine-combiner-madd.<wbr class="">ll<br class="">
llvm/trunk/test/CodeGen/<wbr class="">AArch64/remat.ll<br class="">
llvm/trunk/unittests/Support/<wbr class="">TargetParserTest.cpp<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/<wbr class="">Support/AArch64TargetParser.<wbr class="">def<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/include/<wbr class="">llvm/Support/<wbr class="">AArch64TargetParser.def?rev=<wbr class="">297190&r1=297189&r2=297190&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/include/llvm/<wbr class="">Support/AArch64TargetParser.<wbr class="">def (original)<br class="">
+++ llvm/trunk/include/llvm/<wbr class="">Support/AArch64TargetParser.<wbr class="">def Tue Mar 7 13:42:40 2017<br class="">
@@ -73,8 +73,9 @@ AARCH64_CPU_NAME("falkor", AK_ARMV8A, FK<br class="">
(AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))<br class="">
AARCH64_CPU_NAME("kryo", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,<br class="">
(AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))<br class="">
-AARCH64_CPU_NAME("vulcan", AK_ARMV8_1A, FK_CRYPTO_NEON_FP_ARMV8, false,<br class="">
- (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))<br class="">
+AARCH64_CPU_NAME("<wbr class="">thunderx2t99", AK_ARMV8_1A, FK_CRYPTO_NEON_FP_ARMV8, false,<br class="">
+ (AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_CRC |<br class="">
+ AArch64::AEK_CRYPTO))<br class="">
AARCH64_CPU_NAME("thunderx", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,<br class="">
(AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_PROFILE))<br class="">
AARCH64_CPU_NAME("thunderxt88"<wbr class="">, AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/AArch64.td?rev=297190&<wbr class="">r1=297189&r2=297190&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64.td (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64.td Tue Mar 7 13:42:40 2017<br class="">
@@ -161,7 +161,7 @@ include "AArch64SchedFalkor.td"<br class="">
include "AArch64SchedKryo.td"<br class="">
include "AArch64SchedM1.td"<br class="">
include "AArch64SchedThunderX.td"<br class="">
-include "AArch64SchedVulcan.td"<br class="">
+include "AArch64SchedThunderX2T99.td"<br class="">
<br class="">
def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",<br class="">
"Cortex-A35 ARM processors", [<br class="">
@@ -288,16 +288,18 @@ def ProcFalkor : SubtargetFeature<"falk<br class="">
FeatureZCZeroing<br class="">
]>;<br class="">
<br class="">
-def ProcVulcan : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",<br class="">
- "Broadcom Vulcan processors", [<br class="">
- FeatureCRC,<br class="">
- FeatureCrypto,<br class="">
- FeatureFPARMv8,<br class="">
- FeatureArithmeticBccFusion,<br class="">
- FeatureNEON,<br class="">
- FeaturePostRAScheduler,<br class="">
- FeaturePredictableSelectIsExpe<wbr class="">nsive,<br class="">
- HasV8_1aOps]>;<br class="">
+def ProcThunderX2T99 : SubtargetFeature<"<wbr class="">thunderx2t99", "ARMProcFamily",<br class="">
+ "ThunderX2T99",<br class="">
+ "Cavium ThunderX2 processors", [<br class="">
+ FeatureCRC,<br class="">
+ FeatureCrypto,<br class="">
+ FeatureFPARMv8,<br class="">
+ FeatureArithmeticBccFusion,<br class="">
+ FeatureNEON,<br class="">
+ FeaturePostRAScheduler,<br class="">
+ FeaturePredictableSelectIsExpe<wbr class="">nsive,<br class="">
+ FeatureLSE,<br class="">
+ HasV8_1aOps]>;<br class="">
<br class="">
def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",<br class="">
"Cavium ThunderX processors", [<br class="">
@@ -363,12 +365,13 @@ def : ProcessorModel<"exynos-m2", Exynos<br class="">
def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;<br class="">
def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;<br class="">
def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;<br class="">
-def : ProcessorModel<"vulcan", VulcanModel, [ProcVulcan]>;<br class="">
// Cavium ThunderX/ThunderX T8X Processors<br class="">
def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;<br class="">
def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>;<br class="">
def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>;<br class="">
def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>;<br class="">
+// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.<br class="">
+def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;<br class="">
<br class="">
//===-------------------------<wbr class="">------------------------------<wbr class="">---------------===//<br class="">
// Assembly parser<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedThunderX.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX.td?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/AArch64SchedThunderX.<wbr class="">td?rev=297190&r1=297189&r2=<wbr class="">297190&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedThunderX.td (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedThunderX.td Tue Mar 7 13:42:40 2017<br class="">
@@ -23,6 +23,7 @@ def ThunderXT8XModel : SchedMachineModel<br class="">
let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.<br class="">
let LoadLatency = 3; // Optimistic load latency.<br class="">
let MispredictPenalty = 8; // Branch mispredict penalty.<br class="">
+ let PostRAScheduler = 1; // Use PostRA scheduler.<br class="">
let CompleteModel = 1;<br class="">
}<br class="">
<br class="">
<br class="">
Added: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedThunderX2T99.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td?rev=297190&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/<wbr class="">AArch64SchedThunderX2T99.td?<wbr class="">rev=297190&view=auto</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedThunderX2T99.td (added)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedThunderX2T99.td Tue Mar 7 13:42:40 2017<br class="">
@@ -0,0 +1,852 @@<br class="">
+//=- AArch64SchedThunderX2T99.td - Cavium ThunderX T99 Scheduling ---*- tablegen -*-=//<br class="">
+//<br class="">
+// The LLVM Compiler Infrastructure<br class="">
+//<br class="">
+// This file is distributed under the University of Illinois Open Source<br class="">
+// License. See LICENSE.TXT for details.<br class="">
+//<br class="">
+//===------------------------<wbr class="">------------------------------<wbr class="">----------------===//<br class="">
+//<br class="">
+// This file defines the scheduling model for Cavium ThunderX2T99<br class="">
+// processors.<br class="">
+// Based on Broadcom Vulcan.<br class="">
+//<br class="">
+//===------------------------<wbr class="">------------------------------<wbr class="">----------------===//<br class="">
+<br class="">
+//===------------------------<wbr class="">------------------------------<wbr class="">----------------===//<br class="">
+// 2. Pipeline Description.<br class="">
+<br class="">
+def ThunderX2T99Model : SchedMachineModel {<br class="">
+ let IssueWidth = 4; // 4 micro-ops dispatched at a time.<br class="">
+ let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.<br class="">
+ let LoadLatency = 4; // Optimistic load latency.<br class="">
+ let MispredictPenalty = 12; // Extra cycles for mispredicted branch.<br class="">
+ // Determined via a mix of micro-arch details and experimentation.<br class="">
+ let LoopMicroOpBufferSize = 32;<br class="">
+ let PostRAScheduler = 1; // Using PostRA sched.<br class="">
+ let CompleteModel = 1;<br class="">
+}<br class="">
+<br class="">
+// Define the issue ports.<br class="">
+<br class="">
+// Port 0: ALU, FP/SIMD.<br class="">
+def THX2T99P0 : ProcResource<1>;<br class="">
+<br class="">
+// Port 1: ALU, FP/SIMD, integer mul/div.<br class="">
+def THX2T99P1 : ProcResource<1>;<br class="">
+<br class="">
+// Port 2: ALU, Branch.<br class="">
+def THX2T99P2 : ProcResource<1>;<br class="">
+<br class="">
+// Port 3: Store data.<br class="">
+def THX2T99P3 : ProcResource<1>;<br class="">
+<br class="">
+// Port 4: Load/store.<br class="">
+def THX2T99P4 : ProcResource<1>;<br class="">
+<br class="">
+// Port 5: Load/store.<br class="">
+def THX2T99P5 : ProcResource<1>;<br class="">
+<br class="">
+let SchedModel = ThunderX2T99Model in {<br class="">
+<br class="">
+// Define groups for the functional units on each issue port. Each group<br class="">
+// created will be used by a WriteRes later on.<br class="">
+//<br class="">
+// NOTE: Some groups only contain one member. This is a way to create names for<br class="">
+// the various functional units that share a single issue port. For example,<br class="">
+// "THX2T99I1" for ALU ops on port 1 and "THX2T99F1" for FP ops on port 1.<br class="">
+<br class="">
+// Integer divide and multiply micro-ops only on port 1.<br class="">
+def THX2T99I1 : ProcResGroup<[THX2T99P1]>;<br class="">
+<br class="">
+// Branch micro-ops only on port 2.<br class="">
+def THX2T99I2 : ProcResGroup<[THX2T99P2]>;<br class="">
+<br class="">
+// ALU micro-ops on ports 0, 1, and 2.<br class="">
+def THX2T99I012 : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2]>;<br class="">
+<br class="">
+// Crypto FP/SIMD micro-ops only on port 1.<br class="">
+def THX2T99F1 : ProcResGroup<[THX2T99P1]>;<br class="">
+<br class="">
+// FP/SIMD micro-ops on ports 0 and 1.<br class="">
+def THX2T99F01 : ProcResGroup<[THX2T99P0, THX2T99P1]>;<br class="">
+<br class="">
+// Store data micro-ops only on port 3.<br class="">
+def THX2T99SD : ProcResGroup<[THX2T99P3]>;<br class="">
+<br class="">
+// Load/store micro-ops on ports 4 and 5.<br class="">
+def THX2T99LS01 : ProcResGroup<[THX2T99P4, THX2T99P5]>;<br class="">
+<br class="">
+// 60 entry unified scheduler.<br class="">
+def THX2T99Any : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2,<br class="">
+ THX2T99P3, THX2T99P4, THX2T99P5]> {<br class="">
+ let BufferSize=60;<br class="">
+}<br class="">
+<br class="">
+// Define commonly used write types for InstRW specializations.<br class="">
+// All definitions follow the format: THX2T99Write_<NumCycles>Cyc_<<wbr class="">Resources>.<br class="">
+<br class="">
+// 3 cycles on I1.<br class="">
+def THX2T99Write_3Cyc_I1 : SchedWriteRes<[THX2T99I1]> { let Latency = 3; }<br class="">
+<br class="">
+// 4 cycles on I1.<br class="">
+def THX2T99Write_4Cyc_I1 : SchedWriteRes<[THX2T99I1]> { let Latency = 4; }<br class="">
+<br class="">
+// 1 cycle on I0, I1, or I2.<br class="">
+def THX2T99Write_1Cyc_I012 : SchedWriteRes<[THX2T99I012]> { let Latency = 1; }<br class="">
+<br class="">
+// 5 cycles on F1.<br class="">
+def THX2T99Write_5Cyc_F1 : SchedWriteRes<[THX2T99F1]> { let Latency = 5; }<br class="">
+<br class="">
+// 7 cycles on F1.<br class="">
+def THX2T99Write_7Cyc_F1 : SchedWriteRes<[THX2T99F1]> { let Latency = 7; }<br class="">
+<br class="">
+// 4 cycles on F0 or F1.<br class="">
+def THX2T99Write_4Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 4; }<br class="">
+<br class="">
+// 5 cycles on F0 or F1.<br class="">
+def THX2T99Write_5Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 5; }<br class="">
+<br class="">
+// 6 cycles on F0 or F1.<br class="">
+def THX2T99Write_6Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 6; }<br class="">
+<br class="">
+// 7 cycles on F0 or F1.<br class="">
+def THX2T99Write_7Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 7; }<br class="">
+<br class="">
+// 8 cycles on F0 or F1.<br class="">
+def THX2T99Write_8Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 8; }<br class="">
+<br class="">
+// 16 cycles on F0 or F1.<br class="">
+def THX2T99Write_16Cyc_F01 : SchedWriteRes<[THX2T99F01]> {<br class="">
+ let Latency = 16;<br class="">
+ let ResourceCycles = [8];<br class="">
+}<br class="">
+<br class="">
+// 23 cycles on F0 or F1.<br class="">
+def THX2T99Write_23Cyc_F01 : SchedWriteRes<[THX2T99F01]> {<br class="">
+ let Latency = 23;<br class="">
+ let ResourceCycles = [11];<br class="">
+}<br class="">
+<br class="">
+// 1 cycles on LS0 or LS1.<br class="">
+def THX2T99Write_1Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 1; }<br class="">
+<br class="">
+// 4 cycles on LS0 or LS1.<br class="">
+def THX2T99Write_4Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 4; }<br class="">
+<br class="">
+// 5 cycles on LS0 or LS1.<br class="">
+def THX2T99Write_5Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 5; }<br class="">
+<br class="">
+// 6 cycles on LS0 or LS1.<br class="">
+def THX2T99Write_6Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 6; }<br class="">
+<br class="">
+// 5 cycles on LS0 or LS1 and I0, I1, or I2.<br class="">
+def THX2T99Write_5Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> {<br class="">
+ let Latency = 5;<br class="">
+ let NumMicroOps = 2;<br class="">
+}<br class="">
+<br class="">
+// 5 cycles on LS0 or LS1 and 2 of I0, I1, or I2.<br class="">
+def THX2T99Write_6Cyc_LS01_I012_<wbr class="">I012 :<br class="">
+ SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> {<br class="">
+ let Latency = 6;<br class="">
+ let NumMicroOps = 3;<br class="">
+}<br class="">
+<br class="">
+// 1 cycles on LS0 or LS1 and F0 or F1.<br class="">
+def THX2T99Write_1Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br class="">
+ let Latency = 1;<br class="">
+ let NumMicroOps = 2;<br class="">
+}<br class="">
+<br class="">
+// 5 cycles on LS0 or LS1 and F0 or F1.<br class="">
+def THX2T99Write_5Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br class="">
+ let Latency = 5;<br class="">
+ let NumMicroOps = 2;<br class="">
+}<br class="">
+<br class="">
+// 6 cycles on LS0 or LS1 and F0 or F1.<br class="">
+def THX2T99Write_6Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br class="">
+ let Latency = 6;<br class="">
+ let NumMicroOps = 2;<br class="">
+}<br class="">
+<br class="">
+// 7 cycles on LS0 or LS1 and F0 or F1.<br class="">
+def THX2T99Write_7Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br class="">
+ let Latency = 7;<br class="">
+ let NumMicroOps = 2;<br class="">
+}<br class="">
+<br class="">
+// 8 cycles on LS0 or LS1 and F0 or F1.<br class="">
+def THX2T99Write_8Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br class="">
+ let Latency = 8;<br class="">
+ let NumMicroOps = 2;<br class="">
+}<br class="">
+<br class="">
+// Define commonly used read types.<br class="">
+<br class="">
+// No forwarding is provided for these types.<br class="">
+def : ReadAdvance<ReadI, 0>;<br class="">
+def : ReadAdvance<ReadISReg, 0>;<br class="">
+def : ReadAdvance<ReadIEReg, 0>;<br class="">
+def : ReadAdvance<ReadIM, 0>;<br class="">
+def : ReadAdvance<ReadIMA, 0>;<br class="">
+def : ReadAdvance<ReadID, 0>;<br class="">
+def : ReadAdvance<ReadExtrHi, 0>;<br class="">
+def : ReadAdvance<ReadAdrBase, 0>;<br class="">
+def : ReadAdvance<ReadVLD, 0>;<br class="">
+<br class="">
+}<br class="">
+<br class="">
+<br class="">
+//===------------------------<wbr class="">------------------------------<wbr class="">----------------===//<br class="">
+// 3. Instruction Tables.<br class="">
+<br class="">
+let SchedModel = ThunderX2T99Model in {<br class="">
+<br class="">
+//---<br class="">
+// 3.1 Branch Instructions<br class="">
+//---<br class="">
+<br class="">
+// Branch, immed<br class="">
+// Branch and link, immed<br class="">
+// Compare and branch<br class="">
+def : WriteRes<WriteBr, [THX2T99I2]> { let Latency = 1; }<br class="">
+<br class="">
+def : WriteRes<WriteSys, []> { let Latency = 1; }<br class="">
+def : WriteRes<WriteBarrier, []> { let Latency = 1; }<br class="">
+def : WriteRes<WriteHint, []> { let Latency = 1; }<br class="">
+<br class="">
+def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }<br class="">
+<br class="">
+// Branch, register<br class="">
+// Branch and link, register != LR<br class="">
+// Branch and link, register = LR<br class="">
+def : WriteRes<WriteBrReg, [THX2T99I2]> { let Latency = 1; }<br class="">
+<br class="">
+//---<br class="">
+// 3.2 Arithmetic and Logical Instructions<br class="">
+// 3.3 Move and Shift Instructions<br class="">
+//---<br class="">
+<br class="">
+// ALU, basic<br class="">
+// Conditional compare<br class="">
+// Conditional select<br class="">
+// Address generation<br class="">
+def : WriteRes<WriteI, [THX2T99I012]> { let Latency = 1; }<br class="">
+def : InstRW<[WriteI], (instrs COPY)>;<br class="">
+<br class="">
+// ALU, extend and/or shift<br class="">
+def : WriteRes<WriteISReg, [THX2T99I012]> {<br class="">
+ let Latency = 2;<br class="">
+ let ResourceCycles = [2];<br class="">
+}<br class="">
+<br class="">
+def : WriteRes<WriteIEReg, [THX2T99I012]> {<br class="">
+ let Latency = 2;<br class="">
+ let ResourceCycles = [2];<br class="">
+}<br class="">
+<br class="">
+// Move immed<br class="">
+def : WriteRes<WriteImm, [THX2T99I012]> { let Latency = 1; }<br class="">
+<br class="">
+// Variable shift<br class="">
+def : WriteRes<WriteIS, [THX2T99I012]> { let Latency = 1; }<br class="">
+<br class="">
+//---<br class="">
+// 3.4 Divide and Multiply Instructions<br class="">
+//---<br class="">
+<br class="">
+// Divide, W-form<br class="">
+// Latency range of 13-23. Take the average.<br class="">
+def : WriteRes<WriteID32, [THX2T99I1]> {<br class="">
+ let Latency = 18;<br class="">
+ let ResourceCycles = [18];<br class="">
+}<br class="">
+<br class="">
+// Divide, X-form<br class="">
+// Latency range of 13-39. Take the average.<br class="">
+def : WriteRes<WriteID64, [THX2T99I1]> {<br class="">
+ let Latency = 26;<br class="">
+ let ResourceCycles = [26];<br class="">
+}<br class="">
+<br class="">
+// Multiply accumulate, W-form<br class="">
+def : WriteRes<WriteIM32, [THX2T99I012]> { let Latency = 5; }<br class="">
+<br class="">
+// Multiply accumulate, X-form<br class="">
+def : WriteRes<WriteIM64, [THX2T99I012]> { let Latency = 5; }<br class="">
+<br class="">
+// Bitfield extract, two reg<br class="">
+def : WriteRes<WriteExtr, [THX2T99I012]> { let Latency = 1; }<br class="">
+<br class="">
+// Bitfield move, basic<br class="">
+// Bitfield move, insert<br class="">
+// NOTE: Handled by WriteIS.<br class="">
+<br class="">
+// Count leading<br class="">
+def : InstRW<[THX2T99Write_3Cyc_I1], (instregex "^CLS(W|X)r$",<br class="">
+ "^CLZ(W|X)r$")>;<br class="">
+<br class="">
+// Reverse bits/bytes<br class="">
+// NOTE: Handled by WriteI.<br class="">
+<br class="">
+//---<br class="">
+// 3.6 Load Instructions<br class="">
+// 3.10 FP Load Instructions<br class="">
+//---<br class="">
+<br class="">
+// Load register, literal<br class="">
+// Load register, unscaled immed<br class="">
+// Load register, immed unprivileged<br class="">
+// Load register, unsigned immed<br class="">
+def : WriteRes<WriteLD, [THX2T99LS01]> { let Latency = 4; }<br class="">
+<br class="">
+// Load register, immed post-index<br class="">
+// NOTE: Handled by WriteLD, WriteI.<br class="">
+// Load register, immed pre-index<br class="">
+// NOTE: Handled by WriteLD, WriteAdr.<br class="">
+def : WriteRes<WriteAdr, [THX2T99I012]> { let Latency = 1; }<br class="">
+<br class="">
+// Load register offset, basic<br class="">
+// Load register, register offset, scale by 4/8<br class="">
+// Load register, register offset, scale by 2<br class="">
+// Load register offset, extend<br class="">
+// Load register, register offset, extend, scale by 4/8<br class="">
+// Load register, register offset, extend, scale by 2<br class="">
+def THX2T99WriteLDIdx : SchedWriteVariant<[<br class="">
+ SchedVar<ScaledIdxPred, [THX2T99Write_6Cyc_LS01_I012_<wbr class="">I012]>,<br class="">
+ SchedVar<NoSchedPred, [THX2T99Write_5Cyc_LS01_I012]><wbr class="">]>;<br class="">
+def : SchedAlias<WriteLDIdx, THX2T99WriteLDIdx>;<br class="">
+<br class="">
+def THX2T99ReadAdrBase : SchedReadVariant<[<br class="">
+ SchedVar<ScaledIdxPred, [ReadDefault]>,<br class="">
+ SchedVar<NoSchedPred, [ReadDefault]>]>;<br class="">
+def : SchedAlias<ReadAdrBase, THX2T99ReadAdrBase>;<br class="">
+<br class="">
+// Load pair, immed offset, normal<br class="">
+// Load pair, immed offset, signed words, base != SP<br class="">
+// Load pair, immed offset signed words, base = SP<br class="">
+// LDP only breaks into *one* LS micro-op. Thus<br class="">
+// the resources are handling by WriteLD.<br class="">
+def : WriteRes<WriteLDHi, []> {<br class="">
+ let Latency = 5;<br class="">
+}<br class="">
+<br class="">
+// Load pair, immed pre-index, normal<br class="">
+// Load pair, immed pre-index, signed words<br class="">
+// Load pair, immed post-index, normal<br class="">
+// Load pair, immed post-index, signed words<br class="">
+// NOTE: Handled by WriteLD, WriteLDHi, WriteAdr.<br class="">
+<br class="">
+//--<br class="">
+// 3.7 Store Instructions<br class="">
+// 3.11 FP Store Instructions<br class="">
+//--<br class="">
+<br class="">
+// Store register, unscaled immed<br class="">
+// Store register, immed unprivileged<br class="">
+// Store register, unsigned immed<br class="">
+def : WriteRes<WriteST, [THX2T99LS01, THX2T99SD]> {<br class="">
+ let Latency = 1;<br class="">
+ let NumMicroOps = 2;<br class="">
+}<br class="">
+<br class="">
+// Store register, immed post-index<br class="">
+// NOTE: Handled by WriteAdr, WriteST, ReadAdrBase<br class="">
+<br class="">
+// Store register, immed pre-index<br class="">
+// NOTE: Handled by WriteAdr, WriteST<br class="">
+<br class="">
+// Store register, register offset, basic<br class="">
+// Store register, register offset, scaled by 4/8<br class="">
+// Store register, register offset, scaled by 2<br class="">
+// Store register, register offset, extend<br class="">
+// Store register, register offset, extend, scale by 4/8<br class="">
+// Store register, register offset, extend, scale by 1<br class="">
+def : WriteRes<WriteSTIdx, [THX2T99LS01, THX2T99SD, THX2T99I012]> {<br class="">
+ let Latency = 1;<br class="">
+ let NumMicroOps = 3;<br class="">
+}<br class="">
+<br class="">
+// Store pair, immed offset, W-form<br class="">
+// Store pair, immed offset, X-form<br class="">
+def : WriteRes<WriteSTP, [THX2T99LS01, THX2T99SD]> {<br class="">
+ let Latency = 1;<br class="">
+ let NumMicroOps = 2;<br class="">
+}<br class="">
+<br class="">
+// Store pair, immed post-index, W-form<br class="">
+// Store pair, immed post-index, X-form<br class="">
+// Store pair, immed pre-index, W-form<br class="">
+// Store pair, immed pre-index, X-form<br class="">
+// NOTE: Handled by WriteAdr, WriteSTP.<br class="">
+<br class="">
+//---<br class="">
+// 3.8 FP Data Processing Instructions<br class="">
+//---<br class="">
+<br class="">
+// FP absolute value<br class="">
+// FP min/max<br class="">
+// FP negate<br class="">
+def : WriteRes<WriteF, [THX2T99F01]> { let Latency = 5; }<br class="">
+<br class="">
+// FP arithmetic<br class="">
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr class="">, (instregex "^FADD", "^FSUB")>;<br class="">
+<br class="">
+// FP compare<br class="">
+def : WriteRes<WriteFCmp, [THX2T99F01]> { let Latency = 5; }<br class="">
+<br class="">
+// FP divide, S-form<br class="">
+// FP square root, S-form<br class="">
+def : WriteRes<WriteFDiv, [THX2T99F01]> {<br class="">
+ let Latency = 16;<br class="">
+ let ResourceCycles = [8];<br class="">
+}<br class="">
+<br class="">
+// FP divide, D-form<br class="">
+// FP square root, D-form<br class="">
+def : InstRW<[THX2T99Write_23Cyc_<wbr class="">F01], (instrs FDIVDrr, FSQRTDr)>;<br class="">
+<br class="">
+// FP multiply<br class="">
+// FP multiply accumulate<br class="">
+def : WriteRes<WriteFMul, [THX2T99F01]> { let Latency = 6; }<br class="">
+<br class="">
+// FP round to integral<br class="">
+def : InstRW<[THX2T99Write_7Cyc_F01]<wbr class="">,<br class="">
+ (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)"<wbr class="">)>;<br class="">
+<br class="">
+// FP select<br class="">
+def : InstRW<[THX2T99Write_4Cyc_F01]<wbr class="">, (instregex "^FCSEL")>;<br class="">
+<br class="">
+//---<br class="">
+// 3.9 FP Miscellaneous Instructions<br class="">
+//---<br class="">
+<br class="">
+// FP convert, from vec to vec reg<br class="">
+// FP convert, from gen to vec reg<br class="">
+// FP convert, from vec to gen reg<br class="">
+def : WriteRes<WriteFCvt, [THX2T99F01]> { let Latency = 7; }<br class="">
+<br class="">
+// FP move, immed<br class="">
+// FP move, register<br class="">
+def : WriteRes<WriteFImm, [THX2T99F01]> { let Latency = 4; }<br class="">
+<br class="">
+// FP transfer, from gen to vec reg<br class="">
+// FP transfer, from vec to gen reg<br class="">
+def : WriteRes<WriteFCopy, [THX2T99F01]> { let Latency = 4; }<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instrs FMOVXDHighr, FMOVDXHighr)>;<br class="">
+<br class="">
+//---<br class="">
+// 3.12 ASIMD Integer Instructions<br class="">
+//---<br class="">
+<br class="">
+// ASIMD absolute diff, D-form<br class="">
+// ASIMD absolute diff, Q-form<br class="">
+// ASIMD absolute diff accum, D-form<br class="">
+// ASIMD absolute diff accum, Q-form<br class="">
+// ASIMD absolute diff accum long<br class="">
+// ASIMD absolute diff long<br class="">
+// ASIMD arith, basic<br class="">
+// ASIMD arith, complex<br class="">
+// ASIMD compare<br class="">
+// ASIMD logical (AND, BIC, EOR)<br class="">
+// ASIMD max/min, basic<br class="">
+// ASIMD max/min, reduce, 4H/4S<br class="">
+// ASIMD max/min, reduce, 8B/8H<br class="">
+// ASIMD max/min, reduce, 16B<br class="">
+// ASIMD multiply, D-form<br class="">
+// ASIMD multiply, Q-form<br class="">
+// ASIMD multiply accumulate long<br class="">
+// ASIMD multiply accumulate saturating long<br class="">
+// ASIMD multiply long<br class="">
+// ASIMD pairwise add and accumulate<br class="">
+// ASIMD shift accumulate<br class="">
+// ASIMD shift by immed, basic<br class="">
+// ASIMD shift by immed and insert, basic, D-form<br class="">
+// ASIMD shift by immed and insert, basic, Q-form<br class="">
+// ASIMD shift by immed, complex<br class="">
+// ASIMD shift by register, basic, D-form<br class="">
+// ASIMD shift by register, basic, Q-form<br class="">
+// ASIMD shift by register, complex, D-form<br class="">
+// ASIMD shift by register, complex, Q-form<br class="">
+def : WriteRes<WriteV, [THX2T99F01]> { let Latency = 7; }<br class="">
+<br class="">
+// ASIMD arith, reduce, 4H/4S<br class="">
+// ASIMD arith, reduce, 8B/8H<br class="">
+// ASIMD arith, reduce, 16B<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">,<br class="">
+ (instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>;<br class="">
+<br class="">
+// ASIMD logical (MOV, MVN, ORN, ORR)<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^ORRv", "^ORNv", "^NOTv")>;<br class="">
+<br class="">
+// ASIMD polynomial (8x8) multiply long<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instrs PMULLv8i8, PMULLv16i8)>;<br class="">
+<br class="">
+//---<br class="">
+// 3.13 ASIMD Floating-point Instructions<br class="">
+//---<br class="">
+<br class="">
+// ASIMD FP absolute value<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^FABSv")>;<br class="">
+<br class="">
+// ASIMD FP arith, normal, D-form<br class="">
+// ASIMD FP arith, normal, Q-form<br class="">
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr class="">, (instregex "^FABDv", "^FADDv", "^FSUBv")>;<br class="">
+<br class="">
+// ASIMD FP arith,pairwise, D-form<br class="">
+// ASIMD FP arith, pairwise, Q-form<br class="">
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr class="">, (instregex "^FADDPv")>;<br class="">
+<br class="">
+// ASIMD FP compare, D-form<br class="">
+// ASIMD FP compare, Q-form<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^FACGEv", "^FACGTv")>;<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^FCMEQv", "^FCMGEv",<br class="">
+ "^FCMGTv", "^FCMLEv",<br class="">
+ "^FCMLTv")>;<br class="">
+<br class="">
+// ASIMD FP convert, long<br class="">
+// ASIMD FP convert, narrow<br class="">
+// ASIMD FP convert, other, D-form<br class="">
+// ASIMD FP convert, other, Q-form<br class="">
+// NOTE: Handled by WriteV.<br class="">
+<br class="">
+// ASIMD FP divide, D-form, F32<br class="">
+def : InstRW<[THX2T99Write_16Cyc_<wbr class="">F01], (instrs FDIVv2f32)>;<br class="">
+<br class="">
+// ASIMD FP divide, Q-form, F32<br class="">
+def : InstRW<[THX2T99Write_16Cyc_<wbr class="">F01], (instrs FDIVv4f32)>;<br class="">
+<br class="">
+// ASIMD FP divide, Q-form, F64<br class="">
+def : InstRW<[THX2T99Write_23Cyc_<wbr class="">F01], (instrs FDIVv2f64)>;<br class="">
+<br class="">
+// ASIMD FP max/min, normal, D-form<br class="">
+// ASIMD FP max/min, normal, Q-form<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^FMAXv", "^FMAXNMv",<br class="">
+ "^FMINv", "^FMINNMv")>;<br class="">
+<br class="">
+// ASIMD FP max/min, pairwise, D-form<br class="">
+// ASIMD FP max/min, pairwise, Q-form<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^FMAXPv", "^FMAXNMPv",<br class="">
+ "^FMINPv", "^FMINNMPv")>;<br class="">
+<br class="">
+// ASIMD FP max/min, reduce<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^FMAXVv", "^FMAXNMVv",<br class="">
+ "^FMINVv", "^FMINNMVv")>;<br class="">
+<br class="">
+// ASIMD FP multiply, D-form, FZ<br class="">
+// ASIMD FP multiply, D-form, no FZ<br class="">
+// ASIMD FP multiply, Q-form, FZ<br class="">
+// ASIMD FP multiply, Q-form, no FZ<br class="">
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr class="">, (instregex "^FMULv", "^FMULXv")>;<br class="">
+<br class="">
+// ASIMD FP multiply accumulate, Dform, FZ<br class="">
+// ASIMD FP multiply accumulate, Dform, no FZ<br class="">
+// ASIMD FP multiply accumulate, Qform, FZ<br class="">
+// ASIMD FP multiply accumulate, Qform, no FZ<br class="">
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr class="">, (instregex "^FMLAv", "^FMLSv")>;<br class="">
+<br class="">
+// ASIMD FP negate<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^FNEGv")>;<br class="">
+<br class="">
+// ASIMD FP round, D-form<br class="">
+// ASIMD FP round, Q-form<br class="">
+// NOTE: Handled by WriteV.<br class="">
+<br class="">
+//--<br class="">
+// 3.14 ASIMD Miscellaneous Instructions<br class="">
+//--<br class="">
+<br class="">
+// ASIMD bit reverse<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^RBITv")>;<br class="">
+<br class="">
+// ASIMD bitwise insert, D-form<br class="">
+// ASIMD bitwise insert, Q-form<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^BIFv", "^BITv", "^BSLv")>;<br class="">
+<br class="">
+// ASIMD count, D-form<br class="">
+// ASIMD count, Q-form<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^CLSv", "^CLZv", "^CNTv")>;<br class="">
+<br class="">
+// ASIMD duplicate, gen reg<br class="">
+// ASIMD duplicate, element<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^DUPv")>;<br class="">
+<br class="">
+// ASIMD extract<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^EXTv")>;<br class="">
+<br class="">
+// ASIMD extract narrow<br class="">
+// ASIMD extract narrow, saturating<br class="">
+// NOTE: Handled by WriteV.<br class="">
+<br class="">
+// ASIMD insert, element to element<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^INSv")>;<br class="">
+<br class="">
+// ASIMD move, integer immed<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^MOVIv", "^MOVIDv")>;<br class="">
+<br class="">
+// ASIMD move, FP immed<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^FMOVv")>;<br class="">
+<br class="">
+// ASIMD reciprocal estimate, D-form<br class="">
+// ASIMD reciprocal estimate, Q-form<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">,<br class="">
+ (instregex "^FRECPEv", "^FRECPXv", "^URECPEv",<br class="">
+ "^FRSQRTEv", "^URSQRTEv")>;<br class="">
+<br class="">
+// ASIMD reciprocal step, D-form, FZ<br class="">
+// ASIMD reciprocal step, D-form, no FZ<br class="">
+// ASIMD reciprocal step, Q-form, FZ<br class="">
+// ASIMD reciprocal step, Q-form, no FZ<br class="">
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr class="">, (instregex "^FRECPSv", "^FRSQRTSv")>;<br class="">
+<br class="">
+// ASIMD reverse<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">,<br class="">
+ (instregex "^REV16v", "^REV32v", "^REV64v")>;<br class="">
+<br class="">
+// ASIMD table lookup, D-form<br class="">
+// ASIMD table lookup, Q-form<br class="">
+def : InstRW<[THX2T99Write_8Cyc_F01]<wbr class="">, (instregex "^TBLv", "^TBXv")>;<br class="">
+<br class="">
+// ASIMD transfer, element to word or word<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^UMOVv")>;<br class="">
+<br class="">
+// ASIMD transfer, element to gen reg<br class="">
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr class="">, (instregex "^SMOVv", "^UMOVv")>;<br class="">
+<br class="">
+// ASIMD transfer gen reg to element<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^INSv")>;<br class="">
+<br class="">
+// ASIMD transpose<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^TRN1v", "^TRN2v",<br class="">
+ "^UZP1v", "^UZP2v")>;<br class="">
+<br class="">
+// ASIMD unzip/zip<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr class="">, (instregex "^ZIP1v", "^ZIP2v")>;<br class="">
+<br class="">
+//--<br class="">
+// 3.15 ASIMD Load Instructions<br class="">
+//--<br class="">
+<br class="">
+// ASIMD load, 1 element, multiple, 1 reg, D-form<br class="">
+// ASIMD load, 1 element, multiple, 1 reg, Q-form<br class="">
+def : InstRW<[THX2T99Write_4Cyc_<wbr class="">LS01],<br class="">
+ (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_4Cyc_<wbr class="">LS01, WriteAdr],<br class="">
+ (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 1 element, multiple, 2 reg, D-form<br class="">
+// ASIMD load, 1 element, multiple, 2 reg, Q-form<br class="">
+def : InstRW<[THX2T99Write_4Cyc_<wbr class="">LS01],<br class="">
+ (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_4Cyc_<wbr class="">LS01, WriteAdr],<br class="">
+ (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 1 element, multiple, 3 reg, D-form<br class="">
+// ASIMD load, 1 element, multiple, 3 reg, Q-form<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01],<br class="">
+ (instregex "^LD1Threev(8b|4h|2s|1d|16b|<wbr class="">8h|4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01, WriteAdr],<br class="">
+ (instregex "^LD1Threev(8b|4h|2s|1d|16b|<wbr class="">8h|4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 1 element, multiple, 4 reg, D-form<br class="">
+// ASIMD load, 1 element, multiple, 4 reg, Q-form<br class="">
+def : InstRW<[THX2T99Write_6Cyc_<wbr class="">LS01],<br class="">
+ (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_6Cyc_<wbr class="">LS01, WriteAdr],<br class="">
+ (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 1 element, one lane, B/H/S<br class="">
+// ASIMD load, 1 element, one lane, D<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01], (instregex "^LD1i(8|16|32|64)$")>;<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD1i(8|16|32|64)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 1 element, all lanes, D-form, B/H/S<br class="">
+// ASIMD load, 1 element, all lanes, D-form, D<br class="">
+// ASIMD load, 1 element, all lanes, Q-form<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 2 element, multiple, D-form, B/H/S<br class="">
+// ASIMD load, 2 element, multiple, Q-form, D<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 2 element, one lane, B/H<br class="">
+// ASIMD load, 2 element, one lane, S<br class="">
+// ASIMD load, 2 element, one lane, D<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01], (instregex "^LD2i(8|16|32|64)$")>;<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD2i(8|16|32|64)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 2 element, all lanes, D-form, B/H/S<br class="">
+// ASIMD load, 2 element, all lanes, D-form, D<br class="">
+// ASIMD load, 2 element, all lanes, Q-form<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_5Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 3 element, multiple, D-form, B/H/S<br class="">
+// ASIMD load, 3 element, multiple, Q-form, B/H/S<br class="">
+// ASIMD load, 3 element, multiple, Q-form, D<br class="">
+def : InstRW<[THX2T99Write_8Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^LD3Threev(8b|4h|2s|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_8Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD3Threev(8b|4h|2s|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 3 element, one lone, B/H<br class="">
+// ASIMD load, 3 element, one lane, S<br class="">
+// ASIMD load, 3 element, one lane, D<br class="">
+def : InstRW<[THX2T99Write_7Cyc_<wbr class="">LS01_F01], (instregex "^LD3i(8|16|32|64)$")>;<br class="">
+def : InstRW<[THX2T99Write_7Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD3i(8|16|32|64)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 3 element, all lanes, D-form, B/H/S<br class="">
+// ASIMD load, 3 element, all lanes, D-form, D<br class="">
+// ASIMD load, 3 element, all lanes, Q-form, B/H/S<br class="">
+// ASIMD load, 3 element, all lanes, Q-form, D<br class="">
+def : InstRW<[THX2T99Write_7Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_7Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 4 element, multiple, D-form, B/H/S<br class="">
+// ASIMD load, 4 element, multiple, Q-form, B/H/S<br class="">
+// ASIMD load, 4 element, multiple, Q-form, D<br class="">
+def : InstRW<[THX2T99Write_8Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_8Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 4 element, one lane, B/H<br class="">
+// ASIMD load, 4 element, one lane, S<br class="">
+// ASIMD load, 4 element, one lane, D<br class="">
+def : InstRW<[THX2T99Write_6Cyc_<wbr class="">LS01_F01], (instregex "^LD4i(8|16|32|64)$")>;<br class="">
+def : InstRW<[THX2T99Write_6Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD4i(8|16|32|64)_POST$")>;<br class="">
+<br class="">
+// ASIMD load, 4 element, all lanes, D-form, B/H/S<br class="">
+// ASIMD load, 4 element, all lanes, D-form, D<br class="">
+// ASIMD load, 4 element, all lanes, Q-form, B/H/S<br class="">
+// ASIMD load, 4 element, all lanes, Q-form, D<br class="">
+def : InstRW<[THX2T99Write_6Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_6Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
+<br class="">
+//--<br class="">
+// 3.16 ASIMD Store Instructions<br class="">
+//--<br class="">
+<br class="">
+// ASIMD store, 1 element, multiple, 1 reg, D-form<br class="">
+// ASIMD store, 1 element, multiple, 1 reg, Q-form<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01],<br class="">
+ (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01, WriteAdr],<br class="">
+ (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 1 element, multiple, 2 reg, D-form<br class="">
+// ASIMD store, 1 element, multiple, 2 reg, Q-form<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01],<br class="">
+ (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01, WriteAdr],<br class="">
+ (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 1 element, multiple, 3 reg, D-form<br class="">
+// ASIMD store, 1 element, multiple, 3 reg, Q-form<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01],<br class="">
+ (instregex "^ST1Threev(8b|4h|2s|1d|16b|<wbr class="">8h|4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01, WriteAdr],<br class="">
+ (instregex "^ST1Threev(8b|4h|2s|1d|16b|<wbr class="">8h|4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 1 element, multiple, 4 reg, D-form<br class="">
+// ASIMD store, 1 element, multiple, 4 reg, Q-form<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01],<br class="">
+ (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01, WriteAdr],<br class="">
+ (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 1 element, one lane, B/H/S<br class="">
+// ASIMD store, 1 element, one lane, D<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^ST1i(8|16|32|64)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^ST1i(8|16|32|64)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 2 element, multiple, D-form, B/H/S<br class="">
+// ASIMD store, 2 element, multiple, Q-form, B/H/S<br class="">
+// ASIMD store, 2 element, multiple, Q-form, D<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 2 element, one lane, B/H/S<br class="">
+// ASIMD store, 2 element, one lane, D<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^ST2i(8|16|32|64)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^ST2i(8|16|32|64)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 3 element, multiple, D-form, B/H/S<br class="">
+// ASIMD store, 3 element, multiple, Q-form, B/H/S<br class="">
+// ASIMD store, 3 element, multiple, Q-form, D<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^ST3Threev(8b|4h|2s|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^ST3Threev(8b|4h|2s|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 3 element, one lane, B/H<br class="">
+// ASIMD store, 3 element, one lane, S<br class="">
+// ASIMD store, 3 element, one lane, D<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01], (instregex "^ST3i(8|16|32|64)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^ST3i(8|16|32|64)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 4 element, multiple, D-form, B/H/S<br class="">
+// ASIMD store, 4 element, multiple, Q-form, B/H/S<br class="">
+// ASIMD store, 4 element, multiple, Q-form, D<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01],<br class="">
+ (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
+<br class="">
+// ASIMD store, 4 element, one lane, B/H<br class="">
+// ASIMD store, 4 element, one lane, S<br class="">
+// ASIMD store, 4 element, one lane, D<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01], (instregex "^ST4i(8|16|32|64)$")>;<br class="">
+def : InstRW<[THX2T99Write_1Cyc_<wbr class="">LS01_F01, WriteAdr],<br class="">
+ (instregex "^ST4i(8|16|32|64)_POST$")>;<br class="">
+<br class="">
+//--<br class="">
+// 3.17 Cryptography Extensions<br class="">
+//--<br class="">
+<br class="">
+// Crypto AES ops<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^AES")>;<br class="">
+<br class="">
+// Crypto polynomial (64x64) multiply long<br class="">
+def : InstRW<[THX2T99Write_5Cyc_F1], (instrs PMULLv1i64, PMULLv2i64)>;<br class="">
+<br class="">
+// Crypto SHA1 xor ops<br class="">
+// Crypto SHA1 schedule acceleration ops<br class="">
+// Crypto SHA256 schedule acceleration op (1 u-op)<br class="">
+// Crypto SHA256 schedule acceleration op (2 u-ops)<br class="">
+// Crypto SHA256 hash acceleration ops<br class="">
+def : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA")>;<br class="">
+<br class="">
+//--<br class="">
+// 3.18 CRC<br class="">
+//--<br class="">
+<br class="">
+// CRC checksum ops<br class="">
+def : InstRW<[THX2T99Write_4Cyc_I1], (instregex "^CRC32")>;<br class="">
+<br class="">
+} // SchedModel = ThunderX2T99Model<br class="">
<br class="">
Removed: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedVulcan.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedVulcan.td?rev=297189&view=auto" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/AArch64SchedVulcan.td?<wbr class="">rev=297189&view=auto</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedVulcan.td (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64SchedVulcan.td (removed)<br class="">
@@ -1,852 +0,0 @@<br class="">
-//=- AArch64SchedVulcan.td - Vulcan Scheduling Defs ----------*- tablegen -*-=//<br class="">
-//<br class="">
-// The LLVM Compiler Infrastructure<br class="">
-//<br class="">
-// This file is distributed under the University of Illinois Open Source<br class="">
-// License. See LICENSE.TXT for details.<br class="">
-//<br class="">
-//===------------------------<wbr class="">------------------------------<wbr class="">----------------===//<br class="">
-// 1. Introduction<br class="">
-//<br class="">
-// This file defines the machine model for Broadcom Vulcan to support<br class="">
-// instruction scheduling and other instruction cost heuristics.<br class="">
-//<br class="">
-//===------------------------<wbr class="">------------------------------<wbr class="">----------------===//<br class="">
-<br class="">
-//===------------------------<wbr class="">------------------------------<wbr class="">----------------===//<br class="">
-// 2. Pipeline Description.<br class="">
-<br class="">
-def VulcanModel : SchedMachineModel {<br class="">
- let IssueWidth = 4; // 4 micro-ops dispatched at a time.<br class="">
- let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.<br class="">
- let LoadLatency = 4; // Optimistic load latency.<br class="">
- let MispredictPenalty = 12; // Extra cycles for mispredicted branch.<br class="">
- // Determined via a mix of micro-arch details and experimentation.<br class="">
- let LoopMicroOpBufferSize = 32;<br class="">
- let PostRAScheduler = 1; // Using PostRA sched.<br class="">
- let CompleteModel = 1;<br class="">
-}<br class="">
-<br class="">
-// Define the issue ports.<br class="">
-<br class="">
-// Port 0: ALU, FP/SIMD.<br class="">
-def VulcanP0 : ProcResource<1>;<br class="">
-<br class="">
-// Port 1: ALU, FP/SIMD, integer mul/div.<br class="">
-def VulcanP1 : ProcResource<1>;<br class="">
-<br class="">
-// Port 2: ALU, Branch.<br class="">
-def VulcanP2 : ProcResource<1>;<br class="">
-<br class="">
-// Port 3: Store data.<br class="">
-def VulcanP3 : ProcResource<1>;<br class="">
-<br class="">
-// Port 4: Load/store.<br class="">
-def VulcanP4 : ProcResource<1>;<br class="">
-<br class="">
-// Port 5: Load/store.<br class="">
-def VulcanP5 : ProcResource<1>;<br class="">
-<br class="">
-let SchedModel = VulcanModel in {<br class="">
-<br class="">
-// Define groups for the functional units on each issue port. Each group<br class="">
-// created will be used by a WriteRes later on.<br class="">
-//<br class="">
-// NOTE: Some groups only contain one member. This is a way to create names for<br class="">
-// the various functional units that share a single issue port. For example,<br class="">
-// "VulcanI1" for ALU ops on port 1 and "VulcanF1" for FP ops on port 1.<br class="">
-<br class="">
-// Integer divide and multiply micro-ops only on port 1.<br class="">
-def VulcanI1 : ProcResGroup<[VulcanP1]>;<br class="">
-<br class="">
-// Branch micro-ops only on port 2.<br class="">
-def VulcanI2 : ProcResGroup<[VulcanP2]>;<br class="">
-<br class="">
-// ALU micro-ops on ports 0, 1, and 2.<br class="">
-def VulcanI012 : ProcResGroup<[VulcanP0, VulcanP1, VulcanP2]>;<br class="">
-<br class="">
-// Crypto FP/SIMD micro-ops only on port 1.<br class="">
-def VulcanF1 : ProcResGroup<[VulcanP1]>;<br class="">
-<br class="">
-// FP/SIMD micro-ops on ports 0 and 1.<br class="">
-def VulcanF01 : ProcResGroup<[VulcanP0, VulcanP1]>;<br class="">
-<br class="">
-// Store data micro-ops only on port 3.<br class="">
-def VulcanSD : ProcResGroup<[VulcanP3]>;<br class="">
-<br class="">
-// Load/store micro-ops on ports 4 and 5.<br class="">
-def VulcanLS01 : ProcResGroup<[VulcanP4, VulcanP5]>;<br class="">
-<br class="">
-// 60 entry unified scheduler.<br class="">
-def VulcanAny : ProcResGroup<[VulcanP0, VulcanP1, VulcanP2,<br class="">
- VulcanP3, VulcanP4, VulcanP5]> {<br class="">
- let BufferSize=60;<br class="">
-}<br class="">
-<br class="">
-// Define commonly used write types for InstRW specializations.<br class="">
-// All definitions follow the format: VulcanWrite_<NumCycles>Cyc_<<wbr class="">Resources>.<br class="">
-<br class="">
-// 3 cycles on I1.<br class="">
-def VulcanWrite_3Cyc_I1 : SchedWriteRes<[VulcanI1]> { let Latency = 3; }<br class="">
-<br class="">
-// 4 cycles on I1.<br class="">
-def VulcanWrite_4Cyc_I1 : SchedWriteRes<[VulcanI1]> { let Latency = 4; }<br class="">
-<br class="">
-// 1 cycle on I0, I1, or I2.<br class="">
-def VulcanWrite_1Cyc_I012 : SchedWriteRes<[VulcanI012]> { let Latency = 1; }<br class="">
-<br class="">
-// 5 cycles on F1.<br class="">
-def VulcanWrite_5Cyc_F1 : SchedWriteRes<[VulcanF1]> { let Latency = 5; }<br class="">
-<br class="">
-// 7 cycles on F1.<br class="">
-def VulcanWrite_7Cyc_F1 : SchedWriteRes<[VulcanF1]> { let Latency = 7; }<br class="">
-<br class="">
-// 4 cycles on F0 or F1.<br class="">
-def VulcanWrite_4Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 4; }<br class="">
-<br class="">
-// 5 cycles on F0 or F1.<br class="">
-def VulcanWrite_5Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 5; }<br class="">
-<br class="">
-// 6 cycles on F0 or F1.<br class="">
-def VulcanWrite_6Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 6; }<br class="">
-<br class="">
-// 7 cycles on F0 or F1.<br class="">
-def VulcanWrite_7Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 7; }<br class="">
-<br class="">
-// 8 cycles on F0 or F1.<br class="">
-def VulcanWrite_8Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 8; }<br class="">
-<br class="">
-// 16 cycles on F0 or F1.<br class="">
-def VulcanWrite_16Cyc_F01 : SchedWriteRes<[VulcanF01]> {<br class="">
- let Latency = 16;<br class="">
- let ResourceCycles = [8];<br class="">
-}<br class="">
-<br class="">
-// 23 cycles on F0 or F1.<br class="">
-def VulcanWrite_23Cyc_F01 : SchedWriteRes<[VulcanF01]> {<br class="">
- let Latency = 23;<br class="">
- let ResourceCycles = [11];<br class="">
-}<br class="">
-<br class="">
-// 1 cycles on LS0 or LS1.<br class="">
-def VulcanWrite_1Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 1; }<br class="">
-<br class="">
-// 4 cycles on LS0 or LS1.<br class="">
-def VulcanWrite_4Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 4; }<br class="">
-<br class="">
-// 5 cycles on LS0 or LS1.<br class="">
-def VulcanWrite_5Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 5; }<br class="">
-<br class="">
-// 6 cycles on LS0 or LS1.<br class="">
-def VulcanWrite_6Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 6; }<br class="">
-<br class="">
-// 5 cycles on LS0 or LS1 and I0, I1, or I2.<br class="">
-def VulcanWrite_5Cyc_LS01_I012 : SchedWriteRes<[VulcanLS01, VulcanI012]> {<br class="">
- let Latency = 5;<br class="">
- let NumMicroOps = 2;<br class="">
-}<br class="">
-<br class="">
-// 5 cycles on LS0 or LS1 and 2 of I0, I1, or I2.<br class="">
-def VulcanWrite_6Cyc_LS01_I012_<wbr class="">I012 :<br class="">
- SchedWriteRes<[VulcanLS01, VulcanI012, VulcanI012]> {<br class="">
- let Latency = 6;<br class="">
- let NumMicroOps = 3;<br class="">
-}<br class="">
-<br class="">
-// 1 cycles on LS0 or LS1 and F0 or F1.<br class="">
-def VulcanWrite_1Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br class="">
- let Latency = 1;<br class="">
- let NumMicroOps = 2;<br class="">
-}<br class="">
-<br class="">
-// 5 cycles on LS0 or LS1 and F0 or F1.<br class="">
-def VulcanWrite_5Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br class="">
- let Latency = 5;<br class="">
- let NumMicroOps = 2;<br class="">
-}<br class="">
-<br class="">
-// 6 cycles on LS0 or LS1 and F0 or F1.<br class="">
-def VulcanWrite_6Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br class="">
- let Latency = 6;<br class="">
- let NumMicroOps = 2;<br class="">
-}<br class="">
-<br class="">
-// 7 cycles on LS0 or LS1 and F0 or F1.<br class="">
-def VulcanWrite_7Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br class="">
- let Latency = 7;<br class="">
- let NumMicroOps = 2;<br class="">
-}<br class="">
-<br class="">
-// 8 cycles on LS0 or LS1 and F0 or F1.<br class="">
-def VulcanWrite_8Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br class="">
- let Latency = 8;<br class="">
- let NumMicroOps = 2;<br class="">
-}<br class="">
-<br class="">
-// Define commonly used read types.<br class="">
-<br class="">
-// No forwarding is provided for these types.<br class="">
-def : ReadAdvance<ReadI, 0>;<br class="">
-def : ReadAdvance<ReadISReg, 0>;<br class="">
-def : ReadAdvance<ReadIEReg, 0>;<br class="">
-def : ReadAdvance<ReadIM, 0>;<br class="">
-def : ReadAdvance<ReadIMA, 0>;<br class="">
-def : ReadAdvance<ReadID, 0>;<br class="">
-def : ReadAdvance<ReadExtrHi, 0>;<br class="">
-def : ReadAdvance<ReadAdrBase, 0>;<br class="">
-def : ReadAdvance<ReadVLD, 0>;<br class="">
-<br class="">
-}<br class="">
-<br class="">
-<br class="">
-//===------------------------<wbr class="">------------------------------<wbr class="">----------------===//<br class="">
-// 3. Instruction Tables.<br class="">
-<br class="">
-let SchedModel = VulcanModel in {<br class="">
-<br class="">
-//---<br class="">
-// 3.1 Branch Instructions<br class="">
-//---<br class="">
-<br class="">
-// Branch, immed<br class="">
-// Branch and link, immed<br class="">
-// Compare and branch<br class="">
-def : WriteRes<WriteBr, [VulcanI2]> { let Latency = 1; }<br class="">
-<br class="">
-def : WriteRes<WriteSys, []> { let Latency = 1; }<br class="">
-def : WriteRes<WriteBarrier, []> { let Latency = 1; }<br class="">
-def : WriteRes<WriteHint, []> { let Latency = 1; }<br class="">
-<br class="">
-def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }<br class="">
-<br class="">
-// Branch, register<br class="">
-// Branch and link, register != LR<br class="">
-// Branch and link, register = LR<br class="">
-def : WriteRes<WriteBrReg, [VulcanI2]> { let Latency = 1; }<br class="">
-<br class="">
-//---<br class="">
-// 3.2 Arithmetic and Logical Instructions<br class="">
-// 3.3 Move and Shift Instructions<br class="">
-//---<br class="">
-<br class="">
-// ALU, basic<br class="">
-// Conditional compare<br class="">
-// Conditional select<br class="">
-// Address generation<br class="">
-def : WriteRes<WriteI, [VulcanI012]> { let Latency = 1; }<br class="">
-def : InstRW<[WriteI], (instrs COPY)>;<br class="">
-<br class="">
-// ALU, extend and/or shift<br class="">
-def : WriteRes<WriteISReg, [VulcanI012]> {<br class="">
- let Latency = 2;<br class="">
- let ResourceCycles = [2];<br class="">
-}<br class="">
-<br class="">
-def : WriteRes<WriteIEReg, [VulcanI012]> {<br class="">
- let Latency = 2;<br class="">
- let ResourceCycles = [2];<br class="">
-}<br class="">
-<br class="">
-// Move immed<br class="">
-def : WriteRes<WriteImm, [VulcanI012]> { let Latency = 1; }<br class="">
-<br class="">
-// Variable shift<br class="">
-def : WriteRes<WriteIS, [VulcanI012]> { let Latency = 1; }<br class="">
-<br class="">
-//---<br class="">
-// 3.4 Divide and Multiply Instructions<br class="">
-//---<br class="">
-<br class="">
-// Divide, W-form<br class="">
-// Latency range of 13-23. Take the average.<br class="">
-def : WriteRes<WriteID32, [VulcanI1]> {<br class="">
- let Latency = 18;<br class="">
- let ResourceCycles = [18];<br class="">
-}<br class="">
-<br class="">
-// Divide, X-form<br class="">
-// Latency range of 13-39. Take the average.<br class="">
-def : WriteRes<WriteID64, [VulcanI1]> {<br class="">
- let Latency = 26;<br class="">
- let ResourceCycles = [26];<br class="">
-}<br class="">
-<br class="">
-// Multiply accumulate, W-form<br class="">
-def : WriteRes<WriteIM32, [VulcanI012]> { let Latency = 5; }<br class="">
-<br class="">
-// Multiply accumulate, X-form<br class="">
-def : WriteRes<WriteIM64, [VulcanI012]> { let Latency = 5; }<br class="">
-<br class="">
-// Bitfield extract, two reg<br class="">
-def : WriteRes<WriteExtr, [VulcanI012]> { let Latency = 1; }<br class="">
-<br class="">
-// Bitfield move, basic<br class="">
-// Bitfield move, insert<br class="">
-// NOTE: Handled by WriteIS.<br class="">
-<br class="">
-// Count leading<br class="">
-def : InstRW<[VulcanWrite_3Cyc_I1], (instregex "^CLS(W|X)r$",<br class="">
- "^CLZ(W|X)r$")>;<br class="">
-<br class="">
-// Reverse bits/bytes<br class="">
-// NOTE: Handled by WriteI.<br class="">
-<br class="">
-//---<br class="">
-// 3.6 Load Instructions<br class="">
-// 3.10 FP Load Instructions<br class="">
-//---<br class="">
-<br class="">
-// Load register, literal<br class="">
-// Load register, unscaled immed<br class="">
-// Load register, immed unprivileged<br class="">
-// Load register, unsigned immed<br class="">
-def : WriteRes<WriteLD, [VulcanLS01]> { let Latency = 4; }<br class="">
-<br class="">
-// Load register, immed post-index<br class="">
-// NOTE: Handled by WriteLD, WriteI.<br class="">
-// Load register, immed pre-index<br class="">
-// NOTE: Handled by WriteLD, WriteAdr.<br class="">
-def : WriteRes<WriteAdr, [VulcanI012]> { let Latency = 1; }<br class="">
-<br class="">
-// Load register offset, basic<br class="">
-// Load register, register offset, scale by 4/8<br class="">
-// Load register, register offset, scale by 2<br class="">
-// Load register offset, extend<br class="">
-// Load register, register offset, extend, scale by 4/8<br class="">
-// Load register, register offset, extend, scale by 2<br class="">
-def VulcanWriteLDIdx : SchedWriteVariant<[<br class="">
- SchedVar<ScaledIdxPred, [VulcanWrite_6Cyc_LS01_I012_<wbr class="">I012]>,<br class="">
- SchedVar<NoSchedPred, [VulcanWrite_5Cyc_LS01_I012]>]<wbr class="">>;<br class="">
-def : SchedAlias<WriteLDIdx, VulcanWriteLDIdx>;<br class="">
-<br class="">
-def VulcanReadAdrBase : SchedReadVariant<[<br class="">
- SchedVar<ScaledIdxPred, [ReadDefault]>,<br class="">
- SchedVar<NoSchedPred, [ReadDefault]>]>;<br class="">
-def : SchedAlias<ReadAdrBase, VulcanReadAdrBase>;<br class="">
-<br class="">
-// Load pair, immed offset, normal<br class="">
-// Load pair, immed offset, signed words, base != SP<br class="">
-// Load pair, immed offset signed words, base = SP<br class="">
-// LDP only breaks into *one* LS micro-op. Thus<br class="">
-// the resources are handling by WriteLD.<br class="">
-def : WriteRes<WriteLDHi, []> {<br class="">
- let Latency = 5;<br class="">
-}<br class="">
-<br class="">
-// Load pair, immed pre-index, normal<br class="">
-// Load pair, immed pre-index, signed words<br class="">
-// Load pair, immed post-index, normal<br class="">
-// Load pair, immed post-index, signed words<br class="">
-// NOTE: Handled by WriteLD, WriteLDHi, WriteAdr.<br class="">
-<br class="">
-//--<br class="">
-// 3.7 Store Instructions<br class="">
-// 3.11 FP Store Instructions<br class="">
-//--<br class="">
-<br class="">
-// Store register, unscaled immed<br class="">
-// Store register, immed unprivileged<br class="">
-// Store register, unsigned immed<br class="">
-def : WriteRes<WriteST, [VulcanLS01, VulcanSD]> {<br class="">
- let Latency = 1;<br class="">
- let NumMicroOps = 2;<br class="">
-}<br class="">
-<br class="">
-// Store register, immed post-index<br class="">
-// NOTE: Handled by WriteAdr, WriteST, ReadAdrBase<br class="">
-<br class="">
-// Store register, immed pre-index<br class="">
-// NOTE: Handled by WriteAdr, WriteST<br class="">
-<br class="">
-// Store register, register offset, basic<br class="">
-// Store register, register offset, scaled by 4/8<br class="">
-// Store register, register offset, scaled by 2<br class="">
-// Store register, register offset, extend<br class="">
-// Store register, register offset, extend, scale by 4/8<br class="">
-// Store register, register offset, extend, scale by 1<br class="">
-def : WriteRes<WriteSTIdx, [VulcanLS01, VulcanSD, VulcanI012]> {<br class="">
- let Latency = 1;<br class="">
- let NumMicroOps = 3;<br class="">
-}<br class="">
-<br class="">
-// Store pair, immed offset, W-form<br class="">
-// Store pair, immed offset, X-form<br class="">
-def : WriteRes<WriteSTP, [VulcanLS01, VulcanSD]> {<br class="">
- let Latency = 1;<br class="">
- let NumMicroOps = 2;<br class="">
-}<br class="">
-<br class="">
-// Store pair, immed post-index, W-form<br class="">
-// Store pair, immed post-index, X-form<br class="">
-// Store pair, immed pre-index, W-form<br class="">
-// Store pair, immed pre-index, X-form<br class="">
-// NOTE: Handled by WriteAdr, WriteSTP.<br class="">
-<br class="">
-//---<br class="">
-// 3.8 FP Data Processing Instructions<br class="">
-//---<br class="">
-<br class="">
-// FP absolute value<br class="">
-// FP min/max<br class="">
-// FP negate<br class="">
-def : WriteRes<WriteF, [VulcanF01]> { let Latency = 5; }<br class="">
-<br class="">
-// FP arithmetic<br class="">
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FADD", "^FSUB")>;<br class="">
-<br class="">
-// FP compare<br class="">
-def : WriteRes<WriteFCmp, [VulcanF01]> { let Latency = 5; }<br class="">
-<br class="">
-// FP divide, S-form<br class="">
-// FP square root, S-form<br class="">
-def : WriteRes<WriteFDiv, [VulcanF01]> {<br class="">
- let Latency = 16;<br class="">
- let ResourceCycles = [8];<br class="">
-}<br class="">
-<br class="">
-// FP divide, D-form<br class="">
-// FP square root, D-form<br class="">
-def : InstRW<[VulcanWrite_23Cyc_F01]<wbr class="">, (instrs FDIVDrr, FSQRTDr)>;<br class="">
-<br class="">
-// FP multiply<br class="">
-// FP multiply accumulate<br class="">
-def : WriteRes<WriteFMul, [VulcanF01]> { let Latency = 6; }<br class="">
-<br class="">
-// FP round to integral<br class="">
-def : InstRW<[VulcanWrite_7Cyc_F01],<br class="">
- (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)"<wbr class="">)>;<br class="">
-<br class="">
-// FP select<br class="">
-def : InstRW<[VulcanWrite_4Cyc_F01], (instregex "^FCSEL")>;<br class="">
-<br class="">
-//---<br class="">
-// 3.9 FP Miscellaneous Instructions<br class="">
-//---<br class="">
-<br class="">
-// FP convert, from vec to vec reg<br class="">
-// FP convert, from gen to vec reg<br class="">
-// FP convert, from vec to gen reg<br class="">
-def : WriteRes<WriteFCvt, [VulcanF01]> { let Latency = 7; }<br class="">
-<br class="">
-// FP move, immed<br class="">
-// FP move, register<br class="">
-def : WriteRes<WriteFImm, [VulcanF01]> { let Latency = 4; }<br class="">
-<br class="">
-// FP transfer, from gen to vec reg<br class="">
-// FP transfer, from vec to gen reg<br class="">
-def : WriteRes<WriteFCopy, [VulcanF01]> { let Latency = 4; }<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;<br class="">
-<br class="">
-//---<br class="">
-// 3.12 ASIMD Integer Instructions<br class="">
-//---<br class="">
-<br class="">
-// ASIMD absolute diff, D-form<br class="">
-// ASIMD absolute diff, Q-form<br class="">
-// ASIMD absolute diff accum, D-form<br class="">
-// ASIMD absolute diff accum, Q-form<br class="">
-// ASIMD absolute diff accum long<br class="">
-// ASIMD absolute diff long<br class="">
-// ASIMD arith, basic<br class="">
-// ASIMD arith, complex<br class="">
-// ASIMD compare<br class="">
-// ASIMD logical (AND, BIC, EOR)<br class="">
-// ASIMD max/min, basic<br class="">
-// ASIMD max/min, reduce, 4H/4S<br class="">
-// ASIMD max/min, reduce, 8B/8H<br class="">
-// ASIMD max/min, reduce, 16B<br class="">
-// ASIMD multiply, D-form<br class="">
-// ASIMD multiply, Q-form<br class="">
-// ASIMD multiply accumulate long<br class="">
-// ASIMD multiply accumulate saturating long<br class="">
-// ASIMD multiply long<br class="">
-// ASIMD pairwise add and accumulate<br class="">
-// ASIMD shift accumulate<br class="">
-// ASIMD shift by immed, basic<br class="">
-// ASIMD shift by immed and insert, basic, D-form<br class="">
-// ASIMD shift by immed and insert, basic, Q-form<br class="">
-// ASIMD shift by immed, complex<br class="">
-// ASIMD shift by register, basic, D-form<br class="">
-// ASIMD shift by register, basic, Q-form<br class="">
-// ASIMD shift by register, complex, D-form<br class="">
-// ASIMD shift by register, complex, Q-form<br class="">
-def : WriteRes<WriteV, [VulcanF01]> { let Latency = 7; }<br class="">
-<br class="">
-// ASIMD arith, reduce, 4H/4S<br class="">
-// ASIMD arith, reduce, 8B/8H<br class="">
-// ASIMD arith, reduce, 16B<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01],<br class="">
- (instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>;<br class="">
-<br class="">
-// ASIMD logical (MOV, MVN, ORN, ORR)<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^ORRv", "^ORNv", "^NOTv")>;<br class="">
-<br class="">
-// ASIMD polynomial (8x8) multiply long<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instrs PMULLv8i8, PMULLv16i8)>;<br class="">
-<br class="">
-//---<br class="">
-// 3.13 ASIMD Floating-point Instructions<br class="">
-//---<br class="">
-<br class="">
-// ASIMD FP absolute value<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FABSv")>;<br class="">
-<br class="">
-// ASIMD FP arith, normal, D-form<br class="">
-// ASIMD FP arith, normal, Q-form<br class="">
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FABDv", "^FADDv", "^FSUBv")>;<br class="">
-<br class="">
-// ASIMD FP arith,pairwise, D-form<br class="">
-// ASIMD FP arith, pairwise, Q-form<br class="">
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FADDPv")>;<br class="">
-<br class="">
-// ASIMD FP compare, D-form<br class="">
-// ASIMD FP compare, Q-form<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FACGEv", "^FACGTv")>;<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FCMEQv", "^FCMGEv",<br class="">
- "^FCMGTv", "^FCMLEv",<br class="">
- "^FCMLTv")>;<br class="">
-<br class="">
-// ASIMD FP convert, long<br class="">
-// ASIMD FP convert, narrow<br class="">
-// ASIMD FP convert, other, D-form<br class="">
-// ASIMD FP convert, other, Q-form<br class="">
-// NOTE: Handled by WriteV.<br class="">
-<br class="">
-// ASIMD FP divide, D-form, F32<br class="">
-def : InstRW<[VulcanWrite_16Cyc_F01]<wbr class="">, (instrs FDIVv2f32)>;<br class="">
-<br class="">
-// ASIMD FP divide, Q-form, F32<br class="">
-def : InstRW<[VulcanWrite_16Cyc_F01]<wbr class="">, (instrs FDIVv4f32)>;<br class="">
-<br class="">
-// ASIMD FP divide, Q-form, F64<br class="">
-def : InstRW<[VulcanWrite_23Cyc_F01]<wbr class="">, (instrs FDIVv2f64)>;<br class="">
-<br class="">
-// ASIMD FP max/min, normal, D-form<br class="">
-// ASIMD FP max/min, normal, Q-form<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMAXv", "^FMAXNMv",<br class="">
- "^FMINv", "^FMINNMv")>;<br class="">
-<br class="">
-// ASIMD FP max/min, pairwise, D-form<br class="">
-// ASIMD FP max/min, pairwise, Q-form<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMAXPv", "^FMAXNMPv",<br class="">
- "^FMINPv", "^FMINNMPv")>;<br class="">
-<br class="">
-// ASIMD FP max/min, reduce<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMAXVv", "^FMAXNMVv",<br class="">
- "^FMINVv", "^FMINNMVv")>;<br class="">
-<br class="">
-// ASIMD FP multiply, D-form, FZ<br class="">
-// ASIMD FP multiply, D-form, no FZ<br class="">
-// ASIMD FP multiply, Q-form, FZ<br class="">
-// ASIMD FP multiply, Q-form, no FZ<br class="">
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FMULv", "^FMULXv")>;<br class="">
-<br class="">
-// ASIMD FP multiply accumulate, Dform, FZ<br class="">
-// ASIMD FP multiply accumulate, Dform, no FZ<br class="">
-// ASIMD FP multiply accumulate, Qform, FZ<br class="">
-// ASIMD FP multiply accumulate, Qform, no FZ<br class="">
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FMLAv", "^FMLSv")>;<br class="">
-<br class="">
-// ASIMD FP negate<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FNEGv")>;<br class="">
-<br class="">
-// ASIMD FP round, D-form<br class="">
-// ASIMD FP round, Q-form<br class="">
-// NOTE: Handled by WriteV.<br class="">
-<br class="">
-//--<br class="">
-// 3.14 ASIMD Miscellaneous Instructions<br class="">
-//--<br class="">
-<br class="">
-// ASIMD bit reverse<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^RBITv")>;<br class="">
-<br class="">
-// ASIMD bitwise insert, D-form<br class="">
-// ASIMD bitwise insert, Q-form<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^BIFv", "^BITv", "^BSLv")>;<br class="">
-<br class="">
-// ASIMD count, D-form<br class="">
-// ASIMD count, Q-form<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^CLSv", "^CLZv", "^CNTv")>;<br class="">
-<br class="">
-// ASIMD duplicate, gen reg<br class="">
-// ASIMD duplicate, element<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^DUPv")>;<br class="">
-<br class="">
-// ASIMD extract<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^EXTv")>;<br class="">
-<br class="">
-// ASIMD extract narrow<br class="">
-// ASIMD extract narrow, saturating<br class="">
-// NOTE: Handled by WriteV.<br class="">
-<br class="">
-// ASIMD insert, element to element<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^INSv")>;<br class="">
-<br class="">
-// ASIMD move, integer immed<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^MOVIv", "^MOVIDv")>;<br class="">
-<br class="">
-// ASIMD move, FP immed<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMOVv")>;<br class="">
-<br class="">
-// ASIMD reciprocal estimate, D-form<br class="">
-// ASIMD reciprocal estimate, Q-form<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01],<br class="">
- (instregex "^FRECPEv", "^FRECPXv", "^URECPEv",<br class="">
- "^FRSQRTEv", "^URSQRTEv")>;<br class="">
-<br class="">
-// ASIMD reciprocal step, D-form, FZ<br class="">
-// ASIMD reciprocal step, D-form, no FZ<br class="">
-// ASIMD reciprocal step, Q-form, FZ<br class="">
-// ASIMD reciprocal step, Q-form, no FZ<br class="">
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FRECPSv", "^FRSQRTSv")>;<br class="">
-<br class="">
-// ASIMD reverse<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01],<br class="">
- (instregex "^REV16v", "^REV32v", "^REV64v")>;<br class="">
-<br class="">
-// ASIMD table lookup, D-form<br class="">
-// ASIMD table lookup, Q-form<br class="">
-def : InstRW<[VulcanWrite_8Cyc_F01], (instregex "^TBLv", "^TBXv")>;<br class="">
-<br class="">
-// ASIMD transfer, element to word or word<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^UMOVv")>;<br class="">
-<br class="">
-// ASIMD transfer, element to gen reg<br class="">
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^SMOVv", "^UMOVv")>;<br class="">
-<br class="">
-// ASIMD transfer gen reg to element<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^INSv")>;<br class="">
-<br class="">
-// ASIMD transpose<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^TRN1v", "^TRN2v",<br class="">
- "^UZP1v", "^UZP2v")>;<br class="">
-<br class="">
-// ASIMD unzip/zip<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^ZIP1v", "^ZIP2v")>;<br class="">
-<br class="">
-//--<br class="">
-// 3.15 ASIMD Load Instructions<br class="">
-//--<br class="">
-<br class="">
-// ASIMD load, 1 element, multiple, 1 reg, D-form<br class="">
-// ASIMD load, 1 element, multiple, 1 reg, Q-form<br class="">
-def : InstRW<[VulcanWrite_4Cyc_LS01]<wbr class="">,<br class="">
- (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_4Cyc_LS01, WriteAdr],<br class="">
- (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 1 element, multiple, 2 reg, D-form<br class="">
-// ASIMD load, 1 element, multiple, 2 reg, Q-form<br class="">
-def : InstRW<[VulcanWrite_4Cyc_LS01]<wbr class="">,<br class="">
- (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_4Cyc_LS01, WriteAdr],<br class="">
- (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 1 element, multiple, 3 reg, D-form<br class="">
-// ASIMD load, 1 element, multiple, 3 reg, Q-form<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01]<wbr class="">,<br class="">
- (instregex "^LD1Threev(8b|4h|2s|1d|16b|<wbr class="">8h|4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01, WriteAdr],<br class="">
- (instregex "^LD1Threev(8b|4h|2s|1d|16b|<wbr class="">8h|4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 1 element, multiple, 4 reg, D-form<br class="">
-// ASIMD load, 1 element, multiple, 4 reg, Q-form<br class="">
-def : InstRW<[VulcanWrite_6Cyc_LS01]<wbr class="">,<br class="">
- (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_6Cyc_LS01, WriteAdr],<br class="">
- (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 1 element, one lane, B/H/S<br class="">
-// ASIMD load, 1 element, one lane, D<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01], (instregex "^LD1i(8|16|32|64)$")>;<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD1i(8|16|32|64)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 1 element, all lanes, D-form, B/H/S<br class="">
-// ASIMD load, 1 element, all lanes, D-form, D<br class="">
-// ASIMD load, 1 element, all lanes, Q-form<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 2 element, multiple, D-form, B/H/S<br class="">
-// ASIMD load, 2 element, multiple, Q-form, D<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 2 element, one lane, B/H<br class="">
-// ASIMD load, 2 element, one lane, S<br class="">
-// ASIMD load, 2 element, one lane, D<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01], (instregex "^LD2i(8|16|32|64)$")>;<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD2i(8|16|32|64)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 2 element, all lanes, D-form, B/H/S<br class="">
-// ASIMD load, 2 element, all lanes, D-form, D<br class="">
-// ASIMD load, 2 element, all lanes, Q-form<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 3 element, multiple, D-form, B/H/S<br class="">
-// ASIMD load, 3 element, multiple, Q-form, B/H/S<br class="">
-// ASIMD load, 3 element, multiple, Q-form, D<br class="">
-def : InstRW<[VulcanWrite_8Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^LD3Threev(8b|4h|2s|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_8Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD3Threev(8b|4h|2s|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 3 element, one lone, B/H<br class="">
-// ASIMD load, 3 element, one lane, S<br class="">
-// ASIMD load, 3 element, one lane, D<br class="">
-def : InstRW<[VulcanWrite_7Cyc_LS01_<wbr class="">F01], (instregex "^LD3i(8|16|32|64)$")>;<br class="">
-def : InstRW<[VulcanWrite_7Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD3i(8|16|32|64)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 3 element, all lanes, D-form, B/H/S<br class="">
-// ASIMD load, 3 element, all lanes, D-form, D<br class="">
-// ASIMD load, 3 element, all lanes, Q-form, B/H/S<br class="">
-// ASIMD load, 3 element, all lanes, Q-form, D<br class="">
-def : InstRW<[VulcanWrite_7Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_7Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 4 element, multiple, D-form, B/H/S<br class="">
-// ASIMD load, 4 element, multiple, Q-form, B/H/S<br class="">
-// ASIMD load, 4 element, multiple, Q-form, D<br class="">
-def : InstRW<[VulcanWrite_8Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_8Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 4 element, one lane, B/H<br class="">
-// ASIMD load, 4 element, one lane, S<br class="">
-// ASIMD load, 4 element, one lane, D<br class="">
-def : InstRW<[VulcanWrite_6Cyc_LS01_<wbr class="">F01], (instregex "^LD4i(8|16|32|64)$")>;<br class="">
-def : InstRW<[VulcanWrite_6Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD4i(8|16|32|64)_POST$")>;<br class="">
-<br class="">
-// ASIMD load, 4 element, all lanes, D-form, B/H/S<br class="">
-// ASIMD load, 4 element, all lanes, D-form, D<br class="">
-// ASIMD load, 4 element, all lanes, Q-form, B/H/S<br class="">
-// ASIMD load, 4 element, all lanes, Q-form, D<br class="">
-def : InstRW<[VulcanWrite_6Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_6Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
-<br class="">
-//--<br class="">
-// 3.16 ASIMD Store Instructions<br class="">
-//--<br class="">
-<br class="">
-// ASIMD store, 1 element, multiple, 1 reg, D-form<br class="">
-// ASIMD store, 1 element, multiple, 1 reg, Q-form<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01]<wbr class="">,<br class="">
- (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],<br class="">
- (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 1 element, multiple, 2 reg, D-form<br class="">
-// ASIMD store, 1 element, multiple, 2 reg, Q-form<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01]<wbr class="">,<br class="">
- (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],<br class="">
- (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 1 element, multiple, 3 reg, D-form<br class="">
-// ASIMD store, 1 element, multiple, 3 reg, Q-form<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01]<wbr class="">,<br class="">
- (instregex "^ST1Threev(8b|4h|2s|1d|16b|<wbr class="">8h|4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],<br class="">
- (instregex "^ST1Threev(8b|4h|2s|1d|16b|<wbr class="">8h|4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 1 element, multiple, 4 reg, D-form<br class="">
-// ASIMD store, 1 element, multiple, 4 reg, Q-form<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01]<wbr class="">,<br class="">
- (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],<br class="">
- (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 1 element, one lane, B/H/S<br class="">
-// ASIMD store, 1 element, one lane, D<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^ST1i(8|16|32|64)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^ST1i(8|16|32|64)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 2 element, multiple, D-form, B/H/S<br class="">
-// ASIMD store, 2 element, multiple, Q-form, B/H/S<br class="">
-// ASIMD store, 2 element, multiple, Q-form, D<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 2 element, one lane, B/H/S<br class="">
-// ASIMD store, 2 element, one lane, D<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^ST2i(8|16|32|64)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^ST2i(8|16|32|64)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 3 element, multiple, D-form, B/H/S<br class="">
-// ASIMD store, 3 element, multiple, Q-form, B/H/S<br class="">
-// ASIMD store, 3 element, multiple, Q-form, D<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^ST3Threev(8b|4h|2s|16b|8h|<wbr class="">4s|2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^ST3Threev(8b|4h|2s|16b|8h|<wbr class="">4s|2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 3 element, one lane, B/H<br class="">
-// ASIMD store, 3 element, one lane, S<br class="">
-// ASIMD store, 3 element, one lane, D<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01], (instregex "^ST3i(8|16|32|64)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^ST3i(8|16|32|64)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 4 element, multiple, D-form, B/H/S<br class="">
-// ASIMD store, 4 element, multiple, Q-form, B/H/S<br class="">
-// ASIMD store, 4 element, multiple, Q-form, D<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01],<br class="">
- (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|<wbr class="">2d)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|<wbr class="">2d)_POST$")>;<br class="">
-<br class="">
-// ASIMD store, 4 element, one lane, B/H<br class="">
-// ASIMD store, 4 element, one lane, S<br class="">
-// ASIMD store, 4 element, one lane, D<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01], (instregex "^ST4i(8|16|32|64)$")>;<br class="">
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr class="">F01, WriteAdr],<br class="">
- (instregex "^ST4i(8|16|32|64)_POST$")>;<br class="">
-<br class="">
-//--<br class="">
-// 3.17 Cryptography Extensions<br class="">
-//--<br class="">
-<br class="">
-// Crypto AES ops<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F1], (instregex "^AES")>;<br class="">
-<br class="">
-// Crypto polynomial (64x64) multiply long<br class="">
-def : InstRW<[VulcanWrite_5Cyc_F1], (instrs PMULLv1i64, PMULLv2i64)>;<br class="">
-<br class="">
-// Crypto SHA1 xor ops<br class="">
-// Crypto SHA1 schedule acceleration ops<br class="">
-// Crypto SHA256 schedule acceleration op (1 u-op)<br class="">
-// Crypto SHA256 schedule acceleration op (2 u-ops)<br class="">
-// Crypto SHA256 hash acceleration ops<br class="">
-def : InstRW<[VulcanWrite_7Cyc_F1], (instregex "^SHA")>;<br class="">
-<br class="">
-//--<br class="">
-// 3.18 CRC<br class="">
-//--<br class="">
-<br class="">
-// CRC checksum ops<br class="">
-def : InstRW<[VulcanWrite_4Cyc_I1], (instregex "^CRC32")>;<br class="">
-<br class="">
-} // SchedModel = VulcanModel<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64Subtarget.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/AArch64Subtarget.cpp?<wbr class="">rev=297190&r1=297189&r2=<wbr class="">297190&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64Subtarget.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64Subtarget.cpp Tue Mar 7 13:42:40 2017<br class="">
@@ -81,16 +81,22 @@ void AArch64Subtarget::<wbr class="">initializePropert<br class="">
MinPrefetchStride = 1024;<br class="">
MaxPrefetchIterationsAhead = 11;<br class="">
break;<br class="">
- case Vulcan:<br class="">
+ case ThunderX2T99:<br class="">
+ CacheLineSize = 64;<br class="">
+ PrefFunctionAlignment = 3;<br class="">
+ PrefLoopAlignment = 2;<br class="">
MaxInterleaveFactor = 4;<br class="">
+ PrefetchDistance = 128;<br class="">
+ MinPrefetchStride = 1024;<br class="">
+ MaxPrefetchIterationsAhead = 4;<br class="">
break;<br class="">
case ThunderX:<br class="">
case ThunderXT88:<br class="">
case ThunderXT81:<br class="">
case ThunderXT83:<br class="">
CacheLineSize = 128;<br class="">
- PrefFunctionAlignment = 4;<br class="">
- PrefLoopAlignment = 4;<br class="">
+ PrefFunctionAlignment = 3;<br class="">
+ PrefLoopAlignment = 2;<br class="">
break;<br class="">
case CortexA35: break;<br class="">
case CortexA53: break;<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64Subtarget.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/AArch64Subtarget.h?<wbr class="">rev=297190&r1=297189&r2=<wbr class="">297190&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64Subtarget.h (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64Subtarget.h Tue Mar 7 13:42:40 2017<br class="">
@@ -45,7 +45,7 @@ public:<br class="">
ExynosM1,<br class="">
Falkor,<br class="">
Kryo,<br class="">
- Vulcan,<br class="">
+ ThunderX2T99,<br class="">
ThunderX,<br class="">
ThunderXT81,<br class="">
ThunderXT83,<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/<wbr class="">AArch64/cpus.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cpus.ll?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/AArch64/cpus.ll?rev=<wbr class="">297190&r1=297189&r2=297190&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/<wbr class="">AArch64/cpus.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/<wbr class="">AArch64/cpus.ll Tue Mar 7 13:42:40 2017<br class="">
@@ -12,7 +12,7 @@<br class="">
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s<br class="">
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=falkor 2>&1 | FileCheck %s<br class="">
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s<br class="">
-; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=vulcan 2>&1 | FileCheck %s<br class="">
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s<br class="">
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID<br class="">
<br class="">
; CHECK-NOT: {{.*}} is not a recognized processor for this target<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/<wbr class="">AArch64/machine-combiner-madd.<wbr class="">ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/machine-combiner-madd.ll?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/AArch64/machine-<wbr class="">combiner-madd.ll?rev=297190&<wbr class="">r1=297189&r2=297190&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/<wbr class="">AArch64/machine-combiner-madd.<wbr class="">ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/<wbr class="">AArch64/machine-combiner-madd.<wbr class="">ll Tue Mar 7 13:42:40 2017<br class="">
@@ -6,7 +6,7 @@<br class="">
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 < %s | FileCheck %s<br class="">
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m2 < %s | FileCheck %s<br class="">
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo < %s | FileCheck %s<br class="">
-; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=vulcan < %s | FileCheck %s<br class="">
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s<br class="">
<br class="">
; Make sure that inst-combine fuses the multiply add in the addressing mode of<br class="">
; the load.<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/<wbr class="">AArch64/remat.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/remat.ll?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/AArch64/remat.ll?rev=<wbr class="">297190&r1=297189&r2=297190&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/<wbr class="">AArch64/remat.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/<wbr class="">AArch64/remat.ll Tue Mar 7 13:42:40 2017<br class="">
@@ -8,7 +8,7 @@<br class="">
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s | FileCheck %s<br class="">
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=falkor -o - %s | FileCheck %s<br class="">
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s | FileCheck %s<br class="">
-; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=vulcan -o - %s | FileCheck %s<br class="">
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s<br class="">
; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s<br class="">
<br class="">
%X = type { i64, i64, i64 }<br class="">
<br class="">
Modified: llvm/trunk/unittests/Support/<wbr class="">TargetParserTest.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/unittests/<wbr class="">Support/TargetParserTest.cpp?<wbr class="">rev=297190&r1=297189&r2=<wbr class="">297190&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/unittests/Support/<wbr class="">TargetParserTest.cpp (original)<br class="">
+++ llvm/trunk/unittests/Support/<wbr class="">TargetParserTest.cpp Tue Mar 7 13:42:40 2017<br class="">
@@ -643,8 +643,9 @@ TEST(TargetParserTest, testAArch64CPU) {<br class="">
"kryo", "armv8-a", "crypto-neon-fp-armv8",<br class="">
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD, "8-A"));<br class="">
EXPECT_TRUE(testAArch64CPU(<br class="">
- "vulcan", "armv8.1-a", "crypto-neon-fp-armv8",<br class="">
- AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD, "8.1-A"));<br class="">
+ "thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",<br class="">
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |<br class="">
+ AArch64::AEK_SIMD, "8.1-A"));<br class="">
EXPECT_TRUE(testAArch64CPU(<br class="">
"thunderx", "armv8-a", "crypto-neon-fp-armv8",<br class="">
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |<br class="">
@@ -700,7 +701,7 @@ TEST(TargetParserTest, testAArch64Extens<br class="">
EXPECT_FALSE(<wbr class="">testAArch64Extension("cyclone"<wbr class="">, 0, "ras"));<br class="">
EXPECT_FALSE(<wbr class="">testAArch64Extension("exynos-<wbr class="">m1", 0, "ras"));<br class="">
EXPECT_FALSE(<wbr class="">testAArch64Extension("kryo", 0, "ras"));<br class="">
- EXPECT_FALSE(<wbr class="">testAArch64Extension("vulcan", 0, "ras"));<br class="">
+ EXPECT_FALSE(<wbr class="">testAArch64Extension("<wbr class="">thunderx2t99", 0, "ras"));<br class="">
EXPECT_FALSE(<wbr class="">testAArch64Extension("<wbr class="">thunderx", 0, "lse"));<br class="">
EXPECT_FALSE(<wbr class="">testAArch64Extension("<wbr class="">thunderxt81", 0, "lse"));<br class="">
EXPECT_FALSE(<wbr class="">testAArch64Extension("<wbr class="">thunderxt83", 0, "lse"));<br class="">
<br class="">
<br class="">
______________________________<wbr class="">_________________<br class="">
llvm-commits mailing list<br class="">
<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank" class="">http://lists.llvm.org/cgi-bin/<wbr class="">mailman/listinfo/llvm-commits</a><br class="">
</blockquote></div><br class=""></div>
</div></blockquote></div><br class=""></div></body></html>