<div dir="ltr"><div>Hello Joel,<br><br>It look like this commit broke one of our builders:<br><br><a href="http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/2169">http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/2169</a><br><br>Please have a look at this?<br><br>Thanks<br><br></div>Galina<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Mar 7, 2017 at 11:42 AM, Joel Jones via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: joel_k_jones<br>
Date: Tue Mar 7 13:42:40 2017<br>
New Revision: 297190<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=297190&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=297190&view=rev</a><br>
Log:<br>
[AArch64] Vulcan is now ThunderXT99<br>
<br>
Broadcom Vulcan is now Cavium ThunderX2T99.<br>
<br>
LLVM Bugzilla: <a href="http://bugs.llvm.org/show_bug.cgi?id=32113" rel="noreferrer" target="_blank">http://bugs.llvm.org/show_bug.<wbr>cgi?id=32113</a><br>
<br>
Minor fixes for the alignments of loops and functions for<br>
ThunderX T81/T83/T88 (better performance).<br>
<br>
Patch was tested with SpecCPU2006.<br>
<br>
Patch by Stefan Teleman<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D30510" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D30510</a><br>
<br>
Added:<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedThunderX2T99.td<br>
Removed:<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedVulcan.td<br>
Modified:<br>
llvm/trunk/include/llvm/<wbr>Support/AArch64TargetParser.<wbr>def<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64.td<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedThunderX.td<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64Subtarget.cpp<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64Subtarget.h<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/cpus.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/machine-combiner-madd.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/remat.ll<br>
llvm/trunk/unittests/Support/<wbr>TargetParserTest.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>Support/AArch64TargetParser.<wbr>def<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/Support/<wbr>AArch64TargetParser.def?rev=<wbr>297190&r1=297189&r2=297190&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>Support/AArch64TargetParser.<wbr>def (original)<br>
+++ llvm/trunk/include/llvm/<wbr>Support/AArch64TargetParser.<wbr>def Tue Mar 7 13:42:40 2017<br>
@@ -73,8 +73,9 @@ AARCH64_CPU_NAME("falkor", AK_ARMV8A, FK<br>
(AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))<br>
AARCH64_CPU_NAME("kryo", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,<br>
(AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))<br>
-AARCH64_CPU_NAME("vulcan", AK_ARMV8_1A, FK_CRYPTO_NEON_FP_ARMV8, false,<br>
- (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))<br>
+AARCH64_CPU_NAME("<wbr>thunderx2t99", AK_ARMV8_1A, FK_CRYPTO_NEON_FP_ARMV8, false,<br>
+ (AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_CRC |<br>
+ AArch64::AEK_CRYPTO))<br>
AARCH64_CPU_NAME("thunderx", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,<br>
(AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_PROFILE))<br>
AARCH64_CPU_NAME("thunderxt88"<wbr>, AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64.td?rev=297190&<wbr>r1=297189&r2=297190&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64.td Tue Mar 7 13:42:40 2017<br>
@@ -161,7 +161,7 @@ include "AArch64SchedFalkor.td"<br>
include "AArch64SchedKryo.td"<br>
include "AArch64SchedM1.td"<br>
include "AArch64SchedThunderX.td"<br>
-include "AArch64SchedVulcan.td"<br>
+include "AArch64SchedThunderX2T99.td"<br>
<br>
def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",<br>
"Cortex-A35 ARM processors", [<br>
@@ -288,16 +288,18 @@ def ProcFalkor : SubtargetFeature<"falk<br>
FeatureZCZeroing<br>
]>;<br>
<br>
-def ProcVulcan : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",<br>
- "Broadcom Vulcan processors", [<br>
- FeatureCRC,<br>
- FeatureCrypto,<br>
- FeatureFPARMv8,<br>
- FeatureArithmeticBccFusion,<br>
- FeatureNEON,<br>
- FeaturePostRAScheduler,<br>
- FeaturePredictableSelectIsExpe<wbr>nsive,<br>
- HasV8_1aOps]>;<br>
+def ProcThunderX2T99 : SubtargetFeature<"<wbr>thunderx2t99", "ARMProcFamily",<br>
+ "ThunderX2T99",<br>
+ "Cavium ThunderX2 processors", [<br>
+ FeatureCRC,<br>
+ FeatureCrypto,<br>
+ FeatureFPARMv8,<br>
+ FeatureArithmeticBccFusion,<br>
+ FeatureNEON,<br>
+ FeaturePostRAScheduler,<br>
+ FeaturePredictableSelectIsExpe<wbr>nsive,<br>
+ FeatureLSE,<br>
+ HasV8_1aOps]>;<br>
<br>
def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",<br>
"Cavium ThunderX processors", [<br>
@@ -363,12 +365,13 @@ def : ProcessorModel<"exynos-m2", Exynos<br>
def : ProcessorModel<"exynos-m3", ExynosM1Model, [ProcExynosM2]>;<br>
def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;<br>
def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;<br>
-def : ProcessorModel<"vulcan", VulcanModel, [ProcVulcan]>;<br>
// Cavium ThunderX/ThunderX T8X Processors<br>
def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;<br>
def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>;<br>
def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>;<br>
def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>;<br>
+// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.<br>
+def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
// Assembly parser<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedThunderX.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX.td?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64SchedThunderX.<wbr>td?rev=297190&r1=297189&r2=<wbr>297190&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedThunderX.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedThunderX.td Tue Mar 7 13:42:40 2017<br>
@@ -23,6 +23,7 @@ def ThunderXT8XModel : SchedMachineModel<br>
let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.<br>
let LoadLatency = 3; // Optimistic load latency.<br>
let MispredictPenalty = 8; // Branch mispredict penalty.<br>
+ let PostRAScheduler = 1; // Use PostRA scheduler.<br>
let CompleteModel = 1;<br>
}<br>
<br>
<br>
Added: llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedThunderX2T99.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td?rev=297190&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/<wbr>AArch64SchedThunderX2T99.td?<wbr>rev=297190&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedThunderX2T99.td (added)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedThunderX2T99.td Tue Mar 7 13:42:40 2017<br>
@@ -0,0 +1,852 @@<br>
+//=- AArch64SchedThunderX2T99.td - Cavium ThunderX T99 Scheduling ---*- tablegen -*-=//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+//<br>
+// This file defines the scheduling model for Cavium ThunderX2T99<br>
+// processors.<br>
+// Based on Broadcom Vulcan.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+// 2. Pipeline Description.<br>
+<br>
+def ThunderX2T99Model : SchedMachineModel {<br>
+ let IssueWidth = 4; // 4 micro-ops dispatched at a time.<br>
+ let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.<br>
+ let LoadLatency = 4; // Optimistic load latency.<br>
+ let MispredictPenalty = 12; // Extra cycles for mispredicted branch.<br>
+ // Determined via a mix of micro-arch details and experimentation.<br>
+ let LoopMicroOpBufferSize = 32;<br>
+ let PostRAScheduler = 1; // Using PostRA sched.<br>
+ let CompleteModel = 1;<br>
+}<br>
+<br>
+// Define the issue ports.<br>
+<br>
+// Port 0: ALU, FP/SIMD.<br>
+def THX2T99P0 : ProcResource<1>;<br>
+<br>
+// Port 1: ALU, FP/SIMD, integer mul/div.<br>
+def THX2T99P1 : ProcResource<1>;<br>
+<br>
+// Port 2: ALU, Branch.<br>
+def THX2T99P2 : ProcResource<1>;<br>
+<br>
+// Port 3: Store data.<br>
+def THX2T99P3 : ProcResource<1>;<br>
+<br>
+// Port 4: Load/store.<br>
+def THX2T99P4 : ProcResource<1>;<br>
+<br>
+// Port 5: Load/store.<br>
+def THX2T99P5 : ProcResource<1>;<br>
+<br>
+let SchedModel = ThunderX2T99Model in {<br>
+<br>
+// Define groups for the functional units on each issue port. Each group<br>
+// created will be used by a WriteRes later on.<br>
+//<br>
+// NOTE: Some groups only contain one member. This is a way to create names for<br>
+// the various functional units that share a single issue port. For example,<br>
+// "THX2T99I1" for ALU ops on port 1 and "THX2T99F1" for FP ops on port 1.<br>
+<br>
+// Integer divide and multiply micro-ops only on port 1.<br>
+def THX2T99I1 : ProcResGroup<[THX2T99P1]>;<br>
+<br>
+// Branch micro-ops only on port 2.<br>
+def THX2T99I2 : ProcResGroup<[THX2T99P2]>;<br>
+<br>
+// ALU micro-ops on ports 0, 1, and 2.<br>
+def THX2T99I012 : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2]>;<br>
+<br>
+// Crypto FP/SIMD micro-ops only on port 1.<br>
+def THX2T99F1 : ProcResGroup<[THX2T99P1]>;<br>
+<br>
+// FP/SIMD micro-ops on ports 0 and 1.<br>
+def THX2T99F01 : ProcResGroup<[THX2T99P0, THX2T99P1]>;<br>
+<br>
+// Store data micro-ops only on port 3.<br>
+def THX2T99SD : ProcResGroup<[THX2T99P3]>;<br>
+<br>
+// Load/store micro-ops on ports 4 and 5.<br>
+def THX2T99LS01 : ProcResGroup<[THX2T99P4, THX2T99P5]>;<br>
+<br>
+// 60 entry unified scheduler.<br>
+def THX2T99Any : ProcResGroup<[THX2T99P0, THX2T99P1, THX2T99P2,<br>
+ THX2T99P3, THX2T99P4, THX2T99P5]> {<br>
+ let BufferSize=60;<br>
+}<br>
+<br>
+// Define commonly used write types for InstRW specializations.<br>
+// All definitions follow the format: THX2T99Write_<NumCycles>Cyc_<<wbr>Resources>.<br>
+<br>
+// 3 cycles on I1.<br>
+def THX2T99Write_3Cyc_I1 : SchedWriteRes<[THX2T99I1]> { let Latency = 3; }<br>
+<br>
+// 4 cycles on I1.<br>
+def THX2T99Write_4Cyc_I1 : SchedWriteRes<[THX2T99I1]> { let Latency = 4; }<br>
+<br>
+// 1 cycle on I0, I1, or I2.<br>
+def THX2T99Write_1Cyc_I012 : SchedWriteRes<[THX2T99I012]> { let Latency = 1; }<br>
+<br>
+// 5 cycles on F1.<br>
+def THX2T99Write_5Cyc_F1 : SchedWriteRes<[THX2T99F1]> { let Latency = 5; }<br>
+<br>
+// 7 cycles on F1.<br>
+def THX2T99Write_7Cyc_F1 : SchedWriteRes<[THX2T99F1]> { let Latency = 7; }<br>
+<br>
+// 4 cycles on F0 or F1.<br>
+def THX2T99Write_4Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 4; }<br>
+<br>
+// 5 cycles on F0 or F1.<br>
+def THX2T99Write_5Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 5; }<br>
+<br>
+// 6 cycles on F0 or F1.<br>
+def THX2T99Write_6Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 6; }<br>
+<br>
+// 7 cycles on F0 or F1.<br>
+def THX2T99Write_7Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 7; }<br>
+<br>
+// 8 cycles on F0 or F1.<br>
+def THX2T99Write_8Cyc_F01 : SchedWriteRes<[THX2T99F01]> { let Latency = 8; }<br>
+<br>
+// 16 cycles on F0 or F1.<br>
+def THX2T99Write_16Cyc_F01 : SchedWriteRes<[THX2T99F01]> {<br>
+ let Latency = 16;<br>
+ let ResourceCycles = [8];<br>
+}<br>
+<br>
+// 23 cycles on F0 or F1.<br>
+def THX2T99Write_23Cyc_F01 : SchedWriteRes<[THX2T99F01]> {<br>
+ let Latency = 23;<br>
+ let ResourceCycles = [11];<br>
+}<br>
+<br>
+// 1 cycles on LS0 or LS1.<br>
+def THX2T99Write_1Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 1; }<br>
+<br>
+// 4 cycles on LS0 or LS1.<br>
+def THX2T99Write_4Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 4; }<br>
+<br>
+// 5 cycles on LS0 or LS1.<br>
+def THX2T99Write_5Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 5; }<br>
+<br>
+// 6 cycles on LS0 or LS1.<br>
+def THX2T99Write_6Cyc_LS01 : SchedWriteRes<[THX2T99LS01]> { let Latency = 6; }<br>
+<br>
+// 5 cycles on LS0 or LS1 and I0, I1, or I2.<br>
+def THX2T99Write_5Cyc_LS01_I012 : SchedWriteRes<[THX2T99LS01, THX2T99I012]> {<br>
+ let Latency = 5;<br>
+ let NumMicroOps = 2;<br>
+}<br>
+<br>
+// 5 cycles on LS0 or LS1 and 2 of I0, I1, or I2.<br>
+def THX2T99Write_6Cyc_LS01_I012_<wbr>I012 :<br>
+ SchedWriteRes<[THX2T99LS01, THX2T99I012, THX2T99I012]> {<br>
+ let Latency = 6;<br>
+ let NumMicroOps = 3;<br>
+}<br>
+<br>
+// 1 cycles on LS0 or LS1 and F0 or F1.<br>
+def THX2T99Write_1Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 2;<br>
+}<br>
+<br>
+// 5 cycles on LS0 or LS1 and F0 or F1.<br>
+def THX2T99Write_5Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br>
+ let Latency = 5;<br>
+ let NumMicroOps = 2;<br>
+}<br>
+<br>
+// 6 cycles on LS0 or LS1 and F0 or F1.<br>
+def THX2T99Write_6Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br>
+ let Latency = 6;<br>
+ let NumMicroOps = 2;<br>
+}<br>
+<br>
+// 7 cycles on LS0 or LS1 and F0 or F1.<br>
+def THX2T99Write_7Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br>
+ let Latency = 7;<br>
+ let NumMicroOps = 2;<br>
+}<br>
+<br>
+// 8 cycles on LS0 or LS1 and F0 or F1.<br>
+def THX2T99Write_8Cyc_LS01_F01 : SchedWriteRes<[THX2T99LS01, THX2T99F01]> {<br>
+ let Latency = 8;<br>
+ let NumMicroOps = 2;<br>
+}<br>
+<br>
+// Define commonly used read types.<br>
+<br>
+// No forwarding is provided for these types.<br>
+def : ReadAdvance<ReadI, 0>;<br>
+def : ReadAdvance<ReadISReg, 0>;<br>
+def : ReadAdvance<ReadIEReg, 0>;<br>
+def : ReadAdvance<ReadIM, 0>;<br>
+def : ReadAdvance<ReadIMA, 0>;<br>
+def : ReadAdvance<ReadID, 0>;<br>
+def : ReadAdvance<ReadExtrHi, 0>;<br>
+def : ReadAdvance<ReadAdrBase, 0>;<br>
+def : ReadAdvance<ReadVLD, 0>;<br>
+<br>
+}<br>
+<br>
+<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+// 3. Instruction Tables.<br>
+<br>
+let SchedModel = ThunderX2T99Model in {<br>
+<br>
+//---<br>
+// 3.1 Branch Instructions<br>
+//---<br>
+<br>
+// Branch, immed<br>
+// Branch and link, immed<br>
+// Compare and branch<br>
+def : WriteRes<WriteBr, [THX2T99I2]> { let Latency = 1; }<br>
+<br>
+def : WriteRes<WriteSys, []> { let Latency = 1; }<br>
+def : WriteRes<WriteBarrier, []> { let Latency = 1; }<br>
+def : WriteRes<WriteHint, []> { let Latency = 1; }<br>
+<br>
+def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }<br>
+<br>
+// Branch, register<br>
+// Branch and link, register != LR<br>
+// Branch and link, register = LR<br>
+def : WriteRes<WriteBrReg, [THX2T99I2]> { let Latency = 1; }<br>
+<br>
+//---<br>
+// 3.2 Arithmetic and Logical Instructions<br>
+// 3.3 Move and Shift Instructions<br>
+//---<br>
+<br>
+// ALU, basic<br>
+// Conditional compare<br>
+// Conditional select<br>
+// Address generation<br>
+def : WriteRes<WriteI, [THX2T99I012]> { let Latency = 1; }<br>
+def : InstRW<[WriteI], (instrs COPY)>;<br>
+<br>
+// ALU, extend and/or shift<br>
+def : WriteRes<WriteISReg, [THX2T99I012]> {<br>
+ let Latency = 2;<br>
+ let ResourceCycles = [2];<br>
+}<br>
+<br>
+def : WriteRes<WriteIEReg, [THX2T99I012]> {<br>
+ let Latency = 2;<br>
+ let ResourceCycles = [2];<br>
+}<br>
+<br>
+// Move immed<br>
+def : WriteRes<WriteImm, [THX2T99I012]> { let Latency = 1; }<br>
+<br>
+// Variable shift<br>
+def : WriteRes<WriteIS, [THX2T99I012]> { let Latency = 1; }<br>
+<br>
+//---<br>
+// 3.4 Divide and Multiply Instructions<br>
+//---<br>
+<br>
+// Divide, W-form<br>
+// Latency range of 13-23. Take the average.<br>
+def : WriteRes<WriteID32, [THX2T99I1]> {<br>
+ let Latency = 18;<br>
+ let ResourceCycles = [18];<br>
+}<br>
+<br>
+// Divide, X-form<br>
+// Latency range of 13-39. Take the average.<br>
+def : WriteRes<WriteID64, [THX2T99I1]> {<br>
+ let Latency = 26;<br>
+ let ResourceCycles = [26];<br>
+}<br>
+<br>
+// Multiply accumulate, W-form<br>
+def : WriteRes<WriteIM32, [THX2T99I012]> { let Latency = 5; }<br>
+<br>
+// Multiply accumulate, X-form<br>
+def : WriteRes<WriteIM64, [THX2T99I012]> { let Latency = 5; }<br>
+<br>
+// Bitfield extract, two reg<br>
+def : WriteRes<WriteExtr, [THX2T99I012]> { let Latency = 1; }<br>
+<br>
+// Bitfield move, basic<br>
+// Bitfield move, insert<br>
+// NOTE: Handled by WriteIS.<br>
+<br>
+// Count leading<br>
+def : InstRW<[THX2T99Write_3Cyc_I1], (instregex "^CLS(W|X)r$",<br>
+ "^CLZ(W|X)r$")>;<br>
+<br>
+// Reverse bits/bytes<br>
+// NOTE: Handled by WriteI.<br>
+<br>
+//---<br>
+// 3.6 Load Instructions<br>
+// 3.10 FP Load Instructions<br>
+//---<br>
+<br>
+// Load register, literal<br>
+// Load register, unscaled immed<br>
+// Load register, immed unprivileged<br>
+// Load register, unsigned immed<br>
+def : WriteRes<WriteLD, [THX2T99LS01]> { let Latency = 4; }<br>
+<br>
+// Load register, immed post-index<br>
+// NOTE: Handled by WriteLD, WriteI.<br>
+// Load register, immed pre-index<br>
+// NOTE: Handled by WriteLD, WriteAdr.<br>
+def : WriteRes<WriteAdr, [THX2T99I012]> { let Latency = 1; }<br>
+<br>
+// Load register offset, basic<br>
+// Load register, register offset, scale by 4/8<br>
+// Load register, register offset, scale by 2<br>
+// Load register offset, extend<br>
+// Load register, register offset, extend, scale by 4/8<br>
+// Load register, register offset, extend, scale by 2<br>
+def THX2T99WriteLDIdx : SchedWriteVariant<[<br>
+ SchedVar<ScaledIdxPred, [THX2T99Write_6Cyc_LS01_I012_<wbr>I012]>,<br>
+ SchedVar<NoSchedPred, [THX2T99Write_5Cyc_LS01_I012]><wbr>]>;<br>
+def : SchedAlias<WriteLDIdx, THX2T99WriteLDIdx>;<br>
+<br>
+def THX2T99ReadAdrBase : SchedReadVariant<[<br>
+ SchedVar<ScaledIdxPred, [ReadDefault]>,<br>
+ SchedVar<NoSchedPred, [ReadDefault]>]>;<br>
+def : SchedAlias<ReadAdrBase, THX2T99ReadAdrBase>;<br>
+<br>
+// Load pair, immed offset, normal<br>
+// Load pair, immed offset, signed words, base != SP<br>
+// Load pair, immed offset signed words, base = SP<br>
+// LDP only breaks into *one* LS micro-op. Thus<br>
+// the resources are handling by WriteLD.<br>
+def : WriteRes<WriteLDHi, []> {<br>
+ let Latency = 5;<br>
+}<br>
+<br>
+// Load pair, immed pre-index, normal<br>
+// Load pair, immed pre-index, signed words<br>
+// Load pair, immed post-index, normal<br>
+// Load pair, immed post-index, signed words<br>
+// NOTE: Handled by WriteLD, WriteLDHi, WriteAdr.<br>
+<br>
+//--<br>
+// 3.7 Store Instructions<br>
+// 3.11 FP Store Instructions<br>
+//--<br>
+<br>
+// Store register, unscaled immed<br>
+// Store register, immed unprivileged<br>
+// Store register, unsigned immed<br>
+def : WriteRes<WriteST, [THX2T99LS01, THX2T99SD]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 2;<br>
+}<br>
+<br>
+// Store register, immed post-index<br>
+// NOTE: Handled by WriteAdr, WriteST, ReadAdrBase<br>
+<br>
+// Store register, immed pre-index<br>
+// NOTE: Handled by WriteAdr, WriteST<br>
+<br>
+// Store register, register offset, basic<br>
+// Store register, register offset, scaled by 4/8<br>
+// Store register, register offset, scaled by 2<br>
+// Store register, register offset, extend<br>
+// Store register, register offset, extend, scale by 4/8<br>
+// Store register, register offset, extend, scale by 1<br>
+def : WriteRes<WriteSTIdx, [THX2T99LS01, THX2T99SD, THX2T99I012]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 3;<br>
+}<br>
+<br>
+// Store pair, immed offset, W-form<br>
+// Store pair, immed offset, X-form<br>
+def : WriteRes<WriteSTP, [THX2T99LS01, THX2T99SD]> {<br>
+ let Latency = 1;<br>
+ let NumMicroOps = 2;<br>
+}<br>
+<br>
+// Store pair, immed post-index, W-form<br>
+// Store pair, immed post-index, X-form<br>
+// Store pair, immed pre-index, W-form<br>
+// Store pair, immed pre-index, X-form<br>
+// NOTE: Handled by WriteAdr, WriteSTP.<br>
+<br>
+//---<br>
+// 3.8 FP Data Processing Instructions<br>
+//---<br>
+<br>
+// FP absolute value<br>
+// FP min/max<br>
+// FP negate<br>
+def : WriteRes<WriteF, [THX2T99F01]> { let Latency = 5; }<br>
+<br>
+// FP arithmetic<br>
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr>, (instregex "^FADD", "^FSUB")>;<br>
+<br>
+// FP compare<br>
+def : WriteRes<WriteFCmp, [THX2T99F01]> { let Latency = 5; }<br>
+<br>
+// FP divide, S-form<br>
+// FP square root, S-form<br>
+def : WriteRes<WriteFDiv, [THX2T99F01]> {<br>
+ let Latency = 16;<br>
+ let ResourceCycles = [8];<br>
+}<br>
+<br>
+// FP divide, D-form<br>
+// FP square root, D-form<br>
+def : InstRW<[THX2T99Write_23Cyc_<wbr>F01], (instrs FDIVDrr, FSQRTDr)>;<br>
+<br>
+// FP multiply<br>
+// FP multiply accumulate<br>
+def : WriteRes<WriteFMul, [THX2T99F01]> { let Latency = 6; }<br>
+<br>
+// FP round to integral<br>
+def : InstRW<[THX2T99Write_7Cyc_F01]<wbr>,<br>
+ (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)"<wbr>)>;<br>
+<br>
+// FP select<br>
+def : InstRW<[THX2T99Write_4Cyc_F01]<wbr>, (instregex "^FCSEL")>;<br>
+<br>
+//---<br>
+// 3.9 FP Miscellaneous Instructions<br>
+//---<br>
+<br>
+// FP convert, from vec to vec reg<br>
+// FP convert, from gen to vec reg<br>
+// FP convert, from vec to gen reg<br>
+def : WriteRes<WriteFCvt, [THX2T99F01]> { let Latency = 7; }<br>
+<br>
+// FP move, immed<br>
+// FP move, register<br>
+def : WriteRes<WriteFImm, [THX2T99F01]> { let Latency = 4; }<br>
+<br>
+// FP transfer, from gen to vec reg<br>
+// FP transfer, from vec to gen reg<br>
+def : WriteRes<WriteFCopy, [THX2T99F01]> { let Latency = 4; }<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instrs FMOVXDHighr, FMOVDXHighr)>;<br>
+<br>
+//---<br>
+// 3.12 ASIMD Integer Instructions<br>
+//---<br>
+<br>
+// ASIMD absolute diff, D-form<br>
+// ASIMD absolute diff, Q-form<br>
+// ASIMD absolute diff accum, D-form<br>
+// ASIMD absolute diff accum, Q-form<br>
+// ASIMD absolute diff accum long<br>
+// ASIMD absolute diff long<br>
+// ASIMD arith, basic<br>
+// ASIMD arith, complex<br>
+// ASIMD compare<br>
+// ASIMD logical (AND, BIC, EOR)<br>
+// ASIMD max/min, basic<br>
+// ASIMD max/min, reduce, 4H/4S<br>
+// ASIMD max/min, reduce, 8B/8H<br>
+// ASIMD max/min, reduce, 16B<br>
+// ASIMD multiply, D-form<br>
+// ASIMD multiply, Q-form<br>
+// ASIMD multiply accumulate long<br>
+// ASIMD multiply accumulate saturating long<br>
+// ASIMD multiply long<br>
+// ASIMD pairwise add and accumulate<br>
+// ASIMD shift accumulate<br>
+// ASIMD shift by immed, basic<br>
+// ASIMD shift by immed and insert, basic, D-form<br>
+// ASIMD shift by immed and insert, basic, Q-form<br>
+// ASIMD shift by immed, complex<br>
+// ASIMD shift by register, basic, D-form<br>
+// ASIMD shift by register, basic, Q-form<br>
+// ASIMD shift by register, complex, D-form<br>
+// ASIMD shift by register, complex, Q-form<br>
+def : WriteRes<WriteV, [THX2T99F01]> { let Latency = 7; }<br>
+<br>
+// ASIMD arith, reduce, 4H/4S<br>
+// ASIMD arith, reduce, 8B/8H<br>
+// ASIMD arith, reduce, 16B<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>,<br>
+ (instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>;<br>
+<br>
+// ASIMD logical (MOV, MVN, ORN, ORR)<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^ORRv", "^ORNv", "^NOTv")>;<br>
+<br>
+// ASIMD polynomial (8x8) multiply long<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instrs PMULLv8i8, PMULLv16i8)>;<br>
+<br>
+//---<br>
+// 3.13 ASIMD Floating-point Instructions<br>
+//---<br>
+<br>
+// ASIMD FP absolute value<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^FABSv")>;<br>
+<br>
+// ASIMD FP arith, normal, D-form<br>
+// ASIMD FP arith, normal, Q-form<br>
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr>, (instregex "^FABDv", "^FADDv", "^FSUBv")>;<br>
+<br>
+// ASIMD FP arith,pairwise, D-form<br>
+// ASIMD FP arith, pairwise, Q-form<br>
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr>, (instregex "^FADDPv")>;<br>
+<br>
+// ASIMD FP compare, D-form<br>
+// ASIMD FP compare, Q-form<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^FACGEv", "^FACGTv")>;<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^FCMEQv", "^FCMGEv",<br>
+ "^FCMGTv", "^FCMLEv",<br>
+ "^FCMLTv")>;<br>
+<br>
+// ASIMD FP convert, long<br>
+// ASIMD FP convert, narrow<br>
+// ASIMD FP convert, other, D-form<br>
+// ASIMD FP convert, other, Q-form<br>
+// NOTE: Handled by WriteV.<br>
+<br>
+// ASIMD FP divide, D-form, F32<br>
+def : InstRW<[THX2T99Write_16Cyc_<wbr>F01], (instrs FDIVv2f32)>;<br>
+<br>
+// ASIMD FP divide, Q-form, F32<br>
+def : InstRW<[THX2T99Write_16Cyc_<wbr>F01], (instrs FDIVv4f32)>;<br>
+<br>
+// ASIMD FP divide, Q-form, F64<br>
+def : InstRW<[THX2T99Write_23Cyc_<wbr>F01], (instrs FDIVv2f64)>;<br>
+<br>
+// ASIMD FP max/min, normal, D-form<br>
+// ASIMD FP max/min, normal, Q-form<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^FMAXv", "^FMAXNMv",<br>
+ "^FMINv", "^FMINNMv")>;<br>
+<br>
+// ASIMD FP max/min, pairwise, D-form<br>
+// ASIMD FP max/min, pairwise, Q-form<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^FMAXPv", "^FMAXNMPv",<br>
+ "^FMINPv", "^FMINNMPv")>;<br>
+<br>
+// ASIMD FP max/min, reduce<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^FMAXVv", "^FMAXNMVv",<br>
+ "^FMINVv", "^FMINNMVv")>;<br>
+<br>
+// ASIMD FP multiply, D-form, FZ<br>
+// ASIMD FP multiply, D-form, no FZ<br>
+// ASIMD FP multiply, Q-form, FZ<br>
+// ASIMD FP multiply, Q-form, no FZ<br>
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr>, (instregex "^FMULv", "^FMULXv")>;<br>
+<br>
+// ASIMD FP multiply accumulate, Dform, FZ<br>
+// ASIMD FP multiply accumulate, Dform, no FZ<br>
+// ASIMD FP multiply accumulate, Qform, FZ<br>
+// ASIMD FP multiply accumulate, Qform, no FZ<br>
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr>, (instregex "^FMLAv", "^FMLSv")>;<br>
+<br>
+// ASIMD FP negate<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^FNEGv")>;<br>
+<br>
+// ASIMD FP round, D-form<br>
+// ASIMD FP round, Q-form<br>
+// NOTE: Handled by WriteV.<br>
+<br>
+//--<br>
+// 3.14 ASIMD Miscellaneous Instructions<br>
+//--<br>
+<br>
+// ASIMD bit reverse<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^RBITv")>;<br>
+<br>
+// ASIMD bitwise insert, D-form<br>
+// ASIMD bitwise insert, Q-form<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^BIFv", "^BITv", "^BSLv")>;<br>
+<br>
+// ASIMD count, D-form<br>
+// ASIMD count, Q-form<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^CLSv", "^CLZv", "^CNTv")>;<br>
+<br>
+// ASIMD duplicate, gen reg<br>
+// ASIMD duplicate, element<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^DUPv")>;<br>
+<br>
+// ASIMD extract<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^EXTv")>;<br>
+<br>
+// ASIMD extract narrow<br>
+// ASIMD extract narrow, saturating<br>
+// NOTE: Handled by WriteV.<br>
+<br>
+// ASIMD insert, element to element<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^INSv")>;<br>
+<br>
+// ASIMD move, integer immed<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^MOVIv", "^MOVIDv")>;<br>
+<br>
+// ASIMD move, FP immed<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^FMOVv")>;<br>
+<br>
+// ASIMD reciprocal estimate, D-form<br>
+// ASIMD reciprocal estimate, Q-form<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>,<br>
+ (instregex "^FRECPEv", "^FRECPXv", "^URECPEv",<br>
+ "^FRSQRTEv", "^URSQRTEv")>;<br>
+<br>
+// ASIMD reciprocal step, D-form, FZ<br>
+// ASIMD reciprocal step, D-form, no FZ<br>
+// ASIMD reciprocal step, Q-form, FZ<br>
+// ASIMD reciprocal step, Q-form, no FZ<br>
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr>, (instregex "^FRECPSv", "^FRSQRTSv")>;<br>
+<br>
+// ASIMD reverse<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>,<br>
+ (instregex "^REV16v", "^REV32v", "^REV64v")>;<br>
+<br>
+// ASIMD table lookup, D-form<br>
+// ASIMD table lookup, Q-form<br>
+def : InstRW<[THX2T99Write_8Cyc_F01]<wbr>, (instregex "^TBLv", "^TBXv")>;<br>
+<br>
+// ASIMD transfer, element to word or word<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^UMOVv")>;<br>
+<br>
+// ASIMD transfer, element to gen reg<br>
+def : InstRW<[THX2T99Write_6Cyc_F01]<wbr>, (instregex "^SMOVv", "^UMOVv")>;<br>
+<br>
+// ASIMD transfer gen reg to element<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^INSv")>;<br>
+<br>
+// ASIMD transpose<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^TRN1v", "^TRN2v",<br>
+ "^UZP1v", "^UZP2v")>;<br>
+<br>
+// ASIMD unzip/zip<br>
+def : InstRW<[THX2T99Write_5Cyc_F01]<wbr>, (instregex "^ZIP1v", "^ZIP2v")>;<br>
+<br>
+//--<br>
+// 3.15 ASIMD Load Instructions<br>
+//--<br>
+<br>
+// ASIMD load, 1 element, multiple, 1 reg, D-form<br>
+// ASIMD load, 1 element, multiple, 1 reg, Q-form<br>
+def : InstRW<[THX2T99Write_4Cyc_<wbr>LS01],<br>
+ (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_4Cyc_<wbr>LS01, WriteAdr],<br>
+ (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
+<br>
+// ASIMD load, 1 element, multiple, 2 reg, D-form<br>
+// ASIMD load, 1 element, multiple, 2 reg, Q-form<br>
+def : InstRW<[THX2T99Write_4Cyc_<wbr>LS01],<br>
+ (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_4Cyc_<wbr>LS01, WriteAdr],<br>
+ (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
+<br>
+// ASIMD load, 1 element, multiple, 3 reg, D-form<br>
+// ASIMD load, 1 element, multiple, 3 reg, Q-form<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01],<br>
+ (instregex "^LD1Threev(8b|4h|2s|1d|16b|<wbr>8h|4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01, WriteAdr],<br>
+ (instregex "^LD1Threev(8b|4h|2s|1d|16b|<wbr>8h|4s|2d)_POST$")>;<br>
+<br>
+// ASIMD load, 1 element, multiple, 4 reg, D-form<br>
+// ASIMD load, 1 element, multiple, 4 reg, Q-form<br>
+def : InstRW<[THX2T99Write_6Cyc_<wbr>LS01],<br>
+ (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_6Cyc_<wbr>LS01, WriteAdr],<br>
+ (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
+<br>
+// ASIMD load, 1 element, one lane, B/H/S<br>
+// ASIMD load, 1 element, one lane, D<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01], (instregex "^LD1i(8|16|32|64)$")>;<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD1i(8|16|32|64)_POST$")>;<br>
+<br>
+// ASIMD load, 1 element, all lanes, D-form, B/H/S<br>
+// ASIMD load, 1 element, all lanes, D-form, D<br>
+// ASIMD load, 1 element, all lanes, Q-form<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01],<br>
+ (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)$")>;<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)_POST$")>;<br>
+<br>
+// ASIMD load, 2 element, multiple, D-form, B/H/S<br>
+// ASIMD load, 2 element, multiple, Q-form, D<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01],<br>
+ (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|<wbr>2d)$")>;<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|<wbr>2d)_POST$")>;<br>
+<br>
+// ASIMD load, 2 element, one lane, B/H<br>
+// ASIMD load, 2 element, one lane, S<br>
+// ASIMD load, 2 element, one lane, D<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01], (instregex "^LD2i(8|16|32|64)$")>;<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD2i(8|16|32|64)_POST$")>;<br>
+<br>
+// ASIMD load, 2 element, all lanes, D-form, B/H/S<br>
+// ASIMD load, 2 element, all lanes, D-form, D<br>
+// ASIMD load, 2 element, all lanes, Q-form<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01],<br>
+ (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)$")>;<br>
+def : InstRW<[THX2T99Write_5Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)_POST$")>;<br>
+<br>
+// ASIMD load, 3 element, multiple, D-form, B/H/S<br>
+// ASIMD load, 3 element, multiple, Q-form, B/H/S<br>
+// ASIMD load, 3 element, multiple, Q-form, D<br>
+def : InstRW<[THX2T99Write_8Cyc_<wbr>LS01_F01],<br>
+ (instregex "^LD3Threev(8b|4h|2s|16b|8h|<wbr>4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_8Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD3Threev(8b|4h|2s|16b|8h|<wbr>4s|2d)_POST$")>;<br>
+<br>
+// ASIMD load, 3 element, one lone, B/H<br>
+// ASIMD load, 3 element, one lane, S<br>
+// ASIMD load, 3 element, one lane, D<br>
+def : InstRW<[THX2T99Write_7Cyc_<wbr>LS01_F01], (instregex "^LD3i(8|16|32|64)$")>;<br>
+def : InstRW<[THX2T99Write_7Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD3i(8|16|32|64)_POST$")>;<br>
+<br>
+// ASIMD load, 3 element, all lanes, D-form, B/H/S<br>
+// ASIMD load, 3 element, all lanes, D-form, D<br>
+// ASIMD load, 3 element, all lanes, Q-form, B/H/S<br>
+// ASIMD load, 3 element, all lanes, Q-form, D<br>
+def : InstRW<[THX2T99Write_7Cyc_<wbr>LS01_F01],<br>
+ (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)$")>;<br>
+def : InstRW<[THX2T99Write_7Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)_POST$")>;<br>
+<br>
+// ASIMD load, 4 element, multiple, D-form, B/H/S<br>
+// ASIMD load, 4 element, multiple, Q-form, B/H/S<br>
+// ASIMD load, 4 element, multiple, Q-form, D<br>
+def : InstRW<[THX2T99Write_8Cyc_<wbr>LS01_F01],<br>
+ (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|<wbr>2d)$")>;<br>
+def : InstRW<[THX2T99Write_8Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|<wbr>2d)_POST$")>;<br>
+<br>
+// ASIMD load, 4 element, one lane, B/H<br>
+// ASIMD load, 4 element, one lane, S<br>
+// ASIMD load, 4 element, one lane, D<br>
+def : InstRW<[THX2T99Write_6Cyc_<wbr>LS01_F01], (instregex "^LD4i(8|16|32|64)$")>;<br>
+def : InstRW<[THX2T99Write_6Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD4i(8|16|32|64)_POST$")>;<br>
+<br>
+// ASIMD load, 4 element, all lanes, D-form, B/H/S<br>
+// ASIMD load, 4 element, all lanes, D-form, D<br>
+// ASIMD load, 4 element, all lanes, Q-form, B/H/S<br>
+// ASIMD load, 4 element, all lanes, Q-form, D<br>
+def : InstRW<[THX2T99Write_6Cyc_<wbr>LS01_F01],<br>
+ (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)$")>;<br>
+def : InstRW<[THX2T99Write_6Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)_POST$")>;<br>
+<br>
+//--<br>
+// 3.16 ASIMD Store Instructions<br>
+//--<br>
+<br>
+// ASIMD store, 1 element, multiple, 1 reg, D-form<br>
+// ASIMD store, 1 element, multiple, 1 reg, Q-form<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01],<br>
+ (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01, WriteAdr],<br>
+ (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
+<br>
+// ASIMD store, 1 element, multiple, 2 reg, D-form<br>
+// ASIMD store, 1 element, multiple, 2 reg, Q-form<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01],<br>
+ (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01, WriteAdr],<br>
+ (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
+<br>
+// ASIMD store, 1 element, multiple, 3 reg, D-form<br>
+// ASIMD store, 1 element, multiple, 3 reg, Q-form<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01],<br>
+ (instregex "^ST1Threev(8b|4h|2s|1d|16b|<wbr>8h|4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01, WriteAdr],<br>
+ (instregex "^ST1Threev(8b|4h|2s|1d|16b|<wbr>8h|4s|2d)_POST$")>;<br>
+<br>
+// ASIMD store, 1 element, multiple, 4 reg, D-form<br>
+// ASIMD store, 1 element, multiple, 4 reg, Q-form<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01],<br>
+ (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01, WriteAdr],<br>
+ (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
+<br>
+// ASIMD store, 1 element, one lane, B/H/S<br>
+// ASIMD store, 1 element, one lane, D<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01],<br>
+ (instregex "^ST1i(8|16|32|64)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^ST1i(8|16|32|64)_POST$")>;<br>
+<br>
+// ASIMD store, 2 element, multiple, D-form, B/H/S<br>
+// ASIMD store, 2 element, multiple, Q-form, B/H/S<br>
+// ASIMD store, 2 element, multiple, Q-form, D<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01],<br>
+ (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|<wbr>2d)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|<wbr>2d)_POST$")>;<br>
+<br>
+// ASIMD store, 2 element, one lane, B/H/S<br>
+// ASIMD store, 2 element, one lane, D<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01],<br>
+ (instregex "^ST2i(8|16|32|64)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^ST2i(8|16|32|64)_POST$")>;<br>
+<br>
+// ASIMD store, 3 element, multiple, D-form, B/H/S<br>
+// ASIMD store, 3 element, multiple, Q-form, B/H/S<br>
+// ASIMD store, 3 element, multiple, Q-form, D<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01],<br>
+ (instregex "^ST3Threev(8b|4h|2s|16b|8h|<wbr>4s|2d)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^ST3Threev(8b|4h|2s|16b|8h|<wbr>4s|2d)_POST$")>;<br>
+<br>
+// ASIMD store, 3 element, one lane, B/H<br>
+// ASIMD store, 3 element, one lane, S<br>
+// ASIMD store, 3 element, one lane, D<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01], (instregex "^ST3i(8|16|32|64)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^ST3i(8|16|32|64)_POST$")>;<br>
+<br>
+// ASIMD store, 4 element, multiple, D-form, B/H/S<br>
+// ASIMD store, 4 element, multiple, Q-form, B/H/S<br>
+// ASIMD store, 4 element, multiple, Q-form, D<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01],<br>
+ (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|<wbr>2d)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|<wbr>2d)_POST$")>;<br>
+<br>
+// ASIMD store, 4 element, one lane, B/H<br>
+// ASIMD store, 4 element, one lane, S<br>
+// ASIMD store, 4 element, one lane, D<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01], (instregex "^ST4i(8|16|32|64)$")>;<br>
+def : InstRW<[THX2T99Write_1Cyc_<wbr>LS01_F01, WriteAdr],<br>
+ (instregex "^ST4i(8|16|32|64)_POST$")>;<br>
+<br>
+//--<br>
+// 3.17 Cryptography Extensions<br>
+//--<br>
+<br>
+// Crypto AES ops<br>
+def : InstRW<[THX2T99Write_5Cyc_F1], (instregex "^AES")>;<br>
+<br>
+// Crypto polynomial (64x64) multiply long<br>
+def : InstRW<[THX2T99Write_5Cyc_F1], (instrs PMULLv1i64, PMULLv2i64)>;<br>
+<br>
+// Crypto SHA1 xor ops<br>
+// Crypto SHA1 schedule acceleration ops<br>
+// Crypto SHA256 schedule acceleration op (1 u-op)<br>
+// Crypto SHA256 schedule acceleration op (2 u-ops)<br>
+// Crypto SHA256 hash acceleration ops<br>
+def : InstRW<[THX2T99Write_7Cyc_F1], (instregex "^SHA")>;<br>
+<br>
+//--<br>
+// 3.18 CRC<br>
+//--<br>
+<br>
+// CRC checksum ops<br>
+def : InstRW<[THX2T99Write_4Cyc_I1], (instregex "^CRC32")>;<br>
+<br>
+} // SchedModel = ThunderX2T99Model<br>
<br>
Removed: llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedVulcan.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedVulcan.td?rev=297189&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64SchedVulcan.td?<wbr>rev=297189&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedVulcan.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64SchedVulcan.td (removed)<br>
@@ -1,852 +0,0 @@<br>
-//=- AArch64SchedVulcan.td - Vulcan Scheduling Defs ----------*- tablegen -*-=//<br>
-//<br>
-// The LLVM Compiler Infrastructure<br>
-//<br>
-// This file is distributed under the University of Illinois Open Source<br>
-// License. See LICENSE.TXT for details.<br>
-//<br>
-//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
-// 1. Introduction<br>
-//<br>
-// This file defines the machine model for Broadcom Vulcan to support<br>
-// instruction scheduling and other instruction cost heuristics.<br>
-//<br>
-//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
-<br>
-//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
-// 2. Pipeline Description.<br>
-<br>
-def VulcanModel : SchedMachineModel {<br>
- let IssueWidth = 4; // 4 micro-ops dispatched at a time.<br>
- let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.<br>
- let LoadLatency = 4; // Optimistic load latency.<br>
- let MispredictPenalty = 12; // Extra cycles for mispredicted branch.<br>
- // Determined via a mix of micro-arch details and experimentation.<br>
- let LoopMicroOpBufferSize = 32;<br>
- let PostRAScheduler = 1; // Using PostRA sched.<br>
- let CompleteModel = 1;<br>
-}<br>
-<br>
-// Define the issue ports.<br>
-<br>
-// Port 0: ALU, FP/SIMD.<br>
-def VulcanP0 : ProcResource<1>;<br>
-<br>
-// Port 1: ALU, FP/SIMD, integer mul/div.<br>
-def VulcanP1 : ProcResource<1>;<br>
-<br>
-// Port 2: ALU, Branch.<br>
-def VulcanP2 : ProcResource<1>;<br>
-<br>
-// Port 3: Store data.<br>
-def VulcanP3 : ProcResource<1>;<br>
-<br>
-// Port 4: Load/store.<br>
-def VulcanP4 : ProcResource<1>;<br>
-<br>
-// Port 5: Load/store.<br>
-def VulcanP5 : ProcResource<1>;<br>
-<br>
-let SchedModel = VulcanModel in {<br>
-<br>
-// Define groups for the functional units on each issue port. Each group<br>
-// created will be used by a WriteRes later on.<br>
-//<br>
-// NOTE: Some groups only contain one member. This is a way to create names for<br>
-// the various functional units that share a single issue port. For example,<br>
-// "VulcanI1" for ALU ops on port 1 and "VulcanF1" for FP ops on port 1.<br>
-<br>
-// Integer divide and multiply micro-ops only on port 1.<br>
-def VulcanI1 : ProcResGroup<[VulcanP1]>;<br>
-<br>
-// Branch micro-ops only on port 2.<br>
-def VulcanI2 : ProcResGroup<[VulcanP2]>;<br>
-<br>
-// ALU micro-ops on ports 0, 1, and 2.<br>
-def VulcanI012 : ProcResGroup<[VulcanP0, VulcanP1, VulcanP2]>;<br>
-<br>
-// Crypto FP/SIMD micro-ops only on port 1.<br>
-def VulcanF1 : ProcResGroup<[VulcanP1]>;<br>
-<br>
-// FP/SIMD micro-ops on ports 0 and 1.<br>
-def VulcanF01 : ProcResGroup<[VulcanP0, VulcanP1]>;<br>
-<br>
-// Store data micro-ops only on port 3.<br>
-def VulcanSD : ProcResGroup<[VulcanP3]>;<br>
-<br>
-// Load/store micro-ops on ports 4 and 5.<br>
-def VulcanLS01 : ProcResGroup<[VulcanP4, VulcanP5]>;<br>
-<br>
-// 60 entry unified scheduler.<br>
-def VulcanAny : ProcResGroup<[VulcanP0, VulcanP1, VulcanP2,<br>
- VulcanP3, VulcanP4, VulcanP5]> {<br>
- let BufferSize=60;<br>
-}<br>
-<br>
-// Define commonly used write types for InstRW specializations.<br>
-// All definitions follow the format: VulcanWrite_<NumCycles>Cyc_<<wbr>Resources>.<br>
-<br>
-// 3 cycles on I1.<br>
-def VulcanWrite_3Cyc_I1 : SchedWriteRes<[VulcanI1]> { let Latency = 3; }<br>
-<br>
-// 4 cycles on I1.<br>
-def VulcanWrite_4Cyc_I1 : SchedWriteRes<[VulcanI1]> { let Latency = 4; }<br>
-<br>
-// 1 cycle on I0, I1, or I2.<br>
-def VulcanWrite_1Cyc_I012 : SchedWriteRes<[VulcanI012]> { let Latency = 1; }<br>
-<br>
-// 5 cycles on F1.<br>
-def VulcanWrite_5Cyc_F1 : SchedWriteRes<[VulcanF1]> { let Latency = 5; }<br>
-<br>
-// 7 cycles on F1.<br>
-def VulcanWrite_7Cyc_F1 : SchedWriteRes<[VulcanF1]> { let Latency = 7; }<br>
-<br>
-// 4 cycles on F0 or F1.<br>
-def VulcanWrite_4Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 4; }<br>
-<br>
-// 5 cycles on F0 or F1.<br>
-def VulcanWrite_5Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 5; }<br>
-<br>
-// 6 cycles on F0 or F1.<br>
-def VulcanWrite_6Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 6; }<br>
-<br>
-// 7 cycles on F0 or F1.<br>
-def VulcanWrite_7Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 7; }<br>
-<br>
-// 8 cycles on F0 or F1.<br>
-def VulcanWrite_8Cyc_F01 : SchedWriteRes<[VulcanF01]> { let Latency = 8; }<br>
-<br>
-// 16 cycles on F0 or F1.<br>
-def VulcanWrite_16Cyc_F01 : SchedWriteRes<[VulcanF01]> {<br>
- let Latency = 16;<br>
- let ResourceCycles = [8];<br>
-}<br>
-<br>
-// 23 cycles on F0 or F1.<br>
-def VulcanWrite_23Cyc_F01 : SchedWriteRes<[VulcanF01]> {<br>
- let Latency = 23;<br>
- let ResourceCycles = [11];<br>
-}<br>
-<br>
-// 1 cycles on LS0 or LS1.<br>
-def VulcanWrite_1Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 1; }<br>
-<br>
-// 4 cycles on LS0 or LS1.<br>
-def VulcanWrite_4Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 4; }<br>
-<br>
-// 5 cycles on LS0 or LS1.<br>
-def VulcanWrite_5Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 5; }<br>
-<br>
-// 6 cycles on LS0 or LS1.<br>
-def VulcanWrite_6Cyc_LS01 : SchedWriteRes<[VulcanLS01]> { let Latency = 6; }<br>
-<br>
-// 5 cycles on LS0 or LS1 and I0, I1, or I2.<br>
-def VulcanWrite_5Cyc_LS01_I012 : SchedWriteRes<[VulcanLS01, VulcanI012]> {<br>
- let Latency = 5;<br>
- let NumMicroOps = 2;<br>
-}<br>
-<br>
-// 5 cycles on LS0 or LS1 and 2 of I0, I1, or I2.<br>
-def VulcanWrite_6Cyc_LS01_I012_<wbr>I012 :<br>
- SchedWriteRes<[VulcanLS01, VulcanI012, VulcanI012]> {<br>
- let Latency = 6;<br>
- let NumMicroOps = 3;<br>
-}<br>
-<br>
-// 1 cycles on LS0 or LS1 and F0 or F1.<br>
-def VulcanWrite_1Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
-}<br>
-<br>
-// 5 cycles on LS0 or LS1 and F0 or F1.<br>
-def VulcanWrite_5Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br>
- let Latency = 5;<br>
- let NumMicroOps = 2;<br>
-}<br>
-<br>
-// 6 cycles on LS0 or LS1 and F0 or F1.<br>
-def VulcanWrite_6Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br>
- let Latency = 6;<br>
- let NumMicroOps = 2;<br>
-}<br>
-<br>
-// 7 cycles on LS0 or LS1 and F0 or F1.<br>
-def VulcanWrite_7Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br>
- let Latency = 7;<br>
- let NumMicroOps = 2;<br>
-}<br>
-<br>
-// 8 cycles on LS0 or LS1 and F0 or F1.<br>
-def VulcanWrite_8Cyc_LS01_F01 : SchedWriteRes<[VulcanLS01, VulcanF01]> {<br>
- let Latency = 8;<br>
- let NumMicroOps = 2;<br>
-}<br>
-<br>
-// Define commonly used read types.<br>
-<br>
-// No forwarding is provided for these types.<br>
-def : ReadAdvance<ReadI, 0>;<br>
-def : ReadAdvance<ReadISReg, 0>;<br>
-def : ReadAdvance<ReadIEReg, 0>;<br>
-def : ReadAdvance<ReadIM, 0>;<br>
-def : ReadAdvance<ReadIMA, 0>;<br>
-def : ReadAdvance<ReadID, 0>;<br>
-def : ReadAdvance<ReadExtrHi, 0>;<br>
-def : ReadAdvance<ReadAdrBase, 0>;<br>
-def : ReadAdvance<ReadVLD, 0>;<br>
-<br>
-}<br>
-<br>
-<br>
-//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
-// 3. Instruction Tables.<br>
-<br>
-let SchedModel = VulcanModel in {<br>
-<br>
-//---<br>
-// 3.1 Branch Instructions<br>
-//---<br>
-<br>
-// Branch, immed<br>
-// Branch and link, immed<br>
-// Compare and branch<br>
-def : WriteRes<WriteBr, [VulcanI2]> { let Latency = 1; }<br>
-<br>
-def : WriteRes<WriteSys, []> { let Latency = 1; }<br>
-def : WriteRes<WriteBarrier, []> { let Latency = 1; }<br>
-def : WriteRes<WriteHint, []> { let Latency = 1; }<br>
-<br>
-def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }<br>
-<br>
-// Branch, register<br>
-// Branch and link, register != LR<br>
-// Branch and link, register = LR<br>
-def : WriteRes<WriteBrReg, [VulcanI2]> { let Latency = 1; }<br>
-<br>
-//---<br>
-// 3.2 Arithmetic and Logical Instructions<br>
-// 3.3 Move and Shift Instructions<br>
-//---<br>
-<br>
-// ALU, basic<br>
-// Conditional compare<br>
-// Conditional select<br>
-// Address generation<br>
-def : WriteRes<WriteI, [VulcanI012]> { let Latency = 1; }<br>
-def : InstRW<[WriteI], (instrs COPY)>;<br>
-<br>
-// ALU, extend and/or shift<br>
-def : WriteRes<WriteISReg, [VulcanI012]> {<br>
- let Latency = 2;<br>
- let ResourceCycles = [2];<br>
-}<br>
-<br>
-def : WriteRes<WriteIEReg, [VulcanI012]> {<br>
- let Latency = 2;<br>
- let ResourceCycles = [2];<br>
-}<br>
-<br>
-// Move immed<br>
-def : WriteRes<WriteImm, [VulcanI012]> { let Latency = 1; }<br>
-<br>
-// Variable shift<br>
-def : WriteRes<WriteIS, [VulcanI012]> { let Latency = 1; }<br>
-<br>
-//---<br>
-// 3.4 Divide and Multiply Instructions<br>
-//---<br>
-<br>
-// Divide, W-form<br>
-// Latency range of 13-23. Take the average.<br>
-def : WriteRes<WriteID32, [VulcanI1]> {<br>
- let Latency = 18;<br>
- let ResourceCycles = [18];<br>
-}<br>
-<br>
-// Divide, X-form<br>
-// Latency range of 13-39. Take the average.<br>
-def : WriteRes<WriteID64, [VulcanI1]> {<br>
- let Latency = 26;<br>
- let ResourceCycles = [26];<br>
-}<br>
-<br>
-// Multiply accumulate, W-form<br>
-def : WriteRes<WriteIM32, [VulcanI012]> { let Latency = 5; }<br>
-<br>
-// Multiply accumulate, X-form<br>
-def : WriteRes<WriteIM64, [VulcanI012]> { let Latency = 5; }<br>
-<br>
-// Bitfield extract, two reg<br>
-def : WriteRes<WriteExtr, [VulcanI012]> { let Latency = 1; }<br>
-<br>
-// Bitfield move, basic<br>
-// Bitfield move, insert<br>
-// NOTE: Handled by WriteIS.<br>
-<br>
-// Count leading<br>
-def : InstRW<[VulcanWrite_3Cyc_I1], (instregex "^CLS(W|X)r$",<br>
- "^CLZ(W|X)r$")>;<br>
-<br>
-// Reverse bits/bytes<br>
-// NOTE: Handled by WriteI.<br>
-<br>
-//---<br>
-// 3.6 Load Instructions<br>
-// 3.10 FP Load Instructions<br>
-//---<br>
-<br>
-// Load register, literal<br>
-// Load register, unscaled immed<br>
-// Load register, immed unprivileged<br>
-// Load register, unsigned immed<br>
-def : WriteRes<WriteLD, [VulcanLS01]> { let Latency = 4; }<br>
-<br>
-// Load register, immed post-index<br>
-// NOTE: Handled by WriteLD, WriteI.<br>
-// Load register, immed pre-index<br>
-// NOTE: Handled by WriteLD, WriteAdr.<br>
-def : WriteRes<WriteAdr, [VulcanI012]> { let Latency = 1; }<br>
-<br>
-// Load register offset, basic<br>
-// Load register, register offset, scale by 4/8<br>
-// Load register, register offset, scale by 2<br>
-// Load register offset, extend<br>
-// Load register, register offset, extend, scale by 4/8<br>
-// Load register, register offset, extend, scale by 2<br>
-def VulcanWriteLDIdx : SchedWriteVariant<[<br>
- SchedVar<ScaledIdxPred, [VulcanWrite_6Cyc_LS01_I012_<wbr>I012]>,<br>
- SchedVar<NoSchedPred, [VulcanWrite_5Cyc_LS01_I012]>]<wbr>>;<br>
-def : SchedAlias<WriteLDIdx, VulcanWriteLDIdx>;<br>
-<br>
-def VulcanReadAdrBase : SchedReadVariant<[<br>
- SchedVar<ScaledIdxPred, [ReadDefault]>,<br>
- SchedVar<NoSchedPred, [ReadDefault]>]>;<br>
-def : SchedAlias<ReadAdrBase, VulcanReadAdrBase>;<br>
-<br>
-// Load pair, immed offset, normal<br>
-// Load pair, immed offset, signed words, base != SP<br>
-// Load pair, immed offset signed words, base = SP<br>
-// LDP only breaks into *one* LS micro-op. Thus<br>
-// the resources are handling by WriteLD.<br>
-def : WriteRes<WriteLDHi, []> {<br>
- let Latency = 5;<br>
-}<br>
-<br>
-// Load pair, immed pre-index, normal<br>
-// Load pair, immed pre-index, signed words<br>
-// Load pair, immed post-index, normal<br>
-// Load pair, immed post-index, signed words<br>
-// NOTE: Handled by WriteLD, WriteLDHi, WriteAdr.<br>
-<br>
-//--<br>
-// 3.7 Store Instructions<br>
-// 3.11 FP Store Instructions<br>
-//--<br>
-<br>
-// Store register, unscaled immed<br>
-// Store register, immed unprivileged<br>
-// Store register, unsigned immed<br>
-def : WriteRes<WriteST, [VulcanLS01, VulcanSD]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
-}<br>
-<br>
-// Store register, immed post-index<br>
-// NOTE: Handled by WriteAdr, WriteST, ReadAdrBase<br>
-<br>
-// Store register, immed pre-index<br>
-// NOTE: Handled by WriteAdr, WriteST<br>
-<br>
-// Store register, register offset, basic<br>
-// Store register, register offset, scaled by 4/8<br>
-// Store register, register offset, scaled by 2<br>
-// Store register, register offset, extend<br>
-// Store register, register offset, extend, scale by 4/8<br>
-// Store register, register offset, extend, scale by 1<br>
-def : WriteRes<WriteSTIdx, [VulcanLS01, VulcanSD, VulcanI012]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 3;<br>
-}<br>
-<br>
-// Store pair, immed offset, W-form<br>
-// Store pair, immed offset, X-form<br>
-def : WriteRes<WriteSTP, [VulcanLS01, VulcanSD]> {<br>
- let Latency = 1;<br>
- let NumMicroOps = 2;<br>
-}<br>
-<br>
-// Store pair, immed post-index, W-form<br>
-// Store pair, immed post-index, X-form<br>
-// Store pair, immed pre-index, W-form<br>
-// Store pair, immed pre-index, X-form<br>
-// NOTE: Handled by WriteAdr, WriteSTP.<br>
-<br>
-//---<br>
-// 3.8 FP Data Processing Instructions<br>
-//---<br>
-<br>
-// FP absolute value<br>
-// FP min/max<br>
-// FP negate<br>
-def : WriteRes<WriteF, [VulcanF01]> { let Latency = 5; }<br>
-<br>
-// FP arithmetic<br>
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FADD", "^FSUB")>;<br>
-<br>
-// FP compare<br>
-def : WriteRes<WriteFCmp, [VulcanF01]> { let Latency = 5; }<br>
-<br>
-// FP divide, S-form<br>
-// FP square root, S-form<br>
-def : WriteRes<WriteFDiv, [VulcanF01]> {<br>
- let Latency = 16;<br>
- let ResourceCycles = [8];<br>
-}<br>
-<br>
-// FP divide, D-form<br>
-// FP square root, D-form<br>
-def : InstRW<[VulcanWrite_23Cyc_F01]<wbr>, (instrs FDIVDrr, FSQRTDr)>;<br>
-<br>
-// FP multiply<br>
-// FP multiply accumulate<br>
-def : WriteRes<WriteFMul, [VulcanF01]> { let Latency = 6; }<br>
-<br>
-// FP round to integral<br>
-def : InstRW<[VulcanWrite_7Cyc_F01],<br>
- (instregex "^FRINT(A|I|M|N|P|X|Z)(Sr|Dr)"<wbr>)>;<br>
-<br>
-// FP select<br>
-def : InstRW<[VulcanWrite_4Cyc_F01], (instregex "^FCSEL")>;<br>
-<br>
-//---<br>
-// 3.9 FP Miscellaneous Instructions<br>
-//---<br>
-<br>
-// FP convert, from vec to vec reg<br>
-// FP convert, from gen to vec reg<br>
-// FP convert, from vec to gen reg<br>
-def : WriteRes<WriteFCvt, [VulcanF01]> { let Latency = 7; }<br>
-<br>
-// FP move, immed<br>
-// FP move, register<br>
-def : WriteRes<WriteFImm, [VulcanF01]> { let Latency = 4; }<br>
-<br>
-// FP transfer, from gen to vec reg<br>
-// FP transfer, from vec to gen reg<br>
-def : WriteRes<WriteFCopy, [VulcanF01]> { let Latency = 4; }<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;<br>
-<br>
-//---<br>
-// 3.12 ASIMD Integer Instructions<br>
-//---<br>
-<br>
-// ASIMD absolute diff, D-form<br>
-// ASIMD absolute diff, Q-form<br>
-// ASIMD absolute diff accum, D-form<br>
-// ASIMD absolute diff accum, Q-form<br>
-// ASIMD absolute diff accum long<br>
-// ASIMD absolute diff long<br>
-// ASIMD arith, basic<br>
-// ASIMD arith, complex<br>
-// ASIMD compare<br>
-// ASIMD logical (AND, BIC, EOR)<br>
-// ASIMD max/min, basic<br>
-// ASIMD max/min, reduce, 4H/4S<br>
-// ASIMD max/min, reduce, 8B/8H<br>
-// ASIMD max/min, reduce, 16B<br>
-// ASIMD multiply, D-form<br>
-// ASIMD multiply, Q-form<br>
-// ASIMD multiply accumulate long<br>
-// ASIMD multiply accumulate saturating long<br>
-// ASIMD multiply long<br>
-// ASIMD pairwise add and accumulate<br>
-// ASIMD shift accumulate<br>
-// ASIMD shift by immed, basic<br>
-// ASIMD shift by immed and insert, basic, D-form<br>
-// ASIMD shift by immed and insert, basic, Q-form<br>
-// ASIMD shift by immed, complex<br>
-// ASIMD shift by register, basic, D-form<br>
-// ASIMD shift by register, basic, Q-form<br>
-// ASIMD shift by register, complex, D-form<br>
-// ASIMD shift by register, complex, Q-form<br>
-def : WriteRes<WriteV, [VulcanF01]> { let Latency = 7; }<br>
-<br>
-// ASIMD arith, reduce, 4H/4S<br>
-// ASIMD arith, reduce, 8B/8H<br>
-// ASIMD arith, reduce, 16B<br>
-def : InstRW<[VulcanWrite_5Cyc_F01],<br>
- (instregex "^ADDVv", "^SADDLVv", "^UADDLVv")>;<br>
-<br>
-// ASIMD logical (MOV, MVN, ORN, ORR)<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^ORRv", "^ORNv", "^NOTv")>;<br>
-<br>
-// ASIMD polynomial (8x8) multiply long<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instrs PMULLv8i8, PMULLv16i8)>;<br>
-<br>
-//---<br>
-// 3.13 ASIMD Floating-point Instructions<br>
-//---<br>
-<br>
-// ASIMD FP absolute value<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FABSv")>;<br>
-<br>
-// ASIMD FP arith, normal, D-form<br>
-// ASIMD FP arith, normal, Q-form<br>
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FABDv", "^FADDv", "^FSUBv")>;<br>
-<br>
-// ASIMD FP arith,pairwise, D-form<br>
-// ASIMD FP arith, pairwise, Q-form<br>
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FADDPv")>;<br>
-<br>
-// ASIMD FP compare, D-form<br>
-// ASIMD FP compare, Q-form<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FACGEv", "^FACGTv")>;<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FCMEQv", "^FCMGEv",<br>
- "^FCMGTv", "^FCMLEv",<br>
- "^FCMLTv")>;<br>
-<br>
-// ASIMD FP convert, long<br>
-// ASIMD FP convert, narrow<br>
-// ASIMD FP convert, other, D-form<br>
-// ASIMD FP convert, other, Q-form<br>
-// NOTE: Handled by WriteV.<br>
-<br>
-// ASIMD FP divide, D-form, F32<br>
-def : InstRW<[VulcanWrite_16Cyc_F01]<wbr>, (instrs FDIVv2f32)>;<br>
-<br>
-// ASIMD FP divide, Q-form, F32<br>
-def : InstRW<[VulcanWrite_16Cyc_F01]<wbr>, (instrs FDIVv4f32)>;<br>
-<br>
-// ASIMD FP divide, Q-form, F64<br>
-def : InstRW<[VulcanWrite_23Cyc_F01]<wbr>, (instrs FDIVv2f64)>;<br>
-<br>
-// ASIMD FP max/min, normal, D-form<br>
-// ASIMD FP max/min, normal, Q-form<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMAXv", "^FMAXNMv",<br>
- "^FMINv", "^FMINNMv")>;<br>
-<br>
-// ASIMD FP max/min, pairwise, D-form<br>
-// ASIMD FP max/min, pairwise, Q-form<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMAXPv", "^FMAXNMPv",<br>
- "^FMINPv", "^FMINNMPv")>;<br>
-<br>
-// ASIMD FP max/min, reduce<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMAXVv", "^FMAXNMVv",<br>
- "^FMINVv", "^FMINNMVv")>;<br>
-<br>
-// ASIMD FP multiply, D-form, FZ<br>
-// ASIMD FP multiply, D-form, no FZ<br>
-// ASIMD FP multiply, Q-form, FZ<br>
-// ASIMD FP multiply, Q-form, no FZ<br>
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FMULv", "^FMULXv")>;<br>
-<br>
-// ASIMD FP multiply accumulate, Dform, FZ<br>
-// ASIMD FP multiply accumulate, Dform, no FZ<br>
-// ASIMD FP multiply accumulate, Qform, FZ<br>
-// ASIMD FP multiply accumulate, Qform, no FZ<br>
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FMLAv", "^FMLSv")>;<br>
-<br>
-// ASIMD FP negate<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FNEGv")>;<br>
-<br>
-// ASIMD FP round, D-form<br>
-// ASIMD FP round, Q-form<br>
-// NOTE: Handled by WriteV.<br>
-<br>
-//--<br>
-// 3.14 ASIMD Miscellaneous Instructions<br>
-//--<br>
-<br>
-// ASIMD bit reverse<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^RBITv")>;<br>
-<br>
-// ASIMD bitwise insert, D-form<br>
-// ASIMD bitwise insert, Q-form<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^BIFv", "^BITv", "^BSLv")>;<br>
-<br>
-// ASIMD count, D-form<br>
-// ASIMD count, Q-form<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^CLSv", "^CLZv", "^CNTv")>;<br>
-<br>
-// ASIMD duplicate, gen reg<br>
-// ASIMD duplicate, element<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^DUPv")>;<br>
-<br>
-// ASIMD extract<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^EXTv")>;<br>
-<br>
-// ASIMD extract narrow<br>
-// ASIMD extract narrow, saturating<br>
-// NOTE: Handled by WriteV.<br>
-<br>
-// ASIMD insert, element to element<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^INSv")>;<br>
-<br>
-// ASIMD move, integer immed<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^MOVIv", "^MOVIDv")>;<br>
-<br>
-// ASIMD move, FP immed<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^FMOVv")>;<br>
-<br>
-// ASIMD reciprocal estimate, D-form<br>
-// ASIMD reciprocal estimate, Q-form<br>
-def : InstRW<[VulcanWrite_5Cyc_F01],<br>
- (instregex "^FRECPEv", "^FRECPXv", "^URECPEv",<br>
- "^FRSQRTEv", "^URSQRTEv")>;<br>
-<br>
-// ASIMD reciprocal step, D-form, FZ<br>
-// ASIMD reciprocal step, D-form, no FZ<br>
-// ASIMD reciprocal step, Q-form, FZ<br>
-// ASIMD reciprocal step, Q-form, no FZ<br>
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^FRECPSv", "^FRSQRTSv")>;<br>
-<br>
-// ASIMD reverse<br>
-def : InstRW<[VulcanWrite_5Cyc_F01],<br>
- (instregex "^REV16v", "^REV32v", "^REV64v")>;<br>
-<br>
-// ASIMD table lookup, D-form<br>
-// ASIMD table lookup, Q-form<br>
-def : InstRW<[VulcanWrite_8Cyc_F01], (instregex "^TBLv", "^TBXv")>;<br>
-<br>
-// ASIMD transfer, element to word or word<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^UMOVv")>;<br>
-<br>
-// ASIMD transfer, element to gen reg<br>
-def : InstRW<[VulcanWrite_6Cyc_F01], (instregex "^SMOVv", "^UMOVv")>;<br>
-<br>
-// ASIMD transfer gen reg to element<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^INSv")>;<br>
-<br>
-// ASIMD transpose<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^TRN1v", "^TRN2v",<br>
- "^UZP1v", "^UZP2v")>;<br>
-<br>
-// ASIMD unzip/zip<br>
-def : InstRW<[VulcanWrite_5Cyc_F01], (instregex "^ZIP1v", "^ZIP2v")>;<br>
-<br>
-//--<br>
-// 3.15 ASIMD Load Instructions<br>
-//--<br>
-<br>
-// ASIMD load, 1 element, multiple, 1 reg, D-form<br>
-// ASIMD load, 1 element, multiple, 1 reg, Q-form<br>
-def : InstRW<[VulcanWrite_4Cyc_LS01]<wbr>,<br>
- (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_4Cyc_LS01, WriteAdr],<br>
- (instregex "^LD1Onev(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
-<br>
-// ASIMD load, 1 element, multiple, 2 reg, D-form<br>
-// ASIMD load, 1 element, multiple, 2 reg, Q-form<br>
-def : InstRW<[VulcanWrite_4Cyc_LS01]<wbr>,<br>
- (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_4Cyc_LS01, WriteAdr],<br>
- (instregex "^LD1Twov(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
-<br>
-// ASIMD load, 1 element, multiple, 3 reg, D-form<br>
-// ASIMD load, 1 element, multiple, 3 reg, Q-form<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01]<wbr>,<br>
- (instregex "^LD1Threev(8b|4h|2s|1d|16b|<wbr>8h|4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01, WriteAdr],<br>
- (instregex "^LD1Threev(8b|4h|2s|1d|16b|<wbr>8h|4s|2d)_POST$")>;<br>
-<br>
-// ASIMD load, 1 element, multiple, 4 reg, D-form<br>
-// ASIMD load, 1 element, multiple, 4 reg, Q-form<br>
-def : InstRW<[VulcanWrite_6Cyc_LS01]<wbr>,<br>
- (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_6Cyc_LS01, WriteAdr],<br>
- (instregex "^LD1Fourv(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
-<br>
-// ASIMD load, 1 element, one lane, B/H/S<br>
-// ASIMD load, 1 element, one lane, D<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01], (instregex "^LD1i(8|16|32|64)$")>;<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD1i(8|16|32|64)_POST$")>;<br>
-<br>
-// ASIMD load, 1 element, all lanes, D-form, B/H/S<br>
-// ASIMD load, 1 element, all lanes, D-form, D<br>
-// ASIMD load, 1 element, all lanes, Q-form<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01],<br>
- (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)$")>;<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD1Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)_POST$")>;<br>
-<br>
-// ASIMD load, 2 element, multiple, D-form, B/H/S<br>
-// ASIMD load, 2 element, multiple, Q-form, D<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01],<br>
- (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|<wbr>2d)$")>;<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD2Twov(8b|4h|2s|16b|8h|4s|<wbr>2d)_POST$")>;<br>
-<br>
-// ASIMD load, 2 element, one lane, B/H<br>
-// ASIMD load, 2 element, one lane, S<br>
-// ASIMD load, 2 element, one lane, D<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01], (instregex "^LD2i(8|16|32|64)$")>;<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD2i(8|16|32|64)_POST$")>;<br>
-<br>
-// ASIMD load, 2 element, all lanes, D-form, B/H/S<br>
-// ASIMD load, 2 element, all lanes, D-form, D<br>
-// ASIMD load, 2 element, all lanes, Q-form<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01],<br>
- (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)$")>;<br>
-def : InstRW<[VulcanWrite_5Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD2Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)_POST$")>;<br>
-<br>
-// ASIMD load, 3 element, multiple, D-form, B/H/S<br>
-// ASIMD load, 3 element, multiple, Q-form, B/H/S<br>
-// ASIMD load, 3 element, multiple, Q-form, D<br>
-def : InstRW<[VulcanWrite_8Cyc_LS01_<wbr>F01],<br>
- (instregex "^LD3Threev(8b|4h|2s|16b|8h|<wbr>4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_8Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD3Threev(8b|4h|2s|16b|8h|<wbr>4s|2d)_POST$")>;<br>
-<br>
-// ASIMD load, 3 element, one lone, B/H<br>
-// ASIMD load, 3 element, one lane, S<br>
-// ASIMD load, 3 element, one lane, D<br>
-def : InstRW<[VulcanWrite_7Cyc_LS01_<wbr>F01], (instregex "^LD3i(8|16|32|64)$")>;<br>
-def : InstRW<[VulcanWrite_7Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD3i(8|16|32|64)_POST$")>;<br>
-<br>
-// ASIMD load, 3 element, all lanes, D-form, B/H/S<br>
-// ASIMD load, 3 element, all lanes, D-form, D<br>
-// ASIMD load, 3 element, all lanes, Q-form, B/H/S<br>
-// ASIMD load, 3 element, all lanes, Q-form, D<br>
-def : InstRW<[VulcanWrite_7Cyc_LS01_<wbr>F01],<br>
- (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)$")>;<br>
-def : InstRW<[VulcanWrite_7Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD3Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)_POST$")>;<br>
-<br>
-// ASIMD load, 4 element, multiple, D-form, B/H/S<br>
-// ASIMD load, 4 element, multiple, Q-form, B/H/S<br>
-// ASIMD load, 4 element, multiple, Q-form, D<br>
-def : InstRW<[VulcanWrite_8Cyc_LS01_<wbr>F01],<br>
- (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|<wbr>2d)$")>;<br>
-def : InstRW<[VulcanWrite_8Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD4Fourv(8b|4h|2s|16b|8h|4s|<wbr>2d)_POST$")>;<br>
-<br>
-// ASIMD load, 4 element, one lane, B/H<br>
-// ASIMD load, 4 element, one lane, S<br>
-// ASIMD load, 4 element, one lane, D<br>
-def : InstRW<[VulcanWrite_6Cyc_LS01_<wbr>F01], (instregex "^LD4i(8|16|32|64)$")>;<br>
-def : InstRW<[VulcanWrite_6Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD4i(8|16|32|64)_POST$")>;<br>
-<br>
-// ASIMD load, 4 element, all lanes, D-form, B/H/S<br>
-// ASIMD load, 4 element, all lanes, D-form, D<br>
-// ASIMD load, 4 element, all lanes, Q-form, B/H/S<br>
-// ASIMD load, 4 element, all lanes, Q-form, D<br>
-def : InstRW<[VulcanWrite_6Cyc_LS01_<wbr>F01],<br>
- (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)$")>;<br>
-def : InstRW<[VulcanWrite_6Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^LD4Rv(8b|4h|2s|1d|16b|8h|4s|<wbr>2d)_POST$")>;<br>
-<br>
-//--<br>
-// 3.16 ASIMD Store Instructions<br>
-//--<br>
-<br>
-// ASIMD store, 1 element, multiple, 1 reg, D-form<br>
-// ASIMD store, 1 element, multiple, 1 reg, Q-form<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01]<wbr>,<br>
- (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],<br>
- (instregex "^ST1Onev(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
-<br>
-// ASIMD store, 1 element, multiple, 2 reg, D-form<br>
-// ASIMD store, 1 element, multiple, 2 reg, Q-form<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01]<wbr>,<br>
- (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],<br>
- (instregex "^ST1Twov(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
-<br>
-// ASIMD store, 1 element, multiple, 3 reg, D-form<br>
-// ASIMD store, 1 element, multiple, 3 reg, Q-form<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01]<wbr>,<br>
- (instregex "^ST1Threev(8b|4h|2s|1d|16b|<wbr>8h|4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],<br>
- (instregex "^ST1Threev(8b|4h|2s|1d|16b|<wbr>8h|4s|2d)_POST$")>;<br>
-<br>
-// ASIMD store, 1 element, multiple, 4 reg, D-form<br>
-// ASIMD store, 1 element, multiple, 4 reg, Q-form<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01]<wbr>,<br>
- (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01, WriteAdr],<br>
- (instregex "^ST1Fourv(8b|4h|2s|1d|16b|8h|<wbr>4s|2d)_POST$")>;<br>
-<br>
-// ASIMD store, 1 element, one lane, B/H/S<br>
-// ASIMD store, 1 element, one lane, D<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01],<br>
- (instregex "^ST1i(8|16|32|64)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^ST1i(8|16|32|64)_POST$")>;<br>
-<br>
-// ASIMD store, 2 element, multiple, D-form, B/H/S<br>
-// ASIMD store, 2 element, multiple, Q-form, B/H/S<br>
-// ASIMD store, 2 element, multiple, Q-form, D<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01],<br>
- (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|<wbr>2d)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^ST2Twov(8b|4h|2s|16b|8h|4s|<wbr>2d)_POST$")>;<br>
-<br>
-// ASIMD store, 2 element, one lane, B/H/S<br>
-// ASIMD store, 2 element, one lane, D<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01],<br>
- (instregex "^ST2i(8|16|32|64)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^ST2i(8|16|32|64)_POST$")>;<br>
-<br>
-// ASIMD store, 3 element, multiple, D-form, B/H/S<br>
-// ASIMD store, 3 element, multiple, Q-form, B/H/S<br>
-// ASIMD store, 3 element, multiple, Q-form, D<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01],<br>
- (instregex "^ST3Threev(8b|4h|2s|16b|8h|<wbr>4s|2d)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^ST3Threev(8b|4h|2s|16b|8h|<wbr>4s|2d)_POST$")>;<br>
-<br>
-// ASIMD store, 3 element, one lane, B/H<br>
-// ASIMD store, 3 element, one lane, S<br>
-// ASIMD store, 3 element, one lane, D<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01], (instregex "^ST3i(8|16|32|64)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^ST3i(8|16|32|64)_POST$")>;<br>
-<br>
-// ASIMD store, 4 element, multiple, D-form, B/H/S<br>
-// ASIMD store, 4 element, multiple, Q-form, B/H/S<br>
-// ASIMD store, 4 element, multiple, Q-form, D<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01],<br>
- (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|<wbr>2d)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^ST4Fourv(8b|4h|2s|16b|8h|4s|<wbr>2d)_POST$")>;<br>
-<br>
-// ASIMD store, 4 element, one lane, B/H<br>
-// ASIMD store, 4 element, one lane, S<br>
-// ASIMD store, 4 element, one lane, D<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01], (instregex "^ST4i(8|16|32|64)$")>;<br>
-def : InstRW<[VulcanWrite_1Cyc_LS01_<wbr>F01, WriteAdr],<br>
- (instregex "^ST4i(8|16|32|64)_POST$")>;<br>
-<br>
-//--<br>
-// 3.17 Cryptography Extensions<br>
-//--<br>
-<br>
-// Crypto AES ops<br>
-def : InstRW<[VulcanWrite_5Cyc_F1], (instregex "^AES")>;<br>
-<br>
-// Crypto polynomial (64x64) multiply long<br>
-def : InstRW<[VulcanWrite_5Cyc_F1], (instrs PMULLv1i64, PMULLv2i64)>;<br>
-<br>
-// Crypto SHA1 xor ops<br>
-// Crypto SHA1 schedule acceleration ops<br>
-// Crypto SHA256 schedule acceleration op (1 u-op)<br>
-// Crypto SHA256 schedule acceleration op (2 u-ops)<br>
-// Crypto SHA256 hash acceleration ops<br>
-def : InstRW<[VulcanWrite_7Cyc_F1], (instregex "^SHA")>;<br>
-<br>
-//--<br>
-// 3.18 CRC<br>
-//--<br>
-<br>
-// CRC checksum ops<br>
-def : InstRW<[VulcanWrite_4Cyc_I1], (instregex "^CRC32")>;<br>
-<br>
-} // SchedModel = VulcanModel<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64Subtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64Subtarget.cpp?<wbr>rev=297190&r1=297189&r2=<wbr>297190&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64Subtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64Subtarget.cpp Tue Mar 7 13:42:40 2017<br>
@@ -81,16 +81,22 @@ void AArch64Subtarget::<wbr>initializePropert<br>
MinPrefetchStride = 1024;<br>
MaxPrefetchIterationsAhead = 11;<br>
break;<br>
- case Vulcan:<br>
+ case ThunderX2T99:<br>
+ CacheLineSize = 64;<br>
+ PrefFunctionAlignment = 3;<br>
+ PrefLoopAlignment = 2;<br>
MaxInterleaveFactor = 4;<br>
+ PrefetchDistance = 128;<br>
+ MinPrefetchStride = 1024;<br>
+ MaxPrefetchIterationsAhead = 4;<br>
break;<br>
case ThunderX:<br>
case ThunderXT88:<br>
case ThunderXT81:<br>
case ThunderXT83:<br>
CacheLineSize = 128;<br>
- PrefFunctionAlignment = 4;<br>
- PrefLoopAlignment = 4;<br>
+ PrefFunctionAlignment = 3;<br>
+ PrefLoopAlignment = 2;<br>
break;<br>
case CortexA35: break;<br>
case CortexA53: break;<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64Subtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64Subtarget.h?<wbr>rev=297190&r1=297189&r2=<wbr>297190&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64Subtarget.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64Subtarget.h Tue Mar 7 13:42:40 2017<br>
@@ -45,7 +45,7 @@ public:<br>
ExynosM1,<br>
Falkor,<br>
Kryo,<br>
- Vulcan,<br>
+ ThunderX2T99,<br>
ThunderX,<br>
ThunderXT81,<br>
ThunderXT83,<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/cpus.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cpus.ll?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/cpus.ll?rev=<wbr>297190&r1=297189&r2=297190&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/cpus.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/cpus.ll Tue Mar 7 13:42:40 2017<br>
@@ -12,7 +12,7 @@<br>
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s<br>
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=falkor 2>&1 | FileCheck %s<br>
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s<br>
-; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=vulcan 2>&1 | FileCheck %s<br>
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s<br>
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID<br>
<br>
; CHECK-NOT: {{.*}} is not a recognized processor for this target<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/machine-combiner-madd.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/machine-combiner-madd.ll?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/machine-<wbr>combiner-madd.ll?rev=297190&<wbr>r1=297189&r2=297190&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/machine-combiner-madd.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/machine-combiner-madd.<wbr>ll Tue Mar 7 13:42:40 2017<br>
@@ -6,7 +6,7 @@<br>
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m1 < %s | FileCheck %s<br>
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m2 < %s | FileCheck %s<br>
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo < %s | FileCheck %s<br>
-; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=vulcan < %s | FileCheck %s<br>
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s<br>
<br>
; Make sure that inst-combine fuses the multiply add in the addressing mode of<br>
; the load.<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/remat.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/remat.ll?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/remat.ll?rev=<wbr>297190&r1=297189&r2=297190&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/remat.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/remat.ll Tue Mar 7 13:42:40 2017<br>
@@ -8,7 +8,7 @@<br>
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s | FileCheck %s<br>
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=falkor -o - %s | FileCheck %s<br>
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s | FileCheck %s<br>
-; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=vulcan -o - %s | FileCheck %s<br>
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s<br>
; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s<br>
<br>
%X = type { i64, i64, i64 }<br>
<br>
Modified: llvm/trunk/unittests/Support/<wbr>TargetParserTest.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=297190&r1=297189&r2=297190&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/unittests/<wbr>Support/TargetParserTest.cpp?<wbr>rev=297190&r1=297189&r2=<wbr>297190&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/unittests/Support/<wbr>TargetParserTest.cpp (original)<br>
+++ llvm/trunk/unittests/Support/<wbr>TargetParserTest.cpp Tue Mar 7 13:42:40 2017<br>
@@ -643,8 +643,9 @@ TEST(TargetParserTest, testAArch64CPU) {<br>
"kryo", "armv8-a", "crypto-neon-fp-armv8",<br>
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD, "8-A"));<br>
EXPECT_TRUE(testAArch64CPU(<br>
- "vulcan", "armv8.1-a", "crypto-neon-fp-armv8",<br>
- AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD, "8.1-A"));<br>
+ "thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",<br>
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |<br>
+ AArch64::AEK_SIMD, "8.1-A"));<br>
EXPECT_TRUE(testAArch64CPU(<br>
"thunderx", "armv8-a", "crypto-neon-fp-armv8",<br>
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |<br>
@@ -700,7 +701,7 @@ TEST(TargetParserTest, testAArch64Extens<br>
EXPECT_FALSE(<wbr>testAArch64Extension("cyclone"<wbr>, 0, "ras"));<br>
EXPECT_FALSE(<wbr>testAArch64Extension("exynos-<wbr>m1", 0, "ras"));<br>
EXPECT_FALSE(<wbr>testAArch64Extension("kryo", 0, "ras"));<br>
- EXPECT_FALSE(<wbr>testAArch64Extension("vulcan", 0, "ras"));<br>
+ EXPECT_FALSE(<wbr>testAArch64Extension("<wbr>thunderx2t99", 0, "ras"));<br>
EXPECT_FALSE(<wbr>testAArch64Extension("<wbr>thunderx", 0, "lse"));<br>
EXPECT_FALSE(<wbr>testAArch64Extension("<wbr>thunderxt81", 0, "lse"));<br>
EXPECT_FALSE(<wbr>testAArch64Extension("<wbr>thunderxt83", 0, "lse"));<br>
<br>
<br>
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</blockquote></div><br></div>