<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">I’ll poke Matthias or such tomorrow at work and see if we can figure something out. It’s a fairly small test case so hopefully it’s something trivial…<div class=""><br class=""></div><div class="">—escha</div><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Feb 23, 2017, at 6:13 PM, Mekhanoshin, Stanislav <<a href="mailto:Stanislav.Mekhanoshin@amd.com" class="">Stanislav.Mekhanoshin@amd.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="WordSection1" style="page: WordSection1; font-family: Helvetica; font-size: 12px; font-style: normal; font-variant-caps: normal; font-weight: normal; letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">Is there anything I can use to reproduce it?<o:p class=""></o:p></span></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""><o:p class=""> </o:p></span></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">Stas<o:p class=""></o:p></span></div></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""><o:p class=""> </o:p></span></div><div class=""><div style="border-style: solid none none; border-top-color: rgb(225, 225, 225); border-top-width: 1pt; padding: 3pt 0cm 0cm;" class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><b class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class="">From:</span></b><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span class="Apple-converted-space"> </span><a href="mailto:fglaser@apple.com" class="">fglaser@apple.com</a> [<a href="mailto:fglaser@apple.com" class="">mailto:fglaser@apple.com</a>]<span class="Apple-converted-space"> </span><b class="">On Behalf Of<span class="Apple-converted-space"> </span></b><a href="mailto:escha@apple.com" class="">escha@apple.com</a><br class=""><b class="">Sent:</b><span class="Apple-converted-space"> </span>Thursday, February 23, 2017 6:07 PM<br class=""><b class="">To:</b><span class="Apple-converted-space"> </span>Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com><br class=""><b class="">Cc:</b><span class="Apple-converted-space"> </span>Rui Ueyama <ruiu@google.com>; llvm-commits <llvm-commits@lists.llvm.org><br class=""><b class="">Subject:</b><span class="Apple-converted-space"> </span>Re: [llvm] r296009 - Correct register pressure calculation in presence of subregs<o:p class=""></o:p></span></div></div></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">This commit is causing crashes in our test suite in an out of tree target.<o:p class=""></o:p></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">Assertion failed: (CurrSetPressure[*PSetI] >= Weight && "register pressure underflow"), function decreaseSetPressure, file /Users/_________/llvm-puzzlebox/lib/CodeGen/RegisterPressure.cpp, line 89.<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">0 llc 0x00000001066317a8 llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 40<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">1 llc 0x0000000106631ea6 SignalHandler(int) + 454<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">2 libsystem_platform.dylib 0x00007fff95dbbbba _sigtramp + 26<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">3 libsystem_platform.dylib 000000000000000000 _sigtramp + 1780761696<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">4 libsystem_c.dylib 0x00007fff95c43440 abort + 129<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">5 libsystem_c.dylib 0x00007fff95c0a8b3 basename_r + 0<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">6 llc 0x0000000105e43f96 llvm::RegPressureTracker::decreaseRegPressure(unsigned int, llvm::LaneBitmask, llvm::LaneBitmask) + 326<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">7 llc 0x0000000105e46510 llvm::RegPressureTracker::recede(llvm::RegisterOperands const&, llvm::SmallVectorImpl<llvm::RegisterMaskPair>*) + 368<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">8 llc 0x0000000105e6dcca llvm::ScheduleDAGInstrs::buildSchedGraph(llvm::AAResults*, llvm::RegPressureTracker*, llvm::PressureDiffs*, llvm::LiveIntervals*, bool) + 7194<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">9 llc 0x0000000105d9dac7 llvm::ScheduleDAGMILive::buildDAGWithRegPressure() + 167<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">10 llc 0x0000000105d9d27c llvm::ScheduleDAGMILive::schedule() + 236<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">11 llc 0x0000000105da7da4 (anonymous namespace)::MachineSchedulerBase::scheduleRegions(llvm::ScheduleDAGInstrs&, bool) + 2404<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">12 llc 0x0000000105da72b5 (anonymous namespace)::MachineScheduler::runOnMachineFunction(llvm::MachineFunction&) + 853<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">13 llc 0x0000000105d3ca06 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 310<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">14 llc 0x0000000105ff5ce3 llvm::FPPassManager::runOnFunction(llvm::Function&) + 547<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">15 llc 0x0000000105ff5f43 llvm::FPPassManager::runOnModule(llvm::Module&) + 51<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class=""><br class=""><br class=""><o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif; background-color: white;" class=""><span style="font-size: 8.5pt; font-family: Menlo, serif;" class="">—escha<o:p class=""></o:p></span></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""> </o:p></div><div class=""><blockquote style="margin-top: 5pt; margin-bottom: 5pt;" class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">On Feb 23, 2017, at 2:03 PM, Mekhanoshin, Stanislav via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" style="color: purple; text-decoration: underline;" class="">llvm-commits@lists.llvm.org</a>> wrote:<o:p class=""></o:p></div></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""> </o:p></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">Submitted r296021.</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">Stas</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><b class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class="">From:</span></b><span class="apple-converted-space"><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class=""> </span></span><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class="">Rui Ueyama [<a href="mailto:ruiu@google.com" style="color: purple; text-decoration: underline;" class="">mailto:ruiu@google.com</a>]<span class="apple-converted-space"> </span><br class=""><b class="">Sent:</b><span class="apple-converted-space"> </span>Thursday, February 23, 2017 1:46 PM<br class=""><b class="">To:</b><span class="apple-converted-space"> </span>Mekhanoshin, Stanislav <<a href="mailto:Stanislav.Mekhanoshin@amd.com" style="color: purple; text-decoration: underline;" class="">Stanislav.Mekhanoshin@amd.com</a>><br class=""><b class="">Cc:</b><span class="apple-converted-space"> </span>llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" style="color: purple; text-decoration: underline;" class="">llvm-commits@lists.llvm.org</a>><br class=""><b class="">Subject:</b><span class="apple-converted-space"> </span>Re: [llvm] r296009 - Correct register pressure calculation in presence of subregs</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Thanks!<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">On Thu, Feb 23, 2017 at 1:44 PM, Mekhanoshin, Stanislav <<a href="mailto:Stanislav.Mekhanoshin@amd.com" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">Stanislav.Mekhanoshin@amd.com</span></a>> wrote:<o:p class=""></o:p></div></div><blockquote style="border-style: none none none solid; border-left-color: rgb(204, 204, 204); border-left-width: 1pt; padding: 0cm 0cm 0cm 6pt; margin: 5pt 0cm 5pt 4.8pt;" class=""><div class=""><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">I’m going to add this to shut the warning:</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">diff --git a/lib/Target/AMDGPU/SIRegisterInfo.h b/lib/Target/AMDGPU/SIRegisterInfo.h</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">index 844f031..258de19 100644</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">--- a/lib/Target/AMDGPU/SIRegisterInfo.h</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">+++ b/lib/Target/AMDGPU/SIRegisterInfo.h</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">@@ -26,6 +26,8 @@ class SISubtarget;</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">class SIMachineFunctionInfo;</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">class SIRegisterInfo final : public AMDGPURegisterInfo {</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">+ using AMDGPUGenRegisterInfo::getRegUnitWeight;</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">+</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">I will do it as soon as tests pass.</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">Stas</span><o:p class=""></o:p></div></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div style="border-style: solid none none; border-top-color: rgb(225, 225, 225); border-top-width: 1pt; padding: 3pt 0cm 0cm;" class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><b class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class="">From:</span></b><span class="apple-converted-space"><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class=""> </span></span><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class="">Mekhanoshin, Stanislav<span class="apple-converted-space"> </span><br class=""><b class="">Sent:</b><span class="apple-converted-space"> </span>Thursday, February 23, 2017 1:08 PM<br class=""><b class="">To:</b><span class="apple-converted-space"> </span>'Rui Ueyama' <<a href="mailto:ruiu@google.com" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">ruiu@google.com</span></a>><br class=""><b class="">Cc:</b><span class="apple-converted-space"> </span>llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">llvm-commits@lists.llvm.org</span></a>><br class=""><b class="">Subject:</b><span class="apple-converted-space"> </span>RE: [llvm] r296009 - Correct register pressure calculation in presence of subregs</span><o:p class=""></o:p></div></div></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">Hi,</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">I’m looking into this. Said warning is only issued by clang and hiding was intended here. I’m building with clang instead of gcc now to reproduce.</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">Stas</span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span><o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><b class=""><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class="">From:</span></b><span class="apple-converted-space"><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class=""> </span></span><span lang="EN-US" style="font-size: 11pt; font-family: Calibri, sans-serif;" class="">Rui Ueyama [<a href="mailto:ruiu@google.com" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">mailto:ruiu@google.com</span></a>]<span class="apple-converted-space"> </span><br class=""><b class="">Sent:</b><span class="apple-converted-space"> </span>Thursday, February 23, 2017 12:50 PM<br class=""><b class="">To:</b><span class="apple-converted-space"> </span>Mekhanoshin, Stanislav <<a href="mailto:Stanislav.Mekhanoshin@amd.com" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">Stanislav.Mekhanoshin@amd.com</span></a>><br class=""><b class="">Cc:</b><span class="apple-converted-space"> </span>llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">llvm-commits@lists.llvm.org</span></a>><br class=""><b class="">Subject:</b><span class="apple-converted-space"> </span>Re: [llvm] r296009 - Correct register pressure calculation in presence of subregs</span><o:p class=""></o:p></div></div><div class=""><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Hi,<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">This seems to have caused this warnings. Can you take a look?<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Building CXX object /ssd/b/lib/Target/AMDGPU/CMakeFiles/LLVMAMDGPUCodeGen.dir/SIOptimizeExecMasking.cpp.o<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">In file included from /ssd/llvm-project/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp:11:<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">In file included from //ssd/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h:22:<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">In file included from //ssd/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h:21:<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">//ssd/llvm-project/llvm/lib/Target/AMDGPU/SIRegisterInfo.h:231:12: warning: 'llvm::SIRegisterInfo::getRegUnitWeight' hides overloaded virtual function [-Woverloaded-virtual]<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> unsigned getRegUnitWeight(const MachineRegisterInfo &MRI,<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> ^<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">//ssd/b/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc:17362:12: note: hidden overloaded virtual function 'llvm::AMDGPUGenRegisterInfo::getRegUnitWeight' declared here: different number of parameters (1 vs 3)<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> unsigned getRegUnitWeight(unsigned RegUnit) const override;<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> ^<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">1 warning generated.<o:p class=""></o:p></div></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">On Thu, Feb 23, 2017 at 12:19 PM, Stanislav Mekhanoshin via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">llvm-commits@lists.llvm.org</span></a>> wrote:<o:p class=""></o:p></div></div><blockquote style="border-style: none none none solid; border-left-color: rgb(204, 204, 204); border-left-width: 1pt; padding: 0cm 0cm 0cm 6pt; margin: 5pt 0cm 5pt 4.8pt;" class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Author: rampitec<br class="">Date: Thu Feb 23 14:19:44 2017<br class="">New Revision: 296009<br class=""><br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project?rev=296009&view=rev" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project?rev=296009&view=rev</span></a><br class="">Log:<br class="">Correct register pressure calculation in presence of subregs<br class=""><br class="">If a subreg is used in an instruction it counts as a whole superreg<br class="">for the purpose of register pressure calculation. This patch corrects<br class="">improper register pressure calculation by examining operand's lane mask.<br class=""><br class="">Differential Revision:<span class="apple-converted-space"> </span><a href="https://reviews.llvm.org/D29835" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">https://reviews.llvm.org/D29835</span></a><br class=""><br class="">Added:<br class=""> llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir<br class="">Modified:<br class=""> llvm/trunk/include/llvm/CodeGen/RegisterPressure.h<br class=""> llvm/trunk/include/llvm/Target/TargetRegisterInfo.h<br class=""> llvm/trunk/lib/CodeGen/MachineScheduler.cpp<br class=""> llvm/trunk/lib/CodeGen/RegisterPressure.cpp<br class=""> llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp<br class=""> llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp<br class=""> llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h<br class=""> llvm/trunk/test/CodeGen/AMDGPU/load-global-i32.ll<br class=""><br class="">Modified: llvm/trunk/include/llvm/CodeGen/RegisterPressure.h<br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterPressure.h?rev=296009&r1=296008&r2=296009&view=diff" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterPressure.h?rev=296009&r1=296008&r2=296009&view=diff</span></a><br class="">==============================================================================<br class="">--- llvm/trunk/include/llvm/CodeGen/RegisterPressure.h (original)<br class="">+++ llvm/trunk/include/llvm/CodeGen/RegisterPressure.h Thu Feb 23 14:19:44 2017<br class="">@@ -156,7 +156,7 @@ public:<br class=""> const_iterator begin() const { return &PressureChanges[0]; }<br class=""> const_iterator end() const { return &PressureChanges[MaxPSets]; }<br class=""><br class="">- void addPressureChange(unsigned RegUnit, bool IsDec,<br class="">+ void addPressureChange(RegisterMaskPair P, bool IsDec,<br class=""> const MachineRegisterInfo *MRI);<br class=""><br class=""> void dump(const TargetRegisterInfo &TRI) const;<br class=""><br class="">Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h<br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=296009&r1=296008&r2=296009&view=diff" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=296009&r1=296008&r2=296009&view=diff</span></a><br class="">==============================================================================<br class="">--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)<br class="">+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Feb 23 14:19:44 2017<br class="">@@ -30,6 +30,7 @@ namespace llvm {<br class=""><br class=""> class BitVector;<br class=""> class MachineFunction;<br class="">+class MachineRegisterInfo;<br class=""> class RegScavenger;<br class=""> template<class T> class SmallVectorImpl;<br class=""> class VirtRegMap;<br class="">@@ -719,6 +720,12 @@ public:<br class=""> /// Get the weight in units of pressure for this register unit.<br class=""> virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;<br class=""><br class="">+ /// Get the weight in units of pressure for a sub register of this register<br class="">+ /// unit given a lane mask.<br class="">+ virtual unsigned getRegUnitWeight(const MachineRegisterInfo &MRI,<br class="">+ unsigned RegUnit,<br class="">+ LaneBitmask LaneMask) const;<br class="">+<br class=""> /// Get the number of dimensions of register pressure.<br class=""> virtual unsigned getNumRegPressureSets() const = 0;<br class=""><br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp<br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=296009&r1=296008&r2=296009&view=diff" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=296009&r1=296008&r2=296009&view=diff</span></a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Thu Feb 23 14:19:44 2017<br class="">@@ -1085,7 +1085,7 @@ void ScheduleDAGMILive::updatePressureDi<br class=""> continue;<br class=""><br class=""> PressureDiff &PDiff = getPressureDiff(&SU);<br class="">- PDiff.addPressureChange(Reg, Decrement, &MRI);<br class="">+ PDiff.addPressureChange(P, Decrement, &MRI);<br class=""> DEBUG(<br class=""> dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "<br class=""> << PrintReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)<br class="">@@ -1123,7 +1123,7 @@ void ScheduleDAGMILive::updatePressureDi<br class=""> LI.Query(LIS->getInstructionIndex(*SU->getInstr()));<br class=""> if (LRQ.valueIn() == VNI) {<br class=""> PressureDiff &PDiff = getPressureDiff(SU);<br class="">- PDiff.addPressureChange(Reg, true, &MRI);<br class="">+ PDiff.addPressureChange(P, true, &MRI);<br class=""> DEBUG(<br class=""> dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "<br class=""> << *SU->getInstr();<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/RegisterPressure.cpp<br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterPressure.cpp?rev=296009&r1=296008&r2=296009&view=diff" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterPressure.cpp?rev=296009&r1=296008&r2=296009&view=diff</span></a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/RegisterPressure.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/RegisterPressure.cpp Thu Feb 23 14:19:44 2017<br class="">@@ -46,16 +46,29 @@<br class=""><br class=""> using namespace llvm;<br class=""><br class="">+/// Clamp lane masks to maximum posible value.<br class="">+static void clampMasks(const MachineRegisterInfo &MRI, unsigned Reg,<br class="">+ LaneBitmask& LaneMask1, LaneBitmask& LaneMask2) {<br class="">+ if (TargetRegisterInfo::isVirtualRegister(Reg)) {<br class="">+ LaneBitmask Max = MRI.getMaxLaneMaskForVReg(Reg);<br class="">+ LaneMask1 &= Max;<br class="">+ LaneMask2 &= Max;<br class="">+ }<br class="">+}<br class="">+<br class=""> /// Increase pressure for each pressure set provided by TargetRegisterInfo.<br class=""> static void increaseSetPressure(std::vector<unsigned> &CurrSetPressure,<br class=""> const MachineRegisterInfo &MRI, unsigned Reg,<br class=""> LaneBitmask PrevMask, LaneBitmask NewMask) {<br class=""> assert((PrevMask & ~NewMask).none() && "Must not remove bits");<br class="">- if (PrevMask.any() || NewMask.none())<br class="">+<br class="">+ clampMasks(MRI, Reg, PrevMask, NewMask);<br class="">+ if ((NewMask & ~PrevMask).none())<br class=""> return;<br class=""><br class="">+ const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();<br class="">+ unsigned Weight = TRI->getRegUnitWeight(MRI, Reg, NewMask & ~PrevMask);<br class=""> PSetIterator PSetI = MRI.getPressureSets(Reg);<br class="">- unsigned Weight = PSetI.getWeight();<br class=""> for (; PSetI.isValid(); ++PSetI)<br class=""> CurrSetPressure[*PSetI] += Weight;<br class=""> }<br class="">@@ -65,11 +78,13 @@ static void decreaseSetPressure(std::vec<br class=""> const MachineRegisterInfo &MRI, unsigned Reg,<br class=""> LaneBitmask PrevMask, LaneBitmask NewMask) {<br class=""> //assert((NewMask & !PrevMask) == 0 && "Must not add bits");<br class="">- if (NewMask.any() || PrevMask.none())<br class="">+ clampMasks(MRI, Reg, PrevMask, NewMask);<br class="">+ if ((~NewMask & PrevMask).none())<br class=""> return;<br class=""><br class="">+ const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();<br class="">+ unsigned Weight = TRI->getRegUnitWeight(MRI, Reg, ~NewMask & PrevMask);<br class=""> PSetIterator PSetI = MRI.getPressureSets(Reg);<br class="">- unsigned Weight = PSetI.getWeight();<br class=""> for (; PSetI.isValid(); ++PSetI) {<br class=""> assert(CurrSetPressure[*PSetI] >= Weight && "register pressure underflow");<br class=""> CurrSetPressure[*PSetI] -= Weight;<br class="">@@ -139,11 +154,14 @@ void PressureDiff::dump(const TargetRegi<br class=""> void RegPressureTracker::increaseRegPressure(unsigned RegUnit,<br class=""> LaneBitmask PreviousMask,<br class=""> LaneBitmask NewMask) {<br class="">- if (PreviousMask.any() || NewMask.none())<br class="">+ clampMasks(*MRI, RegUnit, PreviousMask, NewMask);<br class="">+ if ((NewMask & ~PreviousMask).none())<br class=""> return;<br class=""><br class="">+ const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();<br class="">+ unsigned Weight = TRI->getRegUnitWeight(*MRI, RegUnit,<br class="">+ NewMask & ~PreviousMask);<br class=""> PSetIterator PSetI = MRI->getPressureSets(RegUnit);<br class="">- unsigned Weight = PSetI.getWeight();<br class=""> for (; PSetI.isValid(); ++PSetI) {<br class=""> CurrSetPressure[*PSetI] += Weight;<br class=""> P.MaxSetPressure[*PSetI] =<br class="">@@ -644,17 +662,19 @@ void PressureDiffs::addInstruction(unsig<br class=""> PressureDiff &PDiff = (*this)[Idx];<br class=""> assert(!PDiff.begin()->isValid() && "stale PDiff");<br class=""> for (const RegisterMaskPair &P : RegOpers.Defs)<br class="">- PDiff.addPressureChange(P.RegUnit, true, &MRI);<br class="">+ PDiff.addPressureChange(P, true, &MRI);<br class=""><br class=""> for (const RegisterMaskPair &P : RegOpers.Uses)<br class="">- PDiff.addPressureChange(P.RegUnit, false, &MRI);<br class="">+ PDiff.addPressureChange(P, false, &MRI);<br class=""> }<br class=""><br class=""> /// Add a change in pressure to the pressure diff of a given instruction.<br class="">-void PressureDiff::addPressureChange(unsigned RegUnit, bool IsDec,<br class="">+void PressureDiff::addPressureChange(RegisterMaskPair P, bool IsDec,<br class=""> const MachineRegisterInfo *MRI) {<br class="">- PSetIterator PSetI = MRI->getPressureSets(RegUnit);<br class="">- int Weight = IsDec ? -PSetI.getWeight() : PSetI.getWeight();<br class="">+ const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();<br class="">+ int Weight = (int)TRI->getRegUnitWeight(*MRI, P.RegUnit, P.LaneMask);<br class="">+ PSetIterator PSetI = MRI->getPressureSets(P.RegUnit);<br class="">+ if (IsDec) Weight = -Weight;<br class=""> for (; PSetI.isValid(); ++PSetI) {<br class=""> // Find an existing entry in the pressure diff for this PSet.<br class=""> PressureDiff::iterator I = nonconst_begin(), E = nonconst_end();<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp<br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp?rev=296009&r1=296008&r2=296009&view=diff" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp?rev=296009&r1=296008&r2=296009&view=diff</span></a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp Thu Feb 23 14:19:44 2017<br class="">@@ -412,6 +412,15 @@ bool TargetRegisterInfo::regmaskSubsetEq<br class=""> return true;<br class=""> }<br class=""><br class="">+/// Get the weight in units of pressure for a sub register of this register<br class="">+/// unit given a lane mask.<br class="">+unsigned TargetRegisterInfo::getRegUnitWeight(const MachineRegisterInfo &MRI,<br class="">+ unsigned RegUnit,<br class="">+ LaneBitmask LaneMask) const {<br class="">+ PSetIterator PSetI = MRI.getPressureSets(RegUnit);<br class="">+ return PSetI.getWeight();<br class="">+}<br class="">+<br class=""> #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)<br class=""> LLVM_DUMP_METHOD<br class=""> void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,<br class=""><br class="">Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp<br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=296009&r1=296008&r2=296009&view=diff" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=296009&r1=296008&r2=296009&view=diff</span></a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Thu Feb 23 14:19:44 2017<br class="">@@ -21,6 +21,7 @@<br class=""> #include "llvm/CodeGen/RegisterScavenging.h"<br class=""> #include "llvm/IR/Function.h"<br class=""> #include "llvm/IR/LLVMContext.h"<br class="">+#include "llvm/Support/MathExtras.h"<br class=""><br class=""> using namespace llvm;<br class=""><br class="">@@ -1408,3 +1409,18 @@ const int *SIRegisterInfo::getRegUnitPre<br class=""> return Empty;<br class=""> return AMDGPURegisterInfo::getRegUnitPressureSets(RegUnit);<br class=""> }<br class="">+<br class="">+unsigned SIRegisterInfo::getRegUnitWeight(const MachineRegisterInfo &MRI,<br class="">+ unsigned RegUnit,<br class="">+ LaneBitmask LaneMask) const {<br class="">+ unsigned Weight = TargetRegisterInfo::getRegUnitWeight(MRI, RegUnit,<br class="">+ LaneMask);<br class="">+ if (Weight > 1 && LaneMask.any() && !LaneMask.all() &&<br class="">+ isVirtualRegister(RegUnit)) {<br class="">+ LaneBitmask Max = MRI.getMaxLaneMaskForVReg(RegUnit);<br class="">+ if (Max != LaneMask && !Max.all() && !Max.none())<br class="">+ Weight = (Weight * countPopulation(LaneMask.getAsInteger())) /<br class="">+ countPopulation(Max.getAsInteger());<br class="">+ }<br class="">+ return Weight;<br class="">+}<br class=""><br class="">Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h<br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h?rev=296009&r1=296008&r2=296009&view=diff" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h?rev=296009&r1=296008&r2=296009&view=diff</span></a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h (original)<br class="">+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h Thu Feb 23 14:19:44 2017<br class="">@@ -228,6 +228,10 @@ public:<br class=""><br class=""> const int *getRegUnitPressureSets(unsigned RegUnit) const override;<br class=""><br class="">+ unsigned getRegUnitWeight(const MachineRegisterInfo &MRI,<br class="">+ unsigned RegUnit,<br class="">+ LaneBitmask LaneMask) const override;<br class="">+<br class=""> private:<br class=""> void buildSpillLoadStore(MachineBasicBlock::iterator MI,<br class=""> unsigned LoadStoreOp,<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/AMDGPU/load-global-i32.ll<br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-global-i32.ll?rev=296009&r1=296008&r2=296009&view=diff" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-global-i32.ll?rev=296009&r1=296008&r2=296009&view=diff</span></a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/load-global-i32.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/load-global-i32.ll Thu Feb 23 14:19:44 2017<br class="">@@ -424,25 +424,25 @@ define void @global_zextload_v16i32_to_v<br class=""> ; GCN-NOHSA: buffer_store_dwordx4<br class=""> ; GCN-NOHSA: buffer_store_dwordx4<br class=""><br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class=""><br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class=""><br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class=""><br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">-; GCN-HSA: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class="">+; GCN-HSA-DAG: flat_store_dwordx4<br class=""><br class=""> define void @global_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 {<br class=""> %ld = load <32 x i32>, <32 x i32> addrspace(1)* %in<br class=""><br class="">Added: llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir<br class="">URL:<span class="apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir?rev=296009&view=auto" target="_blank" style="color: purple; text-decoration: underline;" class=""><span style="color: purple;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir?rev=296009&view=auto</span></a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir (added)<br class="">+++ llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir Thu Feb 23 14:19:44 2017<br class="">@@ -0,0 +1,67 @@<br class="">+# RUN: llc -march=amdgcn -misched=converge -run-pass machine-scheduler -verify-misched %s -o - -debug-only=misched 2>&1 | FileCheck %s<br class="">+# REQUIRES: asserts<br class="">+<br class="">+# CHECK-LABEL: ScheduleDAGMILive::schedule starting<br class="">+<br class="">+# Check that def and use subregs count with the same weight<br class="">+# CHECK: %vreg9:sub1<def> = V_MUL_LO_I32 %vreg6:sub1, 3<br class="">+# CHECK: Pressure Diff : {{$}}<br class="">+<br class="">+# Check that a subreg does not count as a whole superreg<br class="">+# CHECK: %vreg9:sub0<def> = V_MUL_LO_I32 %vreg6:sub0, %vreg9:sub1<br class="">+# CHECK: Pressure Diff : VGPR_32 1{{$}}<br class="">+<br class="">+# Check that two subregs of the same register count as a whole register<br class="">+# CHECK: DS_WRITE2_B32 %vreg7, %vreg9:sub0, %vreg9:sub1<br class="">+# CHECK: Pressure Diff : VGPR_32 3{{$}}<br class="">+<br class="">+---<br class="">+name: mo_pset<br class="">+alignment: 0<br class="">+exposesReturnsTwice: false<br class="">+legalized: false<br class="">+regBankSelected: false<br class="">+selected: false<br class="">+tracksRegLiveness: true<br class="">+registers:<br class="">+ - { id: 0, class: sreg_128 }<br class="">+ - { id: 1, class: sgpr_64 }<br class="">+ - { id: 2, class: sreg_32_xm0 }<br class="">+ - { id: 3, class: sgpr_32 }<br class="">+ - { id: 4, class: vgpr_32 }<br class="">+ - { id: 5, class: sreg_32_xm0_xexec }<br class="">+ - { id: 6, class: vreg_64 }<br class="">+ - { id: 7, class: vgpr_32 }<br class="">+ - { id: 8, class: vgpr_32 }<br class="">+ - { id: 9, class: vreg_64 }<br class="">+liveins:<br class="">+ - { reg: '%sgpr4_sgpr5', virtual-reg: '%1' }<br class="">+frameInfo:<br class="">+ isFrameAddressTaken: false<br class="">+ isReturnAddressTaken: false<br class="">+ hasStackMap: false<br class="">+ hasPatchPoint: false<br class="">+ stackSize: 0<br class="">+ offsetAdjustment: 0<br class="">+ maxAlignment: 0<br class="">+ adjustsStack: false<br class="">+ hasCalls: false<br class="">+ maxCallFrameSize: 0<br class="">+ hasOpaqueSPAdjustment: false<br class="">+ hasVAStart: false<br class="">+ hasMustTailInVarArgFunc: false<br class="">+body: |<br class="">+ bb.0:<br class="">+ liveins: %sgpr4_sgpr5<br class="">+<br class="">+ %1 = COPY %sgpr4_sgpr5<br class="">+ %5 = S_LOAD_DWORD_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)<br class="">+ %m0 = S_MOV_B32 -1<br class="">+ %7 = COPY %5<br class="">+ %6 = DS_READ2_B32 %7, 0, 1, 0, implicit %m0, implicit %exec<br class="">+ undef %9.sub1 = V_MUL_LO_I32 %6.sub1, 3, implicit %exec<br class="">+ %9.sub0 = V_MUL_LO_I32 %6.sub0, %9.sub1, implicit %exec<br class="">+ DS_WRITE2_B32 %7, %9.sub0, %9.sub1, 4, 5, 0, implicit killed %m0, implicit %exec<br class="">+ S_ENDPGM<br class="">+<br class="">+...<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" target="_blank" style="color: purple; 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