<div dir="ltr"><div>Hi,</div><div><br></div><div>This seems to have caused this warnings. Can you take a look?</div><div><br></div><div>Building CXX object /ssd/b/lib/Target/AMDGPU/<wbr>CMakeFiles/LLVMAMDGPUCodeGen.<wbr>dir/SIOptimizeExecMasking.cpp.<wbr>o</div><div>In file included from /ssd/llvm-project/llvm/lib/<wbr>Target/AMDGPU/<wbr>SIOptimizeExecMasking.cpp:11:</div><div>In file included from //ssd/llvm-project/llvm/lib/<wbr>Target/AMDGPU/AMDGPUSubtarget.<wbr>h:22:</div><div>In file included from //ssd/llvm-project/llvm/lib/<wbr>Target/AMDGPU/SIInstrInfo.h:<wbr>21:</div><div>//ssd/llvm-project/llvm/lib/<wbr>Target/AMDGPU/SIRegisterInfo.<wbr>h:231:12: warning: 'llvm::SIRegisterInfo::<wbr>getRegUnitWeight' hides overloaded virtual function [-Woverloaded-virtual]</div><div> unsigned getRegUnitWeight(const MachineRegisterInfo &MRI,</div><div> ^</div><div>//ssd/b/lib/Target/AMDGPU/<wbr>AMDGPUGenRegisterInfo.inc:<wbr>17362:12: note: hidden overloaded virtual function 'llvm::AMDGPUGenRegisterInfo::<wbr>getRegUnitWeight' declared here: different number of parameters (1 vs 3)</div><div> unsigned getRegUnitWeight(unsigned RegUnit) const override;</div><div> ^</div><div>1 warning generated.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Feb 23, 2017 at 12:19 PM, Stanislav Mekhanoshin via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rampitec<br>
Date: Thu Feb 23 14:19:44 2017<br>
New Revision: 296009<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=296009&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=296009&view=rev</a><br>
Log:<br>
Correct register pressure calculation in presence of subregs<br>
<br>
If a subreg is used in an instruction it counts as a whole superreg<br>
for the purpose of register pressure calculation. This patch corrects<br>
improper register pressure calculation by examining operand's lane mask.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D29835" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D29835</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/schedule-regpressure-<wbr>subregs.mir<br>
Modified:<br>
llvm/trunk/include/llvm/<wbr>CodeGen/RegisterPressure.h<br>
llvm/trunk/include/llvm/<wbr>Target/TargetRegisterInfo.h<br>
llvm/trunk/lib/CodeGen/<wbr>MachineScheduler.cpp<br>
llvm/trunk/lib/CodeGen/<wbr>RegisterPressure.cpp<br>
llvm/trunk/lib/CodeGen/<wbr>TargetRegisterInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>SIRegisterInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/<wbr>SIRegisterInfo.h<br>
llvm/trunk/test/CodeGen/<wbr>AMDGPU/load-global-i32.ll<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>CodeGen/RegisterPressure.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterPressure.h?rev=296009&r1=296008&r2=296009&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/CodeGen/RegisterPressure.<wbr>h?rev=296009&r1=296008&r2=<wbr>296009&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>CodeGen/RegisterPressure.h (original)<br>
+++ llvm/trunk/include/llvm/<wbr>CodeGen/RegisterPressure.h Thu Feb 23 14:19:44 2017<br>
@@ -156,7 +156,7 @@ public:<br>
const_iterator begin() const { return &PressureChanges[0]; }<br>
const_iterator end() const { return &PressureChanges[MaxPSets]; }<br>
<br>
- void addPressureChange(unsigned RegUnit, bool IsDec,<br>
+ void addPressureChange(<wbr>RegisterMaskPair P, bool IsDec,<br>
const MachineRegisterInfo *MRI);<br>
<br>
void dump(const TargetRegisterInfo &TRI) const;<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>Target/TargetRegisterInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=296009&r1=296008&r2=296009&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/Target/<wbr>TargetRegisterInfo.h?rev=<wbr>296009&r1=296008&r2=296009&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>Target/TargetRegisterInfo.h (original)<br>
+++ llvm/trunk/include/llvm/<wbr>Target/TargetRegisterInfo.h Thu Feb 23 14:19:44 2017<br>
@@ -30,6 +30,7 @@ namespace llvm {<br>
<br>
class BitVector;<br>
class MachineFunction;<br>
+class MachineRegisterInfo;<br>
class RegScavenger;<br>
template<class T> class SmallVectorImpl;<br>
class VirtRegMap;<br>
@@ -719,6 +720,12 @@ public:<br>
/// Get the weight in units of pressure for this register unit.<br>
virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;<br>
<br>
+ /// Get the weight in units of pressure for a sub register of this register<br>
+ /// unit given a lane mask.<br>
+ virtual unsigned getRegUnitWeight(const MachineRegisterInfo &MRI,<br>
+ unsigned RegUnit,<br>
+ LaneBitmask LaneMask) const;<br>
+<br>
/// Get the number of dimensions of register pressure.<br>
virtual unsigned getNumRegPressureSets() const = 0;<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>MachineScheduler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=296009&r1=296008&r2=296009&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/MachineScheduler.cpp?<wbr>rev=296009&r1=296008&r2=<wbr>296009&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>MachineScheduler.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>MachineScheduler.cpp Thu Feb 23 14:19:44 2017<br>
@@ -1085,7 +1085,7 @@ void ScheduleDAGMILive::<wbr>updatePressureDi<br>
continue;<br>
<br>
PressureDiff &PDiff = getPressureDiff(&SU);<br>
- PDiff.addPressureChange(Reg, Decrement, &MRI);<br>
+ PDiff.addPressureChange(P, Decrement, &MRI);<br>
DEBUG(<br>
dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "<br>
<< PrintReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)<br>
@@ -1123,7 +1123,7 @@ void ScheduleDAGMILive::<wbr>updatePressureDi<br>
LI.Query(LIS-><wbr>getInstructionIndex(*SU-><wbr>getInstr()));<br>
if (LRQ.valueIn() == VNI) {<br>
PressureDiff &PDiff = getPressureDiff(SU);<br>
- PDiff.addPressureChange(Reg, true, &MRI);<br>
+ PDiff.addPressureChange(P, true, &MRI);<br>
DEBUG(<br>
dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "<br>
<< *SU->getInstr();<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>RegisterPressure.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterPressure.cpp?rev=296009&r1=296008&r2=296009&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/RegisterPressure.cpp?<wbr>rev=296009&r1=296008&r2=<wbr>296009&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>RegisterPressure.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>RegisterPressure.cpp Thu Feb 23 14:19:44 2017<br>
@@ -46,16 +46,29 @@<br>
<br>
using namespace llvm;<br>
<br>
+/// Clamp lane masks to maximum posible value.<br>
+static void clampMasks(const MachineRegisterInfo &MRI, unsigned Reg,<br>
+ LaneBitmask& LaneMask1, LaneBitmask& LaneMask2) {<br>
+ if (TargetRegisterInfo::<wbr>isVirtualRegister(Reg)) {<br>
+ LaneBitmask Max = MRI.getMaxLaneMaskForVReg(Reg)<wbr>;<br>
+ LaneMask1 &= Max;<br>
+ LaneMask2 &= Max;<br>
+ }<br>
+}<br>
+<br>
/// Increase pressure for each pressure set provided by TargetRegisterInfo.<br>
static void increaseSetPressure(std::<wbr>vector<unsigned> &CurrSetPressure,<br>
const MachineRegisterInfo &MRI, unsigned Reg,<br>
LaneBitmask PrevMask, LaneBitmask NewMask) {<br>
assert((PrevMask & ~NewMask).none() && "Must not remove bits");<br>
- if (PrevMask.any() || NewMask.none())<br>
+<br>
+ clampMasks(MRI, Reg, PrevMask, NewMask);<br>
+ if ((NewMask & ~PrevMask).none())<br>
return;<br>
<br>
+ const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();<br>
+ unsigned Weight = TRI->getRegUnitWeight(MRI, Reg, NewMask & ~PrevMask);<br>
PSetIterator PSetI = MRI.getPressureSets(Reg);<br>
- unsigned Weight = PSetI.getWeight();<br>
for (; PSetI.isValid(); ++PSetI)<br>
CurrSetPressure[*PSetI] += Weight;<br>
}<br>
@@ -65,11 +78,13 @@ static void decreaseSetPressure(std::vec<br>
const MachineRegisterInfo &MRI, unsigned Reg,<br>
LaneBitmask PrevMask, LaneBitmask NewMask) {<br>
//assert((NewMask & !PrevMask) == 0 && "Must not add bits");<br>
- if (NewMask.any() || PrevMask.none())<br>
+ clampMasks(MRI, Reg, PrevMask, NewMask);<br>
+ if ((~NewMask & PrevMask).none())<br>
return;<br>
<br>
+ const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();<br>
+ unsigned Weight = TRI->getRegUnitWeight(MRI, Reg, ~NewMask & PrevMask);<br>
PSetIterator PSetI = MRI.getPressureSets(Reg);<br>
- unsigned Weight = PSetI.getWeight();<br>
for (; PSetI.isValid(); ++PSetI) {<br>
assert(CurrSetPressure[*PSetI] >= Weight && "register pressure underflow");<br>
CurrSetPressure[*PSetI] -= Weight;<br>
@@ -139,11 +154,14 @@ void PressureDiff::dump(const TargetRegi<br>
void RegPressureTracker::<wbr>increaseRegPressure(unsigned RegUnit,<br>
LaneBitmask PreviousMask,<br>
LaneBitmask NewMask) {<br>
- if (PreviousMask.any() || NewMask.none())<br>
+ clampMasks(*MRI, RegUnit, PreviousMask, NewMask);<br>
+ if ((NewMask & ~PreviousMask).none())<br>
return;<br>
<br>
+ const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();<br>
+ unsigned Weight = TRI->getRegUnitWeight(*MRI, RegUnit,<br>
+ NewMask & ~PreviousMask);<br>
PSetIterator PSetI = MRI->getPressureSets(RegUnit);<br>
- unsigned Weight = PSetI.getWeight();<br>
for (; PSetI.isValid(); ++PSetI) {<br>
CurrSetPressure[*PSetI] += Weight;<br>
P.MaxSetPressure[*PSetI] =<br>
@@ -644,17 +662,19 @@ void PressureDiffs::addInstruction(<wbr>unsig<br>
PressureDiff &PDiff = (*this)[Idx];<br>
assert(!PDiff.begin()-><wbr>isValid() && "stale PDiff");<br>
for (const RegisterMaskPair &P : RegOpers.Defs)<br>
- PDiff.addPressureChange(P.<wbr>RegUnit, true, &MRI);<br>
+ PDiff.addPressureChange(P, true, &MRI);<br>
<br>
for (const RegisterMaskPair &P : RegOpers.Uses)<br>
- PDiff.addPressureChange(P.<wbr>RegUnit, false, &MRI);<br>
+ PDiff.addPressureChange(P, false, &MRI);<br>
}<br>
<br>
/// Add a change in pressure to the pressure diff of a given instruction.<br>
-void PressureDiff::<wbr>addPressureChange(unsigned RegUnit, bool IsDec,<br>
+void PressureDiff::<wbr>addPressureChange(<wbr>RegisterMaskPair P, bool IsDec,<br>
const MachineRegisterInfo *MRI) {<br>
- PSetIterator PSetI = MRI->getPressureSets(RegUnit);<br>
- int Weight = IsDec ? -PSetI.getWeight() : PSetI.getWeight();<br>
+ const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();<br>
+ int Weight = (int)TRI->getRegUnitWeight(*<wbr>MRI, P.RegUnit, P.LaneMask);<br>
+ PSetIterator PSetI = MRI->getPressureSets(P.<wbr>RegUnit);<br>
+ if (IsDec) Weight = -Weight;<br>
for (; PSetI.isValid(); ++PSetI) {<br>
// Find an existing entry in the pressure diff for this PSet.<br>
PressureDiff::iterator I = nonconst_begin(), E = nonconst_end();<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>TargetRegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp?rev=296009&r1=296008&r2=296009&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/TargetRegisterInfo.<wbr>cpp?rev=296009&r1=296008&r2=<wbr>296009&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>TargetRegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>TargetRegisterInfo.cpp Thu Feb 23 14:19:44 2017<br>
@@ -412,6 +412,15 @@ bool TargetRegisterInfo::<wbr>regmaskSubsetEq<br>
return true;<br>
}<br>
<br>
+/// Get the weight in units of pressure for a sub register of this register<br>
+/// unit given a lane mask.<br>
+unsigned TargetRegisterInfo::<wbr>getRegUnitWeight(const MachineRegisterInfo &MRI,<br>
+ unsigned RegUnit,<br>
+ LaneBitmask LaneMask) const {<br>
+ PSetIterator PSetI = MRI.getPressureSets(RegUnit);<br>
+ return PSetI.getWeight();<br>
+}<br>
+<br>
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)<br>
LLVM_DUMP_METHOD<br>
void TargetRegisterInfo::dumpReg(<wbr>unsigned Reg, unsigned SubRegIndex,<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>SIRegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=296009&r1=296008&r2=296009&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/SIRegisterInfo.cpp?rev=<wbr>296009&r1=296008&r2=296009&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>SIRegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>SIRegisterInfo.cpp Thu Feb 23 14:19:44 2017<br>
@@ -21,6 +21,7 @@<br>
#include "llvm/CodeGen/<wbr>RegisterScavenging.h"<br>
#include "llvm/IR/Function.h"<br>
#include "llvm/IR/LLVMContext.h"<br>
+#include "llvm/Support/MathExtras.h"<br>
<br>
using namespace llvm;<br>
<br>
@@ -1408,3 +1409,18 @@ const int *SIRegisterInfo::getRegUnitPre<br>
return Empty;<br>
return AMDGPURegisterInfo::<wbr>getRegUnitPressureSets(<wbr>RegUnit);<br>
}<br>
+<br>
+unsigned SIRegisterInfo::<wbr>getRegUnitWeight(const MachineRegisterInfo &MRI,<br>
+ unsigned RegUnit,<br>
+ LaneBitmask LaneMask) const {<br>
+ unsigned Weight = TargetRegisterInfo::<wbr>getRegUnitWeight(MRI, RegUnit,<br>
+ LaneMask);<br>
+ if (Weight > 1 && LaneMask.any() && !LaneMask.all() &&<br>
+ isVirtualRegister(RegUnit)) {<br>
+ LaneBitmask Max = MRI.getMaxLaneMaskForVReg(<wbr>RegUnit);<br>
+ if (Max != LaneMask && !Max.all() && !Max.none())<br>
+ Weight = (Weight * countPopulation(LaneMask.<wbr>getAsInteger())) /<br>
+ countPopulation(Max.<wbr>getAsInteger());<br>
+ }<br>
+ return Weight;<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/<wbr>SIRegisterInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h?rev=296009&r1=296008&r2=296009&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AMDGPU/SIRegisterInfo.h?rev=<wbr>296009&r1=296008&r2=296009&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AMDGPU/<wbr>SIRegisterInfo.h (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/<wbr>SIRegisterInfo.h Thu Feb 23 14:19:44 2017<br>
@@ -228,6 +228,10 @@ public:<br>
<br>
const int *getRegUnitPressureSets(<wbr>unsigned RegUnit) const override;<br>
<br>
+ unsigned getRegUnitWeight(const MachineRegisterInfo &MRI,<br>
+ unsigned RegUnit,<br>
+ LaneBitmask LaneMask) const override;<br>
+<br>
private:<br>
void buildSpillLoadStore(<wbr>MachineBasicBlock::iterator MI,<br>
unsigned LoadStoreOp,<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AMDGPU/load-global-i32.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-global-i32.ll?rev=296009&r1=296008&r2=296009&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/load-global-<wbr>i32.ll?rev=296009&r1=296008&<wbr>r2=296009&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/load-global-i32.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/load-global-i32.ll Thu Feb 23 14:19:44 2017<br>
@@ -424,25 +424,25 @@ define void @global_zextload_v16i32_to_v<br>
; GCN-NOHSA: buffer_store_dwordx4<br>
; GCN-NOHSA: buffer_store_dwordx4<br>
<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
-; GCN-HSA: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
+; GCN-HSA-DAG: flat_store_dwordx4<br>
<br>
define void @global_sextload_v32i32_to_<wbr>v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 {<br>
%ld = load <32 x i32>, <32 x i32> addrspace(1)* %in<br>
<br>
Added: llvm/trunk/test/CodeGen/<wbr>AMDGPU/schedule-regpressure-<wbr>subregs.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/schedule-regpressure-subregs.mir?rev=296009&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AMDGPU/schedule-<wbr>regpressure-subregs.mir?rev=<wbr>296009&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AMDGPU/schedule-regpressure-<wbr>subregs.mir (added)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AMDGPU/schedule-regpressure-<wbr>subregs.mir Thu Feb 23 14:19:44 2017<br>
@@ -0,0 +1,67 @@<br>
+# RUN: llc -march=amdgcn -misched=converge -run-pass machine-scheduler -verify-misched %s -o - -debug-only=misched 2>&1 | FileCheck %s<br>
+# REQUIRES: asserts<br>
+<br>
+# CHECK-LABEL: ScheduleDAGMILive::schedule starting<br>
+<br>
+# Check that def and use subregs count with the same weight<br>
+# CHECK: %vreg9:sub1<def> = V_MUL_LO_I32 %vreg6:sub1, 3<br>
+# CHECK: Pressure Diff : {{$}}<br>
+<br>
+# Check that a subreg does not count as a whole superreg<br>
+# CHECK: %vreg9:sub0<def> = V_MUL_LO_I32 %vreg6:sub0, %vreg9:sub1<br>
+# CHECK: Pressure Diff : VGPR_32 1{{$}}<br>
+<br>
+# Check that two subregs of the same register count as a whole register<br>
+# CHECK: DS_WRITE2_B32 %vreg7, %vreg9:sub0, %vreg9:sub1<br>
+# CHECK: Pressure Diff : VGPR_32 3{{$}}<br>
+<br>
+---<br>
+name: mo_pset<br>
+alignment: 0<br>
+exposesReturnsTwice: false<br>
+legalized: false<br>
+regBankSelected: false<br>
+selected: false<br>
+tracksRegLiveness: true<br>
+registers:<br>
+ - { id: 0, class: sreg_128 }<br>
+ - { id: 1, class: sgpr_64 }<br>
+ - { id: 2, class: sreg_32_xm0 }<br>
+ - { id: 3, class: sgpr_32 }<br>
+ - { id: 4, class: vgpr_32 }<br>
+ - { id: 5, class: sreg_32_xm0_xexec }<br>
+ - { id: 6, class: vreg_64 }<br>
+ - { id: 7, class: vgpr_32 }<br>
+ - { id: 8, class: vgpr_32 }<br>
+ - { id: 9, class: vreg_64 }<br>
+liveins:<br>
+ - { reg: '%sgpr4_sgpr5', virtual-reg: '%1' }<br>
+frameInfo:<br>
+ isFrameAddressTaken: false<br>
+ isReturnAddressTaken: false<br>
+ hasStackMap: false<br>
+ hasPatchPoint: false<br>
+ stackSize: 0<br>
+ offsetAdjustment: 0<br>
+ maxAlignment: 0<br>
+ adjustsStack: false<br>
+ hasCalls: false<br>
+ maxCallFrameSize: 0<br>
+ hasOpaqueSPAdjustment: false<br>
+ hasVAStart: false<br>
+ hasMustTailInVarArgFunc: false<br>
+body: |<br>
+ bb.0:<br>
+ liveins: %sgpr4_sgpr5<br>
+<br>
+ %1 = COPY %sgpr4_sgpr5<br>
+ %5 = S_LOAD_DWORD_IMM %1, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(2)* undef`)<br>
+ %m0 = S_MOV_B32 -1<br>
+ %7 = COPY %5<br>
+ %6 = DS_READ2_B32 %7, 0, 1, 0, implicit %m0, implicit %exec<br>
+ undef %9.sub1 = V_MUL_LO_I32 %6.sub1, 3, implicit %exec<br>
+ %9.sub0 = V_MUL_LO_I32 %6.sub0, %9.sub1, implicit %exec<br>
+ DS_WRITE2_B32 %7, %9.sub0, %9.sub1, 4, 5, 0, implicit killed %m0, implicit %exec<br>
+ S_ENDPGM<br>
+<br>
+...<br>
<br>
<br>
______________________________<wbr>_________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br>
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/<wbr>mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br></div>