<div dir="ltr">Why doesn't it complain about this similar code<div><br></div><div> Mask.push_back(ByteBits == ZeroMask ? SM_SentinelZero : i);<br></div><div><br></div><div>Unless the warning is misleading and its really just upset the SM_SentinelZero is signed and i is unsigned. In the code that doesn't fail they are both unsigned.</div></div><div class="gmail_extra"><br clear="all"><div><div class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div>
<br><div class="gmail_quote">On Fri, Feb 17, 2017 at 6:51 PM, Davide Italiano via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Sorry, Simon, I'm terribly late, but this seems to have caused a new<br>
GCC warning.<br>
When you get a chance, can you please take a look?<br>
<br>
[87/122] Building CXX object<br>
lib/Target/X86/CMakeFiles/<wbr>LLVMX86CodeGen.dir/<wbr>X86ISelLowering.cpp.o<br>
../lib/Target/X86/<wbr>X86ISelLowering.cpp: In function ‘bool<br>
getFauxShuffleMask(llvm::<wbr>SDValue, llvm::SmallVectorImpl<int>&, l<br>
lvm::SmallVectorImpl<llvm::<wbr>SDValue>&)’:<br>
../lib/Target/X86/<wbr>X86ISelLowering.cpp:5742:35: warning: enumeral and<br>
non-enumeral type in conditional expression [-Wextra<br>
]<br>
Mask.push_back(i == InIdx ? SM_SentinelZero : i);<br>
~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~<wbr>~~<br>
<br>
--<br>
Davide<br>
<br>
On Tue, Jan 31, 2017 at 5:51 AM, Simon Pilgrim via llvm-commits<br>
<<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
> Author: rksimon<br>
> Date: Tue Jan 31 07:51:10 2017<br>
> New Revision: 293627<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=293627&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=293627&view=rev</a><br>
> Log:<br>
> [X86][SSE] Add support for combining PINSRW into a target shuffle.<br>
><br>
> Also add the ability to recognise PINSR(Vex, 0, Idx).<br>
><br>
> Targets shuffle combines won't replace multiple insertions with a bit mask until a depth of 3 or more, so we avoid codesize bloat.<br>
><br>
> The unnecessary vpblendw in clearupper8xi16a will be fixed in an upcoming patch.<br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
> llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=293627&r1=293626&r2=293627&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86ISelLowering.cpp?rev=<wbr>293627&r1=293626&r2=293627&<wbr>view=diff</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp Tue Jan 31 07:51:10 2017<br>
> @@ -5770,12 +5770,21 @@ static bool getFauxShuffleMask(SDValue N<br>
> return true;<br>
> }<br>
> case X86ISD::PINSRW: {<br>
> - // Attempt to recognise a PINSRW(ASSERTZEXT(PEXTRW)) shuffle pattern.<br>
> - // TODO: Expand this to support PINSRB/INSERT_VECTOR_ELT/etc.<br>
> SDValue InVec = N.getOperand(0);<br>
> SDValue InScl = N.getOperand(1);<br>
> uint64_t InIdx = N.getConstantOperandVal(2);<br>
> assert(InIdx < NumElts && "Illegal insertion index");<br>
> +<br>
> + // Attempt to recognise a PINSRW(VEC, 0, Idx) shuffle pattern.<br>
> + if (X86::isZeroNode(InScl)) {<br>
> + Ops.push_back(InVec);<br>
> + for (unsigned i = 0; i != NumElts; ++i)<br>
> + Mask.push_back(i == InIdx ? SM_SentinelZero : i);<br>
> + return true;<br>
> + }<br>
> +<br>
> + // Attempt to recognise a PINSRW(ASSERTZEXT(PEXTRW)) shuffle pattern.<br>
> + // TODO: Expand this to support PINSRB/INSERT_VECTOR_ELT/etc.<br>
> if (InScl.getOpcode() != ISD::AssertZext ||<br>
> InScl.getOperand(0).getOpcode(<wbr>) != X86ISD::PEXTRW)<br>
> return false;<br>
> @@ -30597,6 +30606,24 @@ static SDValue combineVectorShift(SDNode<br>
> return SDValue();<br>
> }<br>
><br>
> +static SDValue combineVectorInsert(SDNode *N, SelectionDAG &DAG,<br>
> + TargetLowering::<wbr>DAGCombinerInfo &DCI,<br>
> + const X86Subtarget &Subtarget) {<br>
> + unsigned Opcode = N->getOpcode();<br>
> + assert(((X86ISD::PINSRB == Opcode && N->getValueType(0) ==MVT::v16i8) ||<br>
> + (X86ISD::PINSRW == Opcode && N->getValueType(0) ==MVT::v8i16)) &&<br>
> + "Unexpected vector insertion");<br>
> +<br>
> + // Attempt to combine PINSRB/PINSRW patterns to a shuffle.<br>
> + SDValue Op(N, 0);<br>
> + SmallVector<int, 1> NonceMask; // Just a placeholder.<br>
> + NonceMask.push_back(0);<br>
> + combineX86ShufflesRecursively(<wbr>{Op}, 0, Op, NonceMask,<br>
> + /*Depth*/ 1, /*HasVarMask*/ false, DAG,<br>
> + DCI, Subtarget);<br>
> + return SDValue();<br>
> +}<br>
> +<br>
> /// Recognize the distinctive (AND (setcc ...) (setcc ..)) where both setccs<br>
> /// reference the same FP CMP, and rewrite for CMPEQSS and friends. Likewise for<br>
> /// OR -> CMPNEQSS.<br>
> @@ -34159,6 +34186,8 @@ SDValue X86TargetLowering::<wbr>PerformDAGCom<br>
> case X86ISD::VSRLI: return combineVectorShift(N, DAG, DCI, Subtarget);<br>
> case X86ISD::VSEXT:<br>
> case X86ISD::VZEXT: return combineVSZext(N, DAG, DCI, Subtarget);<br>
> + case X86ISD::PINSRB:<br>
> + case X86ISD::PINSRW: return combineVectorInsert(N, DAG, DCI, Subtarget);<br>
> case X86ISD::SHUFP: // Handle all target specific shuffles<br>
> case X86ISD::INSERTPS:<br>
> case X86ISD::PALIGNR:<br>
><br>
> Modified: llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/clear_upper_vector_element_bits.ll?rev=293627&r1=293626&r2=293627&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/clear_upper_<wbr>vector_element_bits.ll?rev=<wbr>293627&r1=293626&r2=293627&<wbr>view=diff</a><br>
> ==============================<wbr>==============================<wbr>==================<br>
> --- llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll Tue Jan 31 07:51:10 2017<br>
> @@ -94,7 +94,8 @@ define <8 x i16> @_clearupper8xi16a(<8 x<br>
> ;<br>
> ; AVX-LABEL: _clearupper8xi16a:<br>
> ; AVX: # BB#0:<br>
> -; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0<br>
> +; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7]<br>
> +; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0<br>
> ; AVX-NEXT: retq<br>
> %x0 = extractelement <8 x i16> %0, i32 0<br>
> %x1 = extractelement <8 x i16> %0, i32 1<br>
> @@ -317,11 +318,7 @@ define <2 x i64> @_clearupper2xi64b(<2 x<br>
> define <4 x i32> @_clearupper4xi32b(<4 x i32>) nounwind {<br>
> ; SSE-LABEL: _clearupper4xi32b:<br>
> ; SSE: # BB#0:<br>
> -; SSE-NEXT: xorl %eax, %eax<br>
> -; SSE-NEXT: pinsrw $1, %eax, %xmm0<br>
> -; SSE-NEXT: pinsrw $3, %eax, %xmm0<br>
> -; SSE-NEXT: pinsrw $5, %eax, %xmm0<br>
> -; SSE-NEXT: pinsrw $7, %eax, %xmm0<br>
> +; SSE-NEXT: andps {{.*}}(%rip), %xmm0<br>
> ; SSE-NEXT: retq<br>
> ;<br>
> ; AVX-LABEL: _clearupper4xi32b:<br>
><br>
><br>
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<span class="HOEnZb"><font color="#888888"><br>
--<br>
Davide<br>
<br>
"There are no solved problems; there are only problems that are more<br>
or less solved" -- Henri Poincare<br>
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</font></span></blockquote></div><br></div>