<div dir="ltr">Hans, this fixes a regression I introduced in r281402.<div><br><div>Assuming this sticks, is it too late to merge into 4.0? I believe this should be safe, as all it does is add a case where we bail out of a combine.</div>(The right PR number is PR31956.)<div><br></div><div>Thanks,</div><div> Michael</div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Feb 15, 2017 at 10:37 AM, Michael Kuperstein via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: mkuper<br>
Date: Wed Feb 15 12:37:26 2017<br>
New Revision: 295213<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=295213&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=295213&view=rev</a><br>
Log:<br>
[DAG] Don't try to create an INSERT_SUBVECTOR with an illegal source<br>
<br>
We currently can't legalize those, but we should really not be creating<br>
them in the first place, since legalization would probably look similar to the<br>
way we legalize CONCAT_VECTORS - basically replace the INSERT with a BUILD.<br>
<br>
This fixes PR311956.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D29961" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D29961</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/<wbr>pr31956.ll<br>
Modified:<br>
llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=295213&r1=295212&r2=295213&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/SelectionDAG/<wbr>DAGCombiner.cpp?rev=295213&r1=<wbr>295212&r2=295213&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>SelectionDAG/DAGCombiner.cpp Wed Feb 15 12:37:26 2017<br>
@@ -13374,9 +13374,15 @@ SDValue DAGCombiner::<wbr>createBuildVecShuff<br>
!TLI.isOperationLegal(ISD::<wbr>VECTOR_SHUFFLE, InVT1))<br>
return SDValue();<br>
<br>
- if (InVT1 != InVT2)<br>
+ // Legalizing INSERT_SUBVECTOR is tricky - you basically have to<br>
+ // lower it back into a BUILD_VECTOR. So if the inserted type is<br>
+ // illegal, don't even try.<br>
+ if (InVT1 != InVT2) {<br>
+ if (!TLI.isTypeLegal(InVT2))<br>
+ return SDValue();<br>
VecIn2 = DAG.getNode(ISD::INSERT_<wbr>SUBVECTOR, DL, InVT1,<br>
DAG.getUNDEF(InVT1), VecIn2, ZeroIdx);<br>
+ }<br>
ShuffleNumElems = NumElems * 2;<br>
} else {<br>
// Both VecIn1 and VecIn2 are wider than the output, and VecIn2 is wider<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/<wbr>pr31956.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr31956.ll?rev=295213&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/pr31956.ll?rev=<wbr>295213&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>pr31956.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>pr31956.ll Wed Feb 15 12:37:26 2017<br>
@@ -0,0 +1,25 @@<br>
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.<wbr>py<br>
+; RUN: llc -mattr=+avx < %s | FileCheck %s<br>
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:<wbr>32:64-S128"<br>
+target triple = "x86_64-scei-ps4"<br>
+<br>
+@G1 = common global <2 x float> zeroinitializer, align 8<br>
+@G2 = common global <8 x float> zeroinitializer, align 32<br>
+<br>
+define <4 x float> @foo() {<br>
+; CHECK-LABEL: foo:<br>
+; CHECK: # BB#0: # %entry<br>
+; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero<br>
+; CHECK-NEXT: vblendpd {{.*#+}} ymm0 = ymm0[0],mem[1,2,3]<br>
+; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1<br>
+; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[2,0]<br>
+; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,1,3]<br>
+; CHECK-NEXT: vzeroupper<br>
+; CHECK-NEXT: retq<br>
+entry:<br>
+ %V = load <2 x float>, <2 x float>* @G1, align 8<br>
+ %shuffle = shufflevector <2 x float> %V, <2 x float> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef><br>
+ %L = load <8 x float>, <8 x float>* @G2, align 32<br>
+ %shuffle1 = shufflevector <8 x float> %shuffle, <8 x float> %L, <4 x i32> <i32 12, i32 10, i32 14, i32 4><br>
+ ret <4 x float> %shuffle1<br>
+}<br>
<br>
<br>
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</blockquote></div><br></div>