<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Fri, Feb 10, 2017 at 8:05 AM, Igor Breger via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Author: ibreger<br>
Date: Fri Feb 10 01:05:56 2017<br>
New Revision: 294723<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=294723&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=294723&view=rev</a><br>
Log:<br>
[X86][GlobalISel] Add general-purpose Register Bank<br>
<br>
Summary:<br>
[X86][GlobalISel] Add general-purpose Register Bank.<br>
Add trivial handling of G_ADD legalization .<br>
Add Regestry Bank selection for COPY and G_ADD instructions<br>
<br>
Reviewers: rovka, zvi, ab, t.p.northover, qcolombet<br>
<br>
Reviewed By: qcolombet<br>
<br>
Subscribers: qcolombet, mgorny, dberris, kristof.beyls, llvm-commits<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D29771" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D29771</a><br>
<br>
Added:<br>
llvm/trunk/lib/Target/X86/<wbr>X86GenRegisterBankInfo.def<br>
llvm/trunk/lib/Target/X86/<wbr>X86LegalizerInfo.cpp<br>
llvm/trunk/lib/Target/X86/<wbr>X86LegalizerInfo.h<br>
llvm/trunk/lib/Target/X86/<wbr>X86RegisterBankInfo.cpp<br>
llvm/trunk/lib/Target/X86/<wbr>X86RegisterBankInfo.h<br>
llvm/trunk/lib/Target/X86/<wbr>X86RegisterBanks.td<br>
llvm/trunk/test/CodeGen/X86/<wbr>GlobalISel/X86-regbankselect.<wbr>mir<br>
llvm/trunk/test/CodeGen/X86/<wbr>GlobalISel/legalize-add.mir<br>
Modified:<br>
llvm/trunk/lib/Target/X86/<wbr>CMakeLists.txt<br>
llvm/trunk/lib/Target/X86/X86.<wbr>td<br>
llvm/trunk/lib/Target/X86/<wbr>X86TargetMachine.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=294723&r1=294722&r2=294723&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/CMakeLists.txt?rev=294723&<wbr>r1=294722&r2=294723&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>CMakeLists.txt Fri Feb 10 01:05:56 2017<br>
@@ -10,11 +10,17 @@ tablegen(LLVM X86GenDAGISel.inc -gen-dag<br>
tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)<br>
tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)<br>
tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)<br>
+if(LLVM_BUILD_GLOBAL_ISEL)<br>
+ tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)<br>
+endif()<br>
+<br>
add_public_tablegen_target(<wbr>X86CommonTableGen)<br>
<br>
# Add GlobalISel files if the build option was enabled.<br>
set(GLOBAL_ISEL_FILES<br>
X86CallLowering.cpp<br>
+ X86LegalizerInfo.cpp<br>
+ X86RegisterBankInfo.cpp<br>
)<br>
<br>
if(LLVM_BUILD_GLOBAL_ISEL)<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86.<wbr>td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=294723&r1=294722&r2=294723&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86.td?rev=294723&r1=<wbr>294722&r2=294723&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/X86.<wbr>td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86.<wbr>td Fri Feb 10 01:05:56 2017<br>
@@ -811,6 +811,7 @@ def : ProcessorModel<"x86-64", SandyBrid<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
include "X86RegisterInfo.td"<br>
+include "X86RegisterBanks.td"<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
// Instruction Descriptions<br>
<br>
Added: llvm/trunk/lib/Target/X86/<wbr>X86GenRegisterBankInfo.def<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86GenRegisterBankInfo.def?rev=294723&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86GenRegisterBankInfo.<wbr>def?rev=294723&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86GenRegisterBankInfo.def (added)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86GenRegisterBankInfo.def Fri Feb 10 01:05:56 2017<br>
@@ -0,0 +1,60 @@<br>
+//===- X86GenRegisterBankInfo.def ----------------------------*- C++ -*-==//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+/// \file<br>
+/// This file defines all the static objects used by X86RegisterBankInfo.<br>
+/// \todo This should be generated by TableGen.<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+<br>
+#ifndef LLVM_BUILD_GLOBAL_ISEL<br>
+#error "You shouldn't build this"<br>
+#endif<br>
+<br>
+namespace llvm {<br>
+RegisterBankInfo::<wbr>PartialMapping X86GenRegisterBankInfo::<wbr>PartMappings[]{<br>
+ /* StartIdx, Length, RegBank */<br>
+ // GPR value<br>
+ {0, 8, X86::GPRRegBank}, // :0<br>
+ {0, 16, X86::GPRRegBank}, // :1<br>
+ {0, 32, X86::GPRRegBank}, // :2<br>
+ {0, 64, X86::GPRRegBank}, // :3<br>
+};<br>
+<br>
+enum PartialMappingIdx {<br>
+ PMI_None = -1,<br>
+ PMI_GPR8,<br>
+ PMI_GPR16,<br>
+ PMI_GPR32,<br>
+ PMI_GPR64,<br>
+};<br>
+<br>
+#define INSTR_3OP(INFO) INFO, INFO, INFO,<br>
+#define BREAKDOWN(INDEX, NUM) \<br>
+ { &X86GenRegisterBankInfo::<wbr>PartMappings[INDEX], NUM }<br>
+// ValueMappings.<br>
+RegisterBankInfo::<wbr>ValueMapping X86GenRegisterBankInfo::<wbr>ValMappings[]{<br>
+ /* BreakDown, NumBreakDowns */<br>
+ // 3-operands instructions (all binary operations should end up with one of<br>
+ // those mapping).<br>
+ INSTR_3OP(BREAKDOWN(PMI_GPR8, 1)) // 0: GPR_8<br>
+ INSTR_3OP(BREAKDOWN(PMI_GPR16, 1)) // 3: GPR_16<br>
+ INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32<br>
+ INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64<br>
+};<br>
+#undef INSTR_3OP<br>
+#undef BREAKDOWN<br>
+<br>
+enum ValueMappingIdx {<br>
+ VMI_None = -1,<br>
+ VMI_3OpsGpr8Idx = 0,<br>
+ VMI_3OpsGpr16Idx = 3,<br>
+ VMI_3OpsGpr32Idx = 6,<br>
+ VMI_3OpsGpr64Idx = 9,<br>
+};<br>
+<br>
+} // End llvm namespace.<br>
<br>
Added: llvm/trunk/lib/Target/X86/<wbr>X86LegalizerInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp?rev=294723&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86LegalizerInfo.cpp?rev=<wbr>294723&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86LegalizerInfo.cpp (added)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86LegalizerInfo.cpp Fri Feb 10 01:05:56 2017<br>
@@ -0,0 +1,54 @@<br>
+//===- X86LegalizerInfo.cpp ------------------------------<wbr>--------*- C++ -*-==//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+/// \file<br>
+/// This file implements the targeting of the Machinelegalizer class for X86.<br>
+/// \todo This should be generated by TableGen.<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+<br>
+#include "X86LegalizerInfo.h"<br>
+#include "X86Subtarget.h"<br>
+#include "llvm/CodeGen/ValueTypes.h"<br>
+#include "llvm/IR/DerivedTypes.h"<br>
+#include "llvm/IR/Type.h"<br>
+#include "llvm/Target/TargetOpcodes.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+#ifndef LLVM_BUILD_GLOBAL_ISEL<br>
+#error "You shouldn't build this"<br>
+#endif<br>
+<br>
+X86LegalizerInfo::<wbr>X86LegalizerInfo(const X86Subtarget &STI) : Subtarget(STI) {<br>
+<br>
+ setLegalizerInfo32bit();<br>
+ setLegalizerInfo64bit();<br>
+<br>
+ computeTables();<br>
+}<br>
+<br>
+void X86LegalizerInfo::<wbr>setLegalizerInfo32bit() {<br>
+<br>
+ const LLT s8 = LLT::scalar(8);<br>
+ const LLT s16 = LLT::scalar(16);<br>
+ const LLT s32 = LLT::scalar(32);<br>
+<br>
+ for (auto Ty : {s8, s16, s32})<br>
+ setAction({TargetOpcode::G_<wbr>ADD, Ty}, Legal);<br>
+}<br>
+void<br>
+<br>
+X86LegalizerInfo::<wbr>setLegalizerInfo64bit() {<br>
+<br>
+ if (!Subtarget.is64Bit())<br>
+ return;<br>
+<br>
+ const LLT s64 = LLT::scalar(64);<br>
+<br>
+ setAction({TargetOpcode::G_<wbr>ADD, s64}, Legal);<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/X86/<wbr>X86LegalizerInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86LegalizerInfo.h?rev=294723&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86LegalizerInfo.h?rev=<wbr>294723&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86LegalizerInfo.h (added)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86LegalizerInfo.h Fri Feb 10 01:05:56 2017<br>
@@ -0,0 +1,39 @@<br>
+//===- X86LegalizerInfo.h ------------------------------<wbr>------------*- C++<br>
+//-*-==//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+/// \file<br>
+/// This file declares the targeting of the Machinelegalizer class for X86.<br>
+/// \todo This should be generated by TableGen.<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+<br>
+#ifndef LLVM_LIB_TARGET_X86_<wbr>X86MACHINELEGALIZER_H<br>
+#define LLVM_LIB_TARGET_X86_<wbr>X86MACHINELEGALIZER_H<br>
+<br>
+#include "llvm/CodeGen/GlobalISel/<wbr>LegalizerInfo.h"<br>
+<br>
+namespace llvm {<br>
+<br>
+class X86Subtarget;<br>
+<br>
+/// This class provides the information for the target register banks.<br>
+class X86LegalizerInfo : public LegalizerInfo {<br>
+private:<br>
+ /// Keep a reference to the X86Subtarget around so that we can<br>
+ /// make the right decision when generating code for different targets.<br>
+ const X86Subtarget &Subtarget;<br>
+<br>
+public:<br>
+ X86LegalizerInfo(const X86Subtarget &STI);<br>
+<br>
+private:<br>
+ void setLegalizerInfo32bit();<br>
+ void setLegalizerInfo64bit();<br>
+};<br>
+} // End llvm namespace.<br>
+#endif<br>
<br>
Added: llvm/trunk/lib/Target/X86/<wbr>X86RegisterBankInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBankInfo.cpp?rev=294723&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86RegisterBankInfo.cpp?<wbr>rev=294723&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86RegisterBankInfo.cpp (added)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86RegisterBankInfo.cpp Fri Feb 10 01:05:56 2017<br>
@@ -0,0 +1,121 @@<br>
+//===- X86RegisterBankInfo.cpp ------------------------------<wbr>-----*- C++ -*-==//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+/// \file<br>
+/// This file implements the targeting of the RegisterBankInfo class for X86.<br>
+/// \todo This should be generated by TableGen.<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+<br>
+#include "X86RegisterBankInfo.h"<br>
+#include "X86InstrInfo.h"<br>
+#include "llvm/CodeGen/GlobalISel/<wbr>RegisterBank.h"<br>
+#include "llvm/CodeGen/GlobalISel/<wbr>RegisterBankInfo.h"<br>
+#include "llvm/CodeGen/<wbr>MachineRegisterInfo.h"<br>
+#include "llvm/Target/<wbr>TargetRegisterInfo.h"<br>
+<br>
+#define GET_TARGET_REGBANK_IMPL<br>
+#include "X86GenRegisterBank.inc"<br>
+<br>
+// This file will be TableGen'ed at some point.<br>
+#include "X86GenRegisterBankInfo.def"<br>
+<br>
+using namespace llvm;<br>
+<br>
+#ifndef LLVM_BUILD_GLOBAL_ISEL<br>
+#error "You shouldn't build this"<br>
+#endif<br>
+<br>
+X86RegisterBankInfo::<wbr>X86RegisterBankInfo(const TargetRegisterInfo &TRI)<br>
+ : X86GenRegisterBankInfo() {<br>
+<br>
+ // validate RegBank initialization.<br>
+ const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID);<br>
+ (void)RBGPR;<br>
+ assert(&X86::GPRRegBank == &RBGPR && "Incorrect RegBanks inizalization.");<br>
+<br>
+ // The GPR register bank is fully defined by all the registers in<br>
+ // GR64 + its subclasses.<br>
+ assert(RBGPR.covers(*TRI.<wbr>getRegClass(X86::<wbr>GR64RegClassID)) &&<br>
+ "Subclass not added?");<br>
+ assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");<br>
+}<br>
+<br>
+const RegisterBank &X86RegisterBankInfo::<wbr>getRegBankFromRegClass(<br>
+ const TargetRegisterClass &RC) const {<br>
+<br>
+ if (X86::GR8RegClass.<wbr>hasSubClassEq(&RC) ||<br>
+ X86::GR16RegClass.<wbr>hasSubClassEq(&RC) ||<br>
+ X86::GR32RegClass.<wbr>hasSubClassEq(&RC) ||<br>
+ X86::GR64RegClass.<wbr>hasSubClassEq(&RC))<br>
+ return getRegBank(X86::GPRRegBankID);<br>
+<br>
+ llvm_unreachable("Unsupported register kind yet.");<br>
+}<br>
+<br>
+RegisterBankInfo::<wbr>InstructionMapping<br>
+X86RegisterBankInfo::<wbr>getOperandsMapping(const MachineInstr &MI, bool isFP) {<br>
+ const MachineFunction &MF = *MI.getParent()->getParent();<br>
+ const MachineRegisterInfo &MRI = MF.getRegInfo();<br>
+<br>
+ unsigned NumOperands = MI.getNumOperands();<br>
+ LLT Ty = MRI.getType(MI.getOperand(0).<wbr>getReg());<br>
+<br>
+ if (NumOperands != 3 ||<br>
+ (Ty != MRI.getType(MI.getOperand(1).<wbr>getReg())) ||<br>
+ (Ty != MRI.getType(MI.getOperand(2).<wbr>getReg())))<br>
+ llvm_unreachable("Unsupported operand maping yet.");<br>
+<br>
+ ValueMappingIdx ValMapIdx = VMI_None;<br>
+ if (!isFP) {<br>
+ switch (Ty.getSizeInBits()) {<br>
+ case 8:<br>
+ ValMapIdx = VMI_3OpsGpr8Idx;<br>
+ break;<br>
+ case 16:<br>
+ ValMapIdx = VMI_3OpsGpr16Idx;<br>
+ break;<br>
+ case 32:<br>
+ ValMapIdx = VMI_3OpsGpr32Idx;<br>
+ break;<br>
+ case 64:<br>
+ ValMapIdx = VMI_3OpsGpr64Idx;<br>
+ break;<br>
+ default:<br>
+ llvm_unreachable("Unsupported register size.");<br>
+ break;<br>
+ }<br>
+ } else {<br>
+ llvm_unreachable("Floating point not supported yet.");<br>
+ }<br>
+<br>
+ return InstructionMapping{<wbr>DefaultMappingID, 1, &ValMappings[ValMapIdx],<br>
+ NumOperands};<br>
+}<br>
+<br>
+RegisterBankInfo::<wbr>InstructionMapping<br>
+X86RegisterBankInfo::<wbr>getInstrMapping(const MachineInstr &MI) const {<br>
+ auto Opc = MI.getOpcode();<br>
+<br>
+ // Try the default logic for non-generic instructions that are either copies<br>
+ // or already have some operands assigned to banks.<br>
+ if (!isPreISelGenericOpcode(Opc)) {<br>
+ InstructionMapping Mapping = getInstrMappingImpl(MI);<br>
+ if (Mapping.isValid())<br>
+ return Mapping;<br>
+ }<br>
+<br>
+ switch (Opc) {<br>
+ case TargetOpcode::G_ADD:<br>
+ return getOperandsMapping(MI, false);<br>
+ break;<br>
+ default:<br>
+ return InstructionMapping{};<br>
+ }<br>
+<br>
+ return InstructionMapping{};<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/X86/<wbr>X86RegisterBankInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBankInfo.h?rev=294723&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86RegisterBankInfo.h?rev=<wbr>294723&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86RegisterBankInfo.h (added)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86RegisterBankInfo.h Fri Feb 10 01:05:56 2017<br>
@@ -0,0 +1,54 @@<br>
+//===- X86RegisterBankInfo ------------------------------<wbr>---------*- C++ -*-==//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+/// \file<br>
+/// This file declares the targeting of the RegisterBankInfo class for X86.<br>
+/// \todo This should be generated by TableGen.<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+<br>
+#ifndef LLVM_LIB_TARGET_X86_<wbr>X86REGISTERBANKINFO_H<br>
+#define LLVM_LIB_TARGET_X86_<wbr>X86REGISTERBANKINFO_H<br>
+<br>
+#include "llvm/CodeGen/GlobalISel/<wbr>RegisterBankInfo.h"<br>
+<br>
+#define GET_REGBANK_DECLARATIONS<br>
+#include "X86GenRegisterBank.inc"<br>
+<br>
+namespace llvm {<br>
+<br>
+class X86GenRegisterBankInfo : public RegisterBankInfo {<br>
+protected:<br>
+ static RegisterBankInfo::<wbr>PartialMapping PartMappings[];<br>
+ static RegisterBankInfo::ValueMapping ValMappings[];<br>
+<br>
+#define GET_TARGET_REGBANK_CLASS<br>
+#include "X86GenRegisterBank.inc"<br>
+};<br>
+<br>
+class TargetRegisterInfo;<br>
+<br>
+/// This class provides the information for the target register banks.<br>
+class X86RegisterBankInfo final : public X86GenRegisterBankInfo {<br>
+private:<br>
+ /// Get an instruction mapping.<br>
+ /// \return An InstructionMappings with a statically allocated<br>
+ /// OperandsMapping.<br>
+ static InstructionMapping getOperandsMapping(const MachineInstr &MI,<br>
+ bool isFP);<br>
+<br>
+public:<br>
+ X86RegisterBankInfo(const TargetRegisterInfo &TRI);<br>
+<br>
+ const RegisterBank &<br>
+ getRegBankFromRegClass(const TargetRegisterClass &RC) const override;<br>
+<br>
+ InstructionMapping getInstrMapping(const MachineInstr &MI) const override;<br>
+};<br>
+<br>
+} // End llvm namespace.<br>
+#endif<br>
<br>
Added: llvm/trunk/lib/Target/X86/<wbr>X86RegisterBanks.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterBanks.td?rev=294723&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86RegisterBanks.td?rev=<wbr>294723&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86RegisterBanks.td (added)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86RegisterBanks.td Fri Feb 10 01:05:56 2017<br>
@@ -0,0 +1,14 @@<br>
+//=- X86RegisterBank.td - Describe the AArch64 Banks -----*- tablegen -*-=//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+//<br>
+//<br>
+//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
+<br>
+/// General Purpose Registers: RAX, RCX,...<br>
+def GPRRegBank : RegisterBank<"GPR", [GR64]>;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=294723&r1=294722&r2=294723&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86TargetMachine.cpp?rev=<wbr>294723&r1=294722&r2=294723&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86TargetMachine.cpp Fri Feb 10 01:05:56 2017<br>
@@ -14,6 +14,8 @@<br>
#include "MCTargetDesc/X86MCTargetDesc.<wbr>h"<br>
#include "X86.h"<br>
#include "X86CallLowering.h"<br>
+#include "X86LegalizerInfo.h"<br>
+#include "X86RegisterBankInfo.h"<br>
#include "X86MacroFusion.h"<br>
#include "X86Subtarget.h"<br>
#include "X86TargetMachine.h"<br>
@@ -28,6 +30,8 @@<br>
#include "llvm/CodeGen/GlobalISel/<wbr>CallLowering.h"<br>
#include "llvm/CodeGen/GlobalISel/<wbr>GISelAccessor.h"<br>
#include "llvm/CodeGen/GlobalISel/<wbr>IRTranslator.h"<br>
+#include "llvm/CodeGen/GlobalISel/<wbr>Legalizer.h"<br>
+#include "llvm/CodeGen/GlobalISel/<wbr>RegBankSelect.h"<br>
#include "llvm/CodeGen/<wbr>MachineScheduler.h"<br>
#include "llvm/CodeGen/Passes.h"<br>
#include "llvm/CodeGen/<wbr>TargetPassConfig.h"<br>
@@ -202,12 +206,12 @@ X86TargetMachine::~<wbr>X86TargetMachine() =<br>
namespace {<br>
<br>
struct X86GISelActualAccessor : public GISelAccessor {<br>
- std::unique_ptr<CallLowering> CL;<br>
-<br>
- X86GISelActualAccessor(<wbr>CallLowering* CL): CL(CL) {}<br>
+ std::unique_ptr<CallLowering> CallLoweringInfo;<br>
+ std::unique_ptr<LegalizerInfo> Legalizer;</blockquote><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+ std::unique_ptr<<wbr>RegisterBankInfo> RegBankInfo;<br>
<br>
const CallLowering *getCallLowering() const override {<br>
- return CL.get();<br>
+ return CallLoweringInfo.get();<br>
}<br>
<br>
const InstructionSelector *getInstructionSelector() const override {<br>
@@ -216,13 +220,11 @@ struct X86GISelActualAccessor : public G<br>
}<br>
<br>
const LegalizerInfo *getLegalizerInfo() const override {<br>
- //TODO: Implement<br>
- return nullptr;<br>
+ return Legalizer.get();<br>
}<br>
<br>
const RegisterBankInfo *getRegBankInfo() const override {<br>
- //TODO: Implement<br>
- return nullptr;<br>
+ return RegBankInfo.get();<br>
}<br>
};<br>
<br>
@@ -271,8 +273,14 @@ X86TargetMachine::<wbr>getSubtargetImpl(const<br>
#ifndef LLVM_BUILD_GLOBAL_ISEL<br>
GISelAccessor *GISel = new GISelAccessor();<br>
#else<br>
- X86GISelActualAccessor *GISel = new X86GISelActualAccessor(<br>
- new X86CallLowering(*I-><wbr>getTargetLowering()));<br>
+ X86GISelActualAccessor *GISel = new X86GISelActualAccessor();<br>
+<br>
+ GISel->CallLoweringInfo.reset(<wbr>new X86CallLowering(*I-><wbr>getTargetLowering()));<br>
+ GISel->Legalizer.reset(new X86LegalizerInfo(*I));<br></blockquote><div><br></div><div>FYI, LegalizerInfo doesn't have a virtual destructor, which leads to crashes with -fsized-deallocation. Fixed in r294757.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
+<br>
+ auto *RBI = new X86RegisterBankInfo(*I-><wbr>getRegisterInfo());<br>
+ GISel->RegBankInfo.reset(RBI);<br>
+<br>
#endif<br>
I->setGISelAccessor(*GISel);<br>
}<br>
@@ -371,12 +379,12 @@ bool X86PassConfig::<wbr>addIRTranslator() {<br>
}<br>
<br>
bool X86PassConfig::<wbr>addLegalizeMachineIR() {<br>
- //TODO: Implement<br>
+ addPass(new Legalizer());<br>
return false;<br>
}<br>
<br>
bool X86PassConfig::<wbr>addRegBankSelect() {<br>
- //TODO: Implement<br>
+ addPass(new RegBankSelect());<br>
return false;<br>
}<br>
<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/<wbr>GlobalISel/X86-regbankselect.<wbr>mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/X86-regbankselect.mir?rev=294723&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/GlobalISel/X86-<wbr>regbankselect.mir?rev=294723&<wbr>view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>GlobalISel/X86-regbankselect.<wbr>mir (added)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>GlobalISel/X86-regbankselect.<wbr>mir Fri Feb 10 01:05:56 2017<br>
@@ -0,0 +1,137 @@<br>
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=regbankselect %s -o - | FileCheck %s<br>
+<br>
+--- |<br>
+ ; ModuleID = 'tmp.ll'<br>
+ source_filename = "tmp.ll"<br>
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:<wbr>32:64-S128"<br>
+ target triple = "x86_64--linux-gnu"<br>
+<br>
+ define i8 @test_add_i8(i8 %arg1, i8 %arg2) {<br>
+ %ret = add i8 %arg1, %arg2<br>
+ ret i8 %ret<br>
+ }<br>
+<br>
+ define i16 @test_add_i16(i16 %arg1, i16 %arg2) {<br>
+ %ret = add i16 %arg1, %arg2<br>
+ ret i16 %ret<br>
+ }<br>
+<br>
+ define i32 @test_add_i32(i32 %arg1, i32 %arg2) {<br>
+ %ret = add i32 %arg1, %arg2<br>
+ ret i32 %ret<br>
+ }<br>
+<br>
+ define i64 @test_add_i64(i64 %arg1, i64 %arg2) {<br>
+ %ret = add i64 %arg1, %arg2<br>
+ ret i64 %ret<br>
+ }<br>
+<br>
+...<br>
+---<br>
+name: test_add_i8<br>
+alignment: 4<br>
+legalized: true<br>
+regBankSelected: false<br>
+selected: false<br>
+tracksRegLiveness: true<br>
+# CHECK-LABEL: name: test_add_i8<br>
+# CHECK: registers:<br>
+# CHECK: - { id: 0, class: gpr }<br>
+# CHECK: - { id: 1, class: gpr }<br>
+# CHECK: - { id: 2, class: gpr }<br>
+registers:<br>
+ - { id: 0, class: _ }<br>
+ - { id: 1, class: _ }<br>
+ - { id: 2, class: _ }<br>
+body: |<br>
+ bb.1 (%ir-block.0):<br>
+ liveins: %edi, %esi<br>
+<br>
+ %0(s8) = COPY %edi<br>
+ %1(s8) = COPY %esi<br>
+ %2(s8) = G_ADD %0, %1<br>
+ %al = COPY %2(s8)<br>
+ RET 0, implicit %al<br>
+<br>
+...<br>
+---<br>
+name: test_add_i16<br>
+alignment: 4<br>
+legalized: true<br>
+regBankSelected: false<br>
+selected: false<br>
+tracksRegLiveness: true<br>
+# CHECK-LABEL: name: test_add_i16<br>
+# CHECK: registers:<br>
+# CHECK: - { id: 0, class: gpr }<br>
+# CHECK: - { id: 1, class: gpr }<br>
+# CHECK: - { id: 2, class: gpr }<br>
+registers:<br>
+ - { id: 0, class: _ }<br>
+ - { id: 1, class: _ }<br>
+ - { id: 2, class: _ }<br>
+body: |<br>
+ bb.1 (%ir-block.0):<br>
+ liveins: %edi, %esi<br>
+<br>
+ %0(s16) = COPY %edi<br>
+ %1(s16) = COPY %esi<br>
+ %2(s16) = G_ADD %0, %1<br>
+ %ax = COPY %2(s16)<br>
+ RET 0, implicit %ax<br>
+<br>
+...<br>
+---<br>
+name: test_add_i32<br>
+alignment: 4<br>
+legalized: true<br>
+regBankSelected: false<br>
+selected: false<br>
+tracksRegLiveness: true<br>
+# CHECK-LABEL: name: test_add_i32<br>
+# CHECK: registers:<br>
+# CHECK: - { id: 0, class: gpr }<br>
+# CHECK: - { id: 1, class: gpr }<br>
+# CHECK: - { id: 2, class: gpr }<br>
+registers:<br>
+ - { id: 0, class: _ }<br>
+ - { id: 1, class: _ }<br>
+ - { id: 2, class: _ }<br>
+body: |<br>
+ bb.1 (%ir-block.0):<br>
+ liveins: %edi, %esi<br>
+<br>
+ %0(s32) = COPY %edi<br>
+ %1(s32) = COPY %esi<br>
+ %2(s32) = G_ADD %0, %1<br>
+ %eax = COPY %2(s32)<br>
+ RET 0, implicit %eax<br>
+<br>
+...<br>
+---<br>
+name: test_add_i64<br>
+alignment: 4<br>
+legalized: true<br>
+regBankSelected: false<br>
+selected: false<br>
+tracksRegLiveness: true<br>
+# CHECK-LABEL: name: test_add_i64<br>
+# CHECK: registers:<br>
+# CHECK: - { id: 0, class: gpr }<br>
+# CHECK: - { id: 1, class: gpr }<br>
+# CHECK: - { id: 2, class: gpr }<br>
+registers:<br>
+ - { id: 0, class: _ }<br>
+ - { id: 1, class: _ }<br>
+ - { id: 2, class: _ }<br>
+body: |<br>
+ bb.1 (%ir-block.0):<br>
+ liveins: %rdi, %rsi<br>
+<br>
+ %0(s64) = COPY %rdi<br>
+ %1(s64) = COPY %rsi<br>
+ %2(s64) = G_ADD %0, %1<br>
+ %rax = COPY %2(s64)<br>
+ RET 0, implicit %rax<br>
+<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/<wbr>GlobalISel/legalize-add.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add.mir?rev=294723&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/GlobalISel/<wbr>legalize-add.mir?rev=294723&<wbr>view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>GlobalISel/legalize-add.mir (added)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>GlobalISel/legalize-add.mir Fri Feb 10 01:05:56 2017<br>
@@ -0,0 +1,40 @@<br>
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s<br>
+<br>
+--- |<br>
+ ; ModuleID = '<stdin>'<br>
+ source_filename = "<stdin>"<br>
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:<wbr>32:64-S128"<br>
+ target triple = "x86_64--linux-gnu"<br>
+<br>
+ define i32 @test_add_i32(i32 %arg1, i32 %arg2) {<br>
+ %ret = add i32 %arg1, %arg2<br>
+ ret i32 %ret<br>
+ }<br>
+<br>
+...<br>
+---<br>
+name: test_add_i32<br>
+alignment: 4<br>
+legalized: false<br>
+regBankSelected: false<br>
+selected: false<br>
+tracksRegLiveness: true<br>
+registers:<br>
+ - { id: 0, class: _ }<br>
+ - { id: 1, class: _ }<br>
+ - { id: 2, class: _ }<br>
+body: |<br>
+ bb.1 (%ir-block.0):<br>
+ liveins: %edi, %esi<br>
+ ; CHECK-LABEL: name: test_add_i32<br>
+ ; CHECK: [[VAL1:%.*]](s32) = COPY %edi<br>
+ ; CHECK: [[VAL2:%.*]](s32) = COPY %esi<br>
+ ; CHECK: [[RES:%.*]](s32) = G_ADD [[VAL1:%.*]], [[VAL2:%.*]]<br>
+<br>
+ %0(s32) = COPY %edi<br>
+ %1(s32) = COPY %esi<br>
+ %2(s32) = G_ADD %0, %1<br>
+ %eax = COPY %2(s32)<br>
+ RET 0, implicit %eax<br>
+<br>
+...<br>
<br>
<br>
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</blockquote></div><br></div></div>