<div dir="ltr">This causes asan failures on the bots. <div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/2617/steps/build%20clang%2Fasan/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/2617/steps/build%20clang%2Fasan/logs/stdio</a><br><div>Please fix or revert ASAP. <br><div><pre style="font-family:"courier new",courier,monotype,monospace;color:rgb(0,0,0);font-size:medium"><span class="gmail-stdout">=================================================================
==10398==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x615000f8a264 at pc 0x0000005a83b8 bp 0x7fff9746af50 sp 0x7fff9746af48
READ of size 4 at 0x615000f8a264 thread T0
#0 0x5a83b7 in (anonymous namespace)::AsmWriterEmitter::EmitPrintAliasInstruction(llvm::raw_ostream&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/utils/TableGen/AsmWriterEmitter.cpp:835:47
#1 0x585df3 in run /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/utils/TableGen/AsmWriterEmitter.cpp:1125:3
#2 0x585df3 in llvm::EmitAsmWriter(llvm::RecordKeeper&, llvm::raw_ostream&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/utils/TableGen/AsmWriterEmitter.cpp:1132
#3 0x8e7992 in (anonymous namespace)::LLVMTableGenMain(llvm::raw_ostream&, llvm::RecordKeeper&) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/utils/TableGen/TableGen.cpp:124:5
#4 0x9bb994 in llvm::TableGenMain(char*, bool (*)(llvm::raw_ostream&, llvm::RecordKeeper&)) /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/lib/TableGen/Main.cpp:109:7
#5 0x8e72bd in main /mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm/utils/TableGen/TableGen.cpp:205:10
#6 0x7f9bf335e82f in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x2082f)
#7 0x425988 in _start (/mnt/b/sanitizer-buildbot3/sanitizer-x86_64-linux-fast/build/llvm_build_asan/bin/llvm-tblgen+0x425988)
0x615000f8a264 is located 28 bytes to the left of 504-byte region [0x615000f8a280,0x615000f8a478)</span></pre></div></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Feb 8, 2017 at 3:28 AM, Amara Emerson via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: aemerson<br>
Date: Wed Feb 8 05:28:08 2017<br>
New Revision: 294437<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=294437&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=294437&view=rev</a><br>
Log:<br>
[AArch64][TableGen] Skip tied result operands for InstAlias<br>
<br>
This patch checks the number of operands in the resulting<br>
instruction instead of just the alias, then skips over<br>
tied operands when generating the printing method.<br>
<br>
This allows us to generate the preferred assembly syntax<br>
for the AArch64 'ins' instruction, which should always be<br>
displayed as 'mov' according to the ARMARM.<br>
<br>
Several unit tests have changed as a result, but only to<br>
reflect the preferred disassembly.<br>
<br>
Some other InstAlias patterns (movk/bic/orr) needed a<br>
slight adjustment to stop them becoming the default<br>
and breaking other unit tests.<br>
<br>
Patch by Graham Hunter.<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D29219" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D29219</a><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64InstrInfo.td<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-AdvSIMD-Scalar.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-build-vector.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-dup.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-indexed-vector-<wbr>ldst.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-neon-copy.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-smaxv.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-sminv.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-stp.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-umaxv.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-uminv.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vaddv.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vcombine.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vector-<wbr>insertion.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/bitreverse.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/concat_vector-scalar-<wbr>combine.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v16-instructions.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v4-instructions.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v8-instructions.<wbr>ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-vector-shuffle.ll<br>
llvm/trunk/test/CodeGen/<wbr>AArch64/vector-fcopysign.ll<br>
llvm/trunk/test/MC/AArch64/<wbr>arm64-advsimd.s<br>
llvm/trunk/test/MC/<wbr>Disassembler/AArch64/arm64-<wbr>advsimd.txt<br>
llvm/trunk/utils/TableGen/<wbr>AsmWriterEmitter.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64InstrInfo.td?<wbr>rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64InstrInfo.td Wed Feb 8 05:28:08 2017<br>
@@ -452,8 +452,8 @@ let PostEncoderMethod = "fixMOVZ" in<br>
defm MOVZ : MoveImmediate<0b10, "movz">;<br>
<br>
// First group of aliases covers an implicit "lsl #0".<br>
-def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;<br>
-def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;<br>
+def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0), 0>;<br>
+def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0), 0>;<br>
def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;<br>
def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;<br>
def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;<br>
@@ -470,10 +470,10 @@ def : InstAlias<"movn $Rd, $sym", (MOVNX<br>
def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;<br>
def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;<br>
<br>
-def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;<br>
-def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;<br>
-def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;<br>
-def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;<br>
+def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48), 0>;<br>
+def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32), 0>;<br>
+def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16), 0>;<br>
+def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0), 0>;<br>
<br>
def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;<br>
def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;<br>
@@ -481,8 +481,8 @@ def : InstAlias<"movz $Rd, $sym", (MOVZW<br>
def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;<br>
def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;<br>
<br>
-def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;<br>
-def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;<br>
+def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16), 0>;<br>
+def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0), 0>;<br>
<br>
// Final group of aliases covers true "mov $Rd, $imm" cases.<br>
multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,<br>
@@ -4396,20 +4396,20 @@ def : InstAlias<"bic $Vd.8h, $imm", (BIC<br>
def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;<br>
def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;<br>
<br>
-def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;<br>
-def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;<br>
-def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;<br>
-def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;<br>
+def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;<br>
+def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;<br>
+def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;<br>
+def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;<br>
<br>
def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;<br>
def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;<br>
def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;<br>
def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;<br>
<br>
-def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;<br>
-def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;<br>
-def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;<br>
-def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;<br>
+def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;<br>
+def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;<br>
+def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;<br>
+def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;<br>
<br>
// AdvSIMD FMOV<br>
def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<<wbr>1, 1, 0, 0b1111, V128, fpimm8,<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-AdvSIMD-Scalar.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-AdvSIMD-<wbr>Scalar.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-AdvSIMD-Scalar.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-AdvSIMD-Scalar.<wbr>ll Wed Feb 8 05:28:08 2017<br>
@@ -17,7 +17,7 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x<br>
; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]<br>
; CHECK-NOOPT: fmov d0, [[COPY_REG3]]<br>
; CHECK-OPT-NOT: fmov<br>
-; CHECK: ins.d v0[1], [[COPY_REG2]]<br>
+; CHECK: mov.d v0[1], [[COPY_REG2]]<br>
; CHECK-NEXT: ret<br>
;<br>
; GENERIC-LABEL: bar:<br>
@@ -29,7 +29,7 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x<br>
; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]]<br>
; GENERIC-NOOPT: fmov d0, [[COPY_REG3]]<br>
; GENERIC-OPT-NOT: fmov<br>
-; GENERIC: ins v0.d[1], [[COPY_REG2]]<br>
+; GENERIC: mov v0.d[1], [[COPY_REG2]]<br>
; GENERIC-NEXT: ret<br>
%add = add <2 x i64> %a, %b<br>
%vgetq_lane = extractelement <2 x i64> %add, i32 0<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-build-vector.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-build-vector.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-build-<wbr>vector.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-build-vector.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-build-vector.ll Wed Feb 8 05:28:08 2017<br>
@@ -5,7 +5,7 @@<br>
define void @one_lane(i32* nocapture %out_int, i32 %skip0) nounwind {<br>
; CHECK-LABEL: one_lane:<br>
; CHECK: dup.16b v[[REG:[0-9]+]], wzr<br>
-; CHECK-NEXT: ins.b v[[REG]][0], w1<br>
+; CHECK-NEXT: mov.b v[[REG]][0], w1<br>
; v and q are aliases, and str is preferred against st.16b when possible<br>
; rdar://11246289<br>
; CHECK: str q[[REG]], [x0]<br>
@@ -23,9 +23,9 @@ define void @one_lane(i32* nocapture %ou<br>
define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind {<br>
; CHECK-LABEL: foo:<br>
; CHECK-NOT: ins.s v0[0], v0[0]<br>
-; CHECK: ins.s v0[1], v1[0]<br>
-; CHECK: ins.s v0[2], v2[0]<br>
-; CHECK: ins.s v0[3], v3[0]<br>
+; CHECK: mov.s v0[1], v1[0]<br>
+; CHECK: mov.s v0[2], v2[0]<br>
+; CHECK: mov.s v0[3], v3[0]<br>
; CHECK: ret<br>
%1 = insertelement <4 x float> undef, float %a, i32 0<br>
%2 = insertelement <4 x float> %1, float %b, i32 1<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-dup.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-dup.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-dup.ll?<wbr>rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-dup.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-dup.ll Wed Feb 8 05:28:08 2017<br>
@@ -261,7 +261,7 @@ entry:<br>
define <2 x i32> @f(i32 %a, i32 %b) nounwind readnone {<br>
; CHECK-LABEL: f:<br>
; CHECK-NEXT: fmov s0, w0<br>
-; CHECK-NEXT: ins.s v0[1], w1<br>
+; CHECK-NEXT: mov.s v0[1], w1<br>
; CHECK-NEXT: ret<br>
%vecinit = insertelement <2 x i32> undef, i32 %a, i32 0<br>
%vecinit1 = insertelement <2 x i32> %vecinit, i32 %b, i32 1<br>
@@ -271,9 +271,9 @@ define <2 x i32> @f(i32 %a, i32 %b) noun<br>
define <4 x i32> @g(i32 %a, i32 %b) nounwind readnone {<br>
; CHECK-LABEL: g:<br>
; CHECK-NEXT: fmov s0, w0<br>
-; CHECK-NEXT: ins.s v0[1], w1<br>
-; CHECK-NEXT: ins.s v0[2], w1<br>
-; CHECK-NEXT: ins.s v0[3], w0<br>
+; CHECK-NEXT: mov.s v0[1], w1<br>
+; CHECK-NEXT: mov.s v0[2], w1<br>
+; CHECK-NEXT: mov.s v0[3], w0<br>
; CHECK-NEXT: ret<br>
%vecinit = insertelement <4 x i32> undef, i32 %a, i32 0<br>
%vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1<br>
@@ -285,7 +285,7 @@ define <4 x i32> @g(i32 %a, i32 %b) noun<br>
define <2 x i64> @h(i64 %a, i64 %b) nounwind readnone {<br>
; CHECK-LABEL: h:<br>
; CHECK-NEXT: fmov d0, x0<br>
-; CHECK-NEXT: ins.d v0[1], x1<br>
+; CHECK-NEXT: mov.d v0[1], x1<br>
; CHECK-NEXT: ret<br>
%vecinit = insertelement <2 x i64> undef, i64 %a, i32 0<br>
%vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-indexed-vector-<wbr>ldst.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-indexed-<wbr>vector-ldst.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-indexed-vector-<wbr>ldst.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-indexed-vector-<wbr>ldst.ll Wed Feb 8 05:28:08 2017<br>
@@ -6180,7 +6180,7 @@ define <4 x float> @test_v4f32_post_reg_<br>
; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0]<br>
; CHECK-NEXT: str q0, [x3]<br>
; CHECK-NEXT: ldr q0, [x4]<br>
-; CHECK-NEXT: ins.s v0[1], v[[LD]][0]<br>
+; CHECK-NEXT: mov.s v0[1], v[[LD]][0]<br>
; CHECK-NEXT: add [[POST:x[0-9]]], x0, x2, lsl #2<br>
; CHECK-NEXT: str [[POST]], [x1]<br>
; CHECK-NEXT: ret<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-neon-copy.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-neon-copy.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-neon-<wbr>copy.ll?rev=294437&r1=294436&<wbr>r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-neon-copy.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-neon-copy.ll Wed Feb 8 05:28:08 2017<br>
@@ -3,56 +3,56 @@<br>
<br>
define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {<br>
; CHECK-LABEL: ins16bw:<br>
-; CHECK: ins {{v[0-9]+}}.b[15], {{w[0-9]+}}<br>
+; CHECK: mov {{v[0-9]+}}.b[15], {{w[0-9]+}}<br>
%tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 15<br>
ret <16 x i8> %tmp3<br>
}<br>
<br>
define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {<br>
; CHECK-LABEL: ins8hw:<br>
-; CHECK: ins {{v[0-9]+}}.h[6], {{w[0-9]+}}<br>
+; CHECK: mov {{v[0-9]+}}.h[6], {{w[0-9]+}}<br>
%tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 6<br>
ret <8 x i16> %tmp3<br>
}<br>
<br>
define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {<br>
; CHECK-LABEL: ins4sw:<br>
-; CHECK: ins {{v[0-9]+}}.s[2], {{w[0-9]+}}<br>
+; CHECK: mov {{v[0-9]+}}.s[2], {{w[0-9]+}}<br>
%tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 2<br>
ret <4 x i32> %tmp3<br>
}<br>
<br>
define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {<br>
; CHECK-LABEL: ins2dw:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{x[0-9]+}}<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{x[0-9]+}}<br>
%tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 1<br>
ret <2 x i64> %tmp3<br>
}<br>
<br>
define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {<br>
; CHECK-LABEL: ins8bw:<br>
-; CHECK: ins {{v[0-9]+}}.b[5], {{w[0-9]+}}<br>
+; CHECK: mov {{v[0-9]+}}.b[5], {{w[0-9]+}}<br>
%tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 5<br>
ret <8 x i8> %tmp3<br>
}<br>
<br>
define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {<br>
; CHECK-LABEL: ins4hw:<br>
-; CHECK: ins {{v[0-9]+}}.h[3], {{w[0-9]+}}<br>
+; CHECK: mov {{v[0-9]+}}.h[3], {{w[0-9]+}}<br>
%tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 3<br>
ret <4 x i16> %tmp3<br>
}<br>
<br>
define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {<br>
; CHECK-LABEL: ins2sw:<br>
-; CHECK: ins {{v[0-9]+}}.s[1], {{w[0-9]+}}<br>
+; CHECK: mov {{v[0-9]+}}.s[1], {{w[0-9]+}}<br>
%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1<br>
ret <2 x i32> %tmp3<br>
}<br>
<br>
define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {<br>
; CHECK-LABEL: ins16b16:<br>
-; CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]<br>
+; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]<br>
%tmp3 = extractelement <16 x i8> %tmp1, i32 2<br>
%tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15<br>
ret <16 x i8> %tmp4<br>
@@ -60,7 +60,7 @@ define <16 x i8> @ins16b16(<16 x i8> %tm<br>
<br>
define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {<br>
; CHECK-LABEL: ins8h8:<br>
-; CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]<br>
+; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]<br>
%tmp3 = extractelement <8 x i16> %tmp1, i32 2<br>
%tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7<br>
ret <8 x i16> %tmp4<br>
@@ -68,7 +68,7 @@ define <8 x i16> @ins8h8(<8 x i16> %tmp1<br>
<br>
define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {<br>
; CHECK-LABEL: ins4s4:<br>
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]<br>
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]<br>
%tmp3 = extractelement <4 x i32> %tmp1, i32 2<br>
%tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1<br>
ret <4 x i32> %tmp4<br>
@@ -76,7 +76,7 @@ define <4 x i32> @ins4s4(<4 x i32> %tmp1<br>
<br>
define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {<br>
; CHECK-LABEL: ins2d2:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
%tmp3 = extractelement <2 x i64> %tmp1, i32 0<br>
%tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1<br>
ret <2 x i64> %tmp4<br>
@@ -84,7 +84,7 @@ define <2 x i64> @ins2d2(<2 x i64> %tmp1<br>
<br>
define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {<br>
; CHECK-LABEL: ins4f4:<br>
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]<br>
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]<br>
%tmp3 = extractelement <4 x float> %tmp1, i32 2<br>
%tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1<br>
ret <4 x float> %tmp4<br>
@@ -92,7 +92,7 @@ define <4 x float> @ins4f4(<4 x float> %<br>
<br>
define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {<br>
; CHECK-LABEL: ins2df2:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
%tmp3 = extractelement <2 x double> %tmp1, i32 0<br>
%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1<br>
ret <2 x double> %tmp4<br>
@@ -100,7 +100,7 @@ define <2 x double> @ins2df2(<2 x double<br>
<br>
define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {<br>
; CHECK-LABEL: ins8b16:<br>
-; CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]<br>
+; CHECK: mov {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]<br>
%tmp3 = extractelement <8 x i8> %tmp1, i32 2<br>
%tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15<br>
ret <16 x i8> %tmp4<br>
@@ -108,7 +108,7 @@ define <16 x i8> @ins8b16(<8 x i8> %tmp1<br>
<br>
define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {<br>
; CHECK-LABEL: ins4h8:<br>
-; CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]<br>
+; CHECK: mov {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]<br>
%tmp3 = extractelement <4 x i16> %tmp1, i32 2<br>
%tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7<br>
ret <8 x i16> %tmp4<br>
@@ -116,7 +116,7 @@ define <8 x i16> @ins4h8(<4 x i16> %tmp1<br>
<br>
define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {<br>
; CHECK-LABEL: ins2s4:<br>
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]<br>
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]<br>
%tmp3 = extractelement <2 x i32> %tmp1, i32 1<br>
%tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1<br>
ret <4 x i32> %tmp4<br>
@@ -124,7 +124,7 @@ define <4 x i32> @ins2s4(<2 x i32> %tmp1<br>
<br>
define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {<br>
; CHECK-LABEL: ins1d2:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
%tmp3 = extractelement <1 x i64> %tmp1, i32 0<br>
%tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1<br>
ret <2 x i64> %tmp4<br>
@@ -132,7 +132,7 @@ define <2 x i64> @ins1d2(<1 x i64> %tmp1<br>
<br>
define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {<br>
; CHECK-LABEL: ins2f4:<br>
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]<br>
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]<br>
%tmp3 = extractelement <2 x float> %tmp1, i32 1<br>
%tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1<br>
ret <4 x float> %tmp4<br>
@@ -140,7 +140,7 @@ define <4 x float> @ins2f4(<2 x float> %<br>
<br>
define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {<br>
; CHECK-LABEL: ins1f2:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
%tmp3 = extractelement <1 x double> %tmp1, i32 0<br>
%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1<br>
ret <2 x double> %tmp4<br>
@@ -148,7 +148,7 @@ define <2 x double> @ins1f2(<1 x double><br>
<br>
define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {<br>
; CHECK-LABEL: ins16b8:<br>
-; CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]<br>
+; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]<br>
%tmp3 = extractelement <16 x i8> %tmp1, i32 2<br>
%tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7<br>
ret <8 x i8> %tmp4<br>
@@ -156,7 +156,7 @@ define <8 x i8> @ins16b8(<16 x i8> %tmp1<br>
<br>
define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {<br>
; CHECK-LABEL: ins8h4:<br>
-; CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]<br>
+; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]<br>
%tmp3 = extractelement <8 x i16> %tmp1, i32 2<br>
%tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3<br>
ret <4 x i16> %tmp4<br>
@@ -164,7 +164,7 @@ define <4 x i16> @ins8h4(<8 x i16> %tmp1<br>
<br>
define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {<br>
; CHECK-LABEL: ins4s2:<br>
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]<br>
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]<br>
%tmp3 = extractelement <4 x i32> %tmp1, i32 2<br>
%tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1<br>
ret <2 x i32> %tmp4<br>
@@ -172,7 +172,7 @@ define <2 x i32> @ins4s2(<4 x i32> %tmp1<br>
<br>
define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {<br>
; CHECK-LABEL: ins2d1:<br>
-; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]<br>
%tmp3 = extractelement <2 x i64> %tmp1, i32 0<br>
%tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0<br>
ret <1 x i64> %tmp4<br>
@@ -180,7 +180,7 @@ define <1 x i64> @ins2d1(<2 x i64> %tmp1<br>
<br>
define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {<br>
; CHECK-LABEL: ins4f2:<br>
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]<br>
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]<br>
%tmp3 = extractelement <4 x float> %tmp1, i32 2<br>
%tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1<br>
ret <2 x float> %tmp4<br>
@@ -196,7 +196,7 @@ define <1 x double> @ins2f1(<2 x double><br>
<br>
define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {<br>
; CHECK-LABEL: ins8b8:<br>
-; CHECK: ins {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]<br>
+; CHECK: mov {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]<br>
%tmp3 = extractelement <8 x i8> %tmp1, i32 2<br>
%tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4<br>
ret <8 x i8> %tmp4<br>
@@ -204,7 +204,7 @@ define <8 x i8> @ins8b8(<8 x i8> %tmp1,<br>
<br>
define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {<br>
; CHECK-LABEL: ins4h4:<br>
-; CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]<br>
+; CHECK: mov {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]<br>
%tmp3 = extractelement <4 x i16> %tmp1, i32 2<br>
%tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3<br>
ret <4 x i16> %tmp4<br>
@@ -212,7 +212,7 @@ define <4 x i16> @ins4h4(<4 x i16> %tmp1<br>
<br>
define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {<br>
; CHECK-LABEL: ins2s2:<br>
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]<br>
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]<br>
%tmp3 = extractelement <2 x i32> %tmp1, i32 0<br>
%tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1<br>
ret <2 x i32> %tmp4<br>
@@ -220,7 +220,7 @@ define <2 x i32> @ins2s2(<2 x i32> %tmp1<br>
<br>
define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {<br>
; CHECK-LABEL: ins1d1:<br>
-; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]<br>
%tmp3 = extractelement <1 x i64> %tmp1, i32 0<br>
%tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0<br>
ret <1 x i64> %tmp4<br>
@@ -228,7 +228,7 @@ define <1 x i64> @ins1d1(<1 x i64> %tmp1<br>
<br>
define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {<br>
; CHECK-LABEL: ins2f2:<br>
-; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]<br>
+; CHECK: mov {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]<br>
%tmp3 = extractelement <2 x float> %tmp1, i32 0<br>
%tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1<br>
ret <2 x float> %tmp4<br>
@@ -388,28 +388,28 @@ define i64 @smovx2s(<2 x i32> %tmp1) {<br>
<br>
define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {<br>
; CHECK-LABEL: test_vcopy_lane_s8:<br>
-; CHECK: ins {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]<br>
+; CHECK: mov {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]<br>
%vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 11, i32 6, i32 7><br>
ret <8 x i8> %vset_lane<br>
}<br>
<br>
define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) {<br>
; CHECK-LABEL: test_vcopyq_laneq_s8:<br>
-; CHECK: ins {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]<br>
+; CHECK: mov {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]<br>
%vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 22, i32 15><br>
ret <16 x i8> %vset_lane<br>
}<br>
<br>
define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {<br>
; CHECK-LABEL: test_vcopy_lane_swap_s8:<br>
-; CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]<br>
+; CHECK: mov {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]<br>
%vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0><br>
ret <8 x i8> %vset_lane<br>
}<br>
<br>
define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {<br>
; CHECK-LABEL: test_vcopyq_laneq_swap_s8:<br>
-; CHECK: ins {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]<br>
+; CHECK: mov {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]<br>
%vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31><br>
ret <16 x i8> %vset_lane<br>
}<br>
@@ -907,9 +907,9 @@ define <8 x i8> @getl(<16 x i8> %x) #0 {<br>
; CHECK-DAG: and [[MASKED_IDX:x[0-9]+]], x0, #0x7<br>
; CHECK: bfi [[PTR:x[0-9]+]], [[MASKED_IDX]], #1, #3<br>
; CHECK-DAG: ld1 { v[[R:[0-9]+]].h }[0], {{\[}}[[PTR]]{{\]}}<br>
-; CHECK-DAG: ins v[[R]].h[1], v0.h[1]<br>
-; CHECK-DAG: ins v[[R]].h[2], v0.h[2]<br>
-; CHECK-DAG: ins v[[R]].h[3], v0.h[3]<br>
+; CHECK-DAG: mov v[[R]].h[1], v0.h[1]<br>
+; CHECK-DAG: mov v[[R]].h[2], v0.h[2]<br>
+; CHECK-DAG: mov v[[R]].h[3], v0.h[3]<br>
define <4 x i16> @test_extracts_inserts_varidx_<wbr>extract(<8 x i16> %x, i32 %idx) {<br>
%tmp = extractelement <8 x i16> %x, i32 %idx<br>
%tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0<br>
@@ -927,9 +927,9 @@ define <4 x i16> @test_extracts_inserts_<br>
; CHECK: bfi x9, [[MASKED_IDX]], #1, #2<br>
; CHECK: st1 { v0.h }[0], [x9]<br>
; CHECK-DAG: ldr d[[R:[0-9]+]]<br>
-; CHECK-DAG: ins v[[R]].h[1], v0.h[1]<br>
-; CHECK-DAG: ins v[[R]].h[2], v0.h[2]<br>
-; CHECK-DAG: ins v[[R]].h[3], v0.h[3]<br>
+; CHECK-DAG: mov v[[R]].h[1], v0.h[1]<br>
+; CHECK-DAG: mov v[[R]].h[2], v0.h[2]<br>
+; CHECK-DAG: mov v[[R]].h[3], v0.h[3]<br>
define <4 x i16> @test_extracts_inserts_varidx_<wbr>insert(<8 x i16> %x, i32 %idx) {<br>
%tmp = extractelement <8 x i16> %x, i32 0<br>
%tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx<br>
@@ -1125,7 +1125,7 @@ define <2 x i32> @test_concat_diff_v1i32<br>
; CHECK-LABEL: test_concat_diff_v1i32_v1i32:<br>
; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}<br>
; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}}<br>
-; CHECK: ins {{v[0-9]+}}.s[1], w{{[0-9]+}}<br>
+; CHECK: mov {{v[0-9]+}}.s[1], w{{[0-9]+}}<br>
entry:<br>
%c = tail call i32 @llvm.aarch64.neon.sqabs.i32(<wbr>i32 %a)<br>
%d = insertelement <2 x i32> undef, i32 %c, i32 0<br>
@@ -1137,7 +1137,7 @@ entry:<br>
<br>
define <16 x i8> @test_concat_v16i8_v16i8_<wbr>v16i8(<16 x i8> %x, <16 x i8> %y) #0 {<br>
; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23><br>
ret <16 x i8> %vecinit30<br>
@@ -1145,7 +1145,7 @@ entry:<br>
<br>
define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<wbr><8 x i8> %x, <16 x i8> %y) #0 {<br>
; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <8 x i8> %x, i32 0<br>
%vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0<br>
@@ -1169,7 +1169,7 @@ entry:<br>
<br>
define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<wbr><16 x i8> %x, <8 x i8> %y) #0 {<br>
; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <16 x i8> %x, i32 0<br>
%vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0<br>
@@ -1208,7 +1208,7 @@ entry:<br>
<br>
define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<<wbr>8 x i8> %x, <8 x i8> %y) #0 {<br>
; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <8 x i8> %x, i32 0<br>
%vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0<br>
@@ -1247,7 +1247,7 @@ entry:<br>
<br>
define <8 x i16> @test_concat_v8i16_v8i16_<wbr>v8i16(<8 x i16> %x, <8 x i16> %y) #0 {<br>
; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11><br>
ret <8 x i16> %vecinit14<br>
@@ -1255,7 +1255,7 @@ entry:<br>
<br>
define <8 x i16> @test_concat_v8i16_v4i16_<wbr>v8i16(<4 x i16> %x, <8 x i16> %y) #0 {<br>
; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <4 x i16> %x, i32 0<br>
%vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0<br>
@@ -1271,7 +1271,7 @@ entry:<br>
<br>
define <8 x i16> @test_concat_v8i16_v8i16_<wbr>v4i16(<8 x i16> %x, <4 x i16> %y) #0 {<br>
; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <8 x i16> %x, i32 0<br>
%vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0<br>
@@ -1294,7 +1294,7 @@ entry:<br>
<br>
define <8 x i16> @test_concat_v8i16_v4i16_<wbr>v4i16(<4 x i16> %x, <4 x i16> %y) #0 {<br>
; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <4 x i16> %x, i32 0<br>
%vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0<br>
@@ -1317,7 +1317,7 @@ entry:<br>
<br>
define <4 x i32> @test_concat_v4i32_v4i32_<wbr>v4i32(<4 x i32> %x, <4 x i32> %y) #0 {<br>
; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5><br>
ret <4 x i32> %vecinit6<br>
@@ -1325,7 +1325,7 @@ entry:<br>
<br>
define <4 x i32> @test_concat_v4i32_v2i32_<wbr>v4i32(<2 x i32> %x, <4 x i32> %y) #0 {<br>
; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <2 x i32> %x, i32 0<br>
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0<br>
@@ -1337,7 +1337,7 @@ entry:<br>
<br>
define <4 x i32> @test_concat_v4i32_v4i32_<wbr>v2i32(<4 x i32> %x, <2 x i32> %y) #0 {<br>
; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <4 x i32> %x, i32 0<br>
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0<br>
@@ -1352,7 +1352,7 @@ entry:<br>
<br>
define <4 x i32> @test_concat_v4i32_v2i32_<wbr>v2i32(<2 x i32> %x, <2 x i32> %y) #0 {<br>
; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecinit6 = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 0, i32 1, i32 2, i32 3><br>
ret <4 x i32> %vecinit6<br>
@@ -1378,7 +1378,7 @@ entry:<br>
<br>
define <2 x i64> @test_concat_v2i64_v2i64_<wbr>v1i64(<2 x i64> %x, <1 x i64> %y) #0 {<br>
; CHECK-LABEL: test_concat_v2i64_v2i64_v1i64:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <2 x i64> %x, i32 0<br>
%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0<br>
@@ -1389,7 +1389,7 @@ entry:<br>
<br>
define <2 x i64> @test_concat_v2i64_v1i64_<wbr>v1i64(<1 x i64> %x, <1 x i64> %y) #0 {<br>
; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:<br>
-; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
+; CHECK: mov {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]<br>
entry:<br>
%vecext = extractelement <1 x i64> %x, i32 0<br>
%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-smaxv.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-smaxv.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-smaxv.<wbr>ll?rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-smaxv.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-smaxv.ll Wed Feb 8 05:28:08 2017<br>
@@ -68,7 +68,7 @@ entry:<br>
define <8 x i8> @test_vmaxv_s8_used_by_laneop(<wbr><8 x i8> %a1, <8 x i8> %a2) {<br>
; CHECK-LABEL: test_vmaxv_s8_used_by_laneop:<br>
; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.<wbr>v8i8(<8 x i8> %a2)<br>
@@ -80,7 +80,7 @@ entry:<br>
define <4 x i16> @test_vmaxv_s16_used_by_<wbr>laneop(<4 x i16> %a1, <4 x i16> %a2) {<br>
; CHECK-LABEL: test_vmaxv_s16_used_by_laneop:<br>
; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.<wbr>v4i16(<4 x i16> %a2)<br>
@@ -92,7 +92,7 @@ entry:<br>
define <2 x i32> @test_vmaxv_s32_used_by_<wbr>laneop(<2 x i32> %a1, <2 x i32> %a2) {<br>
; CHECK-LABEL: test_vmaxv_s32_used_by_laneop:<br>
; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v1<br>
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.<wbr>v2i32(<2 x i32> %a2)<br>
@@ -103,7 +103,7 @@ entry:<br>
define <16 x i8> @test_vmaxvq_s8_used_by_<wbr>laneop(<16 x i8> %a1, <16 x i8> %a2) {<br>
; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop:<br>
; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.<wbr>v16i8(<16 x i8> %a2)<br>
@@ -115,7 +115,7 @@ entry:<br>
define <8 x i16> @test_vmaxvq_s16_used_by_<wbr>laneop(<8 x i16> %a1, <8 x i16> %a2) {<br>
; CHECK-LABEL: test_vmaxvq_s16_used_by_<wbr>laneop:<br>
; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.<wbr>v8i16(<8 x i16> %a2)<br>
@@ -127,7 +127,7 @@ entry:<br>
define <4 x i32> @test_vmaxvq_s32_used_by_<wbr>laneop(<4 x i32> %a1, <4 x i32> %a2) {<br>
; CHECK-LABEL: test_vmaxvq_s32_used_by_<wbr>laneop:<br>
; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.<wbr>v4i32(<4 x i32> %a2)<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-sminv.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-sminv.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-sminv.<wbr>ll?rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-sminv.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-sminv.ll Wed Feb 8 05:28:08 2017<br>
@@ -68,7 +68,7 @@ entry:<br>
define <8 x i8> @test_vminv_s8_used_by_laneop(<wbr><8 x i8> %a1, <8 x i8> %a2) {<br>
; CHECK-LABEL: test_vminv_s8_used_by_laneop:<br>
; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.<wbr>v8i8(<8 x i8> %a2)<br>
@@ -80,7 +80,7 @@ entry:<br>
define <4 x i16> @test_vminv_s16_used_by_<wbr>laneop(<4 x i16> %a1, <4 x i16> %a2) {<br>
; CHECK-LABEL: test_vminv_s16_used_by_laneop:<br>
; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.<wbr>v4i16(<4 x i16> %a2)<br>
@@ -92,7 +92,7 @@ entry:<br>
define <2 x i32> @test_vminv_s32_used_by_<wbr>laneop(<2 x i32> %a1, <2 x i32> %a2) {<br>
; CHECK-LABEL: test_vminv_s32_used_by_laneop:<br>
; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1<br>
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.<wbr>v2i32(<2 x i32> %a2)<br>
@@ -103,7 +103,7 @@ entry:<br>
define <16 x i8> @test_vminvq_s8_used_by_<wbr>laneop(<16 x i8> %a1, <16 x i8> %a2) {<br>
; CHECK-LABEL: test_vminvq_s8_used_by_laneop:<br>
; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.<wbr>v16i8(<16 x i8> %a2)<br>
@@ -115,7 +115,7 @@ entry:<br>
define <8 x i16> @test_vminvq_s16_used_by_<wbr>laneop(<8 x i16> %a1, <8 x i16> %a2) {<br>
; CHECK-LABEL: test_vminvq_s16_used_by_<wbr>laneop:<br>
; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.<wbr>v8i16(<8 x i16> %a2)<br>
@@ -127,7 +127,7 @@ entry:<br>
define <4 x i32> @test_vminvq_s32_used_by_<wbr>laneop(<4 x i32> %a1, <4 x i32> %a2) {<br>
; CHECK-LABEL: test_vminvq_s32_used_by_<wbr>laneop:<br>
; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.sminv.i32.<wbr>v4i32(<4 x i32> %a2)<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-stp.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-stp.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-stp.ll?<wbr>rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-stp.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-stp.ll Wed Feb 8 05:28:08 2017<br>
@@ -106,9 +106,9 @@ entry:<br>
; CHECK-LABEL: nosplat_v4i32:<br>
; CHECK: str w0,<br>
; CHECK: ldr q[[REG1:[0-9]+]],<br>
-; CHECK-DAG: ins v[[REG1]].s[1], w0<br>
-; CHECK-DAG: ins v[[REG1]].s[2], w0<br>
-; CHECK-DAG: ins v[[REG1]].s[3], w0<br>
+; CHECK-DAG: mov v[[REG1]].s[1], w0<br>
+; CHECK-DAG: mov v[[REG1]].s[2], w0<br>
+; CHECK-DAG: mov v[[REG1]].s[3], w0<br>
; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8<br>
; CHECK: stp d[[REG1]], d[[REG2]], [x1]<br>
; CHECK: ret<br>
@@ -128,9 +128,9 @@ define void @nosplat2_v4i32(i32 %v, i32<br>
entry:<br>
<br>
; CHECK-LABEL: nosplat2_v4i32:<br>
-; CHECK: ins v[[REG1]].s[1], w0<br>
-; CHECK-DAG: ins v[[REG1]].s[2], w0<br>
-; CHECK-DAG: ins v[[REG1]].s[3], w0<br>
+; CHECK: mov v[[REG1]].s[1], w0<br>
+; CHECK-DAG: mov v[[REG1]].s[2], w0<br>
+; CHECK-DAG: mov v[[REG1]].s[3], w0<br>
; CHECK: ext v[[REG2:[0-9]+]].16b, v[[REG1]].16b, v[[REG1]].16b, #8<br>
; CHECK: stp d[[REG1]], d[[REG2]], [x1]<br>
; CHECK: ret<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-umaxv.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-umaxv.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-umaxv.<wbr>ll?rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-umaxv.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-umaxv.ll Wed Feb 8 05:28:08 2017<br>
@@ -89,7 +89,7 @@ return:<br>
define <8 x i8> @test_vmaxv_u8_used_by_laneop(<wbr><8 x i8> %a1, <8 x i8> %a2) {<br>
; CHECK-LABEL: test_vmaxv_u8_used_by_laneop:<br>
; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.<wbr>v8i8(<8 x i8> %a2)<br>
@@ -101,7 +101,7 @@ entry:<br>
define <4 x i16> @test_vmaxv_u16_used_by_<wbr>laneop(<4 x i16> %a1, <4 x i16> %a2) {<br>
; CHECK-LABEL: test_vmaxv_u16_used_by_laneop:<br>
; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.<wbr>v4i16(<4 x i16> %a2)<br>
@@ -113,7 +113,7 @@ entry:<br>
define <2 x i32> @test_vmaxv_u32_used_by_<wbr>laneop(<2 x i32> %a1, <2 x i32> %a2) {<br>
; CHECK-LABEL: test_vmaxv_u32_used_by_laneop:<br>
; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1<br>
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.<wbr>v2i32(<2 x i32> %a2)<br>
@@ -124,7 +124,7 @@ entry:<br>
define <16 x i8> @test_vmaxvq_u8_used_by_<wbr>laneop(<16 x i8> %a1, <16 x i8> %a2) {<br>
; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop:<br>
; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.<wbr>v16i8(<16 x i8> %a2)<br>
@@ -136,7 +136,7 @@ entry:<br>
define <8 x i16> @test_vmaxvq_u16_used_by_<wbr>laneop(<8 x i16> %a1, <8 x i16> %a2) {<br>
; CHECK-LABEL: test_vmaxvq_u16_used_by_<wbr>laneop:<br>
; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.<wbr>v8i16(<8 x i16> %a2)<br>
@@ -148,7 +148,7 @@ entry:<br>
define <4 x i32> @test_vmaxvq_u32_used_by_<wbr>laneop(<4 x i32> %a1, <4 x i32> %a2) {<br>
; CHECK-LABEL: test_vmaxvq_u32_used_by_<wbr>laneop:<br>
; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.<wbr>v4i32(<4 x i32> %a2)<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-uminv.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-uminv.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-uminv.<wbr>ll?rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-uminv.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-uminv.ll Wed Feb 8 05:28:08 2017<br>
@@ -89,7 +89,7 @@ return:<br>
define <8 x i8> @test_vminv_u8_used_by_laneop(<wbr><8 x i8> %a1, <8 x i8> %a2) {<br>
; CHECK-LABEL: test_vminv_u8_used_by_laneop:<br>
; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uminv.i32.<wbr>v8i8(<8 x i8> %a2)<br>
@@ -101,7 +101,7 @@ entry:<br>
define <4 x i16> @test_vminv_u16_used_by_<wbr>laneop(<4 x i16> %a1, <4 x i16> %a2) {<br>
; CHECK-LABEL: test_vminv_u16_used_by_laneop:<br>
; CHECK: uminv.4h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uminv.i32.<wbr>v4i16(<4 x i16> %a2)<br>
@@ -113,7 +113,7 @@ entry:<br>
define <2 x i32> @test_vminv_u32_used_by_<wbr>laneop(<2 x i32> %a1, <2 x i32> %a2) {<br>
; CHECK-LABEL: test_vminv_u32_used_by_laneop:<br>
; CHECK: uminp.2s v[[REGNUM:[0-9]+]], v1, v1<br>
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uminv.i32.<wbr>v2i32(<2 x i32> %a2)<br>
@@ -124,7 +124,7 @@ entry:<br>
define <16 x i8> @test_vminvq_u8_used_by_<wbr>laneop(<16 x i8> %a1, <16 x i8> %a2) {<br>
; CHECK-LABEL: test_vminvq_u8_used_by_laneop:<br>
; CHECK: uminv.16b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uminv.i32.<wbr>v16i8(<16 x i8> %a2)<br>
@@ -136,7 +136,7 @@ entry:<br>
define <8 x i16> @test_vminvq_u16_used_by_<wbr>laneop(<8 x i16> %a1, <8 x i16> %a2) {<br>
; CHECK-LABEL: test_vminvq_u16_used_by_<wbr>laneop:<br>
; CHECK: uminv.8h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uminv.i32.<wbr>v8i16(<8 x i16> %a2)<br>
@@ -148,7 +148,7 @@ entry:<br>
define <4 x i32> @test_vminvq_u32_used_by_<wbr>laneop(<4 x i32> %a1, <4 x i32> %a2) {<br>
; CHECK-LABEL: test_vminvq_u32_used_by_<wbr>laneop:<br>
; CHECK: uminv.4s s[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uminv.i32.<wbr>v4i32(<4 x i32> %a2)<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vaddv.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vaddv.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-vaddv.<wbr>ll?rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vaddv.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vaddv.ll Wed Feb 8 05:28:08 2017<br>
@@ -14,7 +14,7 @@ entry:<br>
define <8 x i8> @test_vaddv_s8_used_by_laneop(<wbr><8 x i8> %a1, <8 x i8> %a2) {<br>
; CHECK-LABEL: test_vaddv_s8_used_by_laneop:<br>
; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.<wbr>v8i8(<8 x i8> %a2)<br>
@@ -37,7 +37,7 @@ entry:<br>
define <4 x i16> @test_vaddv_s16_used_by_<wbr>laneop(<4 x i16> %a1, <4 x i16> %a2) {<br>
; CHECK-LABEL: test_vaddv_s16_used_by_laneop:<br>
; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.<wbr>v4i16(<4 x i16> %a2)<br>
@@ -60,7 +60,7 @@ entry:<br>
define <2 x i32> @test_vaddv_s32_used_by_<wbr>laneop(<2 x i32> %a1, <2 x i32> %a2) {<br>
; CHECK-LABEL: test_vaddv_s32_used_by_laneop:<br>
; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1<br>
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.<wbr>v2i32(<2 x i32> %a2)<br>
@@ -81,7 +81,7 @@ entry:<br>
define <2 x i64> @test_vaddv_s64_used_by_<wbr>laneop(<2 x i64> %a1, <2 x i64> %a2) {<br>
; CHECK-LABEL: test_vaddv_s64_used_by_laneop:<br>
; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i64 @llvm.aarch64.neon.saddv.i64.<wbr>v2i64(<2 x i64> %a2)<br>
@@ -103,7 +103,7 @@ entry:<br>
define <8 x i8> @test_vaddv_u8_used_by_laneop(<wbr><8 x i8> %a1, <8 x i8> %a2) {<br>
; CHECK-LABEL: test_vaddv_u8_used_by_laneop:<br>
; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.<wbr>v8i8(<8 x i8> %a2)<br>
@@ -137,7 +137,7 @@ entry:<br>
define <4 x i16> @test_vaddv_u16_used_by_<wbr>laneop(<4 x i16> %a1, <4 x i16> %a2) {<br>
; CHECK-LABEL: test_vaddv_u16_used_by_laneop:<br>
; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.<wbr>v4i16(<4 x i16> %a2)<br>
@@ -171,7 +171,7 @@ entry:<br>
define <2 x i32> @test_vaddv_u32_used_by_<wbr>laneop(<2 x i32> %a1, <2 x i32> %a2) {<br>
; CHECK-LABEL: test_vaddv_u32_used_by_laneop:<br>
; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1<br>
-; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.<wbr>v2i32(<2 x i32> %a2)<br>
@@ -220,7 +220,7 @@ entry:<br>
define <2 x i64> @test_vaddv_u64_used_by_<wbr>laneop(<2 x i64> %a1, <2 x i64> %a2) {<br>
; CHECK-LABEL: test_vaddv_u64_used_by_laneop:<br>
; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i64 @llvm.aarch64.neon.uaddv.i64.<wbr>v2i64(<2 x i64> %a2)<br>
@@ -254,7 +254,7 @@ entry:<br>
define <16 x i8> @test_vaddvq_s8_used_by_<wbr>laneop(<16 x i8> %a1, <16 x i8> %a2) {<br>
; CHECK-LABEL: test_vaddvq_s8_used_by_laneop:<br>
; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.<wbr>v16i8(<16 x i8> %a2)<br>
@@ -277,7 +277,7 @@ entry:<br>
define <8 x i16> @test_vaddvq_s16_used_by_<wbr>laneop(<8 x i16> %a1, <8 x i16> %a2) {<br>
; CHECK-LABEL: test_vaddvq_s16_used_by_<wbr>laneop:<br>
; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.<wbr>v8i16(<8 x i16> %a2)<br>
@@ -299,7 +299,7 @@ entry:<br>
define <4 x i32> @test_vaddvq_s32_used_by_<wbr>laneop(<4 x i32> %a1, <4 x i32> %a2) {<br>
; CHECK-LABEL: test_vaddvq_s32_used_by_<wbr>laneop:<br>
; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.<wbr>v4i32(<4 x i32> %a2)<br>
@@ -321,7 +321,7 @@ entry:<br>
define <16 x i8> @test_vaddvq_u8_used_by_<wbr>laneop(<16 x i8> %a1, <16 x i8> %a2) {<br>
; CHECK-LABEL: test_vaddvq_u8_used_by_laneop:<br>
; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.<wbr>v16i8(<16 x i8> %a2)<br>
@@ -344,7 +344,7 @@ entry:<br>
define <8 x i16> @test_vaddvq_u16_used_by_<wbr>laneop(<8 x i16> %a1, <8 x i16> %a2) {<br>
; CHECK-LABEL: test_vaddvq_u16_used_by_<wbr>laneop:<br>
; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.<wbr>v8i16(<8 x i16> %a2)<br>
@@ -366,7 +366,7 @@ entry:<br>
define <4 x i32> @test_vaddvq_u32_used_by_<wbr>laneop(<4 x i32> %a1, <4 x i32> %a2) {<br>
; CHECK-LABEL: test_vaddvq_u32_used_by_<wbr>laneop:<br>
; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1<br>
-; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]<br>
+; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0]<br>
; CHECK-NEXT: ret<br>
entry:<br>
%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.<wbr>v4i32(<4 x i32> %a2)<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vcombine.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vcombine.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-<wbr>vcombine.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vcombine.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vcombine.ll Wed Feb 8 05:28:08 2017<br>
@@ -6,7 +6,7 @@<br>
define <16 x i8> @test(<16 x i8> %q0, <16 x i8> %q1, i8* nocapture %dest) nounwind {<br>
entry:<br>
; CHECK-LABEL: test:<br>
-; CHECK: ins.d v0[1], v1[0]<br>
+; CHECK: mov.d v0[1], v1[0]<br>
%0 = bitcast <16 x i8> %q0 to <2 x i64><br>
%shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> zeroinitializer<br>
%1 = bitcast <16 x i8> %q1 to <2 x i64><br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vector-<wbr>insertion.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-vector-insertion.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/arm64-vector-<wbr>insertion.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vector-<wbr>insertion.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-vector-<wbr>insertion.ll Wed Feb 8 05:28:08 2017<br>
@@ -9,7 +9,7 @@ entry:<br>
<br>
; CHECK-LABEL: test0f<br>
; CHECK: movi.2d v[[TEMP:[0-9]+]], #0000000000000000<br>
- ; CHECK: ins.s v[[TEMP]][0], v{{[0-9]+}}[0]<br>
+ ; CHECK: mov.s v[[TEMP]][0], v{{[0-9]+}}[0]<br>
; CHECK: str q[[TEMP]], [x0]<br>
; CHECK: ret<br>
<br>
@@ -27,7 +27,7 @@ entry:<br>
; CHECK-LABEL: test1f<br>
; CHECK: fmov s[[TEMP:[0-9]+]], #1.0000000<br>
; CHECK: dup.4s v[[TEMP2:[0-9]+]], v[[TEMP]][0]<br>
- ; CHECK: ins.s v[[TEMP2]][0], v0[0]<br>
+ ; CHECK: mov.s v[[TEMP2]][0], v0[0]<br>
; CHECK: str q[[TEMP2]], [x0]<br>
; CHECK: ret<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/bitreverse.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/bitreverse.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/bitreverse.ll?<wbr>rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/bitreverse.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/bitreverse.ll Wed Feb 8 05:28:08 2017<br>
@@ -11,7 +11,7 @@ define <2 x i16> @f(<2 x i16> %a) {<br>
; CHECK-DAG: fmov s0, [[REG2]]<br>
; CHECK-DAG: mov [[REG3:w[0-9]+]], v0.s[1]<br>
; CHECK-DAG: rbit [[REG4:w[0-9]+]], [[REG3]]<br>
-; CHECK-DAG: ins v0.s[1], [[REG4]]<br>
+; CHECK-DAG: mov v0.s[1], [[REG4]]<br>
; CHECK-DAG: ushr v0.2s, v0.2s, #16<br>
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)<br>
ret <2 x i16> %b<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/concat_vector-scalar-<wbr>combine.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/concat_vector-scalar-combine.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/concat_vector-<wbr>scalar-combine.ll?rev=294437&<wbr>r1=294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/concat_vector-scalar-<wbr>combine.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/concat_vector-scalar-<wbr>combine.ll Wed Feb 8 05:28:08 2017<br>
@@ -38,9 +38,9 @@ entry:<br>
define <8 x i8> @test_concat_scalars_2x_v2i8_<wbr>to_v8i8(i32 %x, i32 %y) #0 {<br>
entry:<br>
; CHECK-LABEL: test_concat_scalars_2x_v2i8_<wbr>to_v8i8:<br>
-; CHECK-NEXT: ins.h v0[0], w0<br>
-; CHECK-NEXT: ins.h v0[1], w1<br>
-; CHECK-NEXT: ins.h v0[3], w1<br>
+; CHECK-NEXT: mov.h v0[0], w0<br>
+; CHECK-NEXT: mov.h v0[1], w1<br>
+; CHECK-NEXT: mov.h v0[3], w1<br>
; CHECK-NEXT: ret<br>
%tx = trunc i32 %x to i16<br>
%ty = trunc i32 %y to i16<br>
@@ -54,7 +54,7 @@ define <8 x i8> @test_concat_scalars_2x_<br>
entry:<br>
; CHECK-LABEL: test_concat_scalars_2x_v4i8_<wbr>to_v8i8_dup:<br>
; CHECK-NEXT: fmov s0, w1<br>
-; CHECK-NEXT: ins.s v0[1], w0<br>
+; CHECK-NEXT: mov.s v0[1], w0<br>
; CHECK-NEXT: ret<br>
%bx = bitcast i32 %x to <4 x i8><br>
%by = bitcast i32 %y to <4 x i8><br>
@@ -66,9 +66,9 @@ define <8 x i16> @test_concat_scalars_2x<br>
entry:<br>
; CHECK-LABEL: test_concat_scalars_2x_v2i16_<wbr>to_v8i16_dup:<br>
; CHECK-NEXT: fmov s0, w0<br>
-; CHECK-NEXT: ins.s v0[1], w1<br>
-; CHECK-NEXT: ins.s v0[2], w1<br>
-; CHECK-NEXT: ins.s v0[3], w0<br>
+; CHECK-NEXT: mov.s v0[1], w1<br>
+; CHECK-NEXT: mov.s v0[2], w1<br>
+; CHECK-NEXT: mov.s v0[3], w0<br>
; CHECK-NEXT: ret<br>
%bx = bitcast i32 %x to <2 x i16><br>
%by = bitcast i32 %y to <2 x i16><br>
@@ -84,10 +84,10 @@ define <8 x i8> @test_concat_scalars_mix<br>
entry:<br>
; CHECK-LABEL: test_concat_scalars_mixed_2x_<wbr>v2i8_to_v8i8:<br>
; CHECK-NEXT: fmov s[[X:[0-9]+]], w0<br>
-; CHECK-NEXT: ins.h v0[0], v[[X]][0]<br>
-; CHECK-NEXT: ins.h v0[1], v1[0]<br>
-; CHECK-NEXT: ins.h v0[2], v[[X]][0]<br>
-; CHECK-NEXT: ins.h v0[3], v1[0]<br>
+; CHECK-NEXT: mov.h v0[0], v[[X]][0]<br>
+; CHECK-NEXT: mov.h v0[1], v1[0]<br>
+; CHECK-NEXT: mov.h v0[2], v[[X]][0]<br>
+; CHECK-NEXT: mov.h v0[3], v1[0]<br>
; CHECK-NEXT: ret<br>
%t = trunc i32 %x to i16<br>
%0 = bitcast i16 %t to <2 x i8><br>
@@ -99,10 +99,10 @@ entry:<br>
define <2 x float> @test_concat_scalars_fp_2x_<wbr>v2i8_to_v8i8(float %dummy, half %x, half %y) #0 {<br>
entry:<br>
; CHECK-LABEL: test_concat_scalars_fp_2x_<wbr>v2i8_to_v8i8:<br>
-; CHECK-NEXT: ins.h v0[0], v1[0]<br>
-; CHECK-NEXT: ins.h v0[1], v2[0]<br>
-; CHECK-NEXT: ins.h v0[2], v1[0]<br>
-; CHECK-NEXT: ins.h v0[3], v2[0]<br>
+; CHECK-NEXT: mov.h v0[0], v1[0]<br>
+; CHECK-NEXT: mov.h v0[1], v2[0]<br>
+; CHECK-NEXT: mov.h v0[2], v1[0]<br>
+; CHECK-NEXT: mov.h v0[3], v2[0]<br>
; CHECK-NEXT: ret<br>
%0 = bitcast half %x to <2 x i8><br>
%y0 = bitcast half %y to <2 x i8><br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v16-instructions.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp16-v16-instructions.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/fp16-v16-<wbr>instructions.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v16-instructions.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v16-instructions.<wbr>ll Wed Feb 8 05:28:08 2017<br>
@@ -11,8 +11,8 @@ define <16 x half> @sitofp_i32(<16 x i32<br>
; CHECK-DAG: fcvtn v1.4h, [[S2]]<br>
; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]<br>
; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]<br>
-; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]<br>
-; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]<br>
+; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]<br>
+; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]<br>
<br>
%1 = sitofp <16 x i32> %a to <16 x half><br>
ret <16 x half> %1<br>
@@ -44,8 +44,8 @@ define <16 x half> @sitofp_i64(<16 x i64<br>
; CHECK-DAG: fcvtn v1.4h, [[S2]].4s<br>
; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s<br>
; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s<br>
-; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]<br>
-; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]<br>
+; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]<br>
+; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]<br>
<br>
%1 = sitofp <16 x i64> %a to <16 x half><br>
ret <16 x half> %1<br>
@@ -62,8 +62,8 @@ define <16 x half> @uitofp_i32(<16 x i32<br>
; CHECK-DAG: fcvtn v1.4h, [[S2]]<br>
; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]<br>
; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]<br>
-; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]<br>
-; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]<br>
+; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]<br>
+; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]<br>
<br>
%1 = uitofp <16 x i32> %a to <16 x half><br>
ret <16 x half> %1<br>
@@ -95,8 +95,8 @@ define <16 x half> @uitofp_i64(<16 x i64<br>
; CHECK-DAG: fcvtn v1.4h, [[S2]].4s<br>
; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s<br>
; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s<br>
-; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]<br>
-; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]<br>
+; CHECK-DAG: mov v0.d[1], v[[R1]].d[0]<br>
+; CHECK-DAG: mov v1.d[1], v[[R3]].d[0]<br>
<br>
%1 = uitofp <16 x i64> %a to <16 x half><br>
ret <16 x half> %1<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v4-instructions.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp16-v4-instructions.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/fp16-v4-<wbr>instructions.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v4-instructions.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v4-instructions.<wbr>ll Wed Feb 8 05:28:08 2017<br>
@@ -87,10 +87,10 @@ define <4 x half> @d_to_h(<4 x double> %<br>
; CHECK-DAG: fcvt<br>
; CHECK-DAG: fcvt<br>
; CHECK-DAG: fcvt<br>
-; CHECK-DAG: ins<br>
-; CHECK-DAG: ins<br>
-; CHECK-DAG: ins<br>
-; CHECK-DAG: ins<br>
+; CHECK-DAG: mov<br>
+; CHECK-DAG: mov<br>
+; CHECK-DAG: mov<br>
+; CHECK-DAG: mov<br>
%1 = fptrunc <4 x double> %a to <4 x half><br>
ret <4 x half> %1<br>
}<br>
@@ -108,10 +108,10 @@ define <4 x double> @h_to_d(<4 x half> %<br>
; CHECK-DAG: fcvt<br>
; CHECK-DAG: fcvt<br>
; CHECK-DAG: fcvt<br>
-; CHECK-DAG: ins<br>
-; CHECK-DAG: ins<br>
-; CHECK-DAG: ins<br>
-; CHECK-DAG: ins<br>
+; CHECK-DAG: mov<br>
+; CHECK-DAG: mov<br>
+; CHECK-DAG: mov<br>
+; CHECK-DAG: mov<br>
%1 = fpext <4 x half> %a to <4 x double><br>
ret <4 x double> %1<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v8-instructions.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp16-v8-instructions.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/fp16-v8-<wbr>instructions.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v8-instructions.<wbr>ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-v8-instructions.<wbr>ll Wed Feb 8 05:28:08 2017<br>
@@ -181,7 +181,7 @@ define <8 x half> @s_to_h(<8 x float> %a<br>
; CHECK-LABEL: s_to_h:<br>
; CHECK-DAG: fcvtn v0.4h, v0.4s<br>
; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s<br>
-; CHECK: ins v0.d[1], [[REG]].d[0]<br>
+; CHECK: mov v0.d[1], [[REG]].d[0]<br>
%1 = fptrunc <8 x float> %a to <8 x half><br>
ret <8 x half> %1<br>
}<br>
@@ -200,14 +200,14 @@ define <8 x half> @d_to_h(<8 x double> %<br>
; CHECK-DAG: fcvt h<br>
; CHECK-DAG: fcvt h<br>
; CHECK-DAG: fcvt h<br>
-; CHECK-DAG: ins v{{[0-9]+}}.h<br>
-; CHECK-DAG: ins v{{[0-9]+}}.h<br>
-; CHECK-DAG: ins v{{[0-9]+}}.h<br>
-; CHECK-DAG: ins v{{[0-9]+}}.h<br>
-; CHECK-DAG: ins v{{[0-9]+}}.h<br>
-; CHECK-DAG: ins v{{[0-9]+}}.h<br>
-; CHECK-DAG: ins v{{[0-9]+}}.h<br>
-; CHECK-DAG: ins v{{[0-9]+}}.h<br>
+; CHECK-DAG: mov v{{[0-9]+}}.h<br>
+; CHECK-DAG: mov v{{[0-9]+}}.h<br>
+; CHECK-DAG: mov v{{[0-9]+}}.h<br>
+; CHECK-DAG: mov v{{[0-9]+}}.h<br>
+; CHECK-DAG: mov v{{[0-9]+}}.h<br>
+; CHECK-DAG: mov v{{[0-9]+}}.h<br>
+; CHECK-DAG: mov v{{[0-9]+}}.h<br>
+; CHECK-DAG: mov v{{[0-9]+}}.h<br>
%1 = fptrunc <8 x double> %a to <8 x half><br>
ret <8 x half> %1<br>
}<br>
@@ -230,10 +230,10 @@ define <8 x double> @h_to_d(<8 x half> %<br>
; CHECK-DAG: fcvt d<br>
; CHECK-DAG: fcvt d<br>
; CHECK-DAG: fcvt d<br>
-; CHECK-DAG: ins<br>
-; CHECK-DAG: ins<br>
-; CHECK-DAG: ins<br>
-; CHECK-DAG: ins<br>
+; CHECK-DAG: mov<br>
+; CHECK-DAG: mov<br>
+; CHECK-DAG: mov<br>
+; CHECK-DAG: mov<br>
%1 = fpext <8 x half> %a to <8 x double><br>
ret <8 x double> %1<br>
}<br>
@@ -263,7 +263,7 @@ define <8 x half> @sitofp_i8(<8 x i8> %a<br>
; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]<br>
; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]<br>
; CHECK-DAG: fcvtn v0.4h, [[HIF]]<br>
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]<br>
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]<br>
%1 = sitofp <8 x i8> %a to <8 x half><br>
ret <8 x half> %1<br>
}<br>
@@ -277,7 +277,7 @@ define <8 x half> @sitofp_i16(<8 x i16><br>
; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]<br>
; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]<br>
; CHECK-DAG: fcvtn v0.4h, [[HIF]]<br>
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]<br>
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]<br>
%1 = sitofp <8 x i16> %a to <8 x half><br>
ret <8 x half> %1<br>
}<br>
@@ -289,7 +289,7 @@ define <8 x half> @sitofp_i32(<8 x i32><br>
; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s<br>
; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]<br>
; CHECK-DAG: fcvtn v0.4h, [[OP1]]<br>
-; CHECK: ins v0.d[1], v[[REG]].d[0]<br>
+; CHECK: mov v0.d[1], v[[REG]].d[0]<br>
%1 = sitofp <8 x i32> %a to <8 x half><br>
ret <8 x half> %1<br>
}<br>
@@ -315,7 +315,7 @@ define <8 x half> @uitofp_i8(<8 x i8> %a<br>
; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]<br>
; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]<br>
; CHECK-DAG: fcvtn v0.4h, [[HIF]]<br>
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]<br>
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]<br>
%1 = uitofp <8 x i8> %a to <8 x half><br>
ret <8 x half> %1<br>
}<br>
@@ -329,7 +329,7 @@ define <8 x half> @uitofp_i16(<8 x i16><br>
; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]<br>
; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]<br>
; CHECK-DAG: fcvtn v0.4h, [[HIF]]<br>
-; CHECK: ins v0.d[1], v[[LOREG]].d[0]<br>
+; CHECK: mov v0.d[1], v[[LOREG]].d[0]<br>
%1 = uitofp <8 x i16> %a to <8 x half><br>
ret <8 x half> %1<br>
}<br>
@@ -341,7 +341,7 @@ define <8 x half> @uitofp_i32(<8 x i32><br>
; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s<br>
; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]<br>
; CHECK-DAG: fcvtn v0.4h, [[OP1]]<br>
-; CHECK: ins v0.d[1], v[[REG]].d[0]<br>
+; CHECK: mov v0.d[1], v[[REG]].d[0]<br>
%1 = uitofp <8 x i32> %a to <8 x half><br>
ret <8 x half> %1<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-vector-shuffle.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fp16-vector-shuffle.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/fp16-vector-<wbr>shuffle.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-vector-shuffle.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/fp16-vector-shuffle.ll Wed Feb 8 05:28:08 2017<br>
@@ -35,7 +35,7 @@ entry:<br>
; }<br>
define <4 x half> @lane_64_64(<4 x half> %a, <4 x half> %b) #0 {<br>
; CHECK-LABEL: lane_64_64:<br>
-; CHECK: ins<br>
+; CHECK: mov<br>
entry:<br>
%0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3><br>
ret <4 x half> %0<br>
@@ -46,7 +46,7 @@ entry:<br>
; }<br>
define <8 x half> @lane_128_64(<8 x half> %a, <4 x half> %b) #0 {<br>
; CHECK-LABEL: lane_128_64:<br>
-; CHECK: ins<br>
+; CHECK: mov<br>
entry:<br>
%0 = bitcast <4 x half> %b to <4 x i16><br>
%vget_lane = extractelement <4 x i16> %0, i32 2<br>
@@ -61,7 +61,7 @@ entry:<br>
; }<br>
define <4 x half> @lane_64_128(<4 x half> %a, <8 x half> %b) #0 {<br>
; CHECK-LABEL: lane_64_128:<br>
-; CHECK: ins<br>
+; CHECK: mov<br>
entry:<br>
%0 = bitcast <8 x half> %b to <8 x i16><br>
%vgetq_lane = extractelement <8 x i16> %0, i32 5<br>
@@ -76,7 +76,7 @@ entry:<br>
; }<br>
define <8 x half> @lane_128_128(<8 x half> %a, <8 x half> %b) #0 {<br>
; CHECK-LABEL: lane_128_128:<br>
-; CHECK: ins<br>
+; CHECK: mov<br>
entry:<br>
%0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7><br>
ret <8 x half> %0<br>
@@ -225,7 +225,7 @@ entry:<br>
define <8 x half> @vcombine(<4 x half> %a, <4 x half> %b) #0 {<br>
entry:<br>
; CHECK-LABEL: vcombine:<br>
-; CHECK: ins<br>
+; CHECK: mov<br>
%shuffle.i = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7><br>
ret <8 x half> %shuffle.i<br>
}<br>
@@ -253,7 +253,7 @@ entry:<br>
define <4 x half> @set_lane_64(<4 x half> %a, half %b) #0 {<br>
; CHECK-LABEL: set_lane_64:<br>
; CHECK: fmov<br>
-; CHECK: ins<br>
+; CHECK: mov<br>
entry:<br>
%0 = bitcast half %b to i16<br>
%1 = bitcast <4 x half> %a to <4 x i16><br>
@@ -267,7 +267,7 @@ entry:<br>
define <8 x half> @set_lane_128(<8 x half> %a, half %b) #0 {<br>
; CHECK-LABEL: set_lane_128:<br>
; CHECK: fmov<br>
-; CHECK: ins<br>
+; CHECK: mov<br>
entry:<br>
%0 = bitcast half %b to i16<br>
%1 = bitcast <8 x half> %a to <8 x i16><br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>AArch64/vector-fcopysign.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/vector-fcopysign.ll?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/AArch64/vector-<wbr>fcopysign.ll?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>AArch64/vector-fcopysign.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>AArch64/vector-fcopysign.ll Wed Feb 8 05:28:08 2017<br>
@@ -106,10 +106,10 @@ define <4 x float> @test_copysign_v4f32_<br>
; CHECK-NEXT: bit.16b v3, v1, v4<br>
; CHECK-NEXT: mov d1, v2[1]<br>
; CHECK-NEXT: fcvt s1, d1<br>
-; CHECK-NEXT: ins.s v0[1], v3[0]<br>
-; CHECK-NEXT: ins.s v0[2], v6[0]<br>
+; CHECK-NEXT: mov.s v0[1], v3[0]<br>
+; CHECK-NEXT: mov.s v0[2], v6[0]<br>
; CHECK-NEXT: bit.16b v7, v1, v4<br>
-; CHECK-NEXT: ins.s v0[3], v7[0]<br>
+; CHECK-NEXT: mov.s v0[3], v7[0]<br>
; CHECK-NEXT: ret<br>
%tmp0 = fptrunc <4 x double> %b to <4 x float><br>
%r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %tmp0)<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/<wbr>arm64-advsimd.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/arm64-advsimd.s?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>AArch64/arm64-advsimd.s?rev=<wbr>294437&r1=294436&r2=294437&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/<wbr>arm64-advsimd.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/<wbr>arm64-advsimd.s Wed Feb 8 05:28:08 2017<br>
@@ -220,15 +220,15 @@ foo:<br>
ins v2.h[1], w5<br>
ins v2.b[1], w5<br>
<br>
-; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]<br>
-; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]<br>
-; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]<br>
-; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]<br>
-<br>
-; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]<br>
-; CHECK: ins.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]<br>
-; CHECK: ins.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]<br>
-; CHECK: ins.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]<br>
+; CHECK: mov.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]<br>
+; CHECK: mov.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]<br>
+; CHECK: mov.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]<br>
+; CHECK: mov.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]<br>
+<br>
+; CHECK: mov.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]<br>
+; CHECK: mov.s v2[1], w5 ; encoding: [0xa2,0x1c,0x0c,0x4e]<br>
+; CHECK: mov.h v2[1], w5 ; encoding: [0xa2,0x1c,0x06,0x4e]<br>
+; CHECK: mov.b v2[1], w5 ; encoding: [0xa2,0x1c,0x03,0x4e]<br>
<br>
ins.d v2[1], v15[1]<br>
ins.s v2[1], v15[1]<br>
@@ -240,15 +240,15 @@ foo:<br>
ins v2.h[7], v15.h[3]<br>
ins v2.b[10], v15.b[5]<br>
<br>
-; CHECK: ins.d v2[1], v15[1] ; encoding: [0xe2,0x45,0x18,0x6e]<br>
-; CHECK: ins.s v2[1], v15[1] ; encoding: [0xe2,0x25,0x0c,0x6e]<br>
-; CHECK: ins.h v2[1], v15[1] ; encoding: [0xe2,0x15,0x06,0x6e]<br>
-; CHECK: ins.b v2[1], v15[1] ; encoding: [0xe2,0x0d,0x03,0x6e]<br>
-<br>
-; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]<br>
-; CHECK: ins.s v2[3], v15[2] ; encoding: [0xe2,0x45,0x1c,0x6e]<br>
-; CHECK: ins.h v2[7], v15[3] ; encoding: [0xe2,0x35,0x1e,0x6e]<br>
-; CHECK: ins.b v2[10], v15[5] ; encoding: [0xe2,0x2d,0x15,0x6e]<br>
+; CHECK: mov.d v2[1], v15[1] ; encoding: [0xe2,0x45,0x18,0x6e]<br>
+; CHECK: mov.s v2[1], v15[1] ; encoding: [0xe2,0x25,0x0c,0x6e]<br>
+; CHECK: mov.h v2[1], v15[1] ; encoding: [0xe2,0x15,0x06,0x6e]<br>
+; CHECK: mov.b v2[1], v15[1] ; encoding: [0xe2,0x0d,0x03,0x6e]<br>
+<br>
+; CHECK: mov.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]<br>
+; CHECK: mov.s v2[3], v15[2] ; encoding: [0xe2,0x45,0x1c,0x6e]<br>
+; CHECK: mov.h v2[7], v15[3] ; encoding: [0xe2,0x35,0x1e,0x6e]<br>
+; CHECK: mov.b v2[10], v15[5] ; encoding: [0xe2,0x2d,0x15,0x6e]<br>
<br>
; MOV aliases for the above INS instructions.<br>
mov.d v2[1], x5<br>
@@ -271,22 +271,22 @@ foo:<br>
mov v8.h[7], v17.h[3]<br>
mov v9.b[10], v18.b[5]<br>
<br>
-; CHECK: ins.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]<br>
-; CHECK: ins.s v3[1], w6 ; encoding: [0xc3,0x1c,0x0c,0x4e]<br>
-; CHECK: ins.h v4[1], w7 ; encoding: [0xe4,0x1c,0x06,0x4e]<br>
-; CHECK: ins.b v5[1], w8 ; encoding: [0x05,0x1d,0x03,0x4e]<br>
-; CHECK: ins.d v9[1], x2 ; encoding: [0x49,0x1c,0x18,0x4e]<br>
-; CHECK: ins.s v8[1], w3 ; encoding: [0x68,0x1c,0x0c,0x4e]<br>
-; CHECK: ins.h v7[1], w4 ; encoding: [0x87,0x1c,0x06,0x4e]<br>
-; CHECK: ins.b v6[1], w5 ; encoding: [0xa6,0x1c,0x03,0x4e]<br>
-; CHECK: ins.d v1[1], v10[1] ; encoding: [0x41,0x45,0x18,0x6e]<br>
-; CHECK: ins.s v2[1], v11[1] ; encoding: [0x62,0x25,0x0c,0x6e]<br>
-; CHECK: ins.h v7[1], v12[1] ; encoding: [0x87,0x15,0x06,0x6e]<br>
-; CHECK: ins.b v8[1], v15[1] ; encoding: [0xe8,0x0d,0x03,0x6e]<br>
-; CHECK: ins.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]<br>
-; CHECK: ins.s v7[3], v16[2] ; encoding: [0x07,0x46,0x1c,0x6e]<br>
-; CHECK: ins.h v8[7], v17[3] ; encoding: [0x28,0x36,0x1e,0x6e]<br>
-; CHECK: ins.b v9[10], v18[5] ; encoding: [0x49,0x2e,0x15,0x6e]<br>
+; CHECK: mov.d v2[1], x5 ; encoding: [0xa2,0x1c,0x18,0x4e]<br>
+; CHECK: mov.s v3[1], w6 ; encoding: [0xc3,0x1c,0x0c,0x4e]<br>
+; CHECK: mov.h v4[1], w7 ; encoding: [0xe4,0x1c,0x06,0x4e]<br>
+; CHECK: mov.b v5[1], w8 ; encoding: [0x05,0x1d,0x03,0x4e]<br>
+; CHECK: mov.d v9[1], x2 ; encoding: [0x49,0x1c,0x18,0x4e]<br>
+; CHECK: mov.s v8[1], w3 ; encoding: [0x68,0x1c,0x0c,0x4e]<br>
+; CHECK: mov.h v7[1], w4 ; encoding: [0x87,0x1c,0x06,0x4e]<br>
+; CHECK: mov.b v6[1], w5 ; encoding: [0xa6,0x1c,0x03,0x4e]<br>
+; CHECK: mov.d v1[1], v10[1] ; encoding: [0x41,0x45,0x18,0x6e]<br>
+; CHECK: mov.s v2[1], v11[1] ; encoding: [0x62,0x25,0x0c,0x6e]<br>
+; CHECK: mov.h v7[1], v12[1] ; encoding: [0x87,0x15,0x06,0x6e]<br>
+; CHECK: mov.b v8[1], v15[1] ; encoding: [0xe8,0x0d,0x03,0x6e]<br>
+; CHECK: mov.d v2[1], v15[0] ; encoding: [0xe2,0x05,0x18,0x6e]<br>
+; CHECK: mov.s v7[3], v16[2] ; encoding: [0x07,0x46,0x1c,0x6e]<br>
+; CHECK: mov.h v8[7], v17[3] ; encoding: [0x28,0x36,0x1e,0x6e]<br>
+; CHECK: mov.b v9[10], v18[5] ; encoding: [0x49,0x2e,0x15,0x6e]<br>
<br>
<br>
and.8b v0, v0, v0<br>
<br>
Modified: llvm/trunk/test/MC/<wbr>Disassembler/AArch64/arm64-<wbr>advsimd.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/arm64-advsimd.txt?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/MC/<wbr>Disassembler/AArch64/arm64-<wbr>advsimd.txt?rev=294437&r1=<wbr>294436&r2=294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/<wbr>Disassembler/AArch64/arm64-<wbr>advsimd.txt (original)<br>
+++ llvm/trunk/test/MC/<wbr>Disassembler/AArch64/arm64-<wbr>advsimd.txt Wed Feb 8 05:28:08 2017<br>
@@ -139,15 +139,15 @@<br>
0xa2 0x1c 0x06 0x4e<br>
0xa2 0x1c 0x03 0x4e<br>
<br>
-# CHECK: ins.d v2[1], x5<br>
-# CHECK: ins.s v2[1], w5<br>
-# CHECK: ins.h v2[1], w5<br>
-# CHECK: ins.b v2[1], w5<br>
-<br>
-# CHECK: ins.d v2[1], x5<br>
-# CHECK: ins.s v2[1], w5<br>
-# CHECK: ins.h v2[1], w5<br>
-# CHECK: ins.b v2[1], w5<br>
+# CHECK: mov.d v2[1], x5<br>
+# CHECK: mov.s v2[1], w5<br>
+# CHECK: mov.h v2[1], w5<br>
+# CHECK: mov.b v2[1], w5<br>
+<br>
+# CHECK: mov.d v2[1], x5<br>
+# CHECK: mov.s v2[1], w5<br>
+# CHECK: mov.h v2[1], w5<br>
+# CHECK: mov.b v2[1], w5<br>
<br>
0xe2 0x45 0x18 0x6e<br>
0xe2 0x25 0x0c 0x6e<br>
@@ -159,15 +159,15 @@<br>
0xe2 0x35 0x1e 0x6e<br>
0xe2 0x2d 0x15 0x6e<br>
<br>
-# CHECK: ins.d v2[1], v15[1]<br>
-# CHECK: ins.s v2[1], v15[1]<br>
-# CHECK: ins.h v2[1], v15[1]<br>
-# CHECK: ins.b v2[1], v15[1]<br>
-<br>
-# CHECK: ins.d v2[1], v15[0]<br>
-# CHECK: ins.s v2[3], v15[2]<br>
-# CHECK: ins.h v2[7], v15[3]<br>
-# CHECK: ins.b v2[10], v15[5]<br>
+# CHECK: mov.d v2[1], v15[1]<br>
+# CHECK: mov.s v2[1], v15[1]<br>
+# CHECK: mov.h v2[1], v15[1]<br>
+# CHECK: mov.b v2[1], v15[1]<br>
+<br>
+# CHECK: mov.d v2[1], v15[0]<br>
+# CHECK: mov.s v2[3], v15[2]<br>
+# CHECK: mov.h v2[7], v15[3]<br>
+# CHECK: mov.b v2[10], v15[5]<br>
<br>
# INS/DUP (non-standard)<br>
0x60 0x0c 0x08 0x4e<br>
@@ -196,15 +196,15 @@<br>
0xe2 0x35 0x1e 0x6e<br>
0xe2 0x2d 0x15 0x6e<br>
<br>
-# CHECK: ins.d v2[1], v15[1]<br>
-# CHECK: ins.s v2[1], v15[1]<br>
-# CHECK: ins.h v2[1], v15[1]<br>
-# CHECK: ins.b v2[1], v15[1]<br>
-<br>
-# CHECK: ins.d v2[1], v15[0]<br>
-# CHECK: ins.s v2[3], v15[2]<br>
-# CHECK: ins.h v2[7], v15[3]<br>
-# CHECK: ins.b v2[10], v15[5]<br>
+# CHECK: mov.d v2[1], v15[1]<br>
+# CHECK: mov.s v2[1], v15[1]<br>
+# CHECK: mov.h v2[1], v15[1]<br>
+# CHECK: mov.b v2[1], v15[1]<br>
+<br>
+# CHECK: mov.d v2[1], v15[0]<br>
+# CHECK: mov.s v2[3], v15[2]<br>
+# CHECK: mov.h v2[7], v15[3]<br>
+# CHECK: mov.b v2[10], v15[5]<br>
<br>
0x00 0x1c 0x20 0x0e<br>
0x00 0x1c 0x20 0x4e<br>
<br>
Modified: llvm/trunk/utils/TableGen/<wbr>AsmWriterEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=294437&r1=294436&r2=294437&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/AsmWriterEmitter.cpp?<wbr>rev=294437&r1=294436&r2=<wbr>294437&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>AsmWriterEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>AsmWriterEmitter.cpp Wed Feb 8 05:28:08 2017<br>
@@ -820,8 +820,8 @@ void AsmWriterEmitter::<wbr>EmitPrintAliasIns<br>
}<br>
<br>
unsigned NumMIOps = 0;<br>
- for (auto &Operand : CGA.ResultOperands)<br>
- NumMIOps += Operand.getMINumOperands();<br>
+ for (auto &Operand : CGA.ResultInst->Operands.<wbr>OperandList)<br>
+ NumMIOps += Operand.MINumOperands;<br>
<br>
std::string Cond;<br>
Cond = std::string("MI-><wbr>getNumOperands() == ") + utostr(NumMIOps);<br>
@@ -831,6 +831,11 @@ void AsmWriterEmitter::<wbr>EmitPrintAliasIns<br>
<br>
unsigned MIOpNum = 0;<br>
for (unsigned i = 0, e = LastOpNo; i != e; ++i) {<br>
+ // Skip over tied operands as they're not part of an alias declaration.<br>
+ if (CGA.ResultInst->Operands[<wbr>MIOpNum].MINumOperands == 1 &&<br>
+ CGA.ResultInst->Operands[<wbr>MIOpNum].getTiedRegister() != -1)<br>
+ ++MIOpNum;<br>
+<br>
std::string Op = "MI->getOperand(" + utostr(MIOpNum) + ")";<br>
<br>
const CodeGenInstAlias::<wbr>ResultOperand &RO = CGA.ResultOperands[i];<br>
<br>
<br>
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</blockquote></div><br></div>