<div dir="ltr">Can we revert this until the errors are sorted out?</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Feb 7, 2017 at 12:24 AM, Krzysztof Parzyszek via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">I meant r294256.<br>
<br>
-K<br>
<br>
On 2/6/2017 5:23 PM, Krzysztof Parzyszek via llvm-commits wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Hopefully r294296 will take care of this.<br>
<br>
-Krzysztof<br>
<br>
On 2/6/2017 4:41 PM, Vitaly Buka wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
This patch introduced memory leaks and "left shift of negative value -1"<br>
<a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/2579" rel="noreferrer" target="_blank">http://lab.llvm.org:8011/build<wbr>ers/sanitizer-x86_64-linux-<wbr>fast/builds/2579</a><br>
<br>
On Mon, Feb 6, 2017 at 11:47 AM Krzysztof Parzyszek via llvm-commits<br>
<<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a> <mailto:<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llv<wbr>m.org</a>>> wrote:<br>
<br>
Author: kparzysz<br>
Date: Mon Feb 6 13:35:46 2017<br>
New Revision: 294226<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=294226&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=294226&view=rev</a><br>
Log:<br>
[Hexagon] Update MCTargetDesc<br>
<br>
Changes include:<br>
- Updates to the instruction descriptor flags.<br>
- Improvements to the packet shuffler and checker.<br>
- Updates to the handling of certain relocations.<br>
- Better handling of duplex instructions.<br>
<br>
Added:<br>
llvm/trunk/test/MC/Hexagon/com<wbr>mon-redeclare.s<br>
llvm/trunk/test/MC/Hexagon/dcf<wbr>etch-symbol.s<br>
llvm/trunk/test/MC/Hexagon/equ<wbr>.s<br>
llvm/trunk/test/MC/Hexagon/ext<wbr>ended_relocations.ll<br>
llvm/trunk/test/MC/Hexagon/mis<wbr>sing_label.s<br>
llvm/trunk/test/MC/Hexagon/non<wbr>-relocatable.s<br>
llvm/trunk/test/MC/Hexagon/not<wbr>-over.s<br>
llvm/trunk/test/MC/Hexagon/not<wbr>_found.s<br>
llvm/trunk/test/MC/Hexagon/off<wbr>set.s<br>
llvm/trunk/test/MC/Hexagon/ope<wbr>rand-range.s<br>
llvm/trunk/test/MC/Hexagon/reg<wbr>_altnames.s<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>Hexagon.td<br>
llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrFormats.td<br>
llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrFormatsV4.td<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonBaseInfo.h<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCAsmInfo.<wbr>cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCChecker.<wbr>cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCChecker.<wbr>h<br>
<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCCodeEmit<wbr>ter.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCCompound<wbr>.cpp<br>
<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCDuplexIn<wbr>fo.cpp<br>
<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCELFStrea<wbr>mer.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCELFStrea<wbr>mer.h<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCExpr.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCInstrInf<wbr>o.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCInstrInf<wbr>o.h<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCShuffler<wbr>.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCShuffler<wbr>.h<br>
<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCTargetDe<wbr>sc.cpp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCTargetDe<wbr>sc.h<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonShuffler.c<wbr>pp<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonShuffler.h<br>
llvm/trunk/test/MC/Hexagon/dis<wbr>-duplex-p0.s<br>
llvm/trunk/test/MC/Hexagon/rel<wbr>ocations.s<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>Hexagon.td<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.td?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/Hexagon.td?rev=294226&r1<wbr>=294225&r2=294226&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>Hexagon.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>Hexagon.td Mon Feb 6 13:35:46 2017<br>
@@ -27,9 +27,9 @@ def ArchV5: SubtargetFeature<"v5", "He<br>
def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55",<br>
"Hexagon V55">;<br>
def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60",<br>
"Hexagon V60">;<br>
<br>
-def FeatureHVX: SubtargetFeature<"hvx", "UseHVXOps", "true",<br>
+def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true",<br>
"Hexagon HVX instructions">;<br>
-def FeatureHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps",<br>
"true",<br>
+def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps",<br>
"true",<br>
"Hexagon HVX Double instructions">;<br>
def FeatureLongCalls: SubtargetFeature<"long-calls",<br>
"UseLongCalls", "true",<br>
"Use constant-extended calls">;<br>
@@ -46,10 +46,10 @@ def HasV60T : Predicate<"HST-<br>
def UseMEMOP : Predicate<"HST->useMemOps()">;<br>
def IEEERndNearV5T : Predicate<"HST->modeIEEERndNea<wbr>r()">;<br>
def UseHVXDbl : Predicate<"HST->useHVXDblOps()<wbr>">,<br>
- AssemblerPredicate<"FeatureHV<wbr>XDbl">;<br>
+ AssemblerPredicate<"Extension<wbr>HVXDbl">;<br>
def UseHVXSgl : Predicate<"HST->useHVXSglOps()<wbr>">;<br>
def UseHVX : Predicate<"HST->useHVXSglOps()<br>
||HST->useHVXDblOps()">,<br>
- AssemblerPredicate<"FeatureHV<wbr>X">;<br>
+ AssemblerPredicate<"Extension<wbr>HVX">;<br>
<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
// Classes used for relation maps.<br>
@@ -271,7 +271,7 @@ def : Proc<"hexagonv5", HexagonModelV4,<br>
def : Proc<"hexagonv55", HexagonModelV55,<br>
[ArchV4, ArchV5, ArchV55]>;<br>
def : Proc<"hexagonv60", HexagonModelV60,<br>
- [ArchV4, ArchV5, ArchV55, ArchV60, FeatureHVX]>;<br>
+ [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>;<br>
<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
// Declare the target which we are implementing<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrFormats.td<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/HexagonInstrFormats.td?<wbr>rev=294226&r1=294225&r2=294226<wbr>&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrFormats.td Mon Feb 6<br>
13:35:46 2017<br>
@@ -13,8 +13,8 @@<br>
// *** Must match HexagonBaseInfo.h ***<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
<br>
-class IType<bits<5> t> {<br>
- bits<5> Value = t;<br>
+class IType<bits<6> t> {<br>
+ bits<6> Value = t;<br>
}<br>
def TypePSEUDO : IType<0>;<br>
def TypeALU32 : IType<1>;<br>
@@ -99,85 +99,85 @@ class InstHexagon<dag outs, dag ins, str<br>
<br>
// Instruction type according to the ISA.<br>
IType Type = type;<br>
- let TSFlags{4-0} = Type.Value;<br>
+ let TSFlags{5-0} = Type.Value;<br>
<br>
// Solo instructions, i.e., those that cannot be in a packet with<br>
others.<br>
bits<1> isSolo = 0;<br>
- let TSFlags{5} = isSolo;<br>
+ let TSFlags{6} = isSolo;<br>
// Packed only with A or X-type instructions.<br>
bits<1> isSoloAX = 0;<br>
- let TSFlags{6} = isSoloAX;<br>
+ let TSFlags{7} = isSoloAX;<br>
// Only A-type instruction in first slot or nothing.<br>
bits<1> isSoloAin1 = 0;<br>
- let TSFlags{7} = isSoloAin1;<br>
+ let TSFlags{8} = isSoloAin1;<br>
<br>
// Predicated instructions.<br>
bits<1> isPredicated = 0;<br>
- let TSFlags{8} = isPredicated;<br>
+ let TSFlags{9} = isPredicated;<br>
bits<1> isPredicatedFalse = 0;<br>
- let TSFlags{9} = isPredicatedFalse;<br>
+ let TSFlags{10} = isPredicatedFalse;<br>
bits<1> isPredicatedNew = 0;<br>
- let TSFlags{10} = isPredicatedNew;<br>
+ let TSFlags{11} = isPredicatedNew;<br>
bits<1> isPredicateLate = 0;<br>
- let TSFlags{11} = isPredicateLate; // Late predicate producer<br>
insn.<br>
+ let TSFlags{12} = isPredicateLate; // Late predicate producer<br>
insn.<br>
<br>
// New-value insn helper fields.<br>
bits<1> isNewValue = 0;<br>
- let TSFlags{12} = isNewValue; // New-value consumer insn.<br>
+ let TSFlags{13} = isNewValue; // New-value consumer insn.<br>
bits<1> hasNewValue = 0;<br>
- let TSFlags{13} = hasNewValue; // New-value producer insn.<br>
+ let TSFlags{14} = hasNewValue; // New-value producer insn.<br>
bits<3> opNewValue = 0;<br>
- let TSFlags{16-14} = opNewValue; // New-value produced operand.<br>
+ let TSFlags{17-15} = opNewValue; // New-value produced operand.<br>
bits<1> isNVStorable = 0;<br>
- let TSFlags{17} = isNVStorable; // Store that can become<br>
new-value store.<br>
+ let TSFlags{18} = isNVStorable; // Store that can become<br>
new-value store.<br>
bits<1> isNVStore = 0;<br>
- let TSFlags{18} = isNVStore; // New-value store insn.<br>
+ let TSFlags{19} = isNVStore; // New-value store insn.<br>
bits<1> isCVLoadable = 0;<br>
- let TSFlags{19} = isCVLoadable; // Load that can become cur-value<br>
load.<br>
+ let TSFlags{20} = isCVLoadable; // Load that can become cur-value<br>
load.<br>
bits<1> isCVLoad = 0;<br>
- let TSFlags{20} = isCVLoad; // Cur-value load insn.<br>
+ let TSFlags{21} = isCVLoad; // Cur-value load insn.<br>
<br>
// Immediate extender helper fields.<br>
bits<1> isExtendable = 0;<br>
- let TSFlags{21} = isExtendable; // Insn may be extended.<br>
+ let TSFlags{22} = isExtendable; // Insn may be extended.<br>
bits<1> isExtended = 0;<br>
- let TSFlags{22} = isExtended; // Insn must be extended.<br>
+ let TSFlags{23} = isExtended; // Insn must be extended.<br>
bits<3> opExtendable = 0;<br>
- let TSFlags{25-23} = opExtendable; // Which operand may be<br>
extended.<br>
+ let TSFlags{26-24} = opExtendable; // Which operand may be<br>
extended.<br>
bits<1> isExtentSigned = 0;<br>
- let TSFlags{26} = isExtentSigned; // Signed or unsigned range.<br>
+ let TSFlags{27} = isExtentSigned; // Signed or unsigned range.<br>
bits<5> opExtentBits = 0;<br>
- let TSFlags{31-27} = opExtentBits; //Number of bits of range<br>
before extending.<br>
+ let TSFlags{32-28} = opExtentBits; //Number of bits of range<br>
before extending.<br>
bits<2> opExtentAlign = 0;<br>
- let TSFlags{33-32} = opExtentAlign; // Alignment exponent before<br>
extending.<br>
+ let TSFlags{34-33} = opExtentAlign; // Alignment exponent before<br>
extending.<br>
<br>
// If an instruction is valid on a subtarget, set the<br>
corresponding<br>
// bit from validSubTargets.<br>
// By default, instruction is valid on all subtargets.<br>
SubTarget validSubTargets = HasAnySubT;<br>
- let TSFlags{39-34} = validSubTargets.Value;<br>
+ let TSFlags{40-35} = validSubTargets.Value;<br>
<br>
// Addressing mode for load/store instructions.<br>
AddrModeType addrMode = NoAddrMode;<br>
- let TSFlags{42-40} = addrMode.Value;<br>
+ let TSFlags{43-41} = addrMode.Value;<br>
<br>
// Memory access size for mem access instructions (load/store)<br>
MemAccessSize accessSize = NoMemAccess;<br>
- let TSFlags{46-43} = accessSize.Value;<br>
+ let TSFlags{47-44} = accessSize.Value;<br>
<br>
bits<1> isTaken = 0;<br>
- let TSFlags {47} = isTaken; // Branch prediction.<br>
+ let TSFlags {48} = isTaken; // Branch prediction.<br>
<br>
bits<1> isFP = 0;<br>
- let TSFlags {48} = isFP; // Floating-point.<br>
+ let TSFlags {49} = isFP; // Floating-point.<br>
<br>
bits<1> hasNewValue2 = 0;<br>
- let TSFlags{50} = hasNewValue2; // Second New-value producer insn.<br>
+ let TSFlags{51} = hasNewValue2; // Second New-value producer insn.<br>
bits<3> opNewValue2 = 0;<br>
- let TSFlags{53-51} = opNewValue2; // Second New-value produced<br>
operand.<br>
+ let TSFlags{54-52} = opNewValue2; // Second New-value produced<br>
operand.<br>
<br>
bits<1> isAccumulator = 0;<br>
- let TSFlags{54} = isAccumulator;<br>
+ let TSFlags{55} = isAccumulator;<br>
<br>
bit cofMax1 = 0;<br>
let TSFlags{60} = cofMax1;<br>
@@ -200,6 +200,7 @@ class InstHexagon<dag outs, dag ins, str<br>
let NValueST = !if(isNVStore, "true", "false");<br>
let isNT = !if(isNonTemporal, "true", "false");<br>
<br>
+ let hasSideEffects = 0;<br>
// *** Must match MCTargetDesc/HexagonBaseInfo.h ***<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrFormatsV4.td<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/HexagonInstrFormatsV4.td<wbr>?rev=294226&r1=294225&r2=29422<wbr>6&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrFormatsV4.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>HexagonInstrFormatsV4.td Mon Feb<br>
6 13:35:46 2017<br>
@@ -18,7 +18,7 @@<br>
<br>
//----------------------------<wbr>------------------------------<wbr>------------------//<br>
<br>
<br>
def TypeV4LDST : IType<9>;<br>
-def TypeNV : IType<10>;<br>
+def TypeNCJ : IType<10>;<br>
def TypeDUPLEX : IType<11>;<br>
def TypeCJ : IType<12>;<br>
def TypeEXTENDER : IType<30>;<br>
@@ -61,7 +61,7 @@ class InstDuplex<bits<4> iClass, list<da<br>
<br>
// *** Must match MCTargetDesc/HexagonBaseInfo.h ***<br>
<br>
- let TSFlags{4-0} = Type.Value;<br>
+ let TSFlags{5-0} = Type.Value;<br>
<br>
// Predicated instructions.<br>
bits<1> isPredicated = 0;<br>
@@ -107,7 +107,7 @@ class InstDuplex<bits<4> iClass, list<da<br>
//<br>
class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern<br>
= [],<br>
string cstr = "", InstrItinClass itin =<br>
NCJ_tc_3or4stall_SLOT0><br>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>,<br>
OpcodeHexagon;<br>
+ : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNCJ>,<br>
OpcodeHexagon;<br>
<br>
class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern<br>
= [],<br>
string cstr = "", InstrItinClass itin =<br>
NCJ_tc_3or4stall_SLOT0><br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonAsmB<wbr>ackend.cpp?rev=294226&r1=<wbr>294225&r2=294226&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp<br>
(original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonAsmBackend<wbr>.cpp<br>
Mon Feb 6 13:35:46 2017<br>
@@ -9,10 +9,10 @@<br>
<br>
#include "Hexagon.h"<br>
#include "HexagonFixupKinds.h"<br>
-#include "HexagonMCTargetDesc.h"<br>
#include "MCTargetDesc/HexagonBaseInfo.<wbr>h"<br>
#include "MCTargetDesc/HexagonMCChecker<wbr>.h"<br>
#include "MCTargetDesc/HexagonMCCodeEmi<wbr>tter.h"<br>
+#include "MCTargetDesc/HexagonMCTargetD<wbr>esc.h"<br>
#include "MCTargetDesc/HexagonMCInstrIn<wbr>fo.h"<br>
#include "MCTargetDesc/HexagonMCShuffle<wbr>r.h"<br>
#include "llvm/MC/MCAsmBackend.h"<br>
@@ -59,9 +59,10 @@ class HexagonAsmBackend : public MCAsmBa<br>
RF.getFixups() = Fixups;<br>
}<br>
public:<br>
- HexagonAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) :<br>
- OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new<br>
MCInst *),<br>
- Extender(nullptr) {}<br>
+ HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t<br>
OSABI,<br>
+ StringRef CPU) :<br>
+ OSABI(OSABI), CPU(CPU), MCII(T.createMCInstrInfo()),<br>
+ RelaxTarget(new MCInst *), Extender(nullptr) {}<br>
<br>
MCObjectWriter *createObjectWriter(raw_pwrite<wbr>_stream &OS) const<br>
override {<br>
return createHexagonELFObjectWriter(O<wbr>S, OSABI, CPU);<br>
@@ -88,101 +89,101 @@ public:<br>
// This table *must* be in same the order of fixup_* kinds in<br>
// HexagonFixupKinds.h.<br>
//<br>
- // namei offset bits flags<br>
- { "fixup_Hexagon_B22_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_B15_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_B7_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_LO16", 0, 32, 0 },<br>
- { "fixup_Hexagon_HI16", 0, 32, 0 },<br>
- { "fixup_Hexagon_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_16", 0, 32, 0 },<br>
- { "fixup_Hexagon_8", 0, 32, 0 },<br>
- { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },<br>
- { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },<br>
- { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },<br>
- { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },<br>
- { "fixup_Hexagon_HL16", 0, 32, 0 },<br>
- { "fixup_Hexagon_B13_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_B9_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_B32_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_32_6_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_B22_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_B15_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_B13_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_B9_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_B7_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_16_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_12_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_11_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_10_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_9_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_8_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_7_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_6_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_32_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_COPY", 0, 32, 0 },<br>
- { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },<br>
- { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },<br>
- { "fixup_Hexagon_RELATIVE", 0, 32, 0 },<br>
- { "fixup_Hexagon_PLT_B22_PCREL",<wbr> 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOT_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOT_16", 0, 32, 0 },<br>
- { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },<br>
- { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },<br>
- { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },<br>
- { "fixup_Hexagon_GD_PLT_B22_PCRE<wbr>L", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_LD_PLT_B22_PCRE<wbr>L", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },<br>
- { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },<br>
- { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },<br>
- { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },<br>
- { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },<br>
- { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_LO16", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_HI16", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_16", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },<br>
- { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },<br>
- { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },<br>
- { "fixup_Hexagon_TPREL_32", 0, 32, 0 },<br>
- { "fixup_Hexagon_TPREL_16", 0, 32, 0 },<br>
- { "fixup_Hexagon_6_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
- { "fixup_Hexagon_GOTREL_32_6_X",<wbr> 0, 32, 0 },<br>
- { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_DTPREL_32_6_X",<wbr> 0, 32, 0 },<br>
- { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_GD_GOT_32_6_X",<wbr> 0, 32, 0 },<br>
- { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_LD_GOT_32_6_X",<wbr> 0, 32, 0 },<br>
- { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_16_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_GOT_32_6_X",<wbr> 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },<br>
- { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 }<br>
+ // namei offset bits flags<br>
+ { "fixup_Hexagon_B22_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_B15_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_B7_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_LO16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_HI16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_8", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },<br>
+ { "fixup_Hexagon_HL16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_B13_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_B9_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_B32_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_32_6_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_B22_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_B15_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_B13_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_B9_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_B7_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_16_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_12_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_11_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_10_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_9_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_8_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_7_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_6_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_32_PCREL", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_COPY", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },<br>
+ { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },<br>
+ { "fixup_Hexagon_RELATIVE", 0, 32, 0 },<br>
+ { "fixup_Hexagon_PLT_B22_PCREL",<wbr> 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOT_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOT_16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GD_PLT_B22_PCRE<wbr>L",0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_LD_PLT_B22_PCRE<wbr>L",0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_LO16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_HI16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_TPREL_32", 0, 32, 0 },<br>
+ { "fixup_Hexagon_TPREL_16", 0, 32, 0 },<br>
+ { "fixup_Hexagon_6_PCREL_X", 0, 32,<br>
MCFixupKindInfo::FKF_IsPCRel },<br>
+ { "fixup_Hexagon_GOTREL_32_6_X",<wbr> 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_DTPREL_32_6_X",<wbr> 0, 32, 0 },<br>
+ { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GD_GOT_32_6_X",<wbr> 0, 32, 0 },<br>
+ { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_LD_GOT_32_6_X",<wbr> 0, 32, 0 },<br>
+ { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_16_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_GOT_32_6_X",<wbr> 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },<br>
+ { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 }<br>
};<br>
<br>
if (Kind < FirstTargetFixupKind)<br>
@@ -526,7 +527,7 @@ public:<br>
if (llvm::HexagonMCInstrInfo::get<wbr>Type(*MCII, HMI) ==<br>
HexagonII::TypeJ ||<br>
(llvm::HexagonMCInstrInfo::ge<wbr>tType(*MCII, HMI) ==<br>
HexagonII::TypeCJ &&<br>
MCID.isBranch()) ||<br>
- (llvm::HexagonMCInstrInfo::get<wbr>Type(*MCII, HMI) ==<br>
HexagonII::TypeNV &&<br>
+ (llvm::HexagonMCInstrInfo::get<wbr>Type(*MCII, HMI) ==<br>
HexagonII::TypeNCJ &&<br>
MCID.isBranch()) ||<br>
(llvm::HexagonMCInstrInfo::ge<wbr>tType(*MCII, HMI) ==<br>
HexagonII::TypeCR &&<br>
HMI.getOpcode() != Hexagon::C4_addipc))<br>
@@ -723,7 +724,8 @@ public:<br>
Size = 0;<br>
}<br>
}<br>
- bool Error = HexagonMCShuffle(*MCII,<br>
RF.getSubtargetInfo(), Inst);<br>
+ bool Error = HexagonMCShuffle(true, *MCII,<br>
RF.getSubtargetInfo(),<br>
+ Inst);<br>
//assert(!Error);<br>
(void)Error;<br>
ReplaceInstruction(Asm.getEmi<wbr>tter(), RF, Inst);<br>
@@ -738,15 +740,17 @@ public:<br>
}<br>
}<br>
}<br>
-};<br>
-} // end anonymous namespace<br>
+}; // class HexagonAsmBackend<br>
<br>
-namespace llvm {<br>
-MCAsmBackend *createHexagonAsmBackend(Targe<wbr>t const &T,<br>
+} // namespace<br>
+<br>
+// MCAsmBackend<br>
+MCAsmBackend *llvm::createHexagonAsmBackend<wbr>(Target const &T,<br>
MCRegisterInfo const &<br>
/*MRI*/,<br>
const Triple &TT, StringRef<br>
CPU,<br>
const MCTargetOptions<br>
&Options) {<br>
uint8_t OSABI = MCELFObjectTargetWriter::getOS<wbr>ABI(TT.getOS());<br>
- return new HexagonAsmBackend(T, OSABI, CPU);<br>
-}<br>
+<br>
+ StringRef CPUString = Hexagon_MC::selectHexagonCPU(T<wbr>T, CPU);<br>
+ return new HexagonAsmBackend(T, TT, OSABI, CPUString);<br>
}<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonBaseInfo.h<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonBase<wbr>Info.h?rev=294226&r1=294225&<wbr>r2=294226&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonBaseInfo.h<br>
(original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonBaseInfo.h Mon<br>
Feb 6 13:35:46 2017<br>
@@ -42,7 +42,7 @@ namespace HexagonII {<br>
TypeSYSTEM = 7,<br>
TypeXTYPE = 8,<br>
TypeV4LDST = 9,<br>
- TypeNV = 10,<br>
+ TypeNCJ = 10,<br>
TypeDUPLEX = 11,<br>
TypeCJ = 12,<br>
TypeCVI_FIRST = 13,<br>
@@ -68,16 +68,10 @@ namespace HexagonII {<br>
};<br>
<br>
enum SubTarget {<br>
- HasV2SubT = 0xf,<br>
- HasV2SubTOnly = 0x1,<br>
- NoV2SubT = 0x0,<br>
- HasV3SubT = 0xe,<br>
- HasV3SubTOnly = 0x2,<br>
- NoV3SubT = 0x1,<br>
- HasV4SubT = 0xc,<br>
- NoV4SubT = 0x3,<br>
- HasV5SubT = 0x8,<br>
- NoV5SubT = 0x7<br>
+ HasV4SubT = 0x3f,<br>
+ HasV5SubT = 0x3e,<br>
+ HasV55SubT = 0x3c,<br>
+ HasV60SubT = 0x38,<br>
};<br>
<br>
enum AddrMode {<br>
@@ -107,102 +101,101 @@ namespace HexagonII {<br>
enum {<br>
// This 5-bit field describes the insn type.<br>
TypePos = 0,<br>
- TypeMask = 0x1f,<br>
+ TypeMask = 0x3f,<br>
<br>
// Solo instructions.<br>
- SoloPos = 5,<br>
+ SoloPos = 6,<br>
SoloMask = 0x1,<br>
// Packed only with A or X-type instructions.<br>
- SoloAXPos = 6,<br>
+ SoloAXPos = 7,<br>
SoloAXMask = 0x1,<br>
// Only A-type instruction in first slot or nothing.<br>
- SoloAin1Pos = 7,<br>
+ SoloAin1Pos = 8,<br>
SoloAin1Mask = 0x1,<br>
<br>
// Predicated instructions.<br>
- PredicatedPos = 8,<br>
+ PredicatedPos = 9,<br>
PredicatedMask = 0x1,<br>
- PredicatedFalsePos = 9,<br>
+ PredicatedFalsePos = 10,<br>
PredicatedFalseMask = 0x1,<br>
- PredicatedNewPos = 10,<br>
+ PredicatedNewPos = 11,<br>
PredicatedNewMask = 0x1,<br>
- PredicateLatePos = 11,<br>
+ PredicateLatePos = 12,<br>
PredicateLateMask = 0x1,<br>
<br>
// New-Value consumer instructions.<br>
- NewValuePos = 12,<br>
+ NewValuePos = 13,<br>
NewValueMask = 0x1,<br>
// New-Value producer instructions.<br>
- hasNewValuePos = 13,<br>
+ hasNewValuePos = 14,<br>
hasNewValueMask = 0x1,<br>
// Which operand consumes or produces a new value.<br>
- NewValueOpPos = 14,<br>
+ NewValueOpPos = 15,<br>
NewValueOpMask = 0x7,<br>
// Stores that can become new-value stores.<br>
- mayNVStorePos = 17,<br>
+ mayNVStorePos = 18,<br>
mayNVStoreMask = 0x1,<br>
// New-value store instructions.<br>
- NVStorePos = 18,<br>
+ NVStorePos = 19,<br>
NVStoreMask = 0x1,<br>
// Loads that can become current-value loads.<br>
- mayCVLoadPos = 19,<br>
+ mayCVLoadPos = 20,<br>
mayCVLoadMask = 0x1,<br>
// Current-value load instructions.<br>
- CVLoadPos = 20,<br>
+ CVLoadPos = 21,<br>
CVLoadMask = 0x1,<br>
<br>
// Extendable insns.<br>
- ExtendablePos = 21,<br>
+ ExtendablePos = 22,<br>
ExtendableMask = 0x1,<br>
// Insns must be extended.<br>
- ExtendedPos = 22,<br>
+ ExtendedPos = 23,<br>
ExtendedMask = 0x1,<br>
// Which operand may be extended.<br>
- ExtendableOpPos = 23,<br>
+ ExtendableOpPos = 24,<br>
ExtendableOpMask = 0x7,<br>
// Signed or unsigned range.<br>
- ExtentSignedPos = 26,<br>
+ ExtentSignedPos = 27,<br>
ExtentSignedMask = 0x1,<br>
// Number of bits of range before extending operand.<br>
- ExtentBitsPos = 27,<br>
+ ExtentBitsPos = 28,<br>
ExtentBitsMask = 0x1f,<br>
// Alignment power-of-two before extending operand.<br>
- ExtentAlignPos = 32,<br>
+ ExtentAlignPos = 33,<br>
ExtentAlignMask = 0x3,<br>
<br>
// Valid subtargets<br>
- validSubTargetPos = 34,<br>
- validSubTargetMask = 0xf,<br>
+ validSubTargetPos = 35,<br>
+ validSubTargetMask = 0x3f,<br>
<br>
// Addressing mode for load/store instructions.<br>
- AddrModePos = 40,<br>
+ AddrModePos = 41,<br>
AddrModeMask = 0x7,<br>
// Access size for load/store instructions.<br>
- MemAccessSizePos = 43,<br>
+ MemAccessSizePos = 44,<br>
MemAccesSizeMask = 0xf,<br>
<br>
// Branch predicted taken.<br>
- TakenPos = 47,<br>
+ TakenPos = 48,<br>
TakenMask = 0x1,<br>
<br>
// Floating-point instructions.<br>
- FPPos = 48,<br>
+ FPPos = 49,<br>
FPMask = 0x1,<br>
<br>
// New-Value producer-2 instructions.<br>
- hasNewValuePos2 = 50,<br>
+ hasNewValuePos2 = 51,<br>
hasNewValueMask2 = 0x1,<br>
-<br>
// Which operand consumes or produces a new value.<br>
- NewValueOpPos2 = 51,<br>
+ NewValueOpPos2 = 52,<br>
NewValueOpMask2 = 0x7,<br>
<br>
// Accumulator instructions.<br>
- AccumulatorPos = 54,<br>
+ AccumulatorPos = 55,<br>
AccumulatorMask = 0x1,<br>
<br>
// Complex XU, prevent xu competition by preferring slot3<br>
- PrefersSlot3Pos = 55,<br>
+ PrefersSlot3Pos = 56,<br>
PrefersSlot3Mask = 0x1,<br>
<br>
CofMax1Pos = 60,<br>
@@ -217,8 +210,6 @@ namespace HexagonII {<br>
// Hexagon Specific MachineOperand flags.<br>
MO_NO_FLAG,<br>
<br>
- HMOTF_ConstExtended = 1,<br>
-<br>
/// MO_PCREL - On a symbol operand, indicates a PC-relative<br>
relocation<br>
/// Used for computing a global address for PIC compilations<br>
MO_PCREL,<br>
@@ -250,7 +241,13 @@ namespace HexagonII {<br>
<br>
// MO_TPREL - indicates relocation for TLS<br>
// local Executable method<br>
- MO_TPREL<br>
+ MO_TPREL,<br>
+<br>
+ // HMOTF_ConstExtended<br>
+ // Addendum to abovem, indicates a const extended op<br>
+ // Can be used as a mask.<br>
+ HMOTF_ConstExtended = 0x80<br>
+<br>
};<br>
<br>
// Hexagon Sub-instruction classes.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCAsmInfo.<wbr>cpp<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonMCAs<wbr>mInfo.cpp?rev=294226&r1=<wbr>294225&r2=294226&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCAsmInfo.<wbr>cpp<br>
(original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCAsmInfo.<wbr>cpp<br>
Mon Feb 6 13:35:46 2017<br>
@@ -23,6 +23,7 @@ HexagonMCAsmInfo::HexagonMCAsm<wbr>Info(const<br>
Data32bitsDirective = "\t.word\t";<br>
Data64bitsDirective = nullptr; // .xword is only supported by V9.<br>
CommentString = "//";<br>
+ SupportsDebugInformation = true;<br>
<br>
LCOMMDirectiveAlignmentType = LCOMM::ByteAlignment;<br>
InlineAsmStart = "# InlineAsm Start";<br>
@@ -30,8 +31,8 @@ HexagonMCAsmInfo::HexagonMCAsm<wbr>Info(const<br>
ZeroDirective = "\t.space\t";<br>
AscizDirective = "\t.string\t";<br>
<br>
- SupportsDebugInformation = true;<br>
MinInstAlignment = 4;<br>
<wbr>UsesELFSectionDirectiveForBSS = true;<br>
ExceptionsType = ExceptionHandling::DwarfCFI;<br>
+ UseLogicalShr = false;<br>
}<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCChecker.<wbr>cpp<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonMCCh<wbr>ecker.cpp?rev=294226&r1=<wbr>294225&r2=294226&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCChecker.<wbr>cpp<br>
(original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCChecker.<wbr>cpp<br>
Mon Feb 6 13:35:46 2017<br>
@@ -47,12 +47,40 @@ void HexagonMCChecker::init() {<br>
if (HexagonMCInstrInfo::isBundle(<wbr>MCB))<br>
// Unfurl a bundle.<br>
for (auto const&I :<br>
HexagonMCInstrInfo::bundleInst<wbr>ructions(MCB)) {<br>
- init(*I.getInst());<br>
+ MCInst const &Inst = *I.getInst();<br>
+ if (HexagonMCInstrInfo::isDuplex(<wbr>MCII, Inst)) {<br>
+ init(*Inst.getOperand(0).getIn<wbr>st());<br>
+ init(*Inst.getOperand(1).getIn<wbr>st());<br>
+ }<br>
+ else<br>
+ init(Inst);<br>
}<br>
else<br>
init(MCB);<br>
}<br>
<br>
+void HexagonMCChecker::initReg(MCIn<wbr>st const &MCI, unsigned R,<br>
unsigned &PredReg,<br>
+ bool &isTrue) {<br>
+ if (HexagonMCInstrInfo::isPredica<wbr>ted(MCII, MCI) &&<br>
isPredicateRegister(R)) {<br>
+ // Note an used predicate register.<br>
+ PredReg = R;<br>
+ isTrue = HexagonMCInstrInfo::isPredicat<wbr>edTrue(MCII, MCI);<br>
+<br>
+ // Note use of new predicate register.<br>
+ if (HexagonMCInstrInfo::isPredica<wbr>tedNew(MCII, MCI))<br>
+ NewPreds.insert(PredReg);<br>
+ }<br>
+ else<br>
+ // Note register use. Super-registers are not tracked directly,<br>
+ // but their components.<br>
+ for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R,<br>
&RI).isValid());<br>
+ SRI.isValid();<br>
+ ++SRI)<br>
+ if (!MCSubRegIterator(*SRI, &RI).isValid())<br>
+ // Skip super-registers used indirectly.<br>
+ Uses.insert(*SRI);<br>
+}<br>
+<br>
void HexagonMCChecker::init(MCInst const& MCI) {<br>
const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MC<wbr>II, MCI);<br>
unsigned PredReg = Hexagon::NoRegister;<br>
@@ -60,28 +88,10 @@ void HexagonMCChecker::init(MCInst const<br>
<br>
// Get used registers.<br>
for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands();<br>
++i)<br>
- if (MCI.getOperand(i).isReg()) {<br>
- unsigned R = MCI.getOperand(i).getReg();<br>
-<br>
- if (HexagonMCInstrInfo::isPredica<wbr>ted(MCII, MCI) &&<br>
isPredicateRegister(R)) {<br>
- // Note an used predicate register.<br>
- PredReg = R;<br>
- isTrue = HexagonMCInstrInfo::isPredicat<wbr>edTrue(MCII, MCI);<br>
-<br>
- // Note use of new predicate register.<br>
- if (HexagonMCInstrInfo::isPredica<wbr>tedNew(MCII, MCI))<br>
- NewPreds.insert(PredReg);<br>
- }<br>
- else<br>
- // Note register use. Super-registers are not tracked<br>
directly,<br>
- // but their components.<br>
- for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R,<br>
&RI).isValid());<br>
- SRI.isValid();<br>
- ++SRI)<br>
- if (!MCSubRegIterator(*SRI, &RI).isValid())<br>
- // Skip super-registers used indirectly.<br>
- Uses.insert(*SRI);<br>
- }<br>
+ if (MCI.getOperand(i).isReg())<br>
+ initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue);<br>
+ for (unsigned i = 0; i < MCID.getNumImplicitUses(); ++i)<br>
+ initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue);<br>
<br>
// Get implicit register definitions.<br>
if (const MCPhysReg *ImpDef = MCID.getImplicitDefs())<br>
@@ -216,9 +226,11 @@ void HexagonMCChecker::init(MCInst const<br>
if (!MCSubRegIterator(N, &RI).isValid()) {<br>
// Super-registers cannot use new values.<br>
if (MCID.isBranch())<br>
- NewUses[N] =<br>
NewSense::Jmp(llvm::HexagonMCI<wbr>nstrInfo::getType(MCII, MCI) ==<br>
HexagonII::TypeNV);<br>
+ NewUses[N] = NewSense::Jmp(<br>
+ llvm::HexagonMCInstrInfo::getT<wbr>ype(MCII, MCI) ==<br>
HexagonII::TypeNCJ);<br>
else<br>
- NewUses[N] = NewSense::Use(PredReg,<br>
HexagonMCInstrInfo::isPredicat<wbr>edTrue(MCII, MCI));<br>
+ NewUses[N] = NewSense::Use(<br>
+ PredReg, HexagonMCInstrInfo::isPredicat<wbr>edTrue(MCII, MCI));<br>
}<br>
}<br>
}<br>
@@ -230,14 +242,18 @@ HexagonMCChecker::HexagonMCChe<wbr>cker(MCIns<br>
init();<br>
}<br>
<br>
-bool HexagonMCChecker::check() {<br>
+bool HexagonMCChecker::check(bool FullCheck) {<br>
bool chkB = checkBranches();<br>
bool chkP = checkPredicates();<br>
bool chkNV = checkNewValues();<br>
bool chkR = checkRegisters();<br>
bool chkS = checkSolo();<br>
- bool chkSh = checkShuffle();<br>
- bool chkSl = checkSlots();<br>
+ bool chkSh = true;<br>
+ if (FullCheck)<br>
+ chkSh = checkShuffle();<br>
+ bool chkSl = true;<br>
+ if (FullCheck)<br>
+ chkSl = checkSlots();<br>
bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh &&<br>
chkSl;<br>
<br>
return chk;<br>
@@ -504,7 +520,7 @@ bool HexagonMCChecker::checkShuffle<wbr>() {<br>
HexagonMCErrInfo errInfo;<br>
// Branch info is lost when duplexing. The unduplexed insns<br>
must be<br>
// checked and only branch errors matter for this case.<br>
- HexagonMCShuffler MCS(MCII, STI, MCB);<br>
+ HexagonMCShuffler MCS(true, MCII, STI, MCB);<br>
if (!MCS.check()) {<br>
if (MCS.getError() == HexagonShuffler::SHUFFLE_ERROR<wbr>_BRANCHES) {<br>
errInfo.setError(HexagonMCErr<wbr>Info::CHECK_ERROR_SHUFFLE);<br>
@@ -513,7 +529,7 @@ bool HexagonMCChecker::checkShuffle<wbr>() {<br>
return false;<br>
}<br>
}<br>
- HexagonMCShuffler MCSDX(MCII, STI, MCBDX);<br>
+ HexagonMCShuffler MCSDX(true, MCII, STI, MCBDX);<br>
if (!MCSDX.check()) {<br>
errInfo.setError(HexagonMCErr<wbr>Info::CHECK_ERROR_SHUFFLE);<br>
errInfo.setShuffleError(<wbr>MCSDX.getError());<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCChecker.<wbr>h<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonMCCh<wbr>ecker.h?rev=294226&r1=294225&<wbr>r2=294226&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCChecker.<wbr>h<br>
(original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCChecker.<wbr>h<br>
Mon Feb 6 13:35:46 2017<br>
@@ -168,6 +168,7 @@ class HexagonMCChecker {<br>
<br>
void init();<br>
void init(MCInst const&);<br>
+ void initReg(MCInst const &, unsigned, unsigned &PredReg, bool<br>
&isTrue);<br>
<br>
// Checks performed.<br>
bool checkBranches();<br>
@@ -177,6 +178,7 @@ class HexagonMCChecker {<br>
bool checkSolo();<br>
bool checkShuffle();<br>
bool checkSlots();<br>
+ bool checkSize();<br>
<br>
static void compoundRegisterMap(unsigned&)<wbr>;<br>
<br>
@@ -196,7 +198,7 @@ class HexagonMCChecker {<br>
explicit HexagonMCChecker(MCInstrInfo const &MCII,<br>
MCSubtargetInfo const &STI, MCInst& mcb, MCInst &mcbdx,<br>
const MCRegisterInfo& ri);<br>
<br>
- bool check();<br>
+ bool check(bool FullCheck = true);<br>
<br>
/// add a new error/warning<br>
void addErrInfo(HexagonMCErrInfo &err) { ErrInfoQ.push(err.s); };<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCCodeEmit<wbr>ter.cpp<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonMCCo<wbr>deEmitter.cpp?rev=294226&r1=<wbr>294225&r2=294226&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
---<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCCodeEmit<wbr>ter.cpp<br>
(original)<br>
+++<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCCodeEmit<wbr>ter.cpp<br>
Mon Feb 6 13:35:46 2017<br>
@@ -65,9 +65,10 @@ uint32_t HexagonMCCodeEmitter::parseBit<wbr>s<br>
return HexagonII::INST_PARSE_NOT_END;<br>
}<br>
<br>
-void HexagonMCCodeEmitter::encodeIn<wbr>struction(MCInst const &MI,<br>
raw_ostream &OS,<br>
+/// EncodeInstruction - Emit the bundle<br>
+void HexagonMCCodeEmitter::encodeIn<wbr>struction(const MCInst &MI,<br>
raw_ostream &OS,<br>
<br>
SmallVectorImpl<MCFixup> &Fixups,<br>
- MCSubtargetInfo const<br>
&STI) const {<br>
+ const MCSubtargetInfo<br>
&STI) const {<br>
MCInst &HMB = const_cast<MCInst &>(MI);<br>
<br>
assert(HexagonMCInstrInfo::is<wbr>Bundle(HMB));<br>
@@ -137,60 +138,7 @@ void HexagonMCCodeEmitter::EncodeSi<wbr>ngleI<br>
MI.getOpcode() <= Hexagon::DuplexIClassF) {<br>
assert(Parse == HexagonII::INST_PARSE_DUPLEX &&<br>
"Emitting duplex without duplex parse bits");<br>
- unsigned dupIClass;<br>
- switch (MI.getOpcode()) {<br>
- case Hexagon::DuplexIClass0:<br>
- dupIClass = 0;<br>
- break;<br>
- case Hexagon::DuplexIClass1:<br>
- dupIClass = 1;<br>
- break;<br>
- case Hexagon::DuplexIClass2:<br>
- dupIClass = 2;<br>
- break;<br>
- case Hexagon::DuplexIClass3:<br>
- dupIClass = 3;<br>
- break;<br>
- case Hexagon::DuplexIClass4:<br>
- dupIClass = 4;<br>
- break;<br>
- case Hexagon::DuplexIClass5:<br>
- dupIClass = 5;<br>
- break;<br>
- case Hexagon::DuplexIClass6:<br>
- dupIClass = 6;<br>
- break;<br>
- case Hexagon::DuplexIClass7:<br>
- dupIClass = 7;<br>
- break;<br>
- case Hexagon::DuplexIClass8:<br>
- dupIClass = 8;<br>
- break;<br>
- case Hexagon::DuplexIClass9:<br>
- dupIClass = 9;<br>
- break;<br>
- case Hexagon::DuplexIClassA:<br>
- dupIClass = 10;<br>
- break;<br>
- case Hexagon::DuplexIClassB:<br>
- dupIClass = 11;<br>
- break;<br>
- case Hexagon::DuplexIClassC:<br>
- dupIClass = 12;<br>
- break;<br>
- case Hexagon::DuplexIClassD:<br>
- dupIClass = 13;<br>
- break;<br>
- case Hexagon::DuplexIClassE:<br>
- dupIClass = 14;<br>
- break;<br>
- case Hexagon::DuplexIClassF:<br>
- dupIClass = 15;<br>
- break;<br>
- default:<br>
- llvm_unreachable("Unimplemente<wbr>d DuplexIClass");<br>
- break;<br>
- }<br>
+ unsigned dupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;<br>
// 29 is the bit position.<br>
// 0b1110 =0xE bits are masked off and down shifted by 1 bit.<br>
// Last bit is moved to bit position 13<br>
@@ -390,7 +338,8 @@ unsigned HexagonMCCodeEmitter::getExprO<wbr>p<br>
int64_t Value;<br>
if (ME->evaluateAsAbsolute(Value)<wbr>)<br>
return Value;<br>
- assert(ME->getKind() == MCExpr::SymbolRef || ME->getKind() ==<br>
MCExpr::Binary);<br>
+ assert(ME->getKind() == MCExpr::SymbolRef ||<br>
+ ME->getKind() == MCExpr::Binary);<br>
if (ME->getKind() == MCExpr::Binary) {<br>
MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);<br>
getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);<br>
@@ -523,7 +472,7 @@ unsigned HexagonMCCodeEmitter::getExprO<wbr>p<br>
else<br>
if (MCID.mayStore() || MCID.mayLoad()) {<br>
for (const MCPhysReg *ImpUses = MCID.getImplicitUses();<br>
*ImpUses;<br>
- ++ImpUses) {<br>
+ ++ImpUses) {<br>
if (*ImpUses != Hexagon::GP)<br>
continue;<br>
switch (HexagonMCInstrInfo::getAccess<wbr>Size(MCII, MI)) {<br>
@@ -543,8 +492,7 @@ unsigned HexagonMCCodeEmitter::getExprO<wbr>p<br>
raise_relocation_error(bits, kind);<br>
}<br>
}<br>
- }<br>
- else<br>
+ } else<br>
raise_relocation_error(bits, kind);<br>
break;<br>
}<br>
@@ -759,6 +707,13 @@ unsigned<br>
HexagonMCCodeEmitter::getMach<wbr>ineOpValue(MCInst const &MI, MCOperand<br>
const &MO,<br>
SmallVectorImpl<MCFixup><br>
&Fixups,<br>
MCSubtargetInfo const &STI)<br>
const {<br>
+ size_t OperandNumber = ~0U;<br>
+ for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)<br>
+ if (&MI.getOperand(i) == &MO) {<br>
+ OperandNumber = i;<br>
+ break;<br>
+ }<br>
+ assert((OperandNumber != ~0U) && "Operand not found");<br>
<br>
if (HexagonMCInstrInfo::isNewValu<wbr>e(MCII, MI) &&<br>
&MO == &MI.getOperand(HexagonMCInstrI<wbr>nfo::getNewValueOp(MCII,<br>
MI))) {<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCCompound<wbr>.cpp<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonMCCo<wbr>mpound.cpp?rev=294226&r1=<wbr>294225&r2=294226&view=diff</a><br>
<br>
<br>
==============================<wbr>==============================<wbr>==================<br>
<br>
--- llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCCompound<wbr>.cpp<br>
(original)<br>
+++ llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCCompound<wbr>.cpp<br>
Mon Feb 6 13:35:46 2017<br>
@@ -14,6 +14,7 @@<br>
#include "Hexagon.h"<br>
#include "MCTargetDesc/HexagonBaseInfo.<wbr>h"<br>
#include "MCTargetDesc/HexagonMCInstrIn<wbr>fo.h"<br>
+#include "MCTargetDesc/HexagonMCShuffle<wbr>r.h"<br>
#include "llvm/MC/MCContext.h"<br>
#include "llvm/MC/MCInst.h"<br>
#include "llvm/Support/Debug.h"<br>
@@ -396,7 +397,7 @@ static bool lookForCompound(MCInstrInfo<br>
/// is found update the contents fo the bundle with the compound<br>
insn.<br>
/// If a compound instruction is found then the bundle will have one<br>
/// additional slot.<br>
-void HexagonMCInstrInfo::tryCompoun<wbr>d(MCInstrInfo const &MCII,<br>
+void HexagonMCInstrInfo::tryCompoun<wbr>d(MCInstrInfo const &MCII,<br>
MCSubtargetInfo const &STI,<br>
MCContext &Context, MCInst<br>
&MCI) {<br>
assert(HexagonMCInstrInfo::is<wbr>Bundle(MCI) &&<br>
"Non-Bundle where Bundle expected");<br>
@@ -405,8 +406,23 @@ void HexagonMCInstrInfo::tryCompoun<wbr>d(MCI<br>
if (MCI.size() < 2)<br>
return;<br>
<br>
+ bool StartedValid = llvm::HexagonMCShuffle(false, MCII, STI, MCI);<br>
+<br>
+ // Create a vector, needed to keep the order of jump instructions.<br>
+ MCInst CheckList(MCI);<br>
+<br>
// Look for compounds until none are found, only update the<br>
bundle when<br>
// a compound is found.<br>
- while (lookForCompound(MCII, Context, MCI))<br>
- ;<br>
+ while (lookForCompound(MCII, Context, CheckList)) {<br>
+ // Keep the original bundle around in case the shuffle fails.<br>
+ MCInst OriginalBundle(MCI);<br>
+<br>
+ // Need to update the bundle.<br>
+ MCI = CheckList;<br>
+<br>
+ if (StartedValid && !llvm::HexagonMCShuffle(false, MCII, STI,<br>
MCI)) {<br>
+ DEBUG(dbgs() << "Found ERROR\n");<br>
+ MCI = OriginalBundle;<br>
+ }<br>
+ }<br>
}<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/<wbr>MCTargetDesc/HexagonMCDuplexIn<wbr>fo.cpp<br>
URL:<br>
<br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp?rev=294226&r1=294225&r2=294226&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/He<wbr>xagon/MCTargetDesc/HexagonMCDu<wbr>plexInfo.cpp?rev=294226&r1=<wbr>294225&r2=294226&view=diff</a></blockquote></blockquote>
</blockquote></div><br></div>