<div dir="ltr">Hi Simon,<div><br></div>I'm getting a "comparison of unsigned expression >= 0 is always true" warning for the "0 <= ExIdx" check in the assert - which makes sense, since ExIdx is a uint_64t. Perhaps just remove that part of the assert? <div><br></div><div>Thanks,</div><div> Michael<br><div><br></div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jan 30, 2017 at 8:58 AM, Simon Pilgrim via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br>
Date: Mon Jan 30 10:58:34 2017<br>
New Revision: 293500<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=293500&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=293500&view=rev</a><br>
Log:<br>
[X86][SSE] Add support for combining PINSRW+ASSERTZEXT+PEXTRW patterns with target shuffles<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=293500&r1=293499&r2=293500&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>X86/X86ISelLowering.cpp?rev=<wbr>293500&r1=293499&r2=293500&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/<wbr>X86ISelLowering.cpp Mon Jan 30 10:58:34 2017<br>
@@ -5769,6 +5769,26 @@ static bool getFauxShuffleMask(SDValue N<br>
Ops.push_back(IsAndN ? N1 : N0);<br>
return true;<br>
}<br>
+ case X86ISD::PINSRW: {<br>
+ // Attempt to recognise a PINSRW(ASSERTZEXT(PEXTRW)) shuffle pattern.<br>
+ // TODO: Expand this to support PINSRB/INSERT_VECTOR_ELT/etc.<br>
+ SDValue InVec = N.getOperand(0);<br>
+ SDValue InScl = N.getOperand(1);<br>
+ uint64_t InIdx = N.getConstantOperandVal(2);<br>
+ assert(0 <= InIdx && InIdx < NumElts && "Illegal insertion index");<br>
+ if (InScl.getOpcode() != ISD::AssertZext ||<br>
+ InScl.getOperand(0).getOpcode(<wbr>) != X86ISD::PEXTRW)<br>
+ return false;<br>
+<br>
+ SDValue ExVec = InScl.getOperand(0).<wbr>getOperand(0);<br>
+ uint64_t ExIdx = InScl.getOperand(0).<wbr>getConstantOperandVal(1);<br>
+ assert(0 <= ExIdx && ExIdx < NumElts && "Illegal extraction index");<br>
+ Ops.push_back(InVec);<br>
+ Ops.push_back(ExVec);<br>
+ for (unsigned i = 0; i != NumElts; ++i)<br>
+ Mask.push_back(i == InIdx ? NumElts + ExIdx : i);<br>
+ return true;<br>
+ }<br>
case X86ISD::VSHLI:<br>
case X86ISD::VSRLI: {<br>
uint64_t ShiftVal = N.getConstantOperandVal(1);<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/clear_upper_vector_element_bits.ll?rev=293500&r1=293499&r2=293500&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/X86/clear_upper_<wbr>vector_element_bits.ll?rev=<wbr>293500&r1=293499&r2=293500&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<wbr>clear_upper_vector_element_<wbr>bits.ll Mon Jan 30 10:58:34 2017<br>
@@ -94,21 +94,7 @@ define <8 x i16> @_clearupper8xi16a(<8 x<br>
;<br>
; AVX-LABEL: _clearupper8xi16a:<br>
; AVX: # BB#0:<br>
-; AVX-NEXT: vpextrw $1, %xmm0, %eax<br>
-; AVX-NEXT: vpextrw $2, %xmm0, %ecx<br>
-; AVX-NEXT: vpextrw $3, %xmm0, %edx<br>
-; AVX-NEXT: vpextrw $4, %xmm0, %esi<br>
-; AVX-NEXT: vpextrw $5, %xmm0, %edi<br>
-; AVX-NEXT: vpextrw $6, %xmm0, %r8d<br>
-; AVX-NEXT: vpextrw $7, %xmm0, %r9d<br>
-; AVX-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrw $3, %edx, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrw $4, %esi, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrw $6, %r8d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpinsrw $7, %r9d, %xmm0, %xmm0<br>
-; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0<br>
+; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0<br>
; AVX-NEXT: retq<br>
%x0 = extractelement <8 x i16> %0, i32 0<br>
%x1 = extractelement <8 x i16> %0, i32 1<br>
<br>
<br>
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</blockquote></div><br></div>