<div dir="ltr"><div><div>Please ignore then. Sorry for the noise.<br><br></div>Thanks<br><br></div>Galina<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jan 27, 2017 at 12:20 PM, Hal Finkel <span dir="ltr"><<a href="mailto:hfinkel@anl.gov" target="_blank">hfinkel@anl.gov</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000"><span class="">
<p><br>
</p>
<div class="m_-8734970090329654492moz-cite-prefix">On 01/27/2017 02:14 PM, Galina
Kistanova via llvm-commits wrote:<br>
</div>
<blockquote type="cite">
<div dir="ltr">Hello Sean,<br>
<br>
It looks like this commit added a warning to one of our
builders:<br>
<br>
llvm/unittests/ProfileData/<wbr>InstrProfTest.cpp:1027:42: warning:
ISO C99 requires rest arguments to be used [enabled by default]<br>
</div>
</blockquote>
<br></span>
That seems unlikely. This commit only affects the PowerPC backend
(and does not touch that file nor anything in Clang). This is not a
PPC buildbot, so it is probably not a miscompile.<br>
<br>
-Hal<div><div class="h5"><br>
<br>
<blockquote type="cite">
<div dir="ltr"><br>
<a href="http://lab.llvm.org:8011/builders/clang-lld-x86_64-2stage" target="_blank">http://lab.llvm.org:8011/<wbr>builders/clang-lld-x86_64-<wbr>2stage</a><br>
<br>
Please have a look at this?<br>
<br>
Thanks<br>
<br>
Galina<br>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Thu, Jan 26, 2017 at 10:59 AM, Sean
Fertile via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author:
sfertile<br>
Date: Thu Jan 26 12:59:15 2017<br>
New Revision: 293200<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=293200&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=293200&view=rev</a><br>
Log:<br>
[PPC] cleanup of mayLoad/mayStore flags and memory operands.<br>
<br>
1) Explicitly sets mayLoad/mayStore property in the tablegen
files on load/store<br>
instructions.<br>
2) Updated the flags on a number of intrinsics indicating
that they write<br>
memory.<br>
3) Added SDNPMemOperand flags for some target dependent
SDNodes so that they<br>
propagate their memory operand<br>
<br>
Review: <a href="https://reviews.llvm.org/D28818" rel="noreferrer" target="_blank">https://reviews.llvm.org/D2881<wbr>8</a><br>
<br>
Modified:<br>
llvm/trunk/include/llvm/IR/Int<wbr>rinsicsPowerPC.td<br>
llvm/trunk/lib/Target/PowerPC/<wbr>PPCISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstr64Bit.td<br>
llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrAltivec.td<br>
llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrInfo.td<br>
llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrVSX.td<br>
llvm/trunk/test/CodeGen/PowerP<wbr>C/swaps-le-7.ll<br>
<br>
Modified: llvm/trunk/include/llvm/IR/Int<wbr>rinsicsPowerPC.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td?rev=293200&r1=293199&r2=293200&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/llvm/<wbr>IR/IntrinsicsPowerPC.td?rev=<wbr>293200&r1=293199&r2=293200&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/IR/Int<wbr>rinsicsPowerPC.td
(original)<br>
+++ llvm/trunk/include/llvm/IR/Int<wbr>rinsicsPowerPC.td Thu
Jan 26 12:59:15 2017<br>
@@ -203,19 +203,19 @@ let TargetPrefix = "ppc" in { // All
in<br>
// source address with a single pointer.<br>
def int_ppc_altivec_stvx :<br>
Intrinsic<[], [llvm_v4i32_ty,
llvm_ptr_ty],<br>
- [IntrArgMemOnly]>;<br>
+ [IntrWriteMem, IntrArgMemOnly]>;<br>
def int_ppc_altivec_stvxl :<br>
Intrinsic<[], [llvm_v4i32_ty,
llvm_ptr_ty],<br>
- [IntrArgMemOnly]>;<br>
+ [IntrWriteMem, IntrArgMemOnly]>;<br>
def int_ppc_altivec_stvebx :<br>
Intrinsic<[], [llvm_v16i8_ty,
llvm_ptr_ty],<br>
- [IntrArgMemOnly]>;<br>
+ [IntrWriteMem, IntrArgMemOnly]>;<br>
def int_ppc_altivec_stvehx :<br>
Intrinsic<[], [llvm_v8i16_ty,
llvm_ptr_ty],<br>
- [IntrArgMemOnly]>;<br>
+ [IntrWriteMem, IntrArgMemOnly]>;<br>
def int_ppc_altivec_stvewx :<br>
Intrinsic<[], [llvm_v4i32_ty,
llvm_ptr_ty],<br>
- [IntrArgMemOnly]>;<br>
+ [IntrWriteMem, IntrArgMemOnly]>;<br>
<br>
// Comparisons setting a vector.<br>
def int_ppc_altivec_vcmpbfp :
GCCBuiltin<"__builtin_altivec_<wbr>vcmpbfp">,<br>
@@ -749,20 +749,20 @@ def int_ppc_vsx_lxvll :<br>
IntrArgMemOnly]>;<br>
def int_ppc_vsx_stxvl :<br>
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty,
llvm_i64_ty],<br>
- [IntrArgMemOnly]>;<br>
+ [IntrWriteMem, IntrArgMemOnly]>;<br>
def int_ppc_vsx_stxvll :<br>
Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty,
llvm_i64_ty],<br>
- [IntrArgMemOnly]>;<br>
+ [IntrWriteMem, IntrArgMemOnly]>;<br>
<br>
// Vector store.<br>
-def int_ppc_vsx_stxvw4x :<br>
- Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
[IntrArgMemOnly]>;<br>
-def int_ppc_vsx_stxvd2x :<br>
- Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty],
[IntrArgMemOnly]>;<br>
-def int_ppc_vsx_stxvw4x_be :<br>
- Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
[IntrArgMemOnly]>;<br>
-def int_ppc_vsx_stxvd2x_be :<br>
- Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty],
[IntrArgMemOnly]>;<br>
+def int_ppc_vsx_stxvw4x : Intrinsic<[], [llvm_v4i32_ty,
llvm_ptr_ty],<br>
+ [IntrWriteMem,
IntrArgMemOnly]>;<br>
+def int_ppc_vsx_stxvd2x : Intrinsic<[], [llvm_v2f64_ty,
llvm_ptr_ty],<br>
+ [IntrWriteMem,
IntrArgMemOnly]>;<br>
+def int_ppc_vsx_stxvw4x_be : Intrinsic<[],
[llvm_v4i32_ty, llvm_ptr_ty],<br>
+ [IntrWriteMem,
IntrArgMemOnly]>;<br>
+def int_ppc_vsx_stxvd2x_be : Intrinsic<[],
[llvm_v2f64_ty, llvm_ptr_ty],<br>
+ [IntrWriteMem,
IntrArgMemOnly]>;<br>
// Vector and scalar maximum.<br>
def int_ppc_vsx_xvmaxdp : PowerPC_VSX_Vec_DDD_Intrinsic<<wbr>"xvmaxdp">;<br>
def int_ppc_vsx_xvmaxsp : PowerPC_VSX_Vec_FFF_Intrinsic<<wbr>"xvmaxsp">;<br>
@@ -953,7 +953,7 @@ class PowerPC_QPX_LoadPerm_Intrinsic<wbr><str<br>
class PowerPC_QPX_Store_Intrinsic<st<wbr>ring
GCCIntSuffix><br>
: PowerPC_QPX_Intrinsic<GCCIntSu<wbr>ffix,<br>
[], [llvm_v4f64_ty, llvm_ptr_ty],<br>
- [IntrArgMemOnly]>;<br>
+ [IntrWriteMem,
IntrArgMemOnly]>;<br>
<br>
//===------------------------<wbr>------------------------------<wbr>----------------===//<br>
// PowerPC QPX Intrinsic Definitions.<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/<wbr>PPCISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=293200&r1=293199&r2=293200&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Po<wbr>werPC/PPCISelDAGToDAG.cpp?rev=<wbr>293200&r1=293199&r2=293200&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/PowerPC/<wbr>PPCISelDAGToDAG.cpp
(original)<br>
+++ llvm/trunk/lib/Target/PowerPC/<wbr>PPCISelDAGToDAG.cpp
Thu Jan 26 12:59:15 2017<br>
@@ -2964,7 +2964,11 @@ void PPCDAGToDAGISel::Select(SDNode
*N)<br>
SelectAddrIdxOnly(LD->getBase<wbr>Ptr(),
Base, Offset)) {<br>
SDValue Chain = LD->getChain();<br>
SDValue Ops[] = { Base, Offset, Chain };<br>
- CurDAG->SelectNodeTo(N, PPC::LXVDSX,
N->getValueType(0), Ops);<br>
+ SDNode *NewN = CurDAG->SelectNodeTo(N,
PPC::LXVDSX,<br>
+
N->getValueType(0), Ops);<br>
+ MachineSDNode::mmo_iterator MemOp =
MF->allocateMemRefsArray(1);<br>
+ MemOp[0] = LD->getMemOperand();<br>
+ cast<MachineSDNode>(NewN)->set<wbr>MemRefs(MemOp,
MemOp + 1);<br>
return;<br>
}<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstr64Bit.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=293200&r1=293199&r2=293200&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Po<wbr>werPC/PPCInstr64Bit.td?rev=293<wbr>200&r1=293199&r2=293200&view=<wbr>diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstr64Bit.td
(original)<br>
+++ llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstr64Bit.td Thu
Jan 26 12:59:15 2017<br>
@@ -253,11 +253,11 @@ def LDAT : X_RD5_RS5_IM5<31, 614,
(outs<br>
Requires<[IsISA3_0]>;<br>
}<br>
<br>
-let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in<br>
+let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects
= 0 in<br>
def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS,
memrr:$dst),<br>
"stdcx. $rS, $dst", IIC_LdStSTDCX,
[]>, isDOT;<br>
<br>
-let mayStore = 1, hasSideEffects = 0 in<br>
+let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in<br>
def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins
g8rc:$rS, g8rc:$rA, u5imm:$FC),<br>
"stdat $rS, $rA, $FC",
IIC_LdStStore>, isPPC64,<br>
Requires<[IsISA3_0]>;<br>
@@ -1082,7 +1082,7 @@ def STDBRX: XForm_8<31, 660,
(outs), (in<br>
}<br>
<br>
// Stores with Update (pre-inc).<br>
-let PPC970_Unit = 2, mayStore = 1 in {<br>
+let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {<br>
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {<br>
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins
g8rc:$rS, memri:$dst),<br>
"stbu $rS, $dst", IIC_LdStStoreUpd,
[]>,<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrAltivec.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=293200&r1=293199&r2=293200&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Po<wbr>werPC/PPCInstrAltivec.td?rev=<wbr>293200&r1=293199&r2=293200&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrAltivec.td
(original)<br>
+++ llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrAltivec.td
Thu Jan 26 12:59:15 2017<br>
@@ -407,7 +407,7 @@ def MTVSCR : VXForm_5<1604, (outs),
(ins<br>
"mtvscr $vB", IIC_LdStLoad,<br>
[(int_ppc_altivec_mtvscr
v4i32:$vB)]>;<br>
<br>
-let PPC970_Unit = 2 in { // Loads.<br>
+let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { //
Loads.<br>
def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins
memrr:$src),<br>
"lvebx $vD, $src", IIC_LdStLoad,<br>
[(set v16i8:$vD, (int_ppc_altivec_lvebx
xoaddr:$src))]>;<br>
@@ -434,7 +434,7 @@ def LVSR : XForm_1<31, 38, (outs
vrrc:$<br>
[(set v16i8:$vD, (int_ppc_altivec_lvsr
xoaddr:$src))]>,<br>
PPC970_Unit_LSU;<br>
<br>
-let PPC970_Unit = 2 in { // Stores.<br>
+let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { //
Stores.<br>
def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS,
memrr:$dst),<br>
"stvebx $rS, $dst", IIC_LdStStore,<br>
[(int_ppc_altivec_stvebx v16i8:$rS,
xoaddr:$dst)]>;<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=293200&r1=293199&r2=293200&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Po<wbr>werPC/PPCInstrInfo.td?rev=2932<wbr>00&r1=293199&r2=293200&view=<wbr>diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrInfo.td
(original)<br>
+++ llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrInfo.td Thu
Jan 26 12:59:15 2017<br>
@@ -114,9 +114,9 @@ def PPCfctiwuz:
SDNode<"PPCISD::FCTIWUZ"<br>
def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,<br>
[SDNPHasChain, SDNPMayStore]>;<br>
def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx,<br>
- [SDNPHasChain, SDNPMayLoad]>;<br>
+ [SDNPHasChain, SDNPMayLoad,
SDNPMemOperand]>;<br>
def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx,<br>
- [SDNPHasChain, SDNPMayLoad]>;<br>
+ [SDNPHasChain, SDNPMayLoad,
SDNPMemOperand]>;<br>
def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx,<br>
[SDNPHasChain, SDNPMayLoad]>;<br>
def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix,<br>
@@ -243,7 +243,7 @@ def PPCcondbranch :
SDNode<"PPCISD::COND<br>
[SDNPHasChain,
SDNPOptInGlue]>;<br>
<br>
def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,<br>
- [SDNPHasChain, SDNPMayLoad]>;<br>
+ [SDNPHasChain, SDNPMayLoad,
SDNPMemOperand]>;<br>
def PPCstbrx : SDNode<"PPCISD::STBRX",
SDT_PPCstbrx,<br>
[SDNPHasChain,
SDNPMayStore]>;<br>
<br>
@@ -1642,7 +1642,7 @@ let usesCustomInserter = 1 in {<br>
}<br>
<br>
// Instructions to support atomic operations<br>
-let mayLoad = 1, hasSideEffects = 0 in {<br>
+let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {<br>
def LBARX : XForm_1<31, 52, (outs gprc:$rD), (ins
memrr:$src),<br>
"lbarx $rD, $src", IIC_LdStLWARX,
[]>,<br>
Requires<[HasPartwordAtomics]<wbr>>;<br>
@@ -1675,7 +1675,7 @@ def LWAT : X_RD5_RS5_IM5<31, 582,
(outs<br>
Requires<[IsISA3_0]>;<br>
}<br>
<br>
-let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {<br>
+let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects
= 0 in {<br>
def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS,
memrr:$dst),<br>
"stbcx. $rS, $dst", IIC_LdStSTWCX,
[]>,<br>
isDOT,
Requires<[HasPartwordAtomics]><wbr>;<br>
@@ -1688,7 +1688,7 @@ def STWCX : XForm_1<31, 150,
(outs), (in<br>
"stwcx. $rS, $dst", IIC_LdStSTWCX,
[]>, isDOT;<br>
}<br>
<br>
-let mayStore = 1, hasSideEffects = 0 in<br>
+let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in<br>
def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins
gprc:$rS, gprc:$rA, u5imm:$FC),<br>
"stwat $rS, $rA, $FC",
IIC_LdStStore>,<br>
Requires<[IsISA3_0]>;<br>
@@ -1734,7 +1734,7 @@ def LFD : DForm_1<50, (outs
f8rc:$rD), (<br>
<br>
<br>
// Unindexed (r+i) Loads with Update (preinc).<br>
-let mayLoad = 1, hasSideEffects = 0 in {<br>
+let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in {<br>
def LBZU : DForm_1<35, (outs gprc:$rD,
ptr_rc_nor0:$ea_result), (ins memri:$addr),<br>
"lbzu $rD, $addr", IIC_LdStLoadUpd,<br>
[]>, RegConstraint<"$addr.reg =
$ea_result">,<br>
@@ -1807,7 +1807,7 @@ def LFDUX : XForm_1<31, 631, (outs
f8rc:<br>
<br>
// Indexed (r+r) Loads.<br>
//<br>
-let PPC970_Unit = 2 in {<br>
+let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in {<br>
def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins
memrr:$src),<br>
"lbzx $rD, $src", IIC_LdStLoad,<br>
[(set i32:$rD, (zextloadi8
xaddr:$src))]>;<br>
@@ -1821,8 +1821,6 @@ def LHZX : XForm_1<31, 279, (outs
gprc:$<br>
def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins
memrr:$src),<br>
"lwzx $rD, $src", IIC_LdStLoad,<br>
[(set i32:$rD, (load xaddr:$src))]>;<br>
-<br>
-<br>
def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins
memrr:$src),<br>
"lhbrx $rD, $src", IIC_LdStLoad,<br>
[(set i32:$rD, (PPClbrx xoaddr:$src,
i16))]>;<br>
@@ -1854,7 +1852,7 @@ def LMW : DForm_1<46, (outs
gprc:$rD), (<br>
//<br>
<br>
// Unindexed (r+i) Stores.<br>
-let PPC970_Unit = 2 in {<br>
+let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {<br>
def STB : DForm_1<38, (outs), (ins gprc:$rS,
memri:$src),<br>
"stb $rS, $src", IIC_LdStStore,<br>
[(truncstorei8 i32:$rS,
iaddr:$src)]>;<br>
@@ -1873,7 +1871,7 @@ def STFD : DForm_1<54, (outs), (ins
f8rc<br>
}<br>
<br>
// Unindexed (r+i) Stores with Update (preinc).<br>
-let PPC970_Unit = 2, mayStore = 1 in {<br>
+let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {<br>
def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins
gprc:$rS, memri:$dst),<br>
"stbu $rS, $dst", IIC_LdStStoreUpd,
[]>,<br>
RegConstraint<"$dst.reg =
$ea_res">, NoEncode<"$ea_res">;<br>
@@ -1942,7 +1940,7 @@ def STFDX : XForm_28<31, 727,
(outs), (i<br>
}<br>
<br>
// Indexed (r+r) Stores with Update (preinc).<br>
-let PPC970_Unit = 2, mayStore = 1 in {<br>
+let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in {<br>
def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res),
(ins gprc:$rS, memrr:$dst),<br>
"stbux $rS, $dst", IIC_LdStStoreUpd,
[]>,<br>
RegConstraint<"$dst.ptrreg =
$ea_res">, NoEncode<"$ea_res">,<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrVSX.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=293200&r1=293199&r2=293200&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/Po<wbr>werPC/PPCInstrVSX.td?rev=29320<wbr>0&r1=293199&r2=293200&view=<wbr>diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrVSX.td
(original)<br>
+++ llvm/trunk/lib/Target/PowerPC/<wbr>PPCInstrVSX.td Thu
Jan 26 12:59:15 2017<br>
@@ -62,7 +62,7 @@ def SDTVecConv : SDTypeProfile<1, 2, [<br>
]>;<br>
<br>
def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x,<br>
- [SDNPHasChain, SDNPMayLoad]>;<br>
+ [SDNPHasChain, SDNPMayLoad,
SDNPMemOperand]>;<br>
def PPCstxvd2x : SDNode<"PPCISD::STXVD2X",
SDT_PPCstxvd2x,<br>
[SDNPHasChain, SDNPMayStore]>;<br>
def PPCxxswapd : SDNode<"PPCISD::XXSWAPD",
SDT_PPCxxswapd, [SDNPHasChain]>;<br>
@@ -117,7 +117,7 @@ let hasSideEffects = 0 in { // VSX instr<br>
let Uses = [RM] in {<br>
<br>
// Load indexed instructions<br>
- let mayLoad = 1 in {<br>
+ let mayLoad = 1, mayStore = 0 in {<br>
let CodeSize = 3 in<br>
def LXSDX : XX1Form<31, 588,<br>
(outs vsfrc:$XT), (ins memrr:$src),<br>
@@ -142,7 +142,7 @@ let Uses = [RM] in {<br>
} // mayLoad<br>
<br>
// Store indexed instructions<br>
- let mayStore = 1 in {<br>
+ let mayStore = 1, mayLoad = 0 in {<br>
let CodeSize = 3 in<br>
def STXSDX : XX1Form<31, 716,<br>
(outs), (ins vsfrc:$XT,
memrr:$dst),<br>
@@ -1197,7 +1197,7 @@ let AddedComplexity = 400 in { //
Prefer<br>
[(set v4i32:$XT, (or v4i32:$XA,
(vnot_ppc v4i32:$XB)))]>;<br>
<br>
// VSX scalar loads introduced in ISA 2.07<br>
- let mayLoad = 1 in {<br>
+ let mayLoad = 1, mayStore = 0 in {<br>
let CodeSize = 3 in<br>
def LXSSPX : XX1Form<31, 524, (outs vssrc:$XT), (ins
memrr:$src),<br>
"lxsspx $XT, $src", IIC_LdStLFD,<br>
@@ -1211,7 +1211,7 @@ let AddedComplexity = 400 in { //
Prefer<br>
} // mayLoad<br>
<br>
// VSX scalar stores introduced in ISA 2.07<br>
- let mayStore = 1 in {<br>
+ let mayStore = 1, mayLoad = 0 in {<br>
let CodeSize = 3 in<br>
def STXSSPX : XX1Form<31, 652, (outs), (ins
vssrc:$XT, memrr:$dst),<br>
"stxsspx $XT, $dst",
IIC_LdStSTFD,<br>
@@ -2335,7 +2335,7 @@ let AddedComplexity = 400, Predicates
=<br>
<br>
// When adding new D-Form loads/stores, be sure to update
the ImmToIdxMap in<br>
// PPCRegisterInfo::PPCRegisterIn<wbr>fo and maybe save
yourself some debugging.<br>
- let mayLoad = 1 in {<br>
+ let mayLoad = 1, mayStore = 0 in {<br>
// Load Vector<br>
def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins
memrix16:$src),<br>
"lxv $XT, $src", IIC_LdStLFD,
[]>, UseVSXReg;<br>
@@ -2383,7 +2383,7 @@ let AddedComplexity = 400, Predicates
=<br>
<br>
// When adding new D-Form loads/stores, be sure to update
the ImmToIdxMap in<br>
// PPCRegisterInfo::PPCRegisterIn<wbr>fo and maybe save
yourself some debugging.<br>
- let mayStore = 1 in {<br>
+ let mayStore = 1, mayLoad = 0 in {<br>
// Store Vector<br>
def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins
vsrc:$XT, memrix16:$dst),<br>
"stxv $XT, $dst",
IIC_LdStSTFD, []>, UseVSXReg;<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerP<wbr>C/swaps-le-7.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/swaps-le-7.ll?rev=293200&r1=293199&r2=293200&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>PowerPC/swaps-le-7.ll?rev=<wbr>293200&r1=293199&r2=293200&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/PowerP<wbr>C/swaps-le-7.ll
(original)<br>
+++ llvm/trunk/test/CodeGen/PowerP<wbr>C/swaps-le-7.ll Thu
Jan 26 12:59:15 2017<br>
@@ -11,11 +11,11 @@<br>
; CHECK-LABEL: @zg<br>
; CHECK: xxspltd<br>
; CHECK-NEXT: xxspltd<br>
-; CHECK-NEXT: xxswapd<br>
; CHECK-NEXT: xvmuldp<br>
; CHECK-NEXT: xvmuldp<br>
; CHECK-NEXT: xvsubdp<br>
; CHECK-NEXT: xvadddp<br>
+; CHECK-NEXT: xxswapd<br>
; CHECK-NEXT: xxpermdi<br>
; CHECK-NEXT: xvsubdp<br>
; CHECK-NEXT: xxswapd<br>
@@ -52,4 +52,4 @@ L.JA291:<br>
ret void<br>
}<br>
<br>
-attributes #0 = { noinline }<br>
\ No newline at end of file<br>
+attributes #0 = { noinline }<br>
<br>
<br>
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</div></div><span class="HOEnZb"><font color="#888888"><pre class="m_-8734970090329654492moz-signature" cols="72">--
Hal Finkel
Lead, Compiler Technology and Programming Languages
Leadership Computing Facility
Argonne National Laboratory</pre>
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