<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Well spotted. It seems it appeared in diff 6 of D27338 and it's a copy of the one that's in the correct location (include/llvm/Target/GlobalISel/RegisterBank.td). I'm not sure how it appeared but it's not used by the build. Fixed in r292771<div class=""><br class=""></div><div class="">Thanks<br class=""><div class=""><div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On 21 Jan 2017, at 06:31, David Majnemer <<a href="mailto:david.majnemer@gmail.com" class="">david.majnemer@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Is there any reason why we have llvm/Target/GlobalISel instead of lib/Target/GlobalISel? I guess it just seems a little weird for the LLVM SVN repro to have a folder called "llvm" which is nearly empty.<br class=""></div><div class="gmail_extra"><br class=""><div class="gmail_quote">On Thu, Jan 19, 2017 at 3:15 AM, Daniel Sanders via llvm-commits <span dir="ltr" class=""><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: dsanders<br class="">
Date: Thu Jan 19 05:15:55 2017<br class="">
New Revision: 292478<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=292478&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project?rev=292478&view=rev</a><br class="">
Log:<br class="">
Re-commit: [globalisel] Tablegen-erate current Register Bank Information<br class="">
<br class="">
Summary:<br class="">
Adds a RegisterBank tablegen class that can be used to declare the register<br class="">
banks and an associated tablegen pass to generate the necessary code.<br class="">
<br class="">
Changes since first commit attempt:<br class="">
* Added missing guards<br class="">
* Added more missing guards<br class="">
* Found and fixed a use-after-free bug involving Twine locals<br class="">
<br class="">
Reviewers: t.p.northover, ab, rovka, qcolombet<br class="">
<br class="">
Reviewed By: qcolombet<br class="">
<br class="">
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka<br class="">
<br class="">
Differential Revision: <a href="https://reviews.llvm.org/D27338" rel="noreferrer" target="_blank" class="">https://reviews.llvm.org/<wbr class="">D27338</a><br class="">
<br class="">
<br class="">
Added:<br class="">
llvm/trunk/include/llvm/<wbr class="">Target/GlobalISel/<br class="">
- copied from r292368, llvm/trunk/include/llvm/<wbr class="">Target/GlobalISel/<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBanks.td<br class="">
- copied unchanged from r292368, llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBanks.td<br class="">
llvm/trunk/llvm/<br class="">
- copied from r292368, llvm/trunk/llvm/<br class="">
llvm/trunk/utils/TableGen/<wbr class="">RegisterBankEmitter.cpp<br class="">
- copied, changed from r292368, llvm/trunk/utils/TableGen/<wbr class="">RegisterBankEmitter.cpp<br class="">
Modified:<br class="">
llvm/trunk/include/llvm/<wbr class="">CodeGen/GlobalISel/<wbr class="">RegisterBank.h<br class="">
llvm/trunk/include/llvm/<wbr class="">Target/Target.td<br class="">
llvm/trunk/lib/CodeGen/<wbr class="">GlobalISel/RegisterBank.cpp<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64.td<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64GenRegisterBankInfo.def<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBankInfo.cpp<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBankInfo.h<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64TargetMachine.cpp<br class="">
llvm/trunk/lib/Target/AArch64/<wbr class="">CMakeLists.txt<br class="">
llvm/trunk/lib/Target/ARM/<wbr class="">ARMRegisterBankInfo.cpp<br class="">
llvm/trunk/utils/TableGen/<wbr class="">CMakeLists.txt<br class="">
llvm/trunk/utils/TableGen/<wbr class="">TableGen.cpp<br class="">
llvm/trunk/utils/TableGen/<wbr class="">TableGenBackends.h<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/<wbr class="">CodeGen/GlobalISel/<wbr class="">RegisterBank.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/include/<wbr class="">llvm/CodeGen/GlobalISel/<wbr class="">RegisterBank.h?rev=292478&r1=<wbr class="">292477&r2=292478&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/include/llvm/<wbr class="">CodeGen/GlobalISel/<wbr class="">RegisterBank.h (original)<br class="">
+++ llvm/trunk/include/llvm/<wbr class="">CodeGen/GlobalISel/<wbr class="">RegisterBank.h Thu Jan 19 05:15:55 2017<br class="">
@@ -42,7 +42,7 @@ private:<br class="">
<br class="">
public:<br class="">
RegisterBank(unsigned ID, const char *Name, unsigned Size,<br class="">
- const uint32_t *ContainedRegClasses);<br class="">
+ const uint32_t *ContainedRegClasses, unsigned NumRegClasses);<br class="">
<br class="">
/// Get the identifier of this register bank.<br class="">
unsigned getID() const { return ID; }<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/<wbr class="">Target/Target.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/include/<wbr class="">llvm/Target/Target.td?rev=<wbr class="">292478&r1=292477&r2=292478&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/include/llvm/<wbr class="">Target/Target.td (original)<br class="">
+++ llvm/trunk/include/llvm/<wbr class="">Target/Target.td Thu Jan 19 05:15:55 2017<br class="">
@@ -1344,4 +1344,5 @@ include "llvm/Target/<wbr class="">TargetSelectionDAG.<br class="">
//===-------------------------<wbr class="">------------------------------<wbr class="">---------------===//<br class="">
// Pull in the common support for Global ISel generation.<br class="">
//<br class="">
+include "llvm/Target/GlobalISel/<wbr class="">RegisterBank.td"<br class="">
include "llvm/Target/TargetGlobalISel.<wbr class="">td"<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/<wbr class="">GlobalISel/RegisterBank.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/<wbr class="">CodeGen/GlobalISel/<wbr class="">RegisterBank.cpp?rev=292478&<wbr class="">r1=292477&r2=292478&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/CodeGen/<wbr class="">GlobalISel/RegisterBank.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/<wbr class="">GlobalISel/RegisterBank.cpp Thu Jan 19 05:15:55 2017<br class="">
@@ -19,10 +19,11 @@ using namespace llvm;<br class="">
<br class="">
const unsigned RegisterBank::InvalidID = UINT_MAX;<br class="">
<br class="">
-RegisterBank::RegisterBank(<wbr class="">unsigned ID, const char *Name, unsigned Size,<br class="">
- const uint32_t *CoveredClasses)<br class="">
+RegisterBank::RegisterBank(<br class="">
+ unsigned ID, const char *Name, unsigned Size,<br class="">
+ const uint32_t *CoveredClasses, unsigned NumRegClasses)<br class="">
: ID(ID), Name(Name), Size(Size) {<br class="">
- ContainedRegClasses.resize(<wbr class="">200);<br class="">
+ ContainedRegClasses.resize(<wbr class="">NumRegClasses);<br class="">
ContainedRegClasses.<wbr class="">setBitsInMask(CoveredClasses);<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/AArch64.td?rev=292478&<wbr class="">r1=292477&r2=292478&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64.td (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64.td Thu Jan 19 05:15:55 2017<br class="">
@@ -127,6 +127,7 @@ def HasV8_2aOps : SubtargetFeature<"v8.2<br class="">
//===-------------------------<wbr class="">------------------------------<wbr class="">---------------===//<br class="">
<br class="">
include "AArch64RegisterInfo.td"<br class="">
+include "AArch64RegisterBanks.td"<br class="">
include "AArch64CallingConvention.td"<br class="">
<br class="">
//===-------------------------<wbr class="">------------------------------<wbr class="">---------------===//<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64GenRegisterBankInfo.def<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/<wbr class="">AArch64GenRegisterBankInfo.<wbr class="">def?rev=292478&r1=292477&r2=<wbr class="">292478&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64GenRegisterBankInfo.def (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64GenRegisterBankInfo.def Thu Jan 19 05:15:55 2017<br class="">
@@ -16,204 +16,81 @@<br class="">
#endif<br class="">
<br class="">
namespace llvm {<br class="">
-namespace AArch64 {<br class="">
-<br class="">
-const uint32_t GPRCoverageData[] = {<br class="">
- // Classes 0-31<br class="">
- (1u << AArch64::GPR32allRegClassID) | (1u << AArch64::GPR32RegClassID) |<br class="">
- (1u << AArch64::GPR32spRegClassID) |<br class="">
- (1u << AArch64::<wbr class="">GPR32commonRegClassID) |<br class="">
- (1u << AArch64::<wbr class="">GPR32sponlyRegClassID) |<br class="">
- (1u << AArch64::GPR64allRegClassID) | (1u << AArch64::GPR64RegClassID) |<br class="">
- (1u << AArch64::GPR64spRegClassID) |<br class="">
- (1u << AArch64::<wbr class="">GPR64commonRegClassID) |<br class="">
- (1u << AArch64::tcGPR64RegClassID) |<br class="">
- (1u << AArch64::<wbr class="">GPR64sponlyRegClassID),<br class="">
- // Classes 32-63<br class="">
- 0,<br class="">
- // FIXME: The entries below this point can be safely removed once this is<br class="">
- // tablegenerated. It's only needed because of the hardcoded register class<br class="">
- // limit.<br class="">
- // Classes 64-96<br class="">
- 0,<br class="">
- // Classes 97-128<br class="">
- 0,<br class="">
- // Classes 129-160<br class="">
- 0,<br class="">
- // Classes 161-192<br class="">
- 0,<br class="">
- // Classes 193-224<br class="">
- 0,<br class="">
-};<br class="">
-<br class="">
-const uint32_t FPRCoverageData[] = {<br class="">
- // Classes 0-31<br class="">
- (1u << AArch64::FPR8RegClassID) | (1u << AArch64::FPR16RegClassID) |<br class="">
- (1u << AArch64::FPR32RegClassID) | (1u << AArch64::FPR64RegClassID) |<br class="">
- (1u << AArch64::DDRegClassID) | (1u << AArch64::FPR128RegClassID) |<br class="">
- (1u << AArch64::FPR128_loRegClassID) | (1u << AArch64::DDDRegClassID) |<br class="">
- (1u << AArch64::DDDDRegClassID),<br class="">
- // Classes 32-63<br class="">
- (1u << (AArch64::QQRegClassID - 32)) |<br class="">
- (1u << (AArch64::QQ_with_qsub0_in_<wbr class="">FPR128_loRegClassID - 32)) |<br class="">
- (1u << (AArch64::QQ_with_qsub1_in_<wbr class="">FPR128_loRegClassID - 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQQ_with_qsub1_in_FPR128_lo_<wbr class="">and_QQQ_with_qsub2_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQQ_with_qsub0_in_FPR128_lo_<wbr class="">and_QQQ_with_qsub2_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)) |<br class="">
- (1u << (AArch64::QQQQRegClassID - 32)) |<br class="">
- (1u << (AArch64::QQQQ_with_qsub0_in_<wbr class="">FPR128_loRegClassID - 32)) |<br class="">
- (1u << (AArch64::QQQQ_with_qsub1_in_<wbr class="">FPR128_loRegClassID - 32)) |<br class="">
- (1u << (AArch64::QQQQ_with_qsub2_in_<wbr class="">FPR128_loRegClassID - 32)) |<br class="">
- (1u << (AArch64::QQQQ_with_qsub3_in_<wbr class="">FPR128_loRegClassID - 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQQQ_with_qsub0_in_FPR128_lo_<wbr class="">and_QQQQ_with_qsub1_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQQQ_with_qsub1_in_FPR128_lo_<wbr class="">and_QQQQ_with_qsub2_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQQQ_with_qsub2_in_FPR128_lo_<wbr class="">and_QQQQ_with_qsub3_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQQQ_with_qsub0_in_FPR128_lo_<wbr class="">and_QQQQ_with_qsub2_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQQQ_with_qsub1_in_FPR128_lo_<wbr class="">and_QQQQ_with_qsub3_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQQQ_with_qsub0_in_FPR128_lo_<wbr class="">and_QQQQ_with_qsub3_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQ_with_qsub0_in_FPR128_lo_<wbr class="">and_QQ_with_qsub1_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)) |<br class="">
- (1u << (AArch64::QQQRegClassID - 32)) |<br class="">
- (1u << (AArch64::QQQ_with_qsub0_in_<wbr class="">FPR128_loRegClassID - 32)) |<br class="">
- (1u << (AArch64::QQQ_with_qsub1_in_<wbr class="">FPR128_loRegClassID - 32)) |<br class="">
- (1u << (AArch64::QQQ_with_qsub2_in_<wbr class="">FPR128_loRegClassID - 32)) |<br class="">
- (1u<br class="">
- << (AArch64::<br class="">
- QQQ_with_qsub0_in_FPR128_lo_<wbr class="">and_QQQ_with_qsub1_in_FPR128_<wbr class="">loRegClassID -<br class="">
- 32)),<br class="">
- // FIXME: The entries below this point can be safely removed once this<br class="">
- // is tablegenerated. It's only needed because of the hardcoded register<br class="">
- // class limit.<br class="">
- // Classes 64-96<br class="">
- 0,<br class="">
- // Classes 97-128<br class="">
- 0,<br class="">
- // Classes 129-160<br class="">
- 0,<br class="">
- // Classes 161-192<br class="">
- 0,<br class="">
- // Classes 193-224<br class="">
- 0,<br class="">
-};<br class="">
-<br class="">
-const uint32_t CCRCoverageData[] = {<br class="">
- // Classes 0-31<br class="">
- 1u << AArch64::CCRRegClassID,<br class="">
- // Classes 32-63<br class="">
- 0,<br class="">
- // FIXME: The entries below this point can be safely removed once this<br class="">
- // is tablegenerated. It's only needed because of the hardcoded register<br class="">
- // class limit.<br class="">
- // Classes 64-96<br class="">
- 0,<br class="">
- // Classes 97-128<br class="">
- 0,<br class="">
- // Classes 129-160<br class="">
- 0,<br class="">
- // Classes 161-192<br class="">
- 0,<br class="">
- // Classes 193-224<br class="">
- 0,<br class="">
-};<br class="">
-<br class="">
-RegisterBank GPRRegBank(AArch64::<wbr class="">GPRRegBankID, "GPR", 64, GPRCoverageData);<br class="">
-RegisterBank FPRRegBank(AArch64::<wbr class="">FPRRegBankID, "FPR", 512, FPRCoverageData);<br class="">
-RegisterBank CCRRegBank(AArch64::<wbr class="">CCRRegBankID, "CCR", 32, CCRCoverageData);<br class="">
-} // end namespace AArch64<br class="">
-<br class="">
-RegisterBank *AArch64GenRegisterBankInfo::<wbr class="">RegBanks[] = {<br class="">
- &AArch64::GPRRegBank, &AArch64::FPRRegBank, &AArch64::CCRRegBank};<br class="">
-<br class="">
RegisterBankInfo::<wbr class="">PartialMapping AArch64GenRegisterBankInfo::<wbr class="">PartMappings[]{<br class="">
/* StartIdx, Length, RegBank */<br class="">
- // 0: GPR 32-bit value.<br class="">
- {0, 32, AArch64::GPRRegBank},<br class="">
- // 1: GPR 64-bit value.<br class="">
- {0, 64, AArch64::GPRRegBank},<br class="">
- // 2: FPR 32-bit value.<br class="">
+ // 0: FPR 32-bit value.<br class="">
{0, 32, AArch64::FPRRegBank},<br class="">
- // 3: FPR 64-bit value.<br class="">
+ // 1: FPR 64-bit value.<br class="">
{0, 64, AArch64::FPRRegBank},<br class="">
- // 4: FPR 128-bit value.<br class="">
+ // 2: FPR 128-bit value.<br class="">
{0, 128, AArch64::FPRRegBank},<br class="">
- // 5: FPR 256-bit value.<br class="">
+ // 3: FPR 256-bit value.<br class="">
{0, 256, AArch64::FPRRegBank},<br class="">
- // 6: FPR 512-bit value.<br class="">
- {0, 512, AArch64::FPRRegBank}};<br class="">
+ // 4: FPR 512-bit value.<br class="">
+ {0, 512, AArch64::FPRRegBank},<br class="">
+ // 5: GPR 32-bit value.<br class="">
+ {0, 32, AArch64::GPRRegBank},<br class="">
+ // 6: GPR 64-bit value.<br class="">
+ {0, 64, AArch64::GPRRegBank},<br class="">
+};<br class="">
<br class="">
// ValueMappings.<br class="">
RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::<wbr class="">ValMappings[]{<br class="">
/* BreakDown, NumBreakDowns */<br class="">
// 3-operands instructions (all binary operations should end up with one of<br class="">
// those mapping).<br class="">
- // 0: GPR 32-bit value. <-- This must match First3OpsIdx.<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR32 - PMI_Min], 1},<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR32 - PMI_Min], 1},<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR32 - PMI_Min], 1},<br class="">
- // 3: GPR 64-bit value.<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1},<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1},<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1},<br class="">
- // 6: FPR 32-bit value.<br class="">
+ // 0: FPR 32-bit value. <-- This must match First3OpsIdx.<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR32 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR32 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR32 - PMI_Min], 1},<br class="">
- // 9: FPR 64-bit value.<br class="">
+ // 3: FPR 64-bit value.<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR64 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR64 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR64 - PMI_Min], 1},<br class="">
- // 12: FPR 128-bit value.<br class="">
+ // 6: FPR 128-bit value.<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR128 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR128 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR128 - PMI_Min], 1},<br class="">
- // 15: FPR 256-bit value.<br class="">
+ // 9: FPR 256-bit value.<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR256 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR256 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR256 - PMI_Min], 1},<br class="">
- // 18: FPR 512-bit value. <-- This must match Last3OpsIdx.<br class="">
+ // 12: FPR 512-bit value.<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR512 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR512 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR512 - PMI_Min], 1},<br class="">
+ // 15: GPR 32-bit value.<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR32 - PMI_Min], 1},<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR32 - PMI_Min], 1},<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR32 - PMI_Min], 1},<br class="">
+ // 18: GPR 64-bit value. <-- This must match Last3OpsIdx.<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1},<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1},<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1},<br class="">
// Cross register bank copies.<br class="">
- // 21: GPR 32-bit value to FPR 32-bit value. <-- This must match<br class="">
+ // 21: FPR 32-bit value to GPR 32-bit value. <-- This must match<br class="">
// FirstCrossRegCpyIdx.<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR32 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR32 - PMI_Min], 1},<br class="">
- // 23: GPR 64-bit value to FPR 64-bit value.<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1},<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR32 - PMI_Min], 1},<br class="">
+ // 23: FPR 64-bit value to GPR 64-bit value.<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR64 - PMI_Min], 1},<br class="">
- // 25: FPR 32-bit value to GPR 32-bit value.<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR32 - PMI_Min], 1},<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1},<br class="">
+ // 25: FPR 128-bit value to GPR 128-bit value (invalid)<br class="">
+ {nullptr, 1},<br class="">
+ {nullptr, 1},<br class="">
+ // 27: FPR 256-bit value to GPR 256-bit value (invalid)<br class="">
+ {nullptr, 1},<br class="">
+ {nullptr, 1},<br class="">
+ // 29: FPR 512-bit value to GPR 512-bit value (invalid)<br class="">
+ {nullptr, 1},<br class="">
+ {nullptr, 1},<br class="">
+ // 31: GPR 32-bit value to FPR 32-bit value.<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR32 - PMI_Min], 1},<br class="">
- // 27: FPR 64-bit value to GPR 64-bit value. <-- This must match<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR32 - PMI_Min], 1},<br class="">
+ // 33: GPR 64-bit value to FPR 64-bit value. <-- This must match<br class="">
// LastCrossRegCpyIdx.<br class="">
+ {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1},<br class="">
{&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_FPR64 - PMI_Min], 1},<br class="">
- {&AArch64GenRegisterBankInfo::<wbr class="">PartMappings[PMI_GPR64 - PMI_Min], 1}<br class="">
};<br class="">
<br class="">
bool AArch64GenRegisterBankInfo::<wbr class="">checkPartialMap(unsigned Idx,<br class="">
@@ -301,9 +178,9 @@ AArch64GenRegisterBankInfo::<wbr class="">getValueMapp<br class="">
<br class="">
AArch64GenRegisterBankInfo::<wbr class="">PartialMappingIdx<br class="">
AArch64GenRegisterBankInfo::<wbr class="">BankIDToCopyMapIdx[]{<br class="">
- PMI_FirstGPR, // GPR<br class="">
- PMI_FirstFPR, // FPR<br class="">
PMI_None, // CCR<br class="">
+ PMI_FirstFPR, // FPR<br class="">
+ PMI_FirstGPR, // GPR<br class="">
};<br class="">
<br class="">
const RegisterBankInfo::ValueMapping *<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBankInfo.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/<wbr class="">AArch64RegisterBankInfo.cpp?<wbr class="">rev=292478&r1=292477&r2=<wbr class="">292478&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBankInfo.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBankInfo.cpp Thu Jan 19 05:15:55 2017<br class="">
@@ -21,6 +21,9 @@<br class="">
#include "llvm/Target/<wbr class="">TargetRegisterInfo.h"<br class="">
#include "llvm/Target/<wbr class="">TargetSubtargetInfo.h"<br class="">
<br class="">
+#define GET_TARGET_REGBANK_IMPL<br class="">
+#include "AArch64GenRegisterBank.inc"<br class="">
+<br class="">
// This file will be TableGen'ed at some point.<br class="">
#include "AArch64GenRegisterBankInfo.<wbr class="">def"<br class="">
<br class="">
@@ -30,9 +33,6 @@ using namespace llvm;<br class="">
#error "You shouldn't build this"<br class="">
#endif<br class="">
<br class="">
-AArch64GenRegisterBankInfo::<wbr class="">AArch64GenRegisterBankInfo()<br class="">
- : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) {}<br class="">
-<br class="">
AArch64RegisterBankInfo::<wbr class="">AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)<br class="">
: AArch64GenRegisterBankInfo() {<br class="">
static bool AlreadyInit = false;<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBankInfo.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/<wbr class="">AArch64RegisterBankInfo.h?rev=<wbr class="">292478&r1=292477&r2=292478&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBankInfo.h (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64RegisterBankInfo.h Thu Jan 19 05:15:55 2017<br class="">
@@ -16,40 +16,30 @@<br class="">
<br class="">
#include "llvm/CodeGen/GlobalISel/<wbr class="">RegisterBankInfo.h"<br class="">
<br class="">
+#define GET_REGBANK_DECLARATIONS<br class="">
+#include "AArch64GenRegisterBank.inc"<br class="">
+<br class="">
namespace llvm {<br class="">
<br class="">
class TargetRegisterInfo;<br class="">
<br class="">
-namespace AArch64 {<br class="">
-enum {<br class="">
- GPRRegBankID = 0, /// General Purpose Registers: W, X.<br class="">
- FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.<br class="">
- CCRRegBankID = 2, /// Conditional register: NZCV.<br class="">
- NumRegisterBanks<br class="">
-};<br class="">
-} // End AArch64 namespace.<br class="">
-<br class="">
class AArch64GenRegisterBankInfo : public RegisterBankInfo {<br class="">
-private:<br class="">
- static RegisterBank *RegBanks[];<br class="">
-<br class="">
protected:<br class="">
- AArch64GenRegisterBankInfo();<br class="">
<br class="">
enum PartialMappingIdx {<br class="">
PMI_None = -1,<br class="">
- PMI_GPR32 = 1,<br class="">
- PMI_GPR64,<br class="">
- PMI_FPR32,<br class="">
+ PMI_FPR32 = 1,<br class="">
PMI_FPR64,<br class="">
PMI_FPR128,<br class="">
PMI_FPR256,<br class="">
PMI_FPR512,<br class="">
+ PMI_GPR32,<br class="">
+ PMI_GPR64,<br class="">
PMI_FirstGPR = PMI_GPR32,<br class="">
PMI_LastGPR = PMI_GPR64,<br class="">
PMI_FirstFPR = PMI_FPR32,<br class="">
PMI_LastFPR = PMI_FPR512,<br class="">
- PMI_Min = PMI_FirstGPR,<br class="">
+ PMI_Min = PMI_FirstFPR,<br class="">
};<br class="">
<br class="">
static RegisterBankInfo::<wbr class="">PartialMapping PartMappings[];<br class="">
@@ -61,7 +51,7 @@ protected:<br class="">
Last3OpsIdx = 18,<br class="">
DistanceBetweenRegBanks = 3,<br class="">
FirstCrossRegCpyIdx = 21,<br class="">
- LastCrossRegCpyIdx = 27,<br class="">
+ LastCrossRegCpyIdx = 33,<br class="">
DistanceBetweenCrossRegCpy = 2<br class="">
};<br class="">
<br class="">
@@ -90,6 +80,9 @@ protected:<br class="">
/// register bank with a size of \p Size.<br class="">
static const RegisterBankInfo::ValueMapping *<br class="">
getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);<br class="">
+<br class="">
+#define GET_TARGET_REGBANK_CLASS<br class="">
+#include "AArch64GenRegisterBank.inc"<br class="">
};<br class="">
<br class="">
/// This class provides the information for the target register banks.<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64TargetMachine.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/AArch64TargetMachine.<wbr class="">cpp?rev=292478&r1=292477&r2=<wbr class="">292478&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64TargetMachine.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">AArch64TargetMachine.cpp Thu Jan 19 05:15:55 2017<br class="">
@@ -14,7 +14,9 @@<br class="">
#include "AArch64CallLowering.h"<br class="">
#include "AArch64InstructionSelector.h"<br class="">
#include "AArch64LegalizerInfo.h"<br class="">
+#ifdef LLVM_BUILD_GLOBAL_ISEL<br class="">
#include "AArch64RegisterBankInfo.h"<br class="">
+#endif<br class="">
#include "AArch64Subtarget.h"<br class="">
#include "AArch64TargetMachine.h"<br class="">
#include "AArch64TargetObjectFile.h"<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<wbr class="">CMakeLists.txt<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">AArch64/CMakeLists.txt?rev=<wbr class="">292478&r1=292477&r2=292478&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<wbr class="">CMakeLists.txt (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<wbr class="">CMakeLists.txt Thu Jan 19 05:15:55 2017<br class="">
@@ -14,6 +14,7 @@ tablegen(LLVM AArch64GenSubtargetInfo.in<br class="">
tablegen(LLVM AArch64GenDisassemblerTables.<wbr class="">inc -gen-disassembler)<br class="">
tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)<br class="">
if(LLVM_BUILD_GLOBAL_ISEL)<br class="">
+ tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)<br class="">
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)<br class="">
endif()<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/ARM/<wbr class="">ARMRegisterBankInfo.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">ARM/ARMRegisterBankInfo.cpp?<wbr class="">rev=292478&r1=292477&r2=<wbr class="">292478&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/ARM/<wbr class="">ARMRegisterBankInfo.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/ARM/<wbr class="">ARMRegisterBankInfo.cpp Thu Jan 19 05:15:55 2017<br class="">
@@ -55,7 +55,9 @@ const uint32_t GPRCoverageData[] = {<br class="">
0,<br class="">
};<br class="">
<br class="">
-RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);<br class="">
+// FIXME: The 200 will be replaced by the number of register classes when this is<br class="">
+// tablegenerated.<br class="">
+RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData, 200);<br class="">
RegisterBank *RegBanks[] = {&GPRRegBank};<br class="">
<br class="">
RegisterBankInfo::<wbr class="">PartialMapping GPRPartialMapping{0, 32, GPRRegBank};<br class="">
<br class="">
Modified: llvm/trunk/utils/TableGen/<wbr class="">CMakeLists.txt<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/utils/<wbr class="">TableGen/CMakeLists.txt?rev=<wbr class="">292478&r1=292477&r2=292478&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/utils/TableGen/<wbr class="">CMakeLists.txt (original)<br class="">
+++ llvm/trunk/utils/TableGen/<wbr class="">CMakeLists.txt Thu Jan 19 05:15:55 2017<br class="">
@@ -27,6 +27,7 @@ add_tablegen(llvm-tblgen LLVM<br class="">
IntrinsicEmitter.cpp<br class="">
OptParserEmitter.cpp<br class="">
PseudoLoweringEmitter.cpp<br class="">
+ RegisterBankEmitter.cpp<br class="">
RegisterInfoEmitter.cpp<br class="">
SearchableTableEmitter.cpp<br class="">
SubtargetEmitter.cpp<br class="">
<br class="">
Copied: llvm/trunk/utils/TableGen/<wbr class="">RegisterBankEmitter.cpp (from r292368, llvm/trunk/utils/TableGen/<wbr class="">RegisterBankEmitter.cpp)<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp?p2=llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp&p1=llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp&r1=292368&r2=292478&rev=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/utils/<wbr class="">TableGen/RegisterBankEmitter.<wbr class="">cpp?p2=llvm/trunk/utils/<wbr class="">TableGen/RegisterBankEmitter.<wbr class="">cpp&p1=llvm/trunk/utils/<wbr class="">TableGen/RegisterBankEmitter.<wbr class="">cpp&r1=292368&r2=292478&rev=<wbr class="">292478&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/utils/TableGen/<wbr class="">RegisterBankEmitter.cpp (original)<br class="">
+++ llvm/trunk/utils/TableGen/<wbr class="">RegisterBankEmitter.cpp Thu Jan 19 05:15:55 2017<br class="">
@@ -173,7 +173,8 @@ static void visitRegisterBankClasses(<br class="">
VisitFn(RC, Kind.str());<br class="">
<br class="">
for (const auto &PossibleSubclass : RegisterClassHierarchy.<wbr class="">getRegClasses()) {<br class="">
- Twine TmpKind = Kind + " (" + PossibleSubclass.getName() + ")";<br class="">
+ std::string TmpKind =<br class="">
+ (Twine(Kind) + " (" + PossibleSubclass.getName() + ")").str();<br class="">
<br class="">
// Visit each subclass of an explicitly named class.<br class="">
if (RC != &PossibleSubclass && RC->hasSubClass(&<wbr class="">PossibleSubclass))<br class="">
@@ -191,9 +192,10 @@ static void visitRegisterBankClasses(<br class="">
BitVector BV(RegisterClassHierarchy.<wbr class="">getRegClasses().size());<br class="">
PossibleSubclass.<wbr class="">getSuperRegClasses(&SubIdx, BV);<br class="">
if (BV.test(RC->EnumValue)) {<br class="">
- Twine TmpKind2 = TmpKind + " " + RC->getName() +<br class="">
- " class-with-subregs: " + RC->getName();<br class="">
- VisitFn(&PossibleSubclass, TmpKind2.str());<br class="">
+ std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +<br class="">
+ " class-with-subregs: " + RC->getName())<br class="">
+ .str();<br class="">
+ VisitFn(&PossibleSubclass, TmpKind2);<br class="">
}<br class="">
}<br class="">
}<br class="">
@@ -217,8 +219,8 @@ void RegisterBankEmitter::<wbr class="">emitBaseClassI<br class="">
for (const auto &RCs : RCsGroupedByWord) {<br class="">
OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";<br class="">
for (const auto &RC : RCs) {<br class="">
- Twine QualifiedRegClassID =<br class="">
- TargetName + "::" + RC->getName() + "RegClassID";<br class="">
+ std::string QualifiedRegClassID =<br class="">
+ (Twine(TargetName) + "::" + RC->getName() + "RegClassID").str();<br class="">
OS << " (1u << (" << QualifiedRegClassID << " - "<br class="">
<< LowestIdxInWord << ")) |\n";<br class="">
}<br class="">
@@ -230,7 +232,8 @@ void RegisterBankEmitter::<wbr class="">emitBaseClassI<br class="">
OS << "\n";<br class="">
<br class="">
for (const auto &Bank : Banks) {<br class="">
- Twine QualifiedBankID = TargetName + "::" + Bank.getEnumeratorName();<br class="">
+ std::string QualifiedBankID =<br class="">
+ (TargetName + "::" + Bank.getEnumeratorName()).str(<wbr class="">);<br class="">
unsigned Size = Bank.getRCWithLargestRegsSize(<wbr class="">)->SpillSize;<br class="">
OS << "RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "<br class="">
<< QualifiedBankID << ", /* Name */ \"" << Bank.getName()<br class="">
<br class="">
Modified: llvm/trunk/utils/TableGen/<wbr class="">TableGen.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/utils/<wbr class="">TableGen/TableGen.cpp?rev=<wbr class="">292478&r1=292477&r2=292478&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/utils/TableGen/<wbr class="">TableGen.cpp (original)<br class="">
+++ llvm/trunk/utils/TableGen/<wbr class="">TableGen.cpp Thu Jan 19 05:15:55 2017<br class="">
@@ -46,6 +46,7 @@ enum ActionType {<br class="">
GenAttributes,<br class="">
GenSearchableTables,<br class="">
GenGlobalISel,<br class="">
+ GenRegisterBank,<br class="">
};<br class="">
<br class="">
namespace {<br class="">
@@ -94,7 +95,9 @@ namespace {<br class="">
clEnumValN(<wbr class="">GenSearchableTables, "gen-searchable-tables",<br class="">
"Generate generic binary-searchable table"),<br class="">
clEnumValN(GenGlobalISel, "gen-global-isel",<br class="">
- "Generate GlobalISel selector")));<br class="">
+ "Generate GlobalISel selector"),<br class="">
+ clEnumValN(GenRegisterBank, "gen-register-bank",<br class="">
+ "Generate registers bank descriptions")));<br class="">
<br class="">
cl::opt<std::string><br class="">
Class("class", cl::desc("Print Enum list for this class"),<br class="">
@@ -182,6 +185,8 @@ bool LLVMTableGenMain(raw_ostream &OS, R<br class="">
break;<br class="">
case GenGlobalISel:<br class="">
EmitGlobalISel(Records, OS);<br class="">
+ case GenRegisterBank:<br class="">
+ EmitRegisterBank(Records, OS);<br class="">
break;<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/utils/TableGen/<wbr class="">TableGenBackends.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGenBackends.h?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/utils/<wbr class="">TableGen/TableGenBackends.h?<wbr class="">rev=292478&r1=292477&r2=<wbr class="">292478&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/utils/TableGen/<wbr class="">TableGenBackends.h (original)<br class="">
+++ llvm/trunk/utils/TableGen/<wbr class="">TableGenBackends.h Thu Jan 19 05:15:55 2017<br class="">
@@ -81,6 +81,7 @@ void EmitCTags(RecordKeeper &RK, raw_ost<br class="">
void EmitAttributes(RecordKeeper &RK, raw_ostream &OS);<br class="">
void EmitSearchableTables(<wbr class="">RecordKeeper &RK, raw_ostream &OS);<br class="">
void EmitGlobalISel(RecordKeeper &RK, raw_ostream &OS);<br class="">
+void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);<br class="">
<br class="">
} // End llvm namespace<br class="">
<br class="">
<br class="">
<br class="">
______________________________<wbr class="">_________________<br class="">
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