<div dir="ltr">Please ignore my previous email, I just saw that Chandler fixed the test in r292774. The bot is green again!<div><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On 23 January 2017 at 10:58, Alex L <span dir="ltr"><<a href="mailto:arphaman@gmail.com" target="_blank">arphaman@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hi Benjamin,<div><br></div><div>I believe that this commit r292761 caused the failure of "<span style="color:rgb(51,51,51);font-size:13px;white-space:pre-wrap">Analysis/ScalarEvolution/<wbr>incorrect-offset-scaling.ll"</span> <wbr>in our Verify-Machineinstrs_AArch64 bot. The build the started failing at <a href="http://lab.llvm.org:8080/green/job/Verify-Machineinstrs_AArch64/3240/" target="_blank">http://lab.llvm.org:8080/gr<wbr>een/job/Verify-Machineinstrs_<wbr>AArch64/3240/</a> . I noticed that you committed r292762 to fix some bot issues, but unfortunately it didn't fix the issue with this bot, as evidenced by the next build at <a href="http://lab.llvm.org:8080/green/job/Verify-Machineinstrs_AArch64/3241/" target="_blank">http://lab.llvm.org:8080/<wbr>green/job/Verify-<wbr>Machineinstrs_AArch64/3241/</a> . Would you be able to fix this issue?</div><div><div><br></div><div>Let me know if you need anything else,</div><div>Alex</div><div><br></div></div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On 22 January 2017 at 20:28, Benjamin Kramer via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: d0k<br>
Date: Sun Jan 22 14:28:56 2017<br>
New Revision: 292761<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=292761&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=292761&view=rev</a><br>
Log:<br>
Fix some broken CHECK lines.<br>
<br>
The colon is important.<br>
<br>
Modified:<br>
llvm/trunk/test/Analysis/Diver<wbr>genceAnalysis/AMDGPU/kernel-<wbr>args.ll<br>
llvm/trunk/test/Analysis/Scala<wbr>rEvolution/incorrect-offset-<wbr>scaling.ll<br>
llvm/trunk/test/CodeGen/AArch6<wbr>4/GlobalISel/legalize-constant<wbr>.mir<br>
llvm/trunk/test/CodeGen/AArch6<wbr>4/arm64-inline-asm.ll<br>
llvm/trunk/test/CodeGen/AArch6<wbr>4/regress-tblgen-chains.ll<br>
llvm/trunk/test/CodeGen/AMDGPU<wbr>/gv-offset-folding.ll<br>
llvm/trunk/test/CodeGen/AMDGPU<wbr>/promote-alloca-volatile.ll<br>
llvm/trunk/test/CodeGen/Mips/c<wbr>ompactbranches/compact-branche<wbr>s.ll<br>
llvm/trunk/test/CodeGen/NVPTX/<wbr>intrinsics.ll<br>
llvm/trunk/test/CodeGen/PowerP<wbr>C/ppc-shrink-wrapping.ll<br>
llvm/trunk/test/CodeGen/PowerP<wbr>C/vec_absd.ll<br>
llvm/trunk/test/CodeGen/PowerP<wbr>C/vsx-p9.ll<br>
llvm/trunk/test/CodeGen/X86/se<wbr>lect_meta.ll<br>
llvm/trunk/test/CodeGen/X86/ta<wbr>il-merge-unreachable.ll<br>
llvm/trunk/test/CodeGen/X86/un<wbr>reachableblockelim.ll<br>
llvm/trunk/test/CodeGen/X86/x8<wbr>6-sanitizer-shrink-wrapping.ll<br>
llvm/trunk/test/Feature/Operan<wbr>dBundles/dse.ll<br>
llvm/trunk/test/MC/AArch64/neo<wbr>n-add-sub-instructions.s<br>
llvm/trunk/test/MC/ARM/ldr-pse<wbr>udo-cond-darwin.s<br>
llvm/trunk/test/MC/ARM/ldr-pse<wbr>udo-cond.s<br>
llvm/trunk/test/MC/Mips/macro-<wbr>li.s<br>
llvm/trunk/test/MC/Mips/microm<wbr>ips32r6/valid.s<br>
llvm/trunk/test/MC/Mips/microm<wbr>ips64r6/valid.s<br>
llvm/trunk/test/Transforms/Glo<wbr>balOpt/externally-initialized-<wbr>aggregate.ll<br>
llvm/trunk/test/Transforms/Ins<wbr>tCombine/convergent.ll<br>
llvm/trunk/test/Transforms/Loo<wbr>pIdiom/unroll.ll<br>
llvm/trunk/test/Transforms/PGO<wbr>Profile/multiple_hash_profile.<wbr>ll<br>
llvm/trunk/test/Transforms/Uti<wbr>l/simplify-dbg-declare-load.ll<br>
<br>
Modified: llvm/trunk/test/Analysis/Diver<wbr>genceAnalysis/AMDGPU/kernel-<wbr>args.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/Analysis<wbr>/DivergenceAnalysis/AMDGPU/<wbr>kernel-args.ll?rev=292761&r1=<wbr>292760&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Analysis/Diver<wbr>genceAnalysis/AMDGPU/kernel-<wbr>args.ll (original)<br>
+++ llvm/trunk/test/Analysis/Diver<wbr>genceAnalysis/AMDGPU/kernel-<wbr>args.ll Sun Jan 22 14:28:56 2017<br>
@@ -3,7 +3,7 @@<br>
; CHECK: DIVERGENT:<br>
; CHECK-NOT: %arg0<br>
; CHECK-NOT: %arg1<br>
-; CHECK-NOT; %arg2<br>
+; CHECK-NOT: %arg2<br>
; CHECK: <2 x i32> %arg3<br>
; CHECK: DIVERGENT: <3 x i32> %arg4<br>
; CHECK: DIVERGENT: float %arg5<br>
<br>
Modified: llvm/trunk/test/Analysis/Scala<wbr>rEvolution/incorrect-offset-<wbr>scaling.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/incorrect-offset-scaling.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/Analysis<wbr>/ScalarEvolution/incorrect-<wbr>offset-scaling.ll?rev=292761&<wbr>r1=292760&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Analysis/Scala<wbr>rEvolution/incorrect-offset-<wbr>scaling.ll (original)<br>
+++ llvm/trunk/test/Analysis/Scala<wbr>rEvolution/incorrect-offset-<wbr>scaling.ll Sun Jan 22 14:28:56 2017<br>
@@ -36,13 +36,13 @@ ib:<br>
%r4 = mul i64 %r3, %r0<br>
%r5 = add i64 %r2, %r4<br>
%r6 = icmp ult i64 %r5, undef<br>
-; CHECK %2 = mul i64 %lsr.iv, %r3<br>
-; CHECK %3 = add i64 %1, -1<br>
-; CHECK %4 = add i64 %0, %r3<br>
-; CHECK %r6<br>
+; CHECK: %2 = mul i64 %lsr.iv, %r3<br>
+; CHECK: %3 = add i64 %2, -1<br>
+; CHECK: %4 = add i64 %0, %3<br>
+; CHECK: %r6<br>
%r7 = getelementptr i64, i64* undef, i64 %r5<br>
store i64 1, i64* %r7, align 8<br>
-; CHECK %5 = mul i64 %lsr.iv, %r3<br>
-; CHECK %6 = add i64 %5, -1<br>
+; CHECK: %5 = mul i64 %lsr.iv, %r3<br>
+; CHECK: %6 = add i64 %5, -1<br>
br label %L<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch6<wbr>4/GlobalISel/legalize-constant<wbr>.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>AArch64/GlobalISel/legalize-<wbr>constant.mir?rev=292761&r1=<wbr>292760&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/AArch6<wbr>4/GlobalISel/legalize-constant<wbr>.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AArch6<wbr>4/GlobalISel/legalize-constant<wbr>.mir Sun Jan 22 14:28:56 2017<br>
@@ -57,7 +57,7 @@ body: |<br>
; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00<br>
; CHECK: %1(s64) = G_FCONSTANT double 2.000000e+00<br>
; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000<br>
- ; CHECK; %2(s16) = G_FPTRUNC [[TMP]]<br>
+ ; CHECK: %2(s16) = G_FPTRUNC [[TMP]]<br>
<br>
%0(s32) = G_FCONSTANT float 1.0<br>
%1(s64) = G_FCONSTANT double 2.0<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch6<wbr>4/arm64-inline-asm.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-inline-asm.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>AArch64/arm64-inline-asm.ll?<wbr>rev=292761&r1=292760&r2=<wbr>292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/AArch6<wbr>4/arm64-inline-asm.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch6<wbr>4/arm64-inline-asm.ll Sun Jan 22 14:28:56 2017<br>
@@ -236,14 +236,14 @@ define void @test_zero_reg(i32* %addr) {<br>
define <2 x float> @test_vreg_64bit(<2 x float> %in) nounwind {<br>
; CHECK-LABEL: test_vreg_64bit:<br>
%1 = tail call <2 x float> asm sideeffect "fadd ${0}.2s, ${1}.2s, ${1}.2s", "={v14},w"(<2 x float> %in) nounwind<br>
- ; CHECK fadd v14.2s, v0.2s, v0.2s:<br>
+ ; CHECK: fadd v14.2s, v0.2s, v0.2s<br>
ret <2 x float> %1<br>
}<br>
<br>
define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind {<br>
; CHECK-LABEL: test_vreg_128bit:<br>
%1 = tail call <4 x float> asm sideeffect "fadd ${0}.4s, ${1}.4s, ${1}.4s", "={v14},w"(<4 x float> %in) nounwind<br>
- ; CHECK fadd v14.4s, v0.4s, v0.4s:<br>
+ ; CHECK: fadd v14.4s, v0.4s, v0.4s<br>
ret <4 x float> %1<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch6<wbr>4/regress-tblgen-chains.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/regress-tblgen-chains.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>AArch64/regress-tblgen-chains.<wbr>ll?rev=292761&r1=292760&r2=<wbr>292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/AArch6<wbr>4/regress-tblgen-chains.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch6<wbr>4/regress-tblgen-chains.ll Sun Jan 22 14:28:56 2017<br>
@@ -28,7 +28,7 @@ define i64 @test_chains() {<br>
; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]]<br>
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #1<br>
; CHECK: sturb w[[STRVAL:[0-9]+]], [x29, [[LOCADDR]]]<br>
-; CHECK; and w0, w[[STRVAL]], #0xff<br>
+; CHECK: and w0, w[[STRVAL]], #0xff<br>
<br>
%ret.1 = load i8, i8* %locvar<br>
%ret.2 = zext i8 %ret.1 to i64<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU<wbr>/gv-offset-folding.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/gv-offset-folding.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>AMDGPU/gv-offset-folding.ll?<wbr>rev=292761&r1=292760&r2=<wbr>292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/AMDGPU<wbr>/gv-offset-folding.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU<wbr>/gv-offset-folding.ll Sun Jan 22 14:28:56 2017<br>
@@ -12,7 +12,7 @@<br>
; for local memory globals.<br>
<br>
; CHECK-LABEL: lds_no_offset:<br>
-; CHECK ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:4<br>
+; CHECK: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:4<br>
define void @lds_no_offset() {<br>
entry:<br>
%ptr = getelementptr [4 x i32], [4 x i32] addrspace(3)* @lds, i32 0, i32 1<br>
<br>
Modified: llvm/trunk/test/CodeGen/AMDGPU<wbr>/promote-alloca-volatile.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/promote-alloca-volatile.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>AMDGPU/promote-alloca-volatile<wbr>.ll?rev=292761&r1=292760&r2=<wbr>292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/AMDGPU<wbr>/promote-alloca-volatile.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AMDGPU<wbr>/promote-alloca-volatile.ll Sun Jan 22 14:28:56 2017<br>
@@ -2,7 +2,7 @@<br>
<br>
; CHECK-LABEL: @volatile_load(<br>
; CHECK: alloca [5 x i32]<br>
-; CHECK load volatile i32, i32*<br>
+; CHECK: load volatile i32, i32*<br>
define void @volatile_load(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {<br>
entry:<br>
%stack = alloca [5 x i32], align 4<br>
@@ -15,7 +15,7 @@ entry:<br>
<br>
; CHECK-LABEL: @volatile_store(<br>
; CHECK: alloca [5 x i32]<br>
-; CHECK store volatile i32 %tmp, i32*<br>
+; CHECK: store volatile i32 %tmp, i32*<br>
define void @volatile_store(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {<br>
entry:<br>
%stack = alloca [5 x i32], align 4<br>
<br>
Modified: llvm/trunk/test/CodeGen/Mips/c<wbr>ompactbranches/compact-branche<wbr>s.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/compactbranches/compact-branches.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>Mips/compactbranches/compact-<wbr>branches.ll?rev=292761&r1=<wbr>292760&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Mips/c<wbr>ompactbranches/compact-branche<wbr>s.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Mips/c<wbr>ompactbranches/compact-branche<wbr>s.ll Sun Jan 22 14:28:56 2017<br>
@@ -38,7 +38,7 @@ entry:<br>
; PIC: jalrc $25<br>
%call1 = tail call i32 @i()<br>
%cmp = icmp eq i32 %call, %call1<br>
-; CHECK beqc<br>
+; CHECK: beqc<br>
br i1 %cmp, label %if.end, label %if.then<br>
<br>
if.then: ; preds = %entry:<br>
@@ -61,7 +61,7 @@ entry:<br>
; PIC: jalrc $25<br>
%call = tail call i32 @k()<br>
%cmp = icmp slt i32 %call, 0<br>
-; CHECK : bgez<br>
+; CHECK: bgez<br>
br i1 %cmp, label %if.then, label %if.end<br>
<br>
if.then: ; preds = %entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/NVPTX/<wbr>intrinsics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/intrinsics.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>NVPTX/intrinsics.ll?rev=<wbr>292761&r1=292760&r2=292761&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/NVPTX/<wbr>intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/NVPTX/<wbr>intrinsics.ll Sun Jan 22 14:28:56 2017<br>
@@ -24,7 +24,7 @@ define float @test_nvvm_sqrt(float %a) {<br>
<br>
; CHECK-LABEL: test_llvm_sqrt(<br>
define float @test_llvm_sqrt(float %a) {<br>
-; CHECK sqrt.rn.f32<br>
+; CHECK: sqrt.rn.f32<br>
%val = call float @llvm.sqrt.f32(float %a)<br>
ret float %val<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerP<wbr>C/ppc-shrink-wrapping.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>PowerPC/ppc-shrink-wrapping.<wbr>ll?rev=292761&r1=292760&r2=<wbr>292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/PowerP<wbr>C/ppc-shrink-wrapping.ll (original)<br>
+++ llvm/trunk/test/CodeGen/PowerP<wbr>C/ppc-shrink-wrapping.ll Sun Jan 22 14:28:56 2017<br>
@@ -403,7 +403,7 @@ entry:<br>
; CHECK: [[ELSE_LABEL]]<br>
; CHECK-NEXT: slwi 3, 4, 1<br>
; DISABLE: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload<br>
-; CHECK-NEXT blr<br>
+; CHECK-NEXT: blr<br>
;<br>
define i32 @inlineAsm(i32 %cond, i32 %N) {<br>
entry:<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerP<wbr>C/vec_absd.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_absd.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>PowerPC/vec_absd.ll?rev=<wbr>292761&r1=292760&r2=292761&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/PowerP<wbr>C/vec_absd.ll (original)<br>
+++ llvm/trunk/test/CodeGen/PowerP<wbr>C/vec_absd.ll Sun Jan 22 14:28:56 2017<br>
@@ -18,7 +18,7 @@ entry:<br>
ret <16 x i8> %res<br>
; CHECK-LABEL: @test_byte<br>
; CHECK: vabsdub 2, 2, 3<br>
-; CHECK blr<br>
+; CHECK: blr<br>
}<br>
<br>
define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) {<br>
@@ -27,7 +27,7 @@ entry:<br>
ret <8 x i16> %res<br>
; CHECK-LABEL: @test_half<br>
; CHECK: vabsduh 2, 2, 3<br>
-; CHECK blr<br>
+; CHECK: blr<br>
}<br>
<br>
define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerP<wbr>C/vsx-p9.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx-p9.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>PowerPC/vsx-p9.ll?rev=292761&<wbr>r1=292760&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/PowerP<wbr>C/vsx-p9.ll (original)<br>
+++ llvm/trunk/test/CodeGen/PowerP<wbr>C/vsx-p9.ll Sun Jan 22 14:28:56 2017<br>
@@ -277,8 +277,8 @@ entry:<br>
%0 = tail call <2 x i64> @llvm.ppc.vsx.xvxexpdp(<2 x double> %a)<br>
ret <2 x i64> %0<br>
; CHECK-LABEL: testXVXEXPDP<br>
-; CHECK xvxexpdp 34, 34<br>
-; CHECK blr<br>
+; CHECK: xvxexpdp 34, 34<br>
+; CHECK: blr<br>
}<br>
; Function Attrs: nounwind readnone<br>
declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>)<br>
@@ -289,8 +289,8 @@ entry:<br>
%0 = tail call <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float> %a)<br>
ret <4 x i32> %0<br>
; CHECK-LABEL: testXVXSIGSP<br>
-; CHECK xvxsigsp 34, 34<br>
-; CHECK blr<br>
+; CHECK: xvxsigsp 34, 34<br>
+; CHECK: blr<br>
}<br>
; Function Attrs: nounwind readnone<br>
declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>)<br>
@@ -301,8 +301,8 @@ entry:<br>
%0 = tail call <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double> %a)<br>
ret <2 x i64> %0<br>
; CHECK-LABEL: testXVXSIGDP<br>
-; CHECK xvxsigdp 34, 34<br>
-; CHECK blr<br>
+; CHECK: xvxsigdp 34, 34<br>
+; CHECK: blr<br>
}<br>
; Function Attrs: nounwind readnone<br>
declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/se<wbr>lect_meta.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select_meta.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/select_meta.ll?rev=292761&<wbr>r1=292760&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/se<wbr>lect_meta.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/se<wbr>lect_meta.ll Sun Jan 22 14:28:56 2017<br>
@@ -13,4 +13,4 @@ define i32 @foo(i32, i32, i32) {<br>
<br>
!0 = !{!"clang version 4.0.0 (trunk 279683)"}<br>
!1 = !{!"branch_weights", i32 1000, i32 1 }<br>
-; CHECK ![[WT]] = !{!"branch_weights", i32 1000, i32 1 }<br>
+; CHECK: ![[WT]] = !{!"branch_weights", i32 1000, i32 1}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/ta<wbr>il-merge-unreachable.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-merge-unreachable.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/tail-merge-unreachable.ll?<wbr>rev=292761&r1=292760&r2=<wbr>292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/ta<wbr>il-merge-unreachable.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/ta<wbr>il-merge-unreachable.ll Sun Jan 22 14:28:56 2017<br>
@@ -29,6 +29,6 @@ end:<br>
; CHECK: [[JUMP_TABLE_BLOCK]]:<br>
; CHECK: btl<br>
; CHECK: jae [[UNREACHABLE_BLOCK:[.][A-Za-z<wbr>0-9_]+]]<br>
-; CHECK [[UNREACHABLE_BLOCK]]:<br>
+; CHECK: [[UNREACHABLE_BLOCK]]:<br>
; CHECK: .Lfunc_end0<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/un<wbr>reachableblockelim.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/unreachableblockelim.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/unreachableblockelim.ll?<wbr>rev=292761&r1=292760&r2=<wbr>292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/un<wbr>reachableblockelim.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/un<wbr>reachableblockelim.ll Sun Jan 22 14:28:56 2017<br>
@@ -7,7 +7,7 @@ target triple = "x86_64-unknown-linux-gn<br>
declare void @abort()<br>
<br>
; CHECK-LABEL: @foo(<br>
-; CHECK-NOT return:<br>
+; CHECK-NOT: return:<br>
define void @foo(i32* %p) {<br>
entry:<br>
%p.addr = alloca i32*, align 8<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/x8<wbr>6-sanitizer-shrink-wrapping.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-sanitizer-shrink-wrapping.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/CodeGen/<wbr>X86/x86-sanitizer-shrink-<wbr>wrapping.ll?rev=292761&r1=<wbr>292760&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/X86/x8<wbr>6-sanitizer-shrink-wrapping.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/x8<wbr>6-sanitizer-shrink-wrapping.ll Sun Jan 22 14:28:56 2017<br>
@@ -12,7 +12,7 @@ target triple = "x86_64-apple-macosx"<br>
; CHECK: popq<br>
; CHECK-NEXT: retq<br>
; CHECK: movl $40, %edi<br>
-; CHECK-NEXT callq ___asan_report_load4<br>
+; CHECK-NEXT: callq ___asan_report_load4<br>
define void @sanitize() #0 {<br>
entry:<br>
%tmp = load i8, i8* inttoptr (i64 17592186044421 to i8*)<br>
<br>
Modified: llvm/trunk/test/Feature/Operan<wbr>dBundles/dse.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/OperandBundles/dse.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/Feature/<wbr>OperandBundles/dse.ll?rev=<wbr>292761&r1=292760&r2=292761&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Feature/Operan<wbr>dBundles/dse.ll (original)<br>
+++ llvm/trunk/test/Feature/Operan<wbr>dBundles/dse.ll Sun Jan 22 14:28:56 2017<br>
@@ -39,7 +39,7 @@ define void @test_2() {<br>
ret void<br>
<br>
; CHECK: tail call void @f() [ "deopt"(i8* %m) ]<br>
-; CHECK-NEXT ret void<br>
+; CHECK-NEXT: ret void<br>
}<br>
<br>
define i8* @test_3() {<br>
<br>
Modified: llvm/trunk/test/MC/AArch64/neo<wbr>n-add-sub-instructions.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-add-sub-instructions.s?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/MC/AArch<wbr>64/neon-add-sub-instructions.<wbr>s?rev=292761&r1=292760&r2=<wbr>292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/AArch64/neo<wbr>n-add-sub-instructions.s (original)<br>
+++ llvm/trunk/test/MC/AArch64/neo<wbr>n-add-sub-instructions.s Sun Jan 22 14:28:56 2017<br>
@@ -67,7 +67,7 @@<br>
fsub v0.2d, v1.2d, v2.2d<br>
<br>
// CHECK: fsub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0xc2,0x0e]<br>
-// CHECK; fsub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0xc2,0x4e]<br>
+// CHECK: fsub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0xc2,0x4e]<br>
// CHECK: fsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0xa2,0x0e]<br>
// CHECK: fsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0xd4,0xa2,0x4e]<br>
// CHECK: fsub v0.2d, v1.2d, v2.2d // encoding: [0x20,0xd4,0xe2,0x4e]<br>
<br>
Modified: llvm/trunk/test/MC/ARM/ldr-pse<wbr>udo-cond-darwin.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/ldr-pseudo-cond-darwin.s?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/MC/ARM/<wbr>ldr-pseudo-cond-darwin.s?rev=<wbr>292761&r1=292760&r2=292761&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/ARM/ldr-pse<wbr>udo-cond-darwin.s (original)<br>
+++ llvm/trunk/test/MC/ARM/ldr-pse<wbr>udo-cond-darwin.s Sun Jan 22 14:28:56 2017<br>
@@ -37,7 +37,7 @@ f2:<br>
@ CHECK-ARM moveq r2, #520093696<br>
@ CHECK-THUMB2 moveq.w r2, #520093696<br>
ldrne r3, = 0x00001234<br>
-@ CHECK movwne r2, #4660<br>
+@ CHECK: movwne r3, #4660<br>
<br>
@<br>
@ Constant Pools<br>
<br>
Modified: llvm/trunk/test/MC/ARM/ldr-pse<wbr>udo-cond.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/ldr-pseudo-cond.s?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/MC/ARM/<wbr>ldr-pseudo-cond.s?rev=292761&<wbr>r1=292760&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/ARM/ldr-pse<wbr>udo-cond.s (original)<br>
+++ llvm/trunk/test/MC/ARM/ldr-pse<wbr>udo-cond.s Sun Jan 22 14:28:56 2017<br>
@@ -37,7 +37,7 @@ f2:<br>
@ CHECK-ARM moveq r2, #520093696<br>
@ CHECK-THUMB2 moveq.w r2, #520093696<br>
ldrne r3, = 0x00001234<br>
-@ CHECK movwne r2, #4660<br>
+@ CHECK: movwne r3, #4660<br>
<br>
@<br>
@ Constant Pools<br>
<br>
Modified: llvm/trunk/test/MC/Mips/macro-<wbr>li.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/macro-li.s?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/MC/Mips/<wbr>macro-li.s?rev=292761&r1=29276<wbr>0&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/macro-<wbr>li.s (original)<br>
+++ llvm/trunk/test/MC/Mips/macro-<wbr>li.s Sun Jan 22 14:28:56 2017<br>
@@ -65,7 +65,7 @@ li $5, 0xc0008000 # CHECK: lui $5, 49152<br>
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]<br>
li $5, 0x80008000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]<br>
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]<br>
-li $4, ~0xffffffff # CHECK; addiu $4, $zero, 0 # encoding: [0x24,0x04,0x00,0x00]<br>
+li $4, ~0xffffffff # CHECK: addiu $4, $zero, 0 # encoding: [0x24,0x04,0x00,0x00]<br>
li $4, ~0x80000001 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff]<br>
# CHECK: ori $4, $4, 65534 # encoding: [0x34,0x84,0xff,0xfe]<br>
li $4, ~0x80000000 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff]<br>
<br>
Modified: llvm/trunk/test/MC/Mips/microm<wbr>ips32r6/valid.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips32r6/valid.s?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/MC/Mips/<wbr>micromips32r6/valid.s?rev=<wbr>292761&r1=292760&r2=292761&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/microm<wbr>ips32r6/valid.s (original)<br>
+++ llvm/trunk/test/MC/Mips/microm<wbr>ips32r6/valid.s Sun Jan 22 14:28:56 2017<br>
@@ -100,10 +100,10 @@<br>
syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]<br>
mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58]<br>
modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8]<br>
- mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]<br>
- muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]<br>
- mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]<br>
- muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]<br>
+ mul $3, $4, $5 # CHECK: mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]<br>
+ muh $3, $4, $5 # CHECK: muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]<br>
+ mulu $3, $4, $5 # CHECK: mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]<br>
+ muhu $3, $4, $5 # CHECK: muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]<br>
nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]<br>
nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0]<br>
or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]<br>
<br>
Modified: llvm/trunk/test/MC/Mips/microm<wbr>ips64r6/valid.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips64r6/valid.s?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/MC/Mips/<wbr>micromips64r6/valid.s?rev=<wbr>292761&r1=292760&r2=292761&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/MC/Mips/microm<wbr>ips64r6/valid.s (original)<br>
+++ llvm/trunk/test/MC/Mips/microm<wbr>ips64r6/valid.s Sun Jan 22 14:28:56 2017<br>
@@ -269,14 +269,14 @@ a:<br>
dneg $10 # CHECK: dneg $10, $10 # encoding: [0x59,0x40,0x51,0x90]<br>
dnegu $1, $11 # CHECK: dnegu $1, $11 # encoding: [0x59,0x60,0x09,0xd0]<br>
dnegu $5 # CHECK: dnegu $5, $5 # encoding: [0x58,0xa0,0x29,0xd0]<br>
- mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]<br>
- muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]<br>
- mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]<br>
- muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]<br>
- dmul $3, $4, $5 # CHECK dmul $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x18]<br>
- dmuh $3, $4, $5 # CHECK dmuh $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x58]<br>
- dmulu $3, $4, $5 # CHECK dmulu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x98]<br>
- dmuhu $3, $4, $5 # CHECK dmuhu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0xd8]<br>
+ mul $3, $4, $5 # CHECK: mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]<br>
+ muh $3, $4, $5 # CHECK: muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]<br>
+ mulu $3, $4, $5 # CHECK: mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]<br>
+ muhu $3, $4, $5 # CHECK: muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]<br>
+ dmul $3, $4, $5 # CHECK: dmul $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x18]<br>
+ dmuh $3, $4, $5 # CHECK: dmuh $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x58]<br>
+ dmulu $3, $4, $5 # CHECK: dmulu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x98]<br>
+ dmuhu $3, $4, $5 # CHECK: dmuhu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0xd8]<br>
lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]<br>
swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]<br>
dsbh $3, $4 # CHECK: dsbh $3, $4 # encoding: [0x58,0x64,0x7b,0x3c]<br>
<br>
Modified: llvm/trunk/test/Transforms/Glo<wbr>balOpt/externally-initialized-<wbr>aggregate.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalOpt/externally-initialized-aggregate.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/Transfor<wbr>ms/GlobalOpt/externally-<wbr>initialized-aggregate.ll?rev=<wbr>292761&r1=292760&r2=292761&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/Glo<wbr>balOpt/externally-initialized-<wbr>aggregate.ll (original)<br>
+++ llvm/trunk/test/Transforms/Glo<wbr>balOpt/externally-initialized-<wbr>aggregate.ll Sun Jan 22 14:28:56 2017<br>
@@ -5,11 +5,11 @@<br>
; store to @a[0] from being constant propagated to the load in @foo, but will not<br>
; prevent @a[1] from being removed since it is dead.<br>
; CHECK: @a.0 = internal unnamed_addr externally_initialized global i32 undef<br>
-; CHECK-NOT @a.1<br>
+; CHECK-NOT: @a.1<br>
@a = internal externally_initialized global [2 x i32] undef, align 4<br>
; This is the same, but a struct rather than an array.<br>
; CHECK: @b.0 = internal unnamed_addr externally_initialized global i32 undef<br>
-; CHECK-NOT @b.1<br>
+; CHECK-NOT: @b.1<br>
@b = internal externally_initialized global {i32, i32} undef, align 4<br>
<br>
define i32 @foo() {<br>
<br>
Modified: llvm/trunk/test/Transforms/Ins<wbr>tCombine/convergent.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/convergent.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/Transfor<wbr>ms/InstCombine/convergent.ll?<wbr>rev=292761&r1=292760&r2=<wbr>292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/Ins<wbr>tCombine/convergent.ll (original)<br>
+++ llvm/trunk/test/Transforms/Ins<wbr>tCombine/convergent.ll Sun Jan 22 14:28:56 2017<br>
@@ -27,7 +27,7 @@ define i32 @no_extern() {<br>
}<br>
<br>
define i32 @indirect_call(i32 ()* %f) {<br>
- ; CHECK call i32 %f() [[CONVERGENT_ATTR]]<br>
+ ; CHECK: call i32 %f() [[CONVERGENT_ATTR]]<br>
%a = call i32 %f() convergent<br>
ret i32 %a<br>
}<br>
<br>
Modified: llvm/trunk/test/Transforms/Loo<wbr>pIdiom/unroll.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopIdiom/unroll.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/Transfor<wbr>ms/LoopIdiom/unroll.ll?rev=<wbr>292761&r1=292760&r2=292761&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/Loo<wbr>pIdiom/unroll.ll (original)<br>
+++ llvm/trunk/test/Transforms/Loo<wbr>pIdiom/unroll.ll Sun Jan 22 14:28:56 2017<br>
@@ -1,7 +1,7 @@<br>
; RUN: opt -basicaa -loop-idiom < %s -S | FileCheck %s<br>
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i1<wbr>6:16:16-i32:32:32-i64:64:64-f3<wbr>2:32:32-f64:64:64-v64:64:64-v1<wbr>28:128:128-a0:0:64-s0:64:64-f8<wbr>0:128:128-n8:16:32:64"<br>
<br>
-; CHECK @.memset_pattern = private unnamed_addr constant [4 x i32] [i32 2, i32 2, i32 2, i32 2], align 16<br>
+; CHECK: @.memset_pattern = private unnamed_addr constant [4 x i32] [i32 2, i32 2, i32 2, i32 2], align 16<br>
<br>
target triple = "x86_64-apple-darwin10.0.0"<br>
<br>
<br>
Modified: llvm/trunk/test/Transforms/PGO<wbr>Profile/multiple_hash_profile.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/PGOProfile/multiple_hash_profile.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/Transfor<wbr>ms/PGOProfile/multiple_hash_<wbr>profile.ll?rev=292761&r1=<wbr>292760&r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/PGO<wbr>Profile/multiple_hash_profile.<wbr>ll (original)<br>
+++ llvm/trunk/test/Transforms/PGO<wbr>Profile/multiple_hash_profile.<wbr>ll Sun Jan 22 14:28:56 2017<br>
@@ -27,8 +27,8 @@ entry:<br>
%cmp.i = icmp sgt i32 %i, 2<br>
%mul.i = select i1 %cmp.i, i32 1, i32 %i<br>
; CHECK: %mul.i = select i1 %cmp.i, i32 1, i32 %i<br>
-; CHECK-SAME !prof ![[BW:[0-9]+]]<br>
-; CHECK ![[BW]] = !{!"branch_weights", i32 12, i32 6}<br>
+; CHECK-SAME: !prof ![[BW:[0-9]+]]<br>
+; CHECK: ![[BW]] = !{!"branch_weights", i32 12, i32 6}<br>
%retval.0.i = mul nsw i32 %mul.i, %i<br>
ret i32 %retval.0.i<br>
}<br>
<br>
Modified: llvm/trunk/test/Transforms/Uti<wbr>l/simplify-dbg-declare-load.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Util/simplify-dbg-declare-load.ll?rev=292761&r1=292760&r2=292761&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/Transfor<wbr>ms/Util/simplify-dbg-declare-<wbr>load.ll?rev=292761&r1=292760&<wbr>r2=292761&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/Uti<wbr>l/simplify-dbg-declare-load.ll (original)<br>
+++ llvm/trunk/test/Transforms/Uti<wbr>l/simplify-dbg-declare-load.ll Sun Jan 22 14:28:56 2017<br>
@@ -19,7 +19,7 @@ fail:<br>
unreachable<br>
<br>
idxend: ; preds = %top<br>
-; CHECK-NOT call void @llvm.dbg.value(metadata %foo* %cp,<br>
+; CHECK-NOT: call void @llvm.dbg.value(metadata %foo* %cp,<br>
%0 = load volatile %foo, %foo* %cp, align 8<br>
; CHECK: call void @llvm.dbg.value(metadata %foo %0,<br>
store volatile %foo %0, %foo* undef, align 8<br>
<br>
<br>
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</blockquote></div><br></div>
</div></div></blockquote></div><br></div>