<div dir="ltr">Is there any reason why we have llvm/Target/GlobalISel instead of lib/Target/GlobalISel? I guess it just seems a little weird for the LLVM SVN repro to have a folder called "llvm" which is nearly empty.<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jan 19, 2017 at 3:15 AM, Daniel Sanders via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: dsanders<br>
Date: Thu Jan 19 05:15:55 2017<br>
New Revision: 292478<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=292478&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=292478&view=rev</a><br>
Log:<br>
Re-commit: [globalisel] Tablegen-erate current Register Bank Information<br>
<br>
Summary:<br>
Adds a RegisterBank tablegen class that can be used to declare the register<br>
banks and an associated tablegen pass to generate the necessary code.<br>
<br>
Changes since first commit attempt:<br>
* Added missing guards<br>
* Added more missing guards<br>
* Found and fixed a use-after-free bug involving Twine locals<br>
<br>
Reviewers: t.p.northover, ab, rovka, qcolombet<br>
<br>
Reviewed By: qcolombet<br>
<br>
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka<br>
<br>
Differential Revision: <a href="https://reviews.llvm.org/D27338" rel="noreferrer" target="_blank">https://reviews.llvm.org/<wbr>D27338</a><br>
<br>
<br>
Added:<br>
llvm/trunk/include/llvm/<wbr>Target/GlobalISel/<br>
- copied from r292368, llvm/trunk/include/llvm/<wbr>Target/GlobalISel/<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBanks.td<br>
- copied unchanged from r292368, llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBanks.td<br>
llvm/trunk/llvm/<br>
- copied from r292368, llvm/trunk/llvm/<br>
llvm/trunk/utils/TableGen/<wbr>RegisterBankEmitter.cpp<br>
- copied, changed from r292368, llvm/trunk/utils/TableGen/<wbr>RegisterBankEmitter.cpp<br>
Modified:<br>
llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>RegisterBank.h<br>
llvm/trunk/include/llvm/<wbr>Target/Target.td<br>
llvm/trunk/lib/CodeGen/<wbr>GlobalISel/RegisterBank.cpp<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64.td<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64GenRegisterBankInfo.def<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBankInfo.cpp<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBankInfo.h<br>
llvm/trunk/lib/Target/AArch64/<wbr>AArch64TargetMachine.cpp<br>
llvm/trunk/lib/Target/AArch64/<wbr>CMakeLists.txt<br>
llvm/trunk/lib/Target/ARM/<wbr>ARMRegisterBankInfo.cpp<br>
llvm/trunk/utils/TableGen/<wbr>CMakeLists.txt<br>
llvm/trunk/utils/TableGen/<wbr>TableGen.cpp<br>
llvm/trunk/utils/TableGen/<wbr>TableGenBackends.h<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>RegisterBank.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBank.h?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/CodeGen/GlobalISel/<wbr>RegisterBank.h?rev=292478&r1=<wbr>292477&r2=292478&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>RegisterBank.h (original)<br>
+++ llvm/trunk/include/llvm/<wbr>CodeGen/GlobalISel/<wbr>RegisterBank.h Thu Jan 19 05:15:55 2017<br>
@@ -42,7 +42,7 @@ private:<br>
<br>
public:<br>
RegisterBank(unsigned ID, const char *Name, unsigned Size,<br>
- const uint32_t *ContainedRegClasses);<br>
+ const uint32_t *ContainedRegClasses, unsigned NumRegClasses);<br>
<br>
/// Get the identifier of this register bank.<br>
unsigned getID() const { return ID; }<br>
<br>
Modified: llvm/trunk/include/llvm/<wbr>Target/Target.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/include/<wbr>llvm/Target/Target.td?rev=<wbr>292478&r1=292477&r2=292478&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/include/llvm/<wbr>Target/Target.td (original)<br>
+++ llvm/trunk/include/llvm/<wbr>Target/Target.td Thu Jan 19 05:15:55 2017<br>
@@ -1344,4 +1344,5 @@ include "llvm/Target/<wbr>TargetSelectionDAG.<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
// Pull in the common support for Global ISel generation.<br>
//<br>
+include "llvm/Target/GlobalISel/<wbr>RegisterBank.td"<br>
include "llvm/Target/TargetGlobalISel.<wbr>td"<br>
<br>
Modified: llvm/trunk/lib/CodeGen/<wbr>GlobalISel/RegisterBank.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBank.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>CodeGen/GlobalISel/<wbr>RegisterBank.cpp?rev=292478&<wbr>r1=292477&r2=292478&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/CodeGen/<wbr>GlobalISel/RegisterBank.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/<wbr>GlobalISel/RegisterBank.cpp Thu Jan 19 05:15:55 2017<br>
@@ -19,10 +19,11 @@ using namespace llvm;<br>
<br>
const unsigned RegisterBank::InvalidID = UINT_MAX;<br>
<br>
-RegisterBank::RegisterBank(<wbr>unsigned ID, const char *Name, unsigned Size,<br>
- const uint32_t *CoveredClasses)<br>
+RegisterBank::RegisterBank(<br>
+ unsigned ID, const char *Name, unsigned Size,<br>
+ const uint32_t *CoveredClasses, unsigned NumRegClasses)<br>
: ID(ID), Name(Name), Size(Size) {<br>
- ContainedRegClasses.resize(<wbr>200);<br>
+ ContainedRegClasses.resize(<wbr>NumRegClasses);<br>
ContainedRegClasses.<wbr>setBitsInMask(CoveredClasses);<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64.td?rev=292478&<wbr>r1=292477&r2=292478&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64.td (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64.td Thu Jan 19 05:15:55 2017<br>
@@ -127,6 +127,7 @@ def HasV8_2aOps : SubtargetFeature<"v8.2<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
include "AArch64RegisterInfo.td"<br>
+include "AArch64RegisterBanks.td"<br>
include "AArch64CallingConvention.td"<br>
<br>
//===-------------------------<wbr>------------------------------<wbr>---------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64GenRegisterBankInfo.def<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64GenRegisterBankInfo.def?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/<wbr>AArch64GenRegisterBankInfo.<wbr>def?rev=292478&r1=292477&r2=<wbr>292478&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64GenRegisterBankInfo.def (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64GenRegisterBankInfo.def Thu Jan 19 05:15:55 2017<br>
@@ -16,204 +16,81 @@<br>
#endif<br>
<br>
namespace llvm {<br>
-namespace AArch64 {<br>
-<br>
-const uint32_t GPRCoverageData[] = {<br>
- // Classes 0-31<br>
- (1u << AArch64::GPR32allRegClassID) | (1u << AArch64::GPR32RegClassID) |<br>
- (1u << AArch64::GPR32spRegClassID) |<br>
- (1u << AArch64::<wbr>GPR32commonRegClassID) |<br>
- (1u << AArch64::<wbr>GPR32sponlyRegClassID) |<br>
- (1u << AArch64::GPR64allRegClassID) | (1u << AArch64::GPR64RegClassID) |<br>
- (1u << AArch64::GPR64spRegClassID) |<br>
- (1u << AArch64::<wbr>GPR64commonRegClassID) |<br>
- (1u << AArch64::tcGPR64RegClassID) |<br>
- (1u << AArch64::<wbr>GPR64sponlyRegClassID),<br>
- // Classes 32-63<br>
- 0,<br>
- // FIXME: The entries below this point can be safely removed once this is<br>
- // tablegenerated. It's only needed because of the hardcoded register class<br>
- // limit.<br>
- // Classes 64-96<br>
- 0,<br>
- // Classes 97-128<br>
- 0,<br>
- // Classes 129-160<br>
- 0,<br>
- // Classes 161-192<br>
- 0,<br>
- // Classes 193-224<br>
- 0,<br>
-};<br>
-<br>
-const uint32_t FPRCoverageData[] = {<br>
- // Classes 0-31<br>
- (1u << AArch64::FPR8RegClassID) | (1u << AArch64::FPR16RegClassID) |<br>
- (1u << AArch64::FPR32RegClassID) | (1u << AArch64::FPR64RegClassID) |<br>
- (1u << AArch64::DDRegClassID) | (1u << AArch64::FPR128RegClassID) |<br>
- (1u << AArch64::FPR128_loRegClassID) | (1u << AArch64::DDDRegClassID) |<br>
- (1u << AArch64::DDDDRegClassID),<br>
- // Classes 32-63<br>
- (1u << (AArch64::QQRegClassID - 32)) |<br>
- (1u << (AArch64::QQ_with_qsub0_in_<wbr>FPR128_loRegClassID - 32)) |<br>
- (1u << (AArch64::QQ_with_qsub1_in_<wbr>FPR128_loRegClassID - 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQQ_with_qsub1_in_FPR128_lo_<wbr>and_QQQ_with_qsub2_in_FPR128_<wbr>loRegClassID -<br>
- 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQQ_with_qsub0_in_FPR128_lo_<wbr>and_QQQ_with_qsub2_in_FPR128_<wbr>loRegClassID -<br>
- 32)) |<br>
- (1u << (AArch64::QQQQRegClassID - 32)) |<br>
- (1u << (AArch64::QQQQ_with_qsub0_in_<wbr>FPR128_loRegClassID - 32)) |<br>
- (1u << (AArch64::QQQQ_with_qsub1_in_<wbr>FPR128_loRegClassID - 32)) |<br>
- (1u << (AArch64::QQQQ_with_qsub2_in_<wbr>FPR128_loRegClassID - 32)) |<br>
- (1u << (AArch64::QQQQ_with_qsub3_in_<wbr>FPR128_loRegClassID - 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQQQ_with_qsub0_in_FPR128_lo_<wbr>and_QQQQ_with_qsub1_in_FPR128_<wbr>loRegClassID -<br>
- 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQQQ_with_qsub1_in_FPR128_lo_<wbr>and_QQQQ_with_qsub2_in_FPR128_<wbr>loRegClassID -<br>
- 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQQQ_with_qsub2_in_FPR128_lo_<wbr>and_QQQQ_with_qsub3_in_FPR128_<wbr>loRegClassID -<br>
- 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQQQ_with_qsub0_in_FPR128_lo_<wbr>and_QQQQ_with_qsub2_in_FPR128_<wbr>loRegClassID -<br>
- 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQQQ_with_qsub1_in_FPR128_lo_<wbr>and_QQQQ_with_qsub3_in_FPR128_<wbr>loRegClassID -<br>
- 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQQQ_with_qsub0_in_FPR128_lo_<wbr>and_QQQQ_with_qsub3_in_FPR128_<wbr>loRegClassID -<br>
- 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQ_with_qsub0_in_FPR128_lo_<wbr>and_QQ_with_qsub1_in_FPR128_<wbr>loRegClassID -<br>
- 32)) |<br>
- (1u << (AArch64::QQQRegClassID - 32)) |<br>
- (1u << (AArch64::QQQ_with_qsub0_in_<wbr>FPR128_loRegClassID - 32)) |<br>
- (1u << (AArch64::QQQ_with_qsub1_in_<wbr>FPR128_loRegClassID - 32)) |<br>
- (1u << (AArch64::QQQ_with_qsub2_in_<wbr>FPR128_loRegClassID - 32)) |<br>
- (1u<br>
- << (AArch64::<br>
- QQQ_with_qsub0_in_FPR128_lo_<wbr>and_QQQ_with_qsub1_in_FPR128_<wbr>loRegClassID -<br>
- 32)),<br>
- // FIXME: The entries below this point can be safely removed once this<br>
- // is tablegenerated. It's only needed because of the hardcoded register<br>
- // class limit.<br>
- // Classes 64-96<br>
- 0,<br>
- // Classes 97-128<br>
- 0,<br>
- // Classes 129-160<br>
- 0,<br>
- // Classes 161-192<br>
- 0,<br>
- // Classes 193-224<br>
- 0,<br>
-};<br>
-<br>
-const uint32_t CCRCoverageData[] = {<br>
- // Classes 0-31<br>
- 1u << AArch64::CCRRegClassID,<br>
- // Classes 32-63<br>
- 0,<br>
- // FIXME: The entries below this point can be safely removed once this<br>
- // is tablegenerated. It's only needed because of the hardcoded register<br>
- // class limit.<br>
- // Classes 64-96<br>
- 0,<br>
- // Classes 97-128<br>
- 0,<br>
- // Classes 129-160<br>
- 0,<br>
- // Classes 161-192<br>
- 0,<br>
- // Classes 193-224<br>
- 0,<br>
-};<br>
-<br>
-RegisterBank GPRRegBank(AArch64::<wbr>GPRRegBankID, "GPR", 64, GPRCoverageData);<br>
-RegisterBank FPRRegBank(AArch64::<wbr>FPRRegBankID, "FPR", 512, FPRCoverageData);<br>
-RegisterBank CCRRegBank(AArch64::<wbr>CCRRegBankID, "CCR", 32, CCRCoverageData);<br>
-} // end namespace AArch64<br>
-<br>
-RegisterBank *AArch64GenRegisterBankInfo::<wbr>RegBanks[] = {<br>
- &AArch64::GPRRegBank, &AArch64::FPRRegBank, &AArch64::CCRRegBank};<br>
-<br>
RegisterBankInfo::<wbr>PartialMapping AArch64GenRegisterBankInfo::<wbr>PartMappings[]{<br>
/* StartIdx, Length, RegBank */<br>
- // 0: GPR 32-bit value.<br>
- {0, 32, AArch64::GPRRegBank},<br>
- // 1: GPR 64-bit value.<br>
- {0, 64, AArch64::GPRRegBank},<br>
- // 2: FPR 32-bit value.<br>
+ // 0: FPR 32-bit value.<br>
{0, 32, AArch64::FPRRegBank},<br>
- // 3: FPR 64-bit value.<br>
+ // 1: FPR 64-bit value.<br>
{0, 64, AArch64::FPRRegBank},<br>
- // 4: FPR 128-bit value.<br>
+ // 2: FPR 128-bit value.<br>
{0, 128, AArch64::FPRRegBank},<br>
- // 5: FPR 256-bit value.<br>
+ // 3: FPR 256-bit value.<br>
{0, 256, AArch64::FPRRegBank},<br>
- // 6: FPR 512-bit value.<br>
- {0, 512, AArch64::FPRRegBank}};<br>
+ // 4: FPR 512-bit value.<br>
+ {0, 512, AArch64::FPRRegBank},<br>
+ // 5: GPR 32-bit value.<br>
+ {0, 32, AArch64::GPRRegBank},<br>
+ // 6: GPR 64-bit value.<br>
+ {0, 64, AArch64::GPRRegBank},<br>
+};<br>
<br>
// ValueMappings.<br>
RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::<wbr>ValMappings[]{<br>
/* BreakDown, NumBreakDowns */<br>
// 3-operands instructions (all binary operations should end up with one of<br>
// those mapping).<br>
- // 0: GPR 32-bit value. <-- This must match First3OpsIdx.<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR32 - PMI_Min], 1},<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR32 - PMI_Min], 1},<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR32 - PMI_Min], 1},<br>
- // 3: GPR 64-bit value.<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1},<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1},<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1},<br>
- // 6: FPR 32-bit value.<br>
+ // 0: FPR 32-bit value. <-- This must match First3OpsIdx.<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR32 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR32 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR32 - PMI_Min], 1},<br>
- // 9: FPR 64-bit value.<br>
+ // 3: FPR 64-bit value.<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR64 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR64 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR64 - PMI_Min], 1},<br>
- // 12: FPR 128-bit value.<br>
+ // 6: FPR 128-bit value.<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR128 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR128 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR128 - PMI_Min], 1},<br>
- // 15: FPR 256-bit value.<br>
+ // 9: FPR 256-bit value.<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR256 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR256 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR256 - PMI_Min], 1},<br>
- // 18: FPR 512-bit value. <-- This must match Last3OpsIdx.<br>
+ // 12: FPR 512-bit value.<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR512 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR512 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR512 - PMI_Min], 1},<br>
+ // 15: GPR 32-bit value.<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR32 - PMI_Min], 1},<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR32 - PMI_Min], 1},<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR32 - PMI_Min], 1},<br>
+ // 18: GPR 64-bit value. <-- This must match Last3OpsIdx.<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1},<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1},<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1},<br>
// Cross register bank copies.<br>
- // 21: GPR 32-bit value to FPR 32-bit value. <-- This must match<br>
+ // 21: FPR 32-bit value to GPR 32-bit value. <-- This must match<br>
// FirstCrossRegCpyIdx.<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR32 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR32 - PMI_Min], 1},<br>
- // 23: GPR 64-bit value to FPR 64-bit value.<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1},<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR32 - PMI_Min], 1},<br>
+ // 23: FPR 64-bit value to GPR 64-bit value.<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR64 - PMI_Min], 1},<br>
- // 25: FPR 32-bit value to GPR 32-bit value.<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR32 - PMI_Min], 1},<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1},<br>
+ // 25: FPR 128-bit value to GPR 128-bit value (invalid)<br>
+ {nullptr, 1},<br>
+ {nullptr, 1},<br>
+ // 27: FPR 256-bit value to GPR 256-bit value (invalid)<br>
+ {nullptr, 1},<br>
+ {nullptr, 1},<br>
+ // 29: FPR 512-bit value to GPR 512-bit value (invalid)<br>
+ {nullptr, 1},<br>
+ {nullptr, 1},<br>
+ // 31: GPR 32-bit value to FPR 32-bit value.<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR32 - PMI_Min], 1},<br>
- // 27: FPR 64-bit value to GPR 64-bit value. <-- This must match<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR32 - PMI_Min], 1},<br>
+ // 33: GPR 64-bit value to FPR 64-bit value. <-- This must match<br>
// LastCrossRegCpyIdx.<br>
+ {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1},<br>
{&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_FPR64 - PMI_Min], 1},<br>
- {&AArch64GenRegisterBankInfo::<wbr>PartMappings[PMI_GPR64 - PMI_Min], 1}<br>
};<br>
<br>
bool AArch64GenRegisterBankInfo::<wbr>checkPartialMap(unsigned Idx,<br>
@@ -301,9 +178,9 @@ AArch64GenRegisterBankInfo::<wbr>getValueMapp<br>
<br>
AArch64GenRegisterBankInfo::<wbr>PartialMappingIdx<br>
AArch64GenRegisterBankInfo::<wbr>BankIDToCopyMapIdx[]{<br>
- PMI_FirstGPR, // GPR<br>
- PMI_FirstFPR, // FPR<br>
PMI_None, // CCR<br>
+ PMI_FirstFPR, // FPR<br>
+ PMI_FirstGPR, // GPR<br>
};<br>
<br>
const RegisterBankInfo::ValueMapping *<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBankInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/<wbr>AArch64RegisterBankInfo.cpp?<wbr>rev=292478&r1=292477&r2=<wbr>292478&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBankInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBankInfo.cpp Thu Jan 19 05:15:55 2017<br>
@@ -21,6 +21,9 @@<br>
#include "llvm/Target/<wbr>TargetRegisterInfo.h"<br>
#include "llvm/Target/<wbr>TargetSubtargetInfo.h"<br>
<br>
+#define GET_TARGET_REGBANK_IMPL<br>
+#include "AArch64GenRegisterBank.inc"<br>
+<br>
// This file will be TableGen'ed at some point.<br>
#include "AArch64GenRegisterBankInfo.<wbr>def"<br>
<br>
@@ -30,9 +33,6 @@ using namespace llvm;<br>
#error "You shouldn't build this"<br>
#endif<br>
<br>
-AArch64GenRegisterBankInfo::<wbr>AArch64GenRegisterBankInfo()<br>
- : RegisterBankInfo(RegBanks, AArch64::NumRegisterBanks) {}<br>
-<br>
AArch64RegisterBankInfo::<wbr>AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)<br>
: AArch64GenRegisterBankInfo() {<br>
static bool AlreadyInit = false;<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBankInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.h?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/<wbr>AArch64RegisterBankInfo.h?rev=<wbr>292478&r1=292477&r2=292478&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBankInfo.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64RegisterBankInfo.h Thu Jan 19 05:15:55 2017<br>
@@ -16,40 +16,30 @@<br>
<br>
#include "llvm/CodeGen/GlobalISel/<wbr>RegisterBankInfo.h"<br>
<br>
+#define GET_REGBANK_DECLARATIONS<br>
+#include "AArch64GenRegisterBank.inc"<br>
+<br>
namespace llvm {<br>
<br>
class TargetRegisterInfo;<br>
<br>
-namespace AArch64 {<br>
-enum {<br>
- GPRRegBankID = 0, /// General Purpose Registers: W, X.<br>
- FPRRegBankID = 1, /// Floating Point/Vector Registers: B, H, S, D, Q.<br>
- CCRRegBankID = 2, /// Conditional register: NZCV.<br>
- NumRegisterBanks<br>
-};<br>
-} // End AArch64 namespace.<br>
-<br>
class AArch64GenRegisterBankInfo : public RegisterBankInfo {<br>
-private:<br>
- static RegisterBank *RegBanks[];<br>
-<br>
protected:<br>
- AArch64GenRegisterBankInfo();<br>
<br>
enum PartialMappingIdx {<br>
PMI_None = -1,<br>
- PMI_GPR32 = 1,<br>
- PMI_GPR64,<br>
- PMI_FPR32,<br>
+ PMI_FPR32 = 1,<br>
PMI_FPR64,<br>
PMI_FPR128,<br>
PMI_FPR256,<br>
PMI_FPR512,<br>
+ PMI_GPR32,<br>
+ PMI_GPR64,<br>
PMI_FirstGPR = PMI_GPR32,<br>
PMI_LastGPR = PMI_GPR64,<br>
PMI_FirstFPR = PMI_FPR32,<br>
PMI_LastFPR = PMI_FPR512,<br>
- PMI_Min = PMI_FirstGPR,<br>
+ PMI_Min = PMI_FirstFPR,<br>
};<br>
<br>
static RegisterBankInfo::<wbr>PartialMapping PartMappings[];<br>
@@ -61,7 +51,7 @@ protected:<br>
Last3OpsIdx = 18,<br>
DistanceBetweenRegBanks = 3,<br>
FirstCrossRegCpyIdx = 21,<br>
- LastCrossRegCpyIdx = 27,<br>
+ LastCrossRegCpyIdx = 33,<br>
DistanceBetweenCrossRegCpy = 2<br>
};<br>
<br>
@@ -90,6 +80,9 @@ protected:<br>
/// register bank with a size of \p Size.<br>
static const RegisterBankInfo::ValueMapping *<br>
getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);<br>
+<br>
+#define GET_TARGET_REGBANK_CLASS<br>
+#include "AArch64GenRegisterBank.inc"<br>
};<br>
<br>
/// This class provides the information for the target register banks.<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>AArch64TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/AArch64TargetMachine.<wbr>cpp?rev=292478&r1=292477&r2=<wbr>292478&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>AArch64TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>AArch64TargetMachine.cpp Thu Jan 19 05:15:55 2017<br>
@@ -14,7 +14,9 @@<br>
#include "AArch64CallLowering.h"<br>
#include "AArch64InstructionSelector.h"<br>
#include "AArch64LegalizerInfo.h"<br>
+#ifdef LLVM_BUILD_GLOBAL_ISEL<br>
#include "AArch64RegisterBankInfo.h"<br>
+#endif<br>
#include "AArch64Subtarget.h"<br>
#include "AArch64TargetMachine.h"<br>
#include "AArch64TargetObjectFile.h"<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<wbr>CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>AArch64/CMakeLists.txt?rev=<wbr>292478&r1=292477&r2=292478&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/AArch64/<wbr>CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<wbr>CMakeLists.txt Thu Jan 19 05:15:55 2017<br>
@@ -14,6 +14,7 @@ tablegen(LLVM AArch64GenSubtargetInfo.in<br>
tablegen(LLVM AArch64GenDisassemblerTables.<wbr>inc -gen-disassembler)<br>
tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables)<br>
if(LLVM_BUILD_GLOBAL_ISEL)<br>
+ tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank)<br>
tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel)<br>
endif()<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/<wbr>ARMRegisterBankInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>ARM/ARMRegisterBankInfo.cpp?<wbr>rev=292478&r1=292477&r2=<wbr>292478&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/<wbr>ARMRegisterBankInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/<wbr>ARMRegisterBankInfo.cpp Thu Jan 19 05:15:55 2017<br>
@@ -55,7 +55,9 @@ const uint32_t GPRCoverageData[] = {<br>
0,<br>
};<br>
<br>
-RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);<br>
+// FIXME: The 200 will be replaced by the number of register classes when this is<br>
+// tablegenerated.<br>
+RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData, 200);<br>
RegisterBank *RegBanks[] = {&GPRRegBank};<br>
<br>
RegisterBankInfo::<wbr>PartialMapping GPRPartialMapping{0, 32, GPRRegBank};<br>
<br>
Modified: llvm/trunk/utils/TableGen/<wbr>CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/CMakeLists.txt?rev=<wbr>292478&r1=292477&r2=292478&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>CMakeLists.txt (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>CMakeLists.txt Thu Jan 19 05:15:55 2017<br>
@@ -27,6 +27,7 @@ add_tablegen(llvm-tblgen LLVM<br>
IntrinsicEmitter.cpp<br>
OptParserEmitter.cpp<br>
PseudoLoweringEmitter.cpp<br>
+ RegisterBankEmitter.cpp<br>
RegisterInfoEmitter.cpp<br>
SearchableTableEmitter.cpp<br>
SubtargetEmitter.cpp<br>
<br>
Copied: llvm/trunk/utils/TableGen/<wbr>RegisterBankEmitter.cpp (from r292368, llvm/trunk/utils/TableGen/<wbr>RegisterBankEmitter.cpp)<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp?p2=llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp&p1=llvm/trunk/utils/TableGen/RegisterBankEmitter.cpp&r1=292368&r2=292478&rev=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/RegisterBankEmitter.<wbr>cpp?p2=llvm/trunk/utils/<wbr>TableGen/RegisterBankEmitter.<wbr>cpp&p1=llvm/trunk/utils/<wbr>TableGen/RegisterBankEmitter.<wbr>cpp&r1=292368&r2=292478&rev=<wbr>292478&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>RegisterBankEmitter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>RegisterBankEmitter.cpp Thu Jan 19 05:15:55 2017<br>
@@ -173,7 +173,8 @@ static void visitRegisterBankClasses(<br>
VisitFn(RC, Kind.str());<br>
<br>
for (const auto &PossibleSubclass : RegisterClassHierarchy.<wbr>getRegClasses()) {<br>
- Twine TmpKind = Kind + " (" + PossibleSubclass.getName() + ")";<br>
+ std::string TmpKind =<br>
+ (Twine(Kind) + " (" + PossibleSubclass.getName() + ")").str();<br>
<br>
// Visit each subclass of an explicitly named class.<br>
if (RC != &PossibleSubclass && RC->hasSubClass(&<wbr>PossibleSubclass))<br>
@@ -191,9 +192,10 @@ static void visitRegisterBankClasses(<br>
BitVector BV(RegisterClassHierarchy.<wbr>getRegClasses().size());<br>
PossibleSubclass.<wbr>getSuperRegClasses(&SubIdx, BV);<br>
if (BV.test(RC->EnumValue)) {<br>
- Twine TmpKind2 = TmpKind + " " + RC->getName() +<br>
- " class-with-subregs: " + RC->getName();<br>
- VisitFn(&PossibleSubclass, TmpKind2.str());<br>
+ std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +<br>
+ " class-with-subregs: " + RC->getName())<br>
+ .str();<br>
+ VisitFn(&PossibleSubclass, TmpKind2);<br>
}<br>
}<br>
}<br>
@@ -217,8 +219,8 @@ void RegisterBankEmitter::<wbr>emitBaseClassI<br>
for (const auto &RCs : RCsGroupedByWord) {<br>
OS << " // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";<br>
for (const auto &RC : RCs) {<br>
- Twine QualifiedRegClassID =<br>
- TargetName + "::" + RC->getName() + "RegClassID";<br>
+ std::string QualifiedRegClassID =<br>
+ (Twine(TargetName) + "::" + RC->getName() + "RegClassID").str();<br>
OS << " (1u << (" << QualifiedRegClassID << " - "<br>
<< LowestIdxInWord << ")) |\n";<br>
}<br>
@@ -230,7 +232,8 @@ void RegisterBankEmitter::<wbr>emitBaseClassI<br>
OS << "\n";<br>
<br>
for (const auto &Bank : Banks) {<br>
- Twine QualifiedBankID = TargetName + "::" + Bank.getEnumeratorName();<br>
+ std::string QualifiedBankID =<br>
+ (TargetName + "::" + Bank.getEnumeratorName()).str(<wbr>);<br>
unsigned Size = Bank.getRCWithLargestRegsSize(<wbr>)->SpillSize;<br>
OS << "RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "<br>
<< QualifiedBankID << ", /* Name */ \"" << Bank.getName()<br>
<br>
Modified: llvm/trunk/utils/TableGen/<wbr>TableGen.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/TableGen.cpp?rev=<wbr>292478&r1=292477&r2=292478&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>TableGen.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>TableGen.cpp Thu Jan 19 05:15:55 2017<br>
@@ -46,6 +46,7 @@ enum ActionType {<br>
GenAttributes,<br>
GenSearchableTables,<br>
GenGlobalISel,<br>
+ GenRegisterBank,<br>
};<br>
<br>
namespace {<br>
@@ -94,7 +95,9 @@ namespace {<br>
clEnumValN(<wbr>GenSearchableTables, "gen-searchable-tables",<br>
"Generate generic binary-searchable table"),<br>
clEnumValN(GenGlobalISel, "gen-global-isel",<br>
- "Generate GlobalISel selector")));<br>
+ "Generate GlobalISel selector"),<br>
+ clEnumValN(GenRegisterBank, "gen-register-bank",<br>
+ "Generate registers bank descriptions")));<br>
<br>
cl::opt<std::string><br>
Class("class", cl::desc("Print Enum list for this class"),<br>
@@ -182,6 +185,8 @@ bool LLVMTableGenMain(raw_ostream &OS, R<br>
break;<br>
case GenGlobalISel:<br>
EmitGlobalISel(Records, OS);<br>
+ case GenRegisterBank:<br>
+ EmitRegisterBank(Records, OS);<br>
break;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/utils/TableGen/<wbr>TableGenBackends.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGenBackends.h?rev=292478&r1=292477&r2=292478&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/utils/<wbr>TableGen/TableGenBackends.h?<wbr>rev=292478&r1=292477&r2=<wbr>292478&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/utils/TableGen/<wbr>TableGenBackends.h (original)<br>
+++ llvm/trunk/utils/TableGen/<wbr>TableGenBackends.h Thu Jan 19 05:15:55 2017<br>
@@ -81,6 +81,7 @@ void EmitCTags(RecordKeeper &RK, raw_ost<br>
void EmitAttributes(RecordKeeper &RK, raw_ostream &OS);<br>
void EmitSearchableTables(<wbr>RecordKeeper &RK, raw_ostream &OS);<br>
void EmitGlobalISel(RecordKeeper &RK, raw_ostream &OS);<br>
+void EmitRegisterBank(RecordKeeper &RK, raw_ostream &OS);<br>
<br>
} // End llvm namespace<br>
<br>
<br>
<br>
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</blockquote></div><br></div>