<div dir="ltr">Sounds good to me - this looks like it should be safe, and the bug it fixes is probably fairly common if you enable scatter/gather (that is, if you're on AVX512).<div>Hans?</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Wed, Jan 18, 2017 at 8:33 AM, Matthew Simpson <span dir="ltr"><<a href="mailto:mssimpso@codeaurora.org" target="_blank">mssimpso@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Hans,<div><br></div><div>I think r292254 and r292280 (test case fix-up) should probably be added to the release branch. Michael, what do you think?</div><div><br></div><div>-- Matt</div></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jan 17, 2017 at 3:51 PM, Matthew Simpson via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: mssimpso<br>
Date: Tue Jan 17 14:51:39 2017<br>
New Revision: 292254<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=292254&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=292254&view=rev</a><br>
Log:<br>
[LV] Mark non-consecutive-like pointers non-uniform<br>
<br>
If a memory instruction will be vectorized, but it's pointer operand is<br>
non-consecutive-like, the instruction is a gather or scatter operation. Its<br>
pointer operand will be non-uniform. This should fix PR31671.<br>
<br>
Reference: <a href="https://llvm.org/bugs/show_bug.cgi?id=31671" rel="noreferrer" target="_blank">https://llvm.org/bugs/show_bug<wbr>.cgi?id=31671</a><br>
Differential Revision: <a href="https://reviews.llvm.org/D28819" rel="noreferrer" target="_blank">https://reviews.llvm.org/D2881<wbr>9</a><br>
<br>
Added:<br>
llvm/trunk/test/Transforms/Loo<wbr>pVectorize/X86/consecutive-ptr<wbr>-uniforms.ll<br>
Modified:<br>
llvm/trunk/lib/Transforms/Vect<wbr>orize/LoopVectorize.cpp<br>
<br>
Modified: llvm/trunk/lib/Transforms/Vect<wbr>orize/LoopVectorize.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/LoopVectorize.cpp?rev=292254&r1=292253&r2=292254&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Transform<wbr>s/Vectorize/LoopVectorize.cpp?<wbr>rev=292254&r1=292253&r2=<wbr>292254&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Transforms/Vect<wbr>orize/LoopVectorize.cpp (original)<br>
+++ llvm/trunk/lib/Transforms/Vect<wbr>orize/LoopVectorize.cpp Tue Jan 17 14:51:39 2017<br>
@@ -5602,6 +5602,13 @@ void LoopVectorizationLegality::col<wbr>lectL<br>
// is consecutive-like, the pointer operand should remain uniform.<br>
else if (hasConsecutiveLikePtrOperand(<wbr>&I))<br>
ConsecutiveLikePtrs.insert(Pt<wbr>r);<br>
+<br>
+ // Otherwise, if the memory instruction will be vectorized and its<br>
+ // pointer operand is non-consecutive-like, the memory instruction should<br>
+ // be a gather or scatter operation. Its pointer operand will be<br>
+ // non-uniform.<br>
+ else<br>
+ PossibleNonUniformPtrs.insert(<wbr>Ptr);<br>
}<br>
<br>
// Add to the Worklist all consecutive and consecutive-like pointers that<br>
<br>
Added: llvm/trunk/test/Transforms/Loo<wbr>pVectorize/X86/consecutive-ptr<wbr>-uniforms.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/consecutive-ptr-uniforms.ll?rev=292254&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/test/Transfor<wbr>ms/LoopVectorize/X86/consecuti<wbr>ve-ptr-uniforms.ll?rev=292254&<wbr>view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/Loo<wbr>pVectorize/X86/consecutive-ptr<wbr>-uniforms.ll (added)<br>
+++ llvm/trunk/test/Transforms/Loo<wbr>pVectorize/X86/consecutive-ptr<wbr>-uniforms.ll Tue Jan 17 14:51:39 2017<br>
@@ -0,0 +1,55 @@<br>
+; RUN: opt < %s -loop-vectorize -instcombine -S -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s<br>
+<br>
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32<wbr>:64-S128"<br>
+target triple = "x86_64-unknown-linux-gnu"<br>
+<br>
+; CHECK-LABEL: PR31671<br>
+;<br>
+; Check a pointer in which one of its uses is consecutive-like and another of<br>
+; its uses is non-consecutive-like. In the test case below, %tmp3 is the<br>
+; pointer operand of an interleaved load, making it consecutive-like. However,<br>
+; it is also the pointer operand of a non-interleaved store that will become a<br>
+; scatter operation. %tmp3 (and the induction variable) should not be marked<br>
+; uniform-after-vectorization.<br>
+;<br>
+; CHECK: LV: Found uniform instruction: %tmp0 = getelementptr inbounds %data, %data* %d, i64 0, i32 3, i64 %i<br>
+; CHECK-NOT: LV: Found uniform instruction: %tmp3 = getelementptr inbounds %data, %data* %d, i64 0, i32 0, i64 %i<br>
+; CHECK-NOT: LV: Found uniform instruction: %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]<br>
+; CHECK-NOT: LV: Found uniform instruction: %i.next = add nuw nsw i64 %i, 5<br>
+; CHECK: vector.body:<br>
+; CHECK: %vec.ind = phi <16 x i64><br>
+; CHECK: %[[T0:.+]] = extractelement <16 x i64> %vec.ind, i32 0<br>
+; CHECK: %[[T1:.+]] = getelementptr inbounds %data, %data* %d, i64 0, i32 3, i64 %[[T0]]<br>
+; CHECK: %[[T2:.+]] = bitcast float* %[[T1]] to <80 x float>*<br>
+; CHECK: load <80 x float>, <80 x float>* %[[T2]], align 4<br>
+; CHECK: %[[T3:.+]] = getelementptr inbounds %data, %data* %d, i64 0, i32 0, i64 %[[T0]]<br>
+; CHECK: %[[T4:.+]] = bitcast float* %[[T3]] to <80 x float>*<br>
+; CHECK: load <80 x float>, <80 x float>* %[[T4]], align 4<br>
+; CHECK: %VectorGep = getelementptr inbounds %data, %data* %d, i64 0, i32 0, <16 x i64> %vec.ind<br>
+; CHECK: call void @llvm.masked.scatter.v16f32({{<wbr>.*}}, <16 x float*> %VectorGep, {{.*}})<br>
+; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body<br>
+<br>
+%data = type { [32000 x float], [3 x i32], [4 x i8], [32000 x float] }<br>
+<br>
+define void @PR31671(float %x, %data* %d) #0 {<br>
+entry:<br>
+ br label %for.body<br>
+<br>
+for.body:<br>
+ %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]<br>
+ %tmp0 = getelementptr inbounds %data, %data* %d, i64 0, i32 3, i64 %i<br>
+ %tmp1 = load float, float* %tmp0, align 4<br>
+ %tmp2 = fmul float %x, %tmp1<br>
+ %tmp3 = getelementptr inbounds %data, %data* %d, i64 0, i32 0, i64 %i<br>
+ %tmp4 = load float, float* %tmp3, align 4<br>
+ %tmp5 = fadd float %tmp4, %tmp2<br>
+ store float %tmp5, float* %tmp3, align 4<br>
+ %i.next = add nuw nsw i64 %i, 5<br>
+ %cond = icmp slt i64 %i.next, 32000<br>
+ br i1 %cond, label %for.body, label %for.end<br>
+<br>
+for.end:<br>
+ ret void<br>
+}<br>
+<br>
+attributes #0 = { "target-cpu"="knl" }<br>
<br>
<br>
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</blockquote></div><br></div>
</div></div></blockquote></div><br></div>