<div dir="ltr">Hi Sanjay,<div><br><div>We've tracked a new assertion failure in our internal test suite to this commit. I've attached an ll file (generated from the following C++ source):</div><div><br></div><div>// ================<br></div><div><div>typedef short __v8hi __attribute__((__vector_size__(16)));</div><div>__v8hi foo(__v8hi &V1, __v8hi &V2, unsigned mask) {</div><div> __v8hi Result = V1;</div><div> if (mask & 0x80)</div><div> Result[0] = V2[0];</div><div> return Result;</div><div>}</div></div><div>// ================</div><div><br></div><div>opt 1.ll -O2 -o foo<br></div><div><div>opt: /home/llvm-upstream/llvm/lib/IR/Constants.cpp:1583: static llvm::Constant* llvm::ConstantExpr::getSExt(llvm::Constant*, llvm::Type*, bool): Assertion `(fromVec == toVec) && "Cannot convert from scalar to/from vector"' failed.</div><div><br></div></div><div>-Greg </div></div></div><div class="gmail_extra"><br><div class="gmail_quote">On 1 November 2016 at 20:08, Sanjay Patel via llvm-commits <span dir="ltr"><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: spatel<br>
Date: Tue Nov 1 15:08:02 2016<br>
New Revision: 285732<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=285732&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=285732&view=rev</a><br>
Log:<br>
[InstCombine] allow splat vector folds in adjustMinMax()<br>
<br>
Modified:<br>
llvm/trunk/lib/Transforms/<wbr>InstCombine/InstCombineSelect.<wbr>cpp<br>
llvm/trunk/test/Transforms/<wbr>InstCombine/adjust-for-minmax.<wbr>ll<br>
<br>
Modified: llvm/trunk/lib/Transforms/<wbr>InstCombine/InstCombineSelect.<wbr>cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=285732&r1=285731&r2=285732&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/<wbr>Transforms/InstCombine/<wbr>InstCombineSelect.cpp?rev=<wbr>285732&r1=285731&r2=285732&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Transforms/<wbr>InstCombine/InstCombineSelect.<wbr>cpp (original)<br>
+++ llvm/trunk/lib/Transforms/<wbr>InstCombine/InstCombineSelect.<wbr>cpp Tue Nov 1 15:08:02 2016<br>
@@ -424,24 +424,20 @@ static bool adjustMinMax(SelectInst &Sel<br>
Value *FalseVal = Sel.getFalseValue();<br>
<br>
// We may move or edit the compare, so make sure the select is the only user.<br>
- if (!Cmp.hasOneUse())<br>
+ const APInt *CmpC;<br>
+ if (!Cmp.hasOneUse() || !match(CmpRHS, m_APInt(CmpC)))<br>
return false;<br>
<br>
- // FIXME: Use m_APInt to allow vector folds.<br>
- auto *CI = dyn_cast<ConstantInt>(CmpRHS);<br>
- if (!CI)<br>
- return false;<br>
-<br>
- // These transformations only work for selects over integers.<br>
- IntegerType *SelectTy = dyn_cast<IntegerType>(Sel.<wbr>getType());<br>
- if (!SelectTy)<br>
+ // These transforms only work for selects of integers or vector integers.<br>
+ auto *SelEltTy = dyn_cast<IntegerType>(Sel.<wbr>getType()->getScalarType());<br>
+ if (!SelEltTy)<br>
return false;<br>
<br>
Constant *AdjustedRHS;<br>
if (Pred == ICmpInst::ICMP_UGT || Pred == ICmpInst::ICMP_SGT)<br>
- AdjustedRHS = ConstantInt::get(CI-><wbr>getContext(), CI->getValue() + 1);<br>
+ AdjustedRHS = ConstantInt::get(CmpRHS-><wbr>getType(), *CmpC + 1);<br>
else if (Pred == ICmpInst::ICMP_ULT || Pred == ICmpInst::ICMP_SLT)<br>
- AdjustedRHS = ConstantInt::get(CI-><wbr>getContext(), CI->getValue() - 1);<br>
+ AdjustedRHS = ConstantInt::get(CmpRHS-><wbr>getType(), *CmpC - 1);<br>
else<br>
return false;<br>
<br>
@@ -454,8 +450,8 @@ static bool adjustMinMax(SelectInst &Sel<br>
// Types do not match. Instead of calculating this with mixed types, promote<br>
// all to the larger type. This enables scalar evolution to analyze this<br>
// expression.<br>
- else if (CmpRHS->getType()-><wbr>getScalarSizeInBits() < SelectTy->getBitWidth()) {<br>
- Constant *SextRHS = ConstantExpr::getSExt(<wbr>AdjustedRHS, SelectTy);<br>
+ else if (CmpRHS->getType()-><wbr>getScalarSizeInBits() < SelEltTy->getBitWidth()) {<br>
+ Constant *SextRHS = ConstantExpr::getSExt(<wbr>AdjustedRHS, Sel.getType());<br>
<br>
// X = sext x; x >s c ? X : C+1 --> X = sext x; X <s C+1 ? C+1 : X<br>
// X = sext x; x <s c ? X : C-1 --> X = sext x; X >s C-1 ? C-1 : X<br>
@@ -469,7 +465,7 @@ static bool adjustMinMax(SelectInst &Sel<br>
CmpLHS = FalseVal;<br>
AdjustedRHS = SextRHS;<br>
} else if (Cmp.isUnsigned()) {<br>
- Constant *ZextRHS = ConstantExpr::getZExt(<wbr>AdjustedRHS, SelectTy);<br>
+ Constant *ZextRHS = ConstantExpr::getZExt(<wbr>AdjustedRHS, Sel.getType());<br>
// X = zext x; x >u c ? X : C+1 --> X = zext x; X <u C+1 ? C+1 : X<br>
// X = zext x; x <u c ? X : C-1 --> X = zext x; X >u C-1 ? C-1 : X<br>
// zext + signed compare cannot be changed:<br>
<br>
Modified: llvm/trunk/test/Transforms/<wbr>InstCombine/adjust-for-minmax.<wbr>ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll?rev=285732&r1=285731&r2=285732&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>Transforms/InstCombine/adjust-<wbr>for-minmax.ll?rev=285732&r1=<wbr>285731&r2=285732&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/Transforms/<wbr>InstCombine/adjust-for-minmax.<wbr>ll (original)<br>
+++ llvm/trunk/test/Transforms/<wbr>InstCombine/adjust-for-minmax.<wbr>ll Tue Nov 1 15:08:02 2016<br>
@@ -68,13 +68,12 @@ define i32 @smax3(i32 %n) {<br>
ret i32 %m<br>
}<br>
<br>
-; FIXME<br>
; Swap vector signed pred and select ops.<br>
<br>
define <2 x i32> @smax3_vec(<2 x i32> %n) {<br>
; CHECK-LABEL: @smax3_vec(<br>
-; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1><br>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer<br>
+; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, zeroinitializer<br>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n<br>
; CHECK-NEXT: ret <2 x i32> [[M]]<br>
;<br>
%t = icmp sgt <2 x i32> %n, <i32 -1, i32 -1><br>
@@ -95,13 +94,12 @@ define i32 @smin3(i32 %n) {<br>
ret i32 %m<br>
}<br>
<br>
-; FIXME<br>
; Swap vector signed pred and select ops.<br>
<br>
define <2 x i32> @smin3_vec(<2 x i32> %n) {<br>
; CHECK-LABEL: @smin3_vec(<br>
-; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1><br>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer<br>
+; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, zeroinitializer<br>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n<br>
; CHECK-NEXT: ret <2 x i32> [[M]]<br>
;<br>
%t = icmp slt <2 x i32> %n, <i32 1, i32 1><br>
@@ -122,13 +120,12 @@ define i32 @umax3(i32 %n) {<br>
ret i32 %m<br>
}<br>
<br>
-; FIXME<br>
; Swap vector unsigned pred and select ops.<br>
<br>
define <2 x i32> @umax3_vec(<2 x i32> %n) {<br>
; CHECK-LABEL: @umax3_vec(<br>
-; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 4, i32 4><br>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 5, i32 5><br>
+; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 5, i32 5><br>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 5, i32 5>, <2 x i32> %n<br>
; CHECK-NEXT: ret <2 x i32> [[M]]<br>
;<br>
%t = icmp ugt <2 x i32> %n, <i32 4, i32 4><br>
@@ -149,13 +146,12 @@ define i32 @umin3(i32 %n) {<br>
ret i32 %m<br>
}<br>
<br>
-; FIXME<br>
; Swap vector unsigned pred and select ops.<br>
<br>
define <2 x i32> @umin3_vec(<2 x i32> %n) {<br>
; CHECK-LABEL: @umin3_vec(<br>
-; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 7, i32 7><br>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 6, i32 6><br>
+; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 6, i32 6><br>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 6, i32 6>, <2 x i32> %n<br>
; CHECK-NEXT: ret <2 x i32> [[M]]<br>
;<br>
%t = icmp ult <2 x i32> %n, <i32 7, i32 7><br>
@@ -176,13 +172,12 @@ define i32 @smax4(i32 %n) {<br>
ret i32 %m<br>
}<br>
<br>
-; FIXME<br>
; Canonicalize vector signed pred and swap pred and select ops.<br>
<br>
define <2 x i32> @smax4_vec(<2 x i32> %n) {<br>
; CHECK-LABEL: @smax4_vec(<br>
-; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1><br>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer<br>
+; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, zeroinitializer<br>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n<br>
; CHECK-NEXT: ret <2 x i32> [[M]]<br>
;<br>
%t = icmp sge <2 x i32> %n, zeroinitializer<br>
@@ -203,13 +198,12 @@ define i32 @smin4(i32 %n) {<br>
ret i32 %m<br>
}<br>
<br>
-; FIXME<br>
; Canonicalize vector signed pred and swap pred and select ops.<br>
<br>
define <2 x i32> @smin4_vec(<2 x i32> %n) {<br>
; CHECK-LABEL: @smin4_vec(<br>
-; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1><br>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer<br>
+; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, zeroinitializer<br>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n<br>
; CHECK-NEXT: ret <2 x i32> [[M]]<br>
;<br>
%t = icmp sle <2 x i32> %n, zeroinitializer<br>
@@ -230,13 +224,12 @@ define i32 @umax4(i32 %n) {<br>
ret i32 %m<br>
}<br>
<br>
-; FIXME<br>
; Canonicalize vector unsigned pred and swap pred and select ops.<br>
<br>
define <2 x i32> @umax4_vec(<2 x i32> %n) {<br>
; CHECK-LABEL: @umax4_vec(<br>
-; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 7, i32 7><br>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 8, i32 8><br>
+; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 8, i32 8><br>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 8, i32 8>, <2 x i32> %n<br>
; CHECK-NEXT: ret <2 x i32> [[M]]<br>
;<br>
%t = icmp uge <2 x i32> %n, <i32 8, i32 8><br>
@@ -257,13 +250,12 @@ define i32 @umin4(i32 %n) {<br>
ret i32 %m<br>
}<br>
<br>
-; FIXME<br>
; Canonicalize vector unsigned pred and swap pred and select ops.<br>
<br>
define <2 x i32> @umin4_vec(<2 x i32> %n) {<br>
; CHECK-LABEL: @umin4_vec(<br>
-; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 10, i32 10><br>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 9, i32 9><br>
+; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 9, i32 9><br>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 9, i32 9>, <2 x i32> %n<br>
; CHECK-NEXT: ret <2 x i32> [[M]]<br>
;<br>
%t = icmp ule <2 x i32> %n, <i32 9, i32 9><br>
@@ -284,12 +276,11 @@ define i64 @smax_sext(i32 %a) {<br>
ret i64 %max<br>
}<br>
<br>
-; FIXME<br>
define <2 x i64> @smax_sext_vec(<2 x i32> %a) {<br>
; CHECK-LABEL: @smax_sext_vec(<br>
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64><br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> %a, <i32 -1, i32 -1><br>
-; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> zeroinitializer<br>
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i64> [[A_EXT]], zeroinitializer<br>
+; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> zeroinitializer, <2 x i64> [[A_EXT]]<br>
; CHECK-NEXT: ret <2 x i64> [[MAX]]<br>
;<br>
%a_ext = sext <2 x i32> %a to <2 x i64><br>
@@ -311,12 +302,11 @@ define i64 @smin_sext(i32 %a) {<br>
ret i64 %min<br>
}<br>
<br>
-; FIXME<br>
define <2 x i64>@smin_sext_vec(<2 x i32> %a) {<br>
; CHECK-LABEL: @smin_sext_vec(<br>
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64><br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> %a, <i32 1, i32 1><br>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> zeroinitializer<br>
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i64> [[A_EXT]], zeroinitializer<br>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> zeroinitializer, <2 x i64> [[A_EXT]]<br>
; CHECK-NEXT: ret <2 x i64> [[MIN]]<br>
;<br>
%a_ext = sext <2 x i32> %a to <2 x i64><br>
@@ -338,12 +328,11 @@ define i64 @umax_sext(i32 %a) {<br>
ret i64 %max<br>
}<br>
<br>
-; FIXME<br>
define <2 x i64> @umax_sext_vec(<2 x i32> %a) {<br>
; CHECK-LABEL: @umax_sext_vec(<br>
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64><br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2><br>
-; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3><br>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3><br>
+; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 3, i64 3>, <2 x i64> [[A_EXT]]<br>
; CHECK-NEXT: ret <2 x i64> [[MAX]]<br>
;<br>
%a_ext = sext <2 x i32> %a to <2 x i64><br>
@@ -365,12 +354,11 @@ define i64 @umin_sext(i32 %a) {<br>
ret i64 %min<br>
}<br>
<br>
-; FIXME<br>
define <2 x i64> @umin_sext_vec(<2 x i32> %a) {<br>
; CHECK-LABEL: @umin_sext_vec(<br>
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64><br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3><br>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2><br>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2><br>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 2, i64 2>, <2 x i64> [[A_EXT]]<br>
; CHECK-NEXT: ret <2 x i64> [[MIN]]<br>
;<br>
%a_ext = sext <2 x i32> %a to <2 x i64><br>
@@ -392,12 +380,11 @@ define i64 @umax_sext2(i32 %a) {<br>
ret i64 %min<br>
}<br>
<br>
-; FIXME<br>
define <2 x i64> @umax_sext2_vec(<2 x i32> %a) {<br>
; CHECK-LABEL: @umax_sext2_vec(<br>
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64><br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3><br>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 2, i64 2>, <2 x i64> [[A_EXT]]<br>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2><br>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2><br>
; CHECK-NEXT: ret <2 x i64> [[MIN]]<br>
;<br>
%a_ext = sext <2 x i32> %a to <2 x i64><br>
@@ -419,12 +406,11 @@ define i64 @umin_sext2(i32 %a) {<br>
ret i64 %min<br>
}<br>
<br>
-; FIXME<br>
define <2 x i64> @umin_sext2_vec(<2 x i32> %a) {<br>
; CHECK-LABEL: @umin_sext2_vec(<br>
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64><br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2><br>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 3, i64 3>, <2 x i64> [[A_EXT]]<br>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3><br>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3><br>
; CHECK-NEXT: ret <2 x i64> [[MIN]]<br>
;<br>
%a_ext = sext <2 x i32> %a to <2 x i64><br>
@@ -446,12 +432,11 @@ define i64 @umax_zext(i32 %a) {<br>
ret i64 %max<br>
}<br>
<br>
-; FIXME<br>
define <2 x i64> @umax_zext_vec(<2 x i32> %a) {<br>
; CHECK-LABEL: @umax_zext_vec(<br>
; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> %a to <2 x i64><br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2><br>
-; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3><br>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3><br>
+; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 3, i64 3>, <2 x i64> [[A_EXT]]<br>
; CHECK-NEXT: ret <2 x i64> [[MAX]]<br>
;<br>
%a_ext = zext <2 x i32> %a to <2 x i64><br>
@@ -473,12 +458,11 @@ define i64 @umin_zext(i32 %a) {<br>
ret i64 %min<br>
}<br>
<br>
-; FIXME<br>
define <2 x i64> @umin_zext_vec(<2 x i32> %a) {<br>
; CHECK-LABEL: @umin_zext_vec(<br>
; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> %a to <2 x i64><br>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3><br>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2><br>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2><br>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 2, i64 2>, <2 x i64> [[A_EXT]]<br>
; CHECK-NEXT: ret <2 x i64> [[MIN]]<br>
;<br>
%a_ext = zext <2 x i32> %a to <2 x i64><br>
<br>
<br>
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