<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Mon, Oct 10, 2016 at 3:29 PM, Justin Bogner <span dir="ltr"><<a href="mailto:mail@justinbogner.com" target="_blank">mail@justinbogner.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><span>Peter Collingbourne via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>><br>
</span>writes:<br>
<span>> You can always use getFlags() and check the flag bit yourself.<br>
><br>
> A nice cleanup may be to replace all of the remaining functions with a<br>
> single hasFlag() function that takes an MCID::Flag.<br>
<br>
</span>Maybe, but the old way has nice documentation for each method and the<br>
API shows you a complete list of what's reasonable to check. Now there's<br>
just a seemingly random spattering of provided API, so users will have<br>
to switch between this and implementing the checks themselves depending<br>
on the flag. I think we should put these back (or remove all of them,<br>
but that seems distinctly worse from an API standpoint)<br>
<br>
On a similar note, there are more bizarre API asynchronies introduced<br>
here, like having a pure virtual getStartLoc with no getEndLoc. It<br>
doesn't even really save code, since every subclass implements it<br>
anyway. This is awkward and, in my opinion, does more harm than good.<br>
<br>
What's the motivation for this change, anyway? I'd rather we revert it.<br></blockquote><div><br></div><div>Okay, I have no strong opinions about this change, so I've reverted it in r283814.</div><div><br></div><div>Peter</div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<div><div><br>
> Peter<br>
><br>
> On Mon, Oct 10, 2016 at 2:20 PM, Aditya Nandakumar <<br>
> <a href="mailto:aditya_nandakumar@apple.com" target="_blank">aditya_nandakumar@apple.com</a>> wrote:<br>
><br>
>> Hi Peter<br>
>><br>
>> I see that you’ve deleted some methods such as isMoveImmediate() or<br>
>> isBitcast() from MCinstrDesc.<br>
>> If out of tree code would need to check for the above conditions, there is<br>
>> no way of doing that if we delete the above.<br>
>> For completeness sake, shouldn’t all of the methods which check the values<br>
>> of Flag bitfields be present as there is no other way of accessing them?<br>
>><br>
>> Thanks<br>
>> Aditya<br>
>> > On Oct 8, 2016, at 9:39 PM, Peter Collingbourne via llvm-commits <<br>
>> <a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br>
>> ><br>
>> > Author: pcc<br>
>> > Date: Sat Oct 8 23:39:13 2016<br>
>> > New Revision: 283691<br>
>> ><br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project?rev=283691&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject?rev=283691&view=rev</a><br>
>> > Log:<br>
>> > MC: Remove unused entities.<br>
>> ><br>
>> > Removed:<br>
>> > llvm/trunk/lib/MC/MCWinEH.cpp<br>
>> > Modified:<br>
>> > llvm/trunk/include/llvm/MC/MCI<wbr>nstrDesc.h<br>
>> > llvm/trunk/include/llvm/MC/MCM<wbr>achObjectWriter.h<br>
>> > llvm/trunk/include/llvm/MC/MCP<wbr>arser/MCParsedAsmOperand.h<br>
>> > llvm/trunk/include/llvm/MC/MCP<wbr>arser/MCTargetAsmParser.h<br>
>> > llvm/trunk/include/llvm/MC/MCS<wbr>treamer.h<br>
>> > llvm/trunk/include/llvm/MC/MCW<wbr>in64EH.h<br>
>> > llvm/trunk/include/llvm/MC/MCW<wbr>inEH.h<br>
>> > llvm/trunk/lib/MC/CMakeLists.t<wbr>xt<br>
>> > llvm/trunk/lib/MC/MCAsmStreame<wbr>r.cpp<br>
>> > llvm/trunk/lib/MC/MCStreamer.c<wbr>pp<br>
>> > llvm/trunk/lib/Target/AArch64/<wbr>AsmParser/AArch64AsmParser.cpp<br>
>> > llvm/trunk/lib/Target/AMDGPU/A<wbr>smParser/AMDGPUAsmParser.cpp<br>
>> > llvm/trunk/lib/Target/ARM/AsmP<wbr>arser/ARMAsmParser.cpp<br>
>> > llvm/trunk/lib/Target/Hexagon/<wbr>AsmParser/HexagonAsmParser.cpp<br>
>> > llvm/trunk/lib/Target/Lanai/As<wbr>mParser/LanaiAsmParser.cpp<br>
>> > llvm/trunk/lib/Target/Mips/Asm<wbr>Parser/MipsAsmParser.cpp<br>
>> > llvm/trunk/lib/Target/PowerPC/<wbr>AsmParser/PPCAsmParser.cpp<br>
>> > llvm/trunk/lib/Target/Sparc/As<wbr>mParser/SparcAsmParser.cpp<br>
>> > llvm/trunk/lib/Target/SystemZ/<wbr>AsmParser/SystemZAsmParser.cpp<br>
>> > llvm/trunk/lib/Target/X86/AsmP<wbr>arser/X86AsmParser.cpp<br>
>> > llvm/trunk/lib/Target/X86/AsmP<wbr>arser/X86Operand.h<br>
>> > llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86WinCOFFStreamer.<wbr>cpp<br>
>> > llvm/trunk/utils/TableGen/AsmM<wbr>atcherEmitter.cpp<br>
>> ><br>
>> > Modified: llvm/trunk/include/llvm/MC/MCI<wbr>nstrDesc.h<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/</a><br>
>> llvm/MC/MCInstrDesc.h?rev=2836<wbr>91&r1=283690&r2=283691&view=<wbr>diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/include/llvm/MC/MCI<wbr>nstrDesc.h (original)<br>
>> > +++ llvm/trunk/include/llvm/MC/MCI<wbr>nstrDesc.h Sat Oct 8 23:39:13 2016<br>
>> > @@ -294,80 +294,13 @@ public:<br>
>> > /// \brief Return true if this instruction is a comparison.<br>
>> > bool isCompare() const { return Flags & (1ULL << MCID::Compare); }<br>
>> ><br>
>> > - /// \brief Return true if this instruction is a move immediate<br>
>> > - /// (including conditional moves) instruction.<br>
>> > - bool isMoveImmediate() const { return Flags & (1ULL <<<br>
>> MCID::MoveImm); }<br>
>> > -<br>
>> > - /// \brief Return true if this instruction is a bitcast instruction.<br>
>> > - bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }<br>
>> > -<br>
>> > /// \brief Return true if this is a select instruction.<br>
>> > bool isSelect() const { return Flags & (1ULL << MCID::Select); }<br>
>> ><br>
>> > - /// \brief Return true if this instruction cannot be safely<br>
>> > - /// duplicated. For example, if the instruction has a unique labels<br>
>> attached<br>
>> > - /// to it, duplicating it would cause multiple definition errors.<br>
>> > - bool isNotDuplicable() const { return Flags & (1ULL <<<br>
>> MCID::NotDuplicable); }<br>
>> > -<br>
>> > /// \brief Returns true if the specified instruction has a delay slot<br>
>> which<br>
>> > /// must be filled by the code generator.<br>
>> > bool hasDelaySlot() const { return Flags & (1ULL << MCID::DelaySlot); }<br>
>> ><br>
>> > - /// \brief Return true for instructions that can be folded as memory<br>
>> operands<br>
>> > - /// in other instructions. The most common use for this is<br>
>> instructions that<br>
>> > - /// are simple loads from memory that don't modify the loaded value<br>
>> in any<br>
>> > - /// way, but it can also be used for instructions that can be<br>
>> expressed as<br>
>> > - /// constant-pool loads, such as V_SETALLONES on x86, to allow them<br>
>> to be<br>
>> > - /// folded when it is beneficial. This should only be set on<br>
>> instructions<br>
>> > - /// that return a value in their only virtual register definition.<br>
>> > - bool canFoldAsLoad() const { return Flags & (1ULL <<<br>
>> MCID::FoldableAsLoad); }<br>
>> > -<br>
>> > - /// \brief Return true if this instruction behaves<br>
>> > - /// the same way as the generic REG_SEQUENCE instructions.<br>
>> > - /// E.g., on ARM,<br>
>> > - /// dX VMOVDRR rY, rZ<br>
>> > - /// is equivalent to<br>
>> > - /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.<br>
>> > - ///<br>
>> > - /// Note that for the optimizers to be able to take advantage of<br>
>> > - /// this property, TargetInstrInfo::getRegSequenc<wbr>eLikeInputs has to<br>
>> be<br>
>> > - /// override accordingly.<br>
>> > - bool isRegSequenceLike() const { return Flags & (1ULL <<<br>
>> MCID::RegSequence); }<br>
>> > -<br>
>> > - /// \brief Return true if this instruction behaves<br>
>> > - /// the same way as the generic EXTRACT_SUBREG instructions.<br>
>> > - /// E.g., on ARM,<br>
>> > - /// rX, rY VMOVRRD dZ<br>
>> > - /// is equivalent to two EXTRACT_SUBREG:<br>
>> > - /// rX = EXTRACT_SUBREG dZ, ssub_0<br>
>> > - /// rY = EXTRACT_SUBREG dZ, ssub_1<br>
>> > - ///<br>
>> > - /// Note that for the optimizers to be able to take advantage of<br>
>> > - /// this property, TargetInstrInfo::getExtractSub<wbr>regLikeInputs has<br>
>> to be<br>
>> > - /// override accordingly.<br>
>> > - bool isExtractSubregLike() const {<br>
>> > - return Flags & (1ULL << MCID::ExtractSubreg);<br>
>> > - }<br>
>> > -<br>
>> > - /// \brief Return true if this instruction behaves<br>
>> > - /// the same way as the generic INSERT_SUBREG instructions.<br>
>> > - /// E.g., on ARM,<br>
>> > - /// dX = VSETLNi32 dY, rZ, Imm<br>
>> > - /// is equivalent to a INSERT_SUBREG:<br>
>> > - /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)<br>
>> > - ///<br>
>> > - /// Note that for the optimizers to be able to take advantage of<br>
>> > - /// this property, TargetInstrInfo::getInsertSubr<wbr>egLikeInputs has to<br>
>> be<br>
>> > - /// override accordingly.<br>
>> > - bool isInsertSubregLike() const { return Flags & (1ULL <<<br>
>> MCID::InsertSubreg); }<br>
>> > -<br>
>> > -<br>
>> > - /// \brief Return true if this instruction is convergent.<br>
>> > - ///<br>
>> > - /// Convergent instructions may not be made control-dependent on any<br>
>> > - /// additional values.<br>
>> > - bool isConvergent() const { return Flags & (1ULL <<<br>
>> MCID::Convergent); }<br>
>> > -<br>
>> > //===------------------------<wbr>------------------------------<wbr>-<br>
>> -------------===//<br>
>> > // Side Effect Analysis<br>
>> > //===------------------------<wbr>------------------------------<wbr>-<br>
>> -------------===//<br>
>> > @@ -383,22 +316,6 @@ public:<br>
>> > /// may not actually modify anything, for example.<br>
>> > bool mayStore() const { return Flags & (1ULL << MCID::MayStore); }<br>
>> ><br>
>> > - /// \brief Return true if this instruction has side<br>
>> > - /// effects that are not modeled by other flags. This does not<br>
>> return true<br>
>> > - /// for instructions whose effects are captured by:<br>
>> > - ///<br>
>> > - /// 1. Their operand list and implicit definition/use list.<br>
>> Register use/def<br>
>> > - /// info is explicit for instructions.<br>
>> > - /// 2. Memory accesses. Use mayLoad/mayStore.<br>
>> > - /// 3. Calling, branching, returning: use isCall/isReturn/isBranch.<br>
>> > - ///<br>
>> > - /// Examples of side effects would be modifying 'invisible' machine<br>
>> state like<br>
>> > - /// a control register, flushing a cache, modifying a register<br>
>> invisible to<br>
>> > - /// LLVM, etc.<br>
>> > - bool hasUnmodeledSideEffects() const {<br>
>> > - return Flags & (1ULL << MCID::UnmodeledSideEffects);<br>
>> > - }<br>
>> > -<br>
>> > //===------------------------<wbr>------------------------------<wbr>-<br>
>> -------------===//<br>
>> > // Flags that indicate whether an instruction can be modified by a<br>
>> method.<br>
>> > //===------------------------<wbr>------------------------------<wbr>-<br>
>> -------------===//<br>
>> > @@ -415,36 +332,6 @@ public:<br>
>> > /// commute them.<br>
>> > bool isCommutable() const { return Flags & (1ULL << MCID::Commutable);<br>
>> }<br>
>> ><br>
>> > - /// \brief Return true if this is a 2-address instruction which can<br>
>> be changed<br>
>> > - /// into a 3-address instruction if needed. Doing this<br>
>> transformation can be<br>
>> > - /// profitable in the register allocator, because it means that the<br>
>> > - /// instruction can use a 2-address form if possible, but degrade<br>
>> into a less<br>
>> > - /// efficient form if the source and dest register cannot be assigned<br>
>> to the<br>
>> > - /// same register. For example, this allows the x86 backend to turn<br>
>> a "shl<br>
>> > - /// reg, 3" instruction into an LEA instruction, which is the same<br>
>> speed as<br>
>> > - /// the shift but has bigger code size.<br>
>> > - ///<br>
>> > - /// If this returns true, then the target must implement the<br>
>> > - /// TargetInstrInfo::convertToThre<wbr>eAddress method for this<br>
>> instruction, which<br>
>> > - /// is allowed to fail if the transformation isn't valid for this<br>
>> specific<br>
>> > - /// instruction (e.g. shl reg, 4 on x86).<br>
>> > - ///<br>
>> > - bool isConvertibleTo3Addr() const {<br>
>> > - return Flags & (1ULL << MCID::ConvertibleTo3Addr);<br>
>> > - }<br>
>> > -<br>
>> > - /// \brief Return true if this instruction requires custom insertion<br>
>> support<br>
>> > - /// when the DAG scheduler is inserting it into a machine basic<br>
>> block. If<br>
>> > - /// this is true for the instruction, it basically means that it is a<br>
>> pseudo<br>
>> > - /// instruction used at SelectionDAG time that is expanded out into<br>
>> magic code<br>
>> > - /// by the target when MachineInstrs are formed.<br>
>> > - ///<br>
>> > - /// If this is true, the TargetLoweringInfo::InsertAtEn<wbr>dOfBasicBlock<br>
>> method<br>
>> > - /// is used to insert this into the MachineBasicBlock.<br>
>> > - bool usesCustomInsertionHook() const {<br>
>> > - return Flags & (1ULL << MCID::UsesCustomInserter);<br>
>> > - }<br>
>> > -<br>
>> > /// \brief Return true if this instruction requires *adjustment* after<br>
>> > /// instruction selection by calling a target hook. For example, this<br>
>> can be<br>
>> > /// used to fill in ARM 's' optional operand depending on whether the<br>
>> > @@ -461,37 +348,6 @@ public:<br>
>> > return Flags & (1ULL << MCID::Rematerializable);<br>
>> > }<br>
>> ><br>
>> > - /// \brief Returns true if this instruction has the same cost (or<br>
>> less) than a<br>
>> > - /// move instruction. This is useful during certain types of<br>
>> optimizations<br>
>> > - /// (e.g., remat during two-address conversion or machine licm) where<br>
>> we would<br>
>> > - /// like to remat or hoist the instruction, but not if it costs more<br>
>> than<br>
>> > - /// moving the instruction into the appropriate register. Note, we<br>
>> are not<br>
>> > - /// marking copies from and to the same register class with this flag.<br>
>> > - ///<br>
>> > - /// This method could be called by interface TargetInstrInfo::<br>
>> isAsCheapAsAMove<br>
>> > - /// for different subtargets.<br>
>> > - bool isAsCheapAsAMove() const { return Flags & (1ULL <<<br>
>> MCID::CheapAsAMove); }<br>
>> > -<br>
>> > - /// \brief Returns true if this instruction source operands have<br>
>> special<br>
>> > - /// register allocation requirements that are not captured by the<br>
>> operand<br>
>> > - /// register classes. e.g. ARM::STRD's two source registers must be<br>
>> an even /<br>
>> > - /// odd pair, ARM::STM registers have to be in ascending order.<br>
>> Post-register<br>
>> > - /// allocation passes should not attempt to change allocations for<br>
>> sources of<br>
>> > - /// instructions with this flag.<br>
>> > - bool hasExtraSrcRegAllocReq() const {<br>
>> > - return Flags & (1ULL << MCID::ExtraSrcRegAllocReq);<br>
>> > - }<br>
>> > -<br>
>> > - /// \brief Returns true if this instruction def operands have special<br>
>> register<br>
>> > - /// allocation requirements that are not captured by the operand<br>
>> register<br>
>> > - /// classes. e.g. ARM::LDRD's two def registers must be an even / odd<br>
>> pair,<br>
>> > - /// ARM::LDM registers have to be in ascending order. Post-register<br>
>> > - /// allocation passes should not attempt to change allocations for<br>
>> definitions<br>
>> > - /// of instructions with this flag.<br>
>> > - bool hasExtraDefRegAllocReq() const {<br>
>> > - return Flags & (1ULL << MCID::ExtraDefRegAllocReq);<br>
>> > - }<br>
>> > -<br>
>> > /// \brief Return a list of registers that are potentially read by any<br>
>> > /// instance of this machine instruction. For example, on X86, the<br>
>> "adc"<br>
>> > /// instruction adds two register operands and adds the carry bit in<br>
>> from the<br>
>> > @@ -535,16 +391,6 @@ public:<br>
>> > }<br>
>> ><br>
>> > /// \brief Return true if this instruction implicitly<br>
>> > - /// uses the specified physical register.<br>
>> > - bool hasImplicitUseOfPhysReg(unsign<wbr>ed Reg) const {<br>
>> > - if (const MCPhysReg *ImpUses = ImplicitUses)<br>
>> > - for (; *ImpUses; ++ImpUses)<br>
>> > - if (*ImpUses == Reg)<br>
>> > - return true;<br>
>> > - return false;<br>
>> > - }<br>
>> > -<br>
>> > - /// \brief Return true if this instruction implicitly<br>
>> > /// defines the specified physical register.<br>
>> > bool hasImplicitDefOfPhysReg(unsign<wbr>ed Reg,<br>
>> > const MCRegisterInfo *MRI = nullptr)<br>
>> const;<br>
>> ><br>
>> > Modified: llvm/trunk/include/llvm/MC/MCM<wbr>achObjectWriter.h<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/</a><br>
>> llvm/MC/MCMachObjectWriter.h?r<wbr>ev=283691&r1=283690&r2=283691&<wbr>view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/include/llvm/MC/MCM<wbr>achObjectWriter.h (original)<br>
>> > +++ llvm/trunk/include/llvm/MC/MCM<wbr>achObjectWriter.h Sat Oct 8 23:39:13<br>
>> 2016<br>
>> > @@ -27,16 +27,11 @@ class MCMachObjectTargetWriter {<br>
>> > const unsigned Is64Bit : 1;<br>
>> > const uint32_t CPUType;<br>
>> > const uint32_t CPUSubtype;<br>
>> > - unsigned LocalDifference_RIT;<br>
>> ><br>
>> > protected:<br>
>> > MCMachObjectTargetWriter(bool Is64Bit_, uint32_t CPUType_,<br>
>> > uint32_t CPUSubtype_);<br>
>> ><br>
>> > - void setLocalDifferenceRelocationTy<wbr>pe(unsigned Type) {<br>
>> > - LocalDifference_RIT = Type;<br>
>> > - }<br>
>> > -<br>
>> > public:<br>
>> > virtual ~MCMachObjectTargetWriter();<br>
>> ><br>
>> > @@ -53,9 +48,6 @@ public:<br>
>> > bool is64Bit() const { return Is64Bit; }<br>
>> > uint32_t getCPUType() const { return CPUType; }<br>
>> > uint32_t getCPUSubtype() const { return CPUSubtype; }<br>
>> > - unsigned getLocalDifferenceRelocationTy<wbr>pe() const {<br>
>> > - return LocalDifference_RIT;<br>
>> > - }<br>
>> ><br>
>> > /// @}<br>
>> ><br>
>> ><br>
>> > Modified: llvm/trunk/include/llvm/MC/MCP<wbr>arser/MCParsedAsmOperand.h<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/</a><br>
>> llvm/MC/MCParser/MCParsedAsmOp<wbr>erand.h?rev=283691&r1=283690&<wbr>r2=283691&<br>
>> view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/include/llvm/MC/MCP<wbr>arser/MCParsedAsmOperand.h (original)<br>
>> > +++ llvm/trunk/include/llvm/MC/MCP<wbr>arser/MCParsedAsmOperand.h Sat Oct 8<br>
>> 23:39:13 2016<br>
>> > @@ -64,21 +64,11 @@ public:<br>
>> ><br>
>> > /// getStartLoc - Get the location of the first token of this operand.<br>
>> > virtual SMLoc getStartLoc() const = 0;<br>
>> > - /// getEndLoc - Get the location of the last token of this operand.<br>
>> > - virtual SMLoc getEndLoc() const = 0;<br>
>> ><br>
>> > /// needAddressOf - Do we need to emit code to get the address of the<br>
>> > /// variable/label? Only valid when parsing MS-style inline assembly.<br>
>> > virtual bool needAddressOf() const { return false; }<br>
>> ><br>
>> > - /// isOffsetOf - Do we need to emit code to get the offset of the<br>
>> variable,<br>
>> > - /// rather then the value of the variable? Only valid when parsing<br>
>> MS-style<br>
>> > - /// inline assembly.<br>
>> > - virtual bool isOffsetOf() const { return false; }<br>
>> > -<br>
>> > - /// getOffsetOfLoc - Get the location of the offset operator.<br>
>> > - virtual SMLoc getOffsetOfLoc() const { return SMLoc(); }<br>
>> > -<br>
>> > /// print - Print a debug representation of the operand to the given<br>
>> stream.<br>
>> > virtual void print(raw_ostream &OS) const = 0;<br>
>> > /// dump - Print to the debug stream.<br>
>> ><br>
>> > Modified: llvm/trunk/include/llvm/MC/MCP<wbr>arser/MCTargetAsmParser.h<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/</a><br>
>> llvm/MC/MCParser/MCTargetAsmPa<wbr>rser.h?rev=283691&r1=283690&<wbr>r2=283691&<br>
>> view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/include/llvm/MC/MCP<wbr>arser/MCTargetAsmParser.h (original)<br>
>> > +++ llvm/trunk/include/llvm/MC/MCP<wbr>arser/MCTargetAsmParser.h Sat Oct 8<br>
>> 23:39:13 2016<br>
>> > @@ -209,9 +209,6 @@ public:<br>
>> > return Match_Success;<br>
>> > }<br>
>> ><br>
>> > - virtual void convertToMapAndConstraints(uns<wbr>igned Kind,<br>
>> > - const OperandVector<br>
>> &Operands) = 0;<br>
>> > -<br>
>> > // Return whether this parser uses assignment statements with equals<br>
>> tokens<br>
>> > virtual bool equalIsAsmAssignment() { return true; };<br>
>> > // Return whether this start of statement identifier is a label<br>
>> ><br>
>> > Modified: llvm/trunk/include/llvm/MC/MCS<wbr>treamer.h<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/</a><br>
>> llvm/MC/MCStreamer.h?rev=28369<wbr>1&r1=283690&r2=283691&view=<wbr>diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/include/llvm/MC/MCS<wbr>treamer.h (original)<br>
>> > +++ llvm/trunk/include/llvm/MC/MCS<wbr>treamer.h Sat Oct 8 23:39:13 2016<br>
>> > @@ -199,8 +199,6 @@ protected:<br>
>> > return CurrentWinFrameInfo;<br>
>> > }<br>
>> ><br>
>> > - virtual void EmitWindowsUnwindTables();<br>
>> > -<br>
>> > virtual void EmitRawTextImpl(StringRef String);<br>
>> ><br>
>> > public:<br>
>> > @@ -277,8 +275,6 @@ public:<br>
>> > /// \brief Add explicit comment T. T is required to be a valid<br>
>> > /// comment in the output and does not need to be escaped.<br>
>> > virtual void addExplicitComment(const Twine &T);<br>
>> > - /// \brief Emit added explicit comments.<br>
>> > - virtual void emitExplicitComments();<br>
>> ><br>
>> > /// AddBlankLine - Emit a blank line to a .s file to pretty it up.<br>
>> > virtual void AddBlankLine() {}<br>
>> ><br>
>> > Modified: llvm/trunk/include/llvm/MC/MCW<wbr>in64EH.h<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/</a><br>
>> llvm/MC/MCWin64EH.h?rev=283691<wbr>&r1=283690&r2=283691&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/include/llvm/MC/MCW<wbr>in64EH.h (original)<br>
>> > +++ llvm/trunk/include/llvm/MC/MCW<wbr>in64EH.h Sat Oct 8 23:39:13 2016<br>
>> > @@ -51,10 +51,10 @@ struct Instruction {<br>
>> > }<br>
>> > };<br>
>> ><br>
>> > -class UnwindEmitter : public WinEH::UnwindEmitter {<br>
>> > +class UnwindEmitter {<br>
>> > public:<br>
>> > - void Emit(MCStreamer &Streamer) const override;<br>
>> > - void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI) const<br>
>> override;<br>
>> > + void Emit(MCStreamer &Streamer) const;<br>
>> > + void EmitUnwindInfo(MCStreamer &Streamer, WinEH::FrameInfo *FI) const;<br>
>> > };<br>
>> > }<br>
>> > } // end namespace llvm<br>
>> ><br>
>> > Modified: llvm/trunk/include/llvm/MC/MCW<wbr>inEH.h<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/include/</a><br>
>> llvm/MC/MCWinEH.h?rev=283691&r<wbr>1=283690&r2=283691&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/include/llvm/MC/MCW<wbr>inEH.h (original)<br>
>> > +++ llvm/trunk/include/llvm/MC/MCW<wbr>inEH.h Sat Oct 8 23:39:13 2016<br>
>> > @@ -52,15 +52,6 @@ struct FrameInfo {<br>
>> > : Begin(BeginFuncEHLabel), Function(Function),<br>
>> > ChainedParent(ChainedParent) {}<br>
>> > };<br>
>> > -<br>
>> > -class UnwindEmitter {<br>
>> > -public:<br>
>> > - virtual ~UnwindEmitter();<br>
>> > -<br>
>> > - /// This emits the unwind info sections (.pdata and .xdata in<br>
>> PE/COFF).<br>
>> > - virtual void Emit(MCStreamer &Streamer) const = 0;<br>
>> > - virtual void EmitUnwindInfo(MCStreamer &Streamer, FrameInfo *FI)<br>
>> const = 0;<br>
>> > -};<br>
>> > }<br>
>> > }<br>
>> ><br>
>> ><br>
>> > Modified: llvm/trunk/lib/MC/CMakeLists.t<wbr>xt<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/MC/</a><br>
>> CMakeLists.txt?rev=283691&r1=2<wbr>83690&r2=283691&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/MC/CMakeLists.t<wbr>xt (original)<br>
>> > +++ llvm/trunk/lib/MC/CMakeLists.t<wbr>xt Sat Oct 8 23:39:13 2016<br>
>> > @@ -41,7 +41,6 @@ add_llvm_library(LLVMMC<br>
>> > MCTargetOptions.cpp<br>
>> > MCValue.cpp<br>
>> > MCWin64EH.cpp<br>
>> > - MCWinEH.cpp<br>
>> > MachObjectWriter.cpp<br>
>> > StringTableBuilder.cpp<br>
>> > SubtargetFeature.cpp<br>
>> ><br>
>> > Modified: llvm/trunk/lib/MC/MCAsmStreame<wbr>r.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/MC/</a><br>
>> MCAsmStreamer.cpp?rev=283691&r<wbr>1=283690&r2=283691&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/MC/MCAsmStreame<wbr>r.cpp (original)<br>
>> > +++ llvm/trunk/lib/MC/MCAsmStreame<wbr>r.cpp Sat Oct 8 23:39:13 2016<br>
>> > @@ -117,7 +117,7 @@ public:<br>
>> > void emitRawComment(const Twine &T, bool TabPrefix = true) override;<br>
>> ><br>
>> > void addExplicitComment(const Twine &T) override;<br>
>> > - void emitExplicitComments() override;<br>
>> > + void emitExplicitComments();<br>
>> ><br>
>> > /// AddBlankLine - Emit a blank line to a .s file to pretty it up.<br>
>> > void AddBlankLine() override {<br>
>> ><br>
>> > Modified: llvm/trunk/lib/MC/MCStreamer.c<wbr>pp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/MC/</a><br>
>> MCStreamer.cpp?rev=283691&r1=2<wbr>83690&r2=283691&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/MC/MCStreamer.c<wbr>pp (original)<br>
>> > +++ llvm/trunk/lib/MC/MCStreamer.c<wbr>pp Sat Oct 8 23:39:13 2016<br>
>> > @@ -72,7 +72,6 @@ raw_ostream &MCStreamer::GetCommentOS()<br>
>> > void MCStreamer::emitRawComment(con<wbr>st Twine &T, bool TabPrefix) {}<br>
>> ><br>
>> > void MCStreamer::addExplicitComment<wbr>(const Twine &T) {}<br>
>> > -void MCStreamer::emitExplicitCommen<wbr>ts() {}<br>
>> ><br>
>> > void MCStreamer::generateCompactUnw<wbr>indEncodings(MCAsmBackend *MAB) {<br>
>> > for (auto &FI : DwarfFrameInfos)<br>
>> > @@ -713,9 +712,6 @@ void MCStreamer::EmitRawText(const Twine<br>
>> > EmitRawTextImpl(T.<wbr>toStringRef(Str));<br>
>> > }<br>
>> ><br>
>> > -void MCStreamer::EmitWindowsUnwindT<wbr>ables() {<br>
>> > -}<br>
>> > -<br>
>> > void MCStreamer::Finish() {<br>
>> > if (!DwarfFrameInfos.empty() && !DwarfFrameInfos.back().End)<br>
>> > report_fatal_error("<wbr>Unfinished frame!");<br>
>> ><br>
>> > Removed: llvm/trunk/lib/MC/MCWinEH.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/MC/</a><br>
>> MCWinEH.cpp?rev=283690&view=au<wbr>to<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/MC/MCWinEH.cpp (original)<br>
>> > +++ llvm/trunk/lib/MC/MCWinEH.cpp (removed)<br>
>> > @@ -1,26 +0,0 @@<br>
>> > -//===- lib/MC/MCWinEH.cpp - Windows EH implementation<br>
>> ---------------------===//<br>
>> > -//<br>
>> > -// The LLVM Compiler Infrastructure<br>
>> > -//<br>
>> > -// This file is distributed under the University of Illinois Open Source<br>
>> > -// License. See LICENSE.TXT for details.<br>
>> > -//<br>
>> > -//===------------------------<wbr>------------------------------<br>
>> ----------------===//<br>
>> > -<br>
>> > -#include "llvm/ADT/StringRef.h"<br>
>> > -#include "llvm/MC/MCContext.h"<br>
>> > -#include "llvm/MC/MCObjectFileInfo.h"<br>
>> > -#include "llvm/MC/MCSectionCOFF.h"<br>
>> > -#include "llvm/MC/MCStreamer.h"<br>
>> > -#include "llvm/MC/MCSymbol.h"<br>
>> > -#include "llvm/MC/MCWinEH.h"<br>
>> > -#include "llvm/Support/COFF.h"<br>
>> > -<br>
>> > -namespace llvm {<br>
>> > -namespace WinEH {<br>
>> > -<br>
>> > -UnwindEmitter::~UnwindEmitter<wbr>() {}<br>
>> > -<br>
>> > -}<br>
>> > -}<br>
>> > -<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/AArch64/<wbr>AsmParser/AArch64AsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> AArch64/AsmParser/AArch64AsmPa<wbr>rser.cpp?rev=283691&r1=283690&<wbr>r2=283691&<br>
>> view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/AArch64/<wbr>AsmParser/AArch64AsmParser.cpp<br>
>> (original)<br>
>> > +++ llvm/trunk/lib/Target/AArch64/<wbr>AsmParser/AArch64AsmParser.cpp Sat<br>
>> Oct 8 23:39:13 2016<br>
>> > @@ -326,7 +326,7 @@ public:<br>
>> > /// getStartLoc - Get the location of the first token of this operand.<br>
>> > SMLoc getStartLoc() const override { return StartLoc; }<br>
>> > /// getEndLoc - Get the location of the last token of this operand.<br>
>> > - SMLoc getEndLoc() const override { return EndLoc; }<br>
>> > + SMLoc getEndLoc() const { return EndLoc; }<br>
>> ><br>
>> > StringRef getToken() const {<br>
>> > assert(Kind == k_Token && "Invalid access!");<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/AMDGPU/A<wbr>smParser/AMDGPUAsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> AMDGPU/AsmParser/AMDGPUAsmPars<wbr>er.cpp?rev=283691&r1=283690&<wbr>r2=283691&<br>
>> view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/AMDGPU/A<wbr>smParser/AMDGPUAsmParser.cpp<br>
>> (original)<br>
>> > +++ llvm/trunk/lib/Target/AMDGPU/A<wbr>smParser/AMDGPUAsmParser.cpp Sat Oct<br>
>> 8 23:39:13 2016<br>
>> > @@ -379,7 +379,7 @@ public:<br>
>> > return StartLoc;<br>
>> > }<br>
>> ><br>
>> > - SMLoc getEndLoc() const override {<br>
>> > + SMLoc getEndLoc() const {<br>
>> > return EndLoc;<br>
>> > }<br>
>> ><br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/ARM/AsmP<wbr>arser/ARMAsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> ARM/AsmParser/ARMAsmParser.cpp<wbr>?rev=283691&r1=283690&r2=28369<wbr>1&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/ARM/AsmP<wbr>arser/ARMAsmParser.cpp (original)<br>
>> > +++ llvm/trunk/lib/Target/ARM/AsmP<wbr>arser/ARMAsmParser.cpp Sat Oct 8<br>
>> 23:39:13 2016<br>
>> > @@ -752,7 +752,7 @@ public:<br>
>> > /// getStartLoc - Get the location of the first token of this operand.<br>
>> > SMLoc getStartLoc() const override { return StartLoc; }<br>
>> > /// getEndLoc - Get the location of the last token of this operand.<br>
>> > - SMLoc getEndLoc() const override { return EndLoc; }<br>
>> > + SMLoc getEndLoc() const { return EndLoc; }<br>
>> > /// getLocRange - Get the range between the first and last token of<br>
>> this<br>
>> > /// operand.<br>
>> > SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/Hexagon/<wbr>AsmParser/HexagonAsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> Hexagon/AsmParser/HexagonAsmPa<wbr>rser.cpp?rev=283691&r1=283690&<wbr>r2=283691&<br>
>> view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/Hexagon/<wbr>AsmParser/HexagonAsmParser.cpp<br>
>> (original)<br>
>> > +++ llvm/trunk/lib/Target/Hexagon/<wbr>AsmParser/HexagonAsmParser.cpp Sat<br>
>> Oct 8 23:39:13 2016<br>
>> > @@ -222,7 +222,7 @@ public:<br>
>> > SMLoc getStartLoc() const { return StartLoc; }<br>
>> ><br>
>> > /// getEndLoc - Get the location of the last token of this operand.<br>
>> > - SMLoc getEndLoc() const { return EndLoc; }<br>
>> > + SMLoc getEndLoc() { return EndLoc; }<br>
>> ><br>
>> > unsigned getReg() const {<br>
>> > assert(Kind == Register && "Invalid access!");<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/Lanai/As<wbr>mParser/LanaiAsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> Lanai/AsmParser/LanaiAsmParser<wbr>.cpp?rev=283691&<br>
>> r1=283690&r2=283691&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/Lanai/As<wbr>mParser/LanaiAsmParser.cpp (original)<br>
>> > +++ llvm/trunk/lib/Target/Lanai/As<wbr>mParser/LanaiAsmParser.cpp Sat Oct 8<br>
>> 23:39:13 2016<br>
>> > @@ -134,7 +134,7 @@ public:<br>
>> > SMLoc getStartLoc() const override { return StartLoc; }<br>
>> ><br>
>> > // getEndLoc - Gets location of the last token of this operand<br>
>> > - SMLoc getEndLoc() const override { return EndLoc; }<br>
>> > + SMLoc getEndLoc() const { return EndLoc; }<br>
>> ><br>
>> > unsigned getReg() const override {<br>
>> > assert(isReg() && "Invalid type access!");<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/Mips/Asm<wbr>Parser/MipsAsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> Mips/AsmParser/MipsAsmParser.c<wbr>pp?rev=283691&r1=283690&r2=283<wbr>691&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/Mips/Asm<wbr>Parser/MipsAsmParser.cpp (original)<br>
>> > +++ llvm/trunk/lib/Target/Mips/Asm<wbr>Parser/MipsAsmParser.cpp Sat Oct 8<br>
>> 23:39:13 2016<br>
>> > @@ -1474,7 +1474,7 @@ public:<br>
>> > /// getStartLoc - Get the location of the first token of this operand.<br>
>> > SMLoc getStartLoc() const override { return StartLoc; }<br>
>> > /// getEndLoc - Get the location of the last token of this operand.<br>
>> > - SMLoc getEndLoc() const override { return EndLoc; }<br>
>> > + SMLoc getEndLoc() const { return EndLoc; }<br>
>> ><br>
>> > virtual ~MipsOperand() {<br>
>> > switch (Kind) {<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/PowerPC/<wbr>AsmParser/PPCAsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> PowerPC/AsmParser/PPCAsmParser<wbr>.cpp?rev=283691&<br>
>> r1=283690&r2=283691&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/PowerPC/<wbr>AsmParser/PPCAsmParser.cpp (original)<br>
>> > +++ llvm/trunk/lib/Target/PowerPC/<wbr>AsmParser/PPCAsmParser.cpp Sat Oct 8<br>
>> 23:39:13 2016<br>
>> > @@ -394,7 +394,7 @@ public:<br>
>> > SMLoc getStartLoc() const override { return StartLoc; }<br>
>> ><br>
>> > /// getEndLoc - Get the location of the last token of this operand.<br>
>> > - SMLoc getEndLoc() const override { return EndLoc; }<br>
>> > + SMLoc getEndLoc() const { return EndLoc; }<br>
>> ><br>
>> > /// isPPC64 - True if this operand is for an instruction in 64-bit<br>
>> mode.<br>
>> > bool isPPC64() const { return IsPPC64; }<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/Sparc/As<wbr>mParser/SparcAsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> Sparc/AsmParser/SparcAsmParser<wbr>.cpp?rev=283691&<br>
>> r1=283690&r2=283691&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/Sparc/As<wbr>mParser/SparcAsmParser.cpp (original)<br>
>> > +++ llvm/trunk/lib/Target/Sparc/As<wbr>mParser/SparcAsmParser.cpp Sat Oct 8<br>
>> 23:39:13 2016<br>
>> > @@ -281,7 +281,7 @@ public:<br>
>> > return StartLoc;<br>
>> > }<br>
>> > /// getEndLoc - Get the location of the last token of this operand.<br>
>> > - SMLoc getEndLoc() const override {<br>
>> > + SMLoc getEndLoc() const {<br>
>> > return EndLoc;<br>
>> > }<br>
>> ><br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/SystemZ/<wbr>AsmParser/SystemZAsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> SystemZ/AsmParser/SystemZAsmPa<wbr>rser.cpp?rev=283691&r1=283690&<wbr>r2=283691&<br>
>> view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/SystemZ/<wbr>AsmParser/SystemZAsmParser.cpp<br>
>> (original)<br>
>> > +++ llvm/trunk/lib/Target/SystemZ/<wbr>AsmParser/SystemZAsmParser.cpp Sat<br>
>> Oct 8 23:39:13 2016<br>
>> > @@ -261,7 +261,7 @@ public:<br>
>> ><br>
>> > // Override MCParsedAsmOperand.<br>
>> > SMLoc getStartLoc() const override { return StartLoc; }<br>
>> > - SMLoc getEndLoc() const override { return EndLoc; }<br>
>> > + SMLoc getEndLoc() const { return EndLoc; }<br>
>> > void print(raw_ostream &OS) const override;<br>
>> ><br>
>> > // Used by the TableGen code to add particular types of operand<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/X86/AsmP<wbr>arser/X86AsmParser.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> X86/AsmParser/X86AsmParser.cpp<wbr>?rev=283691&r1=283690&r2=28369<wbr>1&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/X86/AsmP<wbr>arser/X86AsmParser.cpp (original)<br>
>> > +++ llvm/trunk/lib/Target/X86/AsmP<wbr>arser/X86AsmParser.cpp Sat Oct 8<br>
>> 23:39:13 2016<br>
>> > @@ -1696,7 +1696,7 @@ std::unique_ptr<X86Operand> X86AsmParser<br>
>> > unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX :<br>
>> X86::BX);<br>
>> ><br>
>> > return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,<br>
>> > - OffsetOfLoc, Identifier, Info.OpDecl);<br>
>> > + Identifier, Info.OpDecl);<br>
>> > }<br>
>> ><br>
>> > enum IntelOperatorKind {<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/X86/AsmP<wbr>arser/X86Operand.h<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> X86/AsmParser/X86Operand.h?rev<wbr>=283691&r1=283690&r2=283691&<wbr>view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/X86/AsmP<wbr>arser/X86Operand.h (original)<br>
>> > +++ llvm/trunk/lib/Target/X86/AsmP<wbr>arser/X86Operand.h Sat Oct 8<br>
>> 23:39:13 2016<br>
>> > @@ -31,7 +31,6 @@ struct X86Operand : public MCParsedAsmOp<br>
>> > } Kind;<br>
>> ><br>
>> > SMLoc StartLoc, EndLoc;<br>
>> > - SMLoc OffsetOfLoc;<br>
>> > StringRef SymName;<br>
>> > void *OpDecl;<br>
>> > bool AddressOf;<br>
>> > @@ -75,12 +74,10 @@ struct X86Operand : public MCParsedAsmOp<br>
>> > /// getStartLoc - Get the location of the first token of this operand.<br>
>> > SMLoc getStartLoc() const override { return StartLoc; }<br>
>> > /// getEndLoc - Get the location of the last token of this operand.<br>
>> > - SMLoc getEndLoc() const override { return EndLoc; }<br>
>> > + SMLoc getEndLoc() const { return EndLoc; }<br>
>> > /// getLocRange - Get the range between the first and last token of<br>
>> this<br>
>> > /// operand.<br>
>> > SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }<br>
>> > - /// getOffsetOfLoc - Get the location of the offset operator.<br>
>> > - SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }<br>
>> ><br>
>> > void print(raw_ostream &OS) const override {}<br>
>> ><br>
>> > @@ -197,10 +194,6 @@ struct X86Operand : public MCParsedAsmOp<br>
>> > return isImmUnsignedi8Value(CE->getVa<wbr>lue());<br>
>> > }<br>
>> ><br>
>> > - bool isOffsetOf() const override {<br>
>> > - return OffsetOfLoc.getPointer();<br>
>> > - }<br>
>> > -<br>
>> > bool needAddressOf() const override {<br>
>> > return AddressOf;<br>
>> > }<br>
>> > @@ -474,12 +467,11 @@ struct X86Operand : public MCParsedAsmOp<br>
>> ><br>
>> > static std::unique_ptr<X86Operand><br>
>> > CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,<br>
>> > - bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),<br>
>> > - StringRef SymName = StringRef(), void *OpDecl = nullptr) {<br>
>> > + bool AddressOf = false, StringRef SymName = StringRef(),<br>
>> > + void *OpDecl = nullptr) {<br>
>> > auto Res = llvm::make_unique<X86Operand>(<wbr>Register, StartLoc,<br>
>> EndLoc);<br>
>> > Res->Reg.RegNo = RegNo;<br>
>> > Res->AddressOf = AddressOf;<br>
>> > - Res->OffsetOfLoc = OffsetOfLoc;<br>
>> > Res->SymName = SymName;<br>
>> > Res->OpDecl = OpDecl;<br>
>> > return Res;<br>
>> ><br>
>> > Modified: llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86WinCOFFStreamer.<wbr>cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/lib/Target/</a><br>
>> X86/MCTargetDesc/X86WinCOFFStr<wbr>eamer.cpp?rev=283691&r1=<wbr>283690&r2=283691&<br>
>> view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86WinCOFFStreamer.<wbr>cpp<br>
>> (original)<br>
>> > +++ llvm/trunk/lib/Target/X86/MCTa<wbr>rgetDesc/X86WinCOFFStreamer.<wbr>cpp Sat<br>
>> Oct 8 23:39:13 2016<br>
>> > @@ -22,7 +22,7 @@ public:<br>
>> > : MCWinCOFFStreamer(C, AB, *CE, OS) {}<br>
>> ><br>
>> > void EmitWinEHHandlerData() override;<br>
>> > - void EmitWindowsUnwindTables() override;<br>
>> > + void EmitWindowsUnwindTables();<br>
>> > void FinishImpl() override;<br>
>> > };<br>
>> ><br>
>> ><br>
>> > Modified: llvm/trunk/utils/TableGen/AsmM<wbr>atcherEmitter.cpp<br>
>> > URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-pr<wbr>oject/llvm/trunk/utils/</a><br>
>> TableGen/AsmMatcherEmitter.cpp<wbr>?rev=283691&r1=283690&r2=28369<wbr>1&view=diff<br>
>> > ==============================<wbr>==============================<br>
>> ==================<br>
>> > --- llvm/trunk/utils/TableGen/AsmM<wbr>atcherEmitter.cpp (original)<br>
>> > +++ llvm/trunk/utils/TableGen/AsmM<wbr>atcherEmitter.cpp Sat Oct 8 23:39:13<br>
>> 2016<br>
>> > @@ -2893,7 +2893,7 @@ void AsmMatcherEmitter::run(raw_ost<wbr>ream<br>
>> > << " const OperandVector &Operands);\n";<br>
>> > }<br>
>> > OS << " void convertToMapAndConstraints(uns<wbr>igned Kind,\n<br>
>> ";<br>
>> > - OS << " const OperandVector &Operands) override;\n";<br>
>> > + OS << " const OperandVector &Operands);\n";<br>
>> > if (HasMnemonicFirst)<br>
>> > OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned<br>
>> VariantID);\n";<br>
>> > OS << " unsigned MatchInstructionImpl(const OperandVector<br>
>> &Operands,\n"<br>
>> ><br>
>> ><br>
>> > ______________________________<wbr>_________________<br>
>> > llvm-commits mailing list<br>
>> > <a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a><br>
>> > <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/<wbr>mailman/listinfo/llvm-commits</a><br>
>><br>
>><br>
><br>
><br>
> --<br>
</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><div><div dir="ltr">-- <div>Peter</div></div></div>
</div></div>