<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
</head>
<body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">
Hi Renato,
<div class=""><br class="">
</div>
<div class="">I’ve reverted this in r281451 - it looks like it caused PR30373 too.</div>
<div class=""><br class="">
</div>
<div class="">Sorry it took so long - that bot was rather slow and I was also deluged by false-positive failmail so I missed it.</div>
<div class=""><br class="">
</div>
<div class="">Cheers,</div>
<div class=""><br class="">
</div>
<div class="">James<br class="">
<div class="">
<div>
<blockquote type="cite" class="">
<div class="">On 14 Sep 2016, at 00:29, Renato Golin <<a href="mailto:renato.golin@linaro.org" class="">renato.golin@linaro.org</a>> wrote:</div>
<br class="Apple-interchange-newline">
<div class="">
<p dir="ltr" class="">Hi James, </p>
<p dir="ltr" class="">This one looks yours, again... </p>
<p dir="ltr" class=""><a href="http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/4073" class="">http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/4073</a></p>
<p dir="ltr" class="">Cheers, <br class="">
Renato </p>
<div class="gmail_extra"><br class="">
<div class="gmail_quote">On 13 Sep 2016 1:21 p.m., "James Molloy via llvm-commits" <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br type="attribution" class="">
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: jamesm<br class="">
Date: Tue Sep 13 07:12:32 2016<br class="">
New Revision: 281323<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=281323&view=rev" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project?rev=281323&view=rev</a><br class="">
Log:<br class="">
[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently<br class="">
<br class="">
For the common pattern (CMPZ (AND x, #bitmask), #0), we can do some more efficient instruction selection if the bitmask is one consecutive sequence of set bits (32 - clz(bm) - ctz(bm) == popcount(bm)).<br class="">
<br class="">
1) If the bitmask touches the LSB, then we can remove all the upper bits and set the flags by doing one LSLS.<br class="">
2) If the bitmask touches the MSB, then we can remove all the lower bits and set the flags with one LSRS.<br class="">
3) If the bitmask has popcount == 1 (only one set bit), we can shift that bit into the sign bit with one LSLS and change the condition query from NE/EQ to MI/PL (we could also implement this by shifting into the carry bit and branching on BCC/BCS).<br class="">
4) Otherwise, we can emit a sequence of LSLS+LSRS to remove the upper and lower zero bits of the mask.<br class="">
<br class="">
1-3 require only one 16-bit instruction and can elide the CMP. 4 requires two 16-bit instructions but can elide the CMP and doesn't require materializing a complex immediate, so is also a win.<br class="">
<br class="">
Added:<br class="">
llvm/trunk/test/CodeGen/ARM/<wbr class="">and-cmpz.ll<br class="">
Modified:<br class="">
llvm/trunk/lib/Target/ARM/<wbr class="">ARMBaseInstrInfo.cpp<br class="">
llvm/trunk/lib/Target/ARM/<wbr class="">ARMISelDAGToDAG.cpp<br class="">
llvm/trunk/test/CodeGen/ARM/<wbr class="">arm-and-tst-peephole.ll<br class="">
llvm/trunk/test/CodeGen/ARM/<wbr class="">arm-shrink-wrapping.ll<br class="">
llvm/trunk/test/CodeGen/ARM/<wbr class="">call-tc.ll<br class="">
llvm/trunk/test/CodeGen/ARM/<wbr class="">debug-info-branch-folding.ll<br class="">
llvm/trunk/test/CodeGen/Thumb/<wbr class="">thumb-shrink-wrapping.ll<br class="">
llvm/trunk/test/CodeGen/<wbr class="">Thumb2/float-ops.ll<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/ARM/<wbr class="">ARMBaseInstrInfo.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">ARM/ARMBaseInstrInfo.cpp?rev=<wbr class="">281323&r1=281322&r2=281323&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/ARM/<wbr class="">ARMBaseInstrInfo.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/ARM/<wbr class="">ARMBaseInstrInfo.cpp Tue Sep 13 07:12:32 2016<br class="">
@@ -2528,7 +2528,11 @@ bool ARMBaseInstrInfo::<wbr class="">optimizeCompareIn<br class="">
case ARM::EORrr:<br class="">
case ARM::EORri:<br class="">
case ARM::t2EORrr:<br class="">
- case ARM::t2EORri: {<br class="">
+ case ARM::t2EORri:<br class="">
+ case ARM::t2LSRri:<br class="">
+ case ARM::t2LSRrr:<br class="">
+ case ARM::t2LSLri:<br class="">
+ case ARM::t2LSLrr: {<br class="">
// Scan forward for the use of CPSR<br class="">
// When checking against MI: if it's a conditional code that requires<br class="">
// checking of the V bit or C bit, then this is not safe to do.<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/ARM/<wbr class="">ARMISelDAGToDAG.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/Target/<wbr class="">ARM/ARMISelDAGToDAG.cpp?rev=<wbr class="">281323&r1=281322&r2=281323&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Target/ARM/<wbr class="">ARMISelDAGToDAG.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/ARM/<wbr class="">ARMISelDAGToDAG.cpp Tue Sep 13 07:12:32 2016<br class="">
@@ -244,7 +244,8 @@ private:<br class="">
bool tryInlineAsm(SDNode *N);<br class="">
<br class="">
void SelectConcatVector(SDNode *N);<br class="">
-<br class="">
+ void SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI);<br class="">
+<br class="">
bool trySMLAWSMULW(SDNode *N);<br class="">
<br class="">
void SelectCMP_SWAP(SDNode *N);<br class="">
@@ -2693,6 +2694,83 @@ void ARMDAGToDAGISel::<wbr class="">SelectConcatVector<br class="">
ReplaceNode(N, createDRegPairNode(VT, N->getOperand(0), N->getOperand(1)));<br class="">
}<br class="">
<br class="">
+static Optional<std::pair<unsigned, unsigned>><br class="">
+getContiguousRangeOfSetBits(<wbr class="">const APInt &A) {<br class="">
+ unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;<br class="">
+ unsigned LastOne = A.countTrailingZeros();<br class="">
+ if (A.countPopulation() != (FirstOne - LastOne + 1))<br class="">
+ return Optional<std::pair<unsigned,<wbr class="">unsigned>>();<br class="">
+ return std::make_pair(FirstOne, LastOne);<br class="">
+}<br class="">
+<br class="">
+void ARMDAGToDAGISel::SelectCMPZ(<wbr class="">SDNode *N, bool &SwitchEQNEToPLMI) {<br class="">
+ assert(N->getOpcode() == ARMISD::CMPZ);<br class="">
+ SwitchEQNEToPLMI = false;<br class="">
+<br class="">
+ if (!Subtarget->isThumb())<br class="">
+ // FIXME: Work out whether it is profitable to do this in A32 mode - LSL and<br class="">
+ // LSR don't exist as standalone instructions - they need the barrel shifter.<br class="">
+ return;<br class="">
+ // select (cmpz (and X, C), #0) -> (LSLS X) or (LSRS X) or (LSRS (LSLS X))<br class="">
+ SDValue And = N->getOperand(0);<br class="">
+ SDValue Zero = N->getOperand(1);<br class="">
+ if (!isa<ConstantSDNode>(Zero) || !cast<ConstantSDNode>(Zero)-><wbr class="">isNullValue() ||<br class="">
+ And->getOpcode() != ISD::AND)<br class="">
+ return;<br class="">
+ SDValue X = And.getOperand(0);<br class="">
+ auto C = dyn_cast<ConstantSDNode>(And.<wbr class="">getOperand(1));<br class="">
+<br class="">
+ if (!C || !X->hasOneUse())<br class="">
+ return;<br class="">
+ auto Range = getContiguousRangeOfSetBits(C-<wbr class="">>getAPIntValue());<br class="">
+ if (!Range)<br class="">
+ return;<br class="">
+<br class="">
+ // There are several ways to lower this:<br class="">
+ SDNode *NewN;<br class="">
+ SDLoc dl(N);<br class="">
+<br class="">
+ auto EmitShift = [&](unsigned Opc, SDValue Src, unsigned Imm) -> SDNode* {<br class="">
+ if (Subtarget->isThumb2()) {<br class="">
+ Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri;<br class="">
+ SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32),<br class="">
+ getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),<br class="">
+ CurDAG->getRegister(0, MVT::i32) };<br class="">
+ return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);<br class="">
+ } else {<br class="">
+ SDValue Ops[] = {CurDAG->getRegister(ARM::<wbr class="">CPSR, MVT::i32), Src,<br class="">
+ CurDAG->getTargetConstant(Imm, dl, MVT::i32),<br class="">
+ getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32)};<br class="">
+ return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);<br class="">
+ }<br class="">
+ };<br class="">
+<br class="">
+ if (Range->second == 0) {<br class="">
+ // 1. Mask includes the LSB -> Simply shift the top N bits off<br class="">
+ NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);<br class="">
+ ReplaceNode(And.getNode(), NewN);<br class="">
+ } else if (Range->first == 31) {<br class="">
+ // 2. Mask includes the MSB -> Simply shift the bottom N bits off<br class="">
+ NewN = EmitShift(ARM::tLSRri, X, Range->second);<br class="">
+ ReplaceNode(And.getNode(), NewN);<br class="">
+ } else if (Range->first == Range->second) {<br class="">
+ // 3. Only one bit is set. We can shift this into the sign bit and use a<br class="">
+ // PL/MI comparison.<br class="">
+ NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);<br class="">
+ ReplaceNode(And.getNode(), NewN);<br class="">
+<br class="">
+ SwitchEQNEToPLMI = true;<br class="">
+ } else if (!Subtarget->hasV6T2Ops()) {<br class="">
+ // 4. Do a double shift to clear bottom and top bits, but only in<br class="">
+ // thumb-1 mode as in thumb-2 we can use UBFX.<br class="">
+ NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);<br class="">
+ NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0),<br class="">
+ Range->second + (31 - Range->first));<br class="">
+ ReplaceNode(And.getNode(), NewN);<br class="">
+ }<br class="">
+<br class="">
+}<br class="">
+<br class="">
void ARMDAGToDAGISel::Select(SDNode *N) {<br class="">
SDLoc dl(N);<br class="">
<br class="">
@@ -2920,6 +2998,7 @@ void ARMDAGToDAGISel::Select(SDNode *N)<br class="">
return;<br class="">
}<br class="">
}<br class="">
+<br class="">
break;<br class="">
}<br class="">
case ARMISD::VMOVRRD:<br class="">
@@ -3110,9 +3189,27 @@ void ARMDAGToDAGISel::Select(SDNode *N)<br class="">
assert(N2.getOpcode() == ISD::Constant);<br class="">
assert(N3.getOpcode() == ISD::Register);<br class="">
<br class="">
- SDValue Tmp2 = CurDAG->getTargetConstant(((<wbr class="">unsigned)<br class="">
- cast<ConstantSDNode>(N2)-><wbr class="">getZExtValue()), dl,<br class="">
- MVT::i32);<br class="">
+ unsigned CC = (unsigned) cast<ConstantSDNode>(N2)-><wbr class="">getZExtValue();<br class="">
+<br class="">
+ if (InFlag.getOpcode() == ARMISD::CMPZ) {<br class="">
+ bool SwitchEQNEToPLMI;<br class="">
+ SelectCMPZ(InFlag.getNode(), SwitchEQNEToPLMI);<br class="">
+ InFlag = N->getOperand(4);<br class="">
+<br class="">
+ if (SwitchEQNEToPLMI) {<br class="">
+ switch ((ARMCC::CondCodes)CC) {<br class="">
+ default: llvm_unreachable("CMPZ must be either NE or EQ!");<br class="">
+ case ARMCC::NE:<br class="">
+ CC = (unsigned)ARMCC::MI;<br class="">
+ break;<br class="">
+ case ARMCC::EQ:<br class="">
+ CC = (unsigned)ARMCC::PL;<br class="">
+ break;<br class="">
+ }<br class="">
+ }<br class="">
+ }<br class="">
+<br class="">
+ SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32);<br class="">
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };<br class="">
SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,<br class="">
MVT::Glue, Ops);<br class="">
@@ -3166,6 +3263,38 @@ void ARMDAGToDAGISel::Select(SDNode *N)<br class="">
}<br class="">
// Other cases are autogenerated.<br class="">
break;<br class="">
+ }<br class="">
+<br class="">
+ case ARMISD::CMOV: {<br class="">
+ SDValue InFlag = N->getOperand(4);<br class="">
+<br class="">
+ if (InFlag.getOpcode() == ARMISD::CMPZ) {<br class="">
+ bool SwitchEQNEToPLMI;<br class="">
+ SelectCMPZ(InFlag.getNode(), SwitchEQNEToPLMI);<br class="">
+<br class="">
+ if (SwitchEQNEToPLMI) {<br class="">
+ SDValue ARMcc = N->getOperand(2);<br class="">
+ ARMCC::CondCodes CC =<br class="">
+ (ARMCC::CondCodes)cast<<wbr class="">ConstantSDNode>(ARMcc)-><wbr class="">getZExtValue();<br class="">
+<br class="">
+ switch (CC) {<br class="">
+ default: llvm_unreachable("CMPZ must be either NE or EQ!");<br class="">
+ case ARMCC::NE:<br class="">
+ CC = ARMCC::MI;<br class="">
+ break;<br class="">
+ case ARMCC::EQ:<br class="">
+ CC = ARMCC::PL;<br class="">
+ break;<br class="">
+ }<br class="">
+ SDValue NewARMcc = CurDAG->getConstant((unsigned)<wbr class="">CC, dl, MVT::i32);<br class="">
+ SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc,<br class="">
+ N->getOperand(3), N->getOperand(4)};<br class="">
+ CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops);<br class="">
+ }<br class="">
+<br class="">
+ }<br class="">
+ // Other cases are autogenerated.<br class="">
+ break;<br class="">
}<br class="">
<br class="">
case ARMISD::VZIP: {<br class="">
<br class="">
Added: llvm/trunk/test/CodeGen/ARM/<wbr class="">and-cmpz.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/and-cmpz.ll?rev=281323&view=auto" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/ARM/and-cmpz.ll?rev=<wbr class="">281323&view=auto</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/ARM/<wbr class="">and-cmpz.ll (added)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/<wbr class="">and-cmpz.ll Tue Sep 13 07:12:32 2016<br class="">
@@ -0,0 +1,71 @@<br class="">
+; RUN: llc -mtriple=thumbv7m-linux-gnu < %s | FileCheck %s --check-prefix=CHECK --check-prefix=T2<br class="">
+; RUN: llc -mtriple=thumbv6m-linux-gnu < %s | FileCheck %s --check-prefix=CHECK --check-prefix=T1<br class="">
+<br class="">
+; CHECK-LABEL: single_bit:<br class="">
+; CHECK: lsls r0, r0, #23<br class="">
+; T2-NEXT: mov<br class="">
+; T2-NEXT: it<br class="">
+; T1-NEXT: bmi<br class="">
+define i32 @single_bit(i32 %p) {<br class="">
+ %a = and i32 %p, 256<br class="">
+ %b = icmp eq i32 %a, 0<br class="">
+ br i1 %b, label %true, label %false<br class="">
+<br class="">
+true:<br class="">
+ ret i32 1<br class="">
+<br class="">
+false:<br class="">
+ ret i32 2<br class="">
+}<br class="">
+<br class="">
+; CHECK-LABEL: multi_bit_lsb_ubfx:<br class="">
+; CHECK: lsls r0, r0, #24<br class="">
+; T2-NEXT: mov<br class="">
+; T2-NEXT: it<br class="">
+; T1-NEXT: beq<br class="">
+define i32 @multi_bit_lsb_ubfx(i32 %p) {<br class="">
+ %a = and i32 %p, 255<br class="">
+ %b = icmp eq i32 %a, 0<br class="">
+ br i1 %b, label %true, label %false<br class="">
+<br class="">
+true:<br class="">
+ ret i32 1<br class="">
+<br class="">
+false:<br class="">
+ ret i32 2<br class="">
+}<br class="">
+<br class="">
+; CHECK-LABEL: multi_bit_msb:<br class="">
+; CHECK: lsrs r0, r0, #24<br class="">
+; T2-NEXT: mov<br class="">
+; T2-NEXT: it<br class="">
+; T1-NEXT: beq<br class="">
+define i32 @multi_bit_msb(i32 %p) {<br class="">
+ %a = and i32 %p, 4278190080 ; 0xff000000<br class="">
+ %b = icmp eq i32 %a, 0<br class="">
+ br i1 %b, label %true, label %false<br class="">
+<br class="">
+true:<br class="">
+ ret i32 1<br class="">
+<br class="">
+false:<br class="">
+ ret i32 2<br class="">
+}<br class="">
+<br class="">
+; CHECK-LABEL: multi_bit_nosb:<br class="">
+; T1: lsls r0, r0, #8<br class="">
+; T1-NEXT: lsrs r0, r0, #24<br class="">
+; T2: tst.w<br class="">
+; T2-NEXT: it<br class="">
+; T1-NEXT: beq<br class="">
+define i32 @multi_bit_nosb(i32 %p) {<br class="">
+ %a = and i32 %p, 16711680 ; 0x00ff0000<br class="">
+ %b = icmp eq i32 %a, 0<br class="">
+ br i1 %b, label %true, label %false<br class="">
+<br class="">
+true:<br class="">
+ ret i32 1<br class="">
+<br class="">
+false:<br class="">
+ ret i32 2<br class="">
+}<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/ARM/<wbr class="">arm-and-tst-peephole.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/ARM/arm-and-tst-<wbr class="">peephole.ll?rev=281323&r1=<wbr class="">281322&r2=281323&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/ARM/<wbr class="">arm-and-tst-peephole.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/<wbr class="">arm-and-tst-peephole.ll Tue Sep 13 07:12:32 2016<br class="">
@@ -28,12 +28,10 @@ tailrecurse:<br class="">
; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3<br class="">
; ARM-NEXT: beq<br class="">
<br class="">
-; THUMB: movs r[[R0:[0-9]+]], #3<br class="">
-; THUMB-NEXT: ands r[[R0]], r<br class="">
-; THUMB-NEXT: cmp r[[R0]], #0<br class="">
+; THUMB: lsls r[[R0:[0-9]+]], r{{.*}}, #30<br class="">
; THUMB-NEXT: beq<br class="">
<br class="">
-; T2: ands {{r[0-9]+}}, {{r[0-9]+}}, #3<br class="">
+; T2: lsls r[[R0:[0-9]+]], r{{.*}}, #30<br class="">
; T2-NEXT: beq<br class="">
<br class="">
%and = and i32 %0, 3<br class="">
@@ -93,7 +91,7 @@ entry:<br class="">
%1 = load i8, i8* %0, align 1<br class="">
%2 = zext i8 %1 to i32<br class="">
; ARM: ands<br class="">
-; THUMB: ands<br class="">
+; THUMB: lsls<br class="">
; T2: ands<br class="">
; V8: ands<br class="">
; V8-NEXT: beq<br class="">
@@ -150,10 +148,9 @@ define i32 @test_tst_assessment(i1 %lhs,<br class="">
%rhs32 = zext i1 %rhs to i32<br class="">
%diff = sub nsw i32 %lhs32, %rhs32<br class="">
; ARM: tst r1, #1<br class="">
-; THUMB: movs [[RTMP:r[0-9]+]], #1<br class="">
-; THUMB: tst r1, [[RTMP]]<br class="">
-; T2: tst.w r1, #1<br class="">
-; V8: tst.w r1, #1<br class="">
+; THUMB: lsls r1, r1, #31<br class="">
+; T2: lsls r1, r1, #31<br class="">
+; V8: lsls r1, r1, #31<br class="">
ret i32 %diff<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/ARM/<wbr class="">arm-shrink-wrapping.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-shrink-wrapping.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/ARM/arm-shrink-<wbr class="">wrapping.ll?rev=281323&r1=<wbr class="">281322&r2=281323&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/ARM/<wbr class="">arm-shrink-wrapping.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/<wbr class="">arm-shrink-wrapping.ll Tue Sep 13 07:12:32 2016<br class="">
@@ -638,12 +638,12 @@ declare double @llvm.pow.f64(double, dou<br class="">
; during PEI with shrink-wrapping enable.<br class="">
; CHECK-LABEL: debug_info:<br class="">
;<br class="">
-; ENABLE: tst{{(\.w)?}} r2, #1<br class="">
+; ENABLE: {{tst r2, #1|lsls r1, r2, #31}}<br class="">
; ENABLE-NEXT: beq [[BB13:LBB[0-9_]+]]<br class="">
;<br class="">
; CHECK: push<br class="">
;<br class="">
-; DISABLE: tst{{(\.w)?}} r2, #1<br class="">
+; DISABLE: {{tst r2, #1|lsls r1, r2, #31}}<br class="">
; DISABLE-NEXT: beq [[BB13:LBB[0-9_]+]]<br class="">
;<br class="">
; CHECK: bl{{x?}} _pow<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/ARM/<wbr class="">call-tc.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call-tc.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/ARM/call-tc.ll?rev=<wbr class="">281323&r1=281322&r2=281323&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/ARM/<wbr class="">call-tc.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/<wbr class="">call-tc.ll Tue Sep 13 07:12:32 2016<br class="">
@@ -120,7 +120,7 @@ if.end:<br class="">
br i1 %tobool2, label %if.end5, label %if.then3<br class="">
<br class="">
if.then3: ; preds = %if.end<br class="">
-; CHECKT2D: bne.w _b<br class="">
+; CHECKT2D: bmi.w _b<br class="">
%call4 = tail call i32 @b(i32 %x) nounwind<br class="">
br label %return<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/ARM/<wbr class="">debug-info-branch-folding.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/ARM/debug-info-branch-<wbr class="">folding.ll?rev=281323&r1=<wbr class="">281322&r2=281323&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/ARM/<wbr class="">debug-info-branch-folding.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/<wbr class="">debug-info-branch-folding.ll Tue Sep 13 07:12:32 2016<br class="">
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:3<br class="">
target triple = "thumbv7-apple-macosx10.6.7"<br class="">
<br class="">
;CHECK: vadd.f32 q4, q8, q8<br class="">
-;CHECK-NEXT: Ltmp1<br class="">
+;CHECK-NEXT: Ltmp<br class="">
;CHECK-NEXT: LBB0_1<br class="">
<br class="">
;CHECK:@DEBUG_VALUE: x <- %Q4{{$}}<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/Thumb/<wbr class="">thumb-shrink-wrapping.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/Thumb/thumb-shrink-<wbr class="">wrapping.ll?rev=281323&r1=<wbr class="">281322&r2=281323&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/Thumb/<wbr class="">thumb-shrink-wrapping.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/Thumb/<wbr class="">thumb-shrink-wrapping.ll Tue Sep 13 07:12:32 2016<br class="">
@@ -650,11 +650,14 @@ define i1 @beq_to_bx(i32* %y, i32 %head)<br class="">
<br class="">
; CHECK: tst r3, r4<br class="">
; ENABLE-NEXT: pop {r4}<br class="">
-; ENABLE-NEXT: pop {r3}<br class="">
-; ENABLE-NEXT: mov lr, r3<br class="">
+; ENABLE-NEXT: mov r12, r{{.*}}<br class="">
+; ENABLE-NEXT: pop {r0}<br class="">
+; ENABLE-NEXT: mov lr, r0<br class="">
+; ENABLE-NEXT: mov r0, r12<br class="">
; CHECK-NEXT: beq [[EXIT_LABEL]]<br class="">
<br class="">
; CHECK: str r1, [r2]<br class="">
+; CHECK: str r3, [r2]<br class="">
; CHECK-NEXT: movs r0, #0<br class="">
; CHECK-NEXT: [[EXIT_LABEL]]: @ %cleanup<br class="">
; ENABLE-NEXT: bx lr<br class="">
@@ -675,6 +678,7 @@ if.end:<br class="">
<br class="">
if.end4:<br class="">
store i32 %head, i32* %y, align 4<br class="">
+ store volatile i32 %z, i32* %y, align 4<br class="">
br label %cleanup<br class="">
<br class="">
cleanup:<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/<wbr class="">Thumb2/float-ops.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/float-ops.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/Thumb2/float-ops.ll?<wbr class="">rev=281323&r1=281322&r2=<wbr class="">281323&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/<wbr class="">Thumb2/float-ops.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/<wbr class="">Thumb2/float-ops.ll Tue Sep 13 07:12:32 2016<br class="">
@@ -259,9 +259,9 @@ define i64 @bitcast_d_to_i(double %a) {<br class="">
<br class="">
define float @select_f(float %a, float %b, i1 %c) {<br class="">
; CHECK-LABEL: select_f:<br class="">
-; NONE: tst.w r2, #1<br class="">
+; NONE: lsls r2, r2, #31<br class="">
; NONE: moveq r0, r1<br class="">
-; HARD: tst.w r0, #1<br class="">
+; HARD: lsls r0, r0, #31<br class="">
; VFP4-ALL: vmovne.f32 s1, s0<br class="">
; VFP4-ALL: vmov.f32 s0, s1<br class="">
; FP-ARMv8: vseleq.f32 s0, s1, s0<br class="">
@@ -271,18 +271,18 @@ define float @select_f(float %a, float %<br class="">
<br class="">
define double @select_d(double %a, double %b, i1 %c) {<br class="">
; CHECK-LABEL: select_d:<br class="">
-; NONE: ldr.w [[REG:r[0-9]+]], [sp]<br class="">
-; NONE: ands [[REG]], [[REG]], #1<br class="">
+; NONE: ldr{{(.w)?}} [[REG:r[0-9]+]], [sp]<br class="">
+; NONE: lsls{{(.w)?}} [[REG]], [[REG]], #31<br class="">
; NONE: moveq r0, r2<br class="">
; NONE: moveq r1, r3<br class="">
-; SP: ands r0, r0, #1<br class="">
+; SP: lsls r0, r0, #31<br class="">
; SP-DAG: vmov [[ALO:r[0-9]+]], [[AHI:r[0-9]+]], d0<br class="">
; SP-DAG: vmov [[BLO:r[0-9]+]], [[BHI:r[0-9]+]], d1<br class="">
; SP: itt ne<br class="">
; SP-DAG: movne [[BLO]], [[ALO]]<br class="">
; SP-DAG: movne [[BHI]], [[AHI]]<br class="">
; SP: vmov d0, [[BLO]], [[BHI]]<br class="">
-; DP: tst.w r0, #1<br class="">
+; DP: lsls r0, r0, #31<br class="">
; VFP4-DP: vmovne.f64 d1, d0<br class="">
; VFP4-DP: vmov.f64 d0, d1<br class="">
; FP-ARMV8: vseleq.f64 d0, d1, d0<br class="">
<br class="">
<br class="">
______________________________<wbr class="">_________________<br class="">
llvm-commits mailing list<br class="">
<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">
<a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank" class="">http://lists.llvm.org/cgi-bin/<wbr class="">mailman/listinfo/llvm-commits</a><br class="">
</blockquote>
</div>
</div>
</div>
</blockquote>
</div>
<br class="">
</div>
</div>
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose,
or store or copy the information in any medium. Thank you.
</body>
</html>