<p dir="ltr">Hi James, </p>
<p dir="ltr">This one looks yours, again... </p>
<p dir="ltr"><a href="http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/4073">http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15-full-sh/builds/4073</a></p>
<p dir="ltr">Cheers, <br>
Renato </p>
<div class="gmail_extra"><br><div class="gmail_quote">On 13 Sep 2016 1:21 p.m., "James Molloy via llvm-commits" <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: jamesm<br>
Date: Tue Sep 13 07:12:32 2016<br>
New Revision: 281323<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=281323&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project?rev=281323&view=rev</a><br>
Log:<br>
[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently<br>
<br>
For the common pattern (CMPZ (AND x, #bitmask), #0), we can do some more efficient instruction selection if the bitmask is one consecutive sequence of set bits (32 - clz(bm) - ctz(bm) == popcount(bm)).<br>
<br>
1) If the bitmask touches the LSB, then we can remove all the upper bits and set the flags by doing one LSLS.<br>
2) If the bitmask touches the MSB, then we can remove all the lower bits and set the flags with one LSRS.<br>
3) If the bitmask has popcount == 1 (only one set bit), we can shift that bit into the sign bit with one LSLS and change the condition query from NE/EQ to MI/PL (we could also implement this by shifting into the carry bit and branching on BCC/BCS).<br>
4) Otherwise, we can emit a sequence of LSLS+LSRS to remove the upper and lower zero bits of the mask.<br>
<br>
1-3 require only one 16-bit instruction and can elide the CMP. 4 requires two 16-bit instructions but can elide the CMP and doesn't require materializing a complex immediate, so is also a win.<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/ARM/<wbr>and-cmpz.ll<br>
Modified:<br>
llvm/trunk/lib/Target/ARM/<wbr>ARMBaseInstrInfo.cpp<br>
llvm/trunk/lib/Target/ARM/<wbr>ARMISelDAGToDAG.cpp<br>
llvm/trunk/test/CodeGen/ARM/<wbr>arm-and-tst-peephole.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>arm-shrink-wrapping.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>call-tc.ll<br>
llvm/trunk/test/CodeGen/ARM/<wbr>debug-info-branch-folding.ll<br>
llvm/trunk/test/CodeGen/Thumb/<wbr>thumb-shrink-wrapping.ll<br>
llvm/trunk/test/CodeGen/<wbr>Thumb2/float-ops.ll<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/<wbr>ARMBaseInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>ARM/ARMBaseInstrInfo.cpp?rev=<wbr>281323&r1=281322&r2=281323&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/<wbr>ARMBaseInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/<wbr>ARMBaseInstrInfo.cpp Tue Sep 13 07:12:32 2016<br>
@@ -2528,7 +2528,11 @@ bool ARMBaseInstrInfo::<wbr>optimizeCompareIn<br>
case ARM::EORrr:<br>
case ARM::EORri:<br>
case ARM::t2EORrr:<br>
- case ARM::t2EORri: {<br>
+ case ARM::t2EORri:<br>
+ case ARM::t2LSRri:<br>
+ case ARM::t2LSRrr:<br>
+ case ARM::t2LSLri:<br>
+ case ARM::t2LSLrr: {<br>
// Scan forward for the use of CPSR<br>
// When checking against MI: if it's a conditional code that requires<br>
// checking of the V bit or C bit, then this is not safe to do.<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/<wbr>ARMISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/lib/Target/<wbr>ARM/ARMISelDAGToDAG.cpp?rev=<wbr>281323&r1=281322&r2=281323&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/lib/Target/ARM/<wbr>ARMISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/<wbr>ARMISelDAGToDAG.cpp Tue Sep 13 07:12:32 2016<br>
@@ -244,7 +244,8 @@ private:<br>
bool tryInlineAsm(SDNode *N);<br>
<br>
void SelectConcatVector(SDNode *N);<br>
-<br>
+ void SelectCMPZ(SDNode *N, bool &SwitchEQNEToPLMI);<br>
+<br>
bool trySMLAWSMULW(SDNode *N);<br>
<br>
void SelectCMP_SWAP(SDNode *N);<br>
@@ -2693,6 +2694,83 @@ void ARMDAGToDAGISel::<wbr>SelectConcatVector<br>
ReplaceNode(N, createDRegPairNode(VT, N->getOperand(0), N->getOperand(1)));<br>
}<br>
<br>
+static Optional<std::pair<unsigned, unsigned>><br>
+getContiguousRangeOfSetBits(<wbr>const APInt &A) {<br>
+ unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1;<br>
+ unsigned LastOne = A.countTrailingZeros();<br>
+ if (A.countPopulation() != (FirstOne - LastOne + 1))<br>
+ return Optional<std::pair<unsigned,<wbr>unsigned>>();<br>
+ return std::make_pair(FirstOne, LastOne);<br>
+}<br>
+<br>
+void ARMDAGToDAGISel::SelectCMPZ(<wbr>SDNode *N, bool &SwitchEQNEToPLMI) {<br>
+ assert(N->getOpcode() == ARMISD::CMPZ);<br>
+ SwitchEQNEToPLMI = false;<br>
+<br>
+ if (!Subtarget->isThumb())<br>
+ // FIXME: Work out whether it is profitable to do this in A32 mode - LSL and<br>
+ // LSR don't exist as standalone instructions - they need the barrel shifter.<br>
+ return;<br>
+ // select (cmpz (and X, C), #0) -> (LSLS X) or (LSRS X) or (LSRS (LSLS X))<br>
+ SDValue And = N->getOperand(0);<br>
+ SDValue Zero = N->getOperand(1);<br>
+ if (!isa<ConstantSDNode>(Zero) || !cast<ConstantSDNode>(Zero)-><wbr>isNullValue() ||<br>
+ And->getOpcode() != ISD::AND)<br>
+ return;<br>
+ SDValue X = And.getOperand(0);<br>
+ auto C = dyn_cast<ConstantSDNode>(And.<wbr>getOperand(1));<br>
+<br>
+ if (!C || !X->hasOneUse())<br>
+ return;<br>
+ auto Range = getContiguousRangeOfSetBits(C-<wbr>>getAPIntValue());<br>
+ if (!Range)<br>
+ return;<br>
+<br>
+ // There are several ways to lower this:<br>
+ SDNode *NewN;<br>
+ SDLoc dl(N);<br>
+<br>
+ auto EmitShift = [&](unsigned Opc, SDValue Src, unsigned Imm) -> SDNode* {<br>
+ if (Subtarget->isThumb2()) {<br>
+ Opc = (Opc == ARM::tLSLri) ? ARM::t2LSLri : ARM::t2LSRri;<br>
+ SDValue Ops[] = { Src, CurDAG->getTargetConstant(Imm, dl, MVT::i32),<br>
+ getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32),<br>
+ CurDAG->getRegister(0, MVT::i32) };<br>
+ return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);<br>
+ } else {<br>
+ SDValue Ops[] = {CurDAG->getRegister(ARM::<wbr>CPSR, MVT::i32), Src,<br>
+ CurDAG->getTargetConstant(Imm, dl, MVT::i32),<br>
+ getAL(CurDAG, dl), CurDAG->getRegister(0, MVT::i32)};<br>
+ return CurDAG->getMachineNode(Opc, dl, MVT::i32, Ops);<br>
+ }<br>
+ };<br>
+<br>
+ if (Range->second == 0) {<br>
+ // 1. Mask includes the LSB -> Simply shift the top N bits off<br>
+ NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);<br>
+ ReplaceNode(And.getNode(), NewN);<br>
+ } else if (Range->first == 31) {<br>
+ // 2. Mask includes the MSB -> Simply shift the bottom N bits off<br>
+ NewN = EmitShift(ARM::tLSRri, X, Range->second);<br>
+ ReplaceNode(And.getNode(), NewN);<br>
+ } else if (Range->first == Range->second) {<br>
+ // 3. Only one bit is set. We can shift this into the sign bit and use a<br>
+ // PL/MI comparison.<br>
+ NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);<br>
+ ReplaceNode(And.getNode(), NewN);<br>
+<br>
+ SwitchEQNEToPLMI = true;<br>
+ } else if (!Subtarget->hasV6T2Ops()) {<br>
+ // 4. Do a double shift to clear bottom and top bits, but only in<br>
+ // thumb-1 mode as in thumb-2 we can use UBFX.<br>
+ NewN = EmitShift(ARM::tLSLri, X, 31 - Range->first);<br>
+ NewN = EmitShift(ARM::tLSRri, SDValue(NewN, 0),<br>
+ Range->second + (31 - Range->first));<br>
+ ReplaceNode(And.getNode(), NewN);<br>
+ }<br>
+<br>
+}<br>
+<br>
void ARMDAGToDAGISel::Select(SDNode *N) {<br>
SDLoc dl(N);<br>
<br>
@@ -2920,6 +2998,7 @@ void ARMDAGToDAGISel::Select(SDNode *N)<br>
return;<br>
}<br>
}<br>
+<br>
break;<br>
}<br>
case ARMISD::VMOVRRD:<br>
@@ -3110,9 +3189,27 @@ void ARMDAGToDAGISel::Select(SDNode *N)<br>
assert(N2.getOpcode() == ISD::Constant);<br>
assert(N3.getOpcode() == ISD::Register);<br>
<br>
- SDValue Tmp2 = CurDAG->getTargetConstant(((<wbr>unsigned)<br>
- cast<ConstantSDNode>(N2)-><wbr>getZExtValue()), dl,<br>
- MVT::i32);<br>
+ unsigned CC = (unsigned) cast<ConstantSDNode>(N2)-><wbr>getZExtValue();<br>
+<br>
+ if (InFlag.getOpcode() == ARMISD::CMPZ) {<br>
+ bool SwitchEQNEToPLMI;<br>
+ SelectCMPZ(InFlag.getNode(), SwitchEQNEToPLMI);<br>
+ InFlag = N->getOperand(4);<br>
+<br>
+ if (SwitchEQNEToPLMI) {<br>
+ switch ((ARMCC::CondCodes)CC) {<br>
+ default: llvm_unreachable("CMPZ must be either NE or EQ!");<br>
+ case ARMCC::NE:<br>
+ CC = (unsigned)ARMCC::MI;<br>
+ break;<br>
+ case ARMCC::EQ:<br>
+ CC = (unsigned)ARMCC::PL;<br>
+ break;<br>
+ }<br>
+ }<br>
+ }<br>
+<br>
+ SDValue Tmp2 = CurDAG->getTargetConstant(CC, dl, MVT::i32);<br>
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };<br>
SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,<br>
MVT::Glue, Ops);<br>
@@ -3166,6 +3263,38 @@ void ARMDAGToDAGISel::Select(SDNode *N)<br>
}<br>
// Other cases are autogenerated.<br>
break;<br>
+ }<br>
+<br>
+ case ARMISD::CMOV: {<br>
+ SDValue InFlag = N->getOperand(4);<br>
+<br>
+ if (InFlag.getOpcode() == ARMISD::CMPZ) {<br>
+ bool SwitchEQNEToPLMI;<br>
+ SelectCMPZ(InFlag.getNode(), SwitchEQNEToPLMI);<br>
+<br>
+ if (SwitchEQNEToPLMI) {<br>
+ SDValue ARMcc = N->getOperand(2);<br>
+ ARMCC::CondCodes CC =<br>
+ (ARMCC::CondCodes)cast<<wbr>ConstantSDNode>(ARMcc)-><wbr>getZExtValue();<br>
+<br>
+ switch (CC) {<br>
+ default: llvm_unreachable("CMPZ must be either NE or EQ!");<br>
+ case ARMCC::NE:<br>
+ CC = ARMCC::MI;<br>
+ break;<br>
+ case ARMCC::EQ:<br>
+ CC = ARMCC::PL;<br>
+ break;<br>
+ }<br>
+ SDValue NewARMcc = CurDAG->getConstant((unsigned)<wbr>CC, dl, MVT::i32);<br>
+ SDValue Ops[] = {N->getOperand(0), N->getOperand(1), NewARMcc,<br>
+ N->getOperand(3), N->getOperand(4)};<br>
+ CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops);<br>
+ }<br>
+<br>
+ }<br>
+ // Other cases are autogenerated.<br>
+ break;<br>
}<br>
<br>
case ARMISD::VZIP: {<br>
<br>
Added: llvm/trunk/test/CodeGen/ARM/<wbr>and-cmpz.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/and-cmpz.ll?rev=281323&view=auto" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/and-cmpz.ll?rev=<wbr>281323&view=auto</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>and-cmpz.ll (added)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>and-cmpz.ll Tue Sep 13 07:12:32 2016<br>
@@ -0,0 +1,71 @@<br>
+; RUN: llc -mtriple=thumbv7m-linux-gnu < %s | FileCheck %s --check-prefix=CHECK --check-prefix=T2<br>
+; RUN: llc -mtriple=thumbv6m-linux-gnu < %s | FileCheck %s --check-prefix=CHECK --check-prefix=T1<br>
+<br>
+; CHECK-LABEL: single_bit:<br>
+; CHECK: lsls r0, r0, #23<br>
+; T2-NEXT: mov<br>
+; T2-NEXT: it<br>
+; T1-NEXT: bmi<br>
+define i32 @single_bit(i32 %p) {<br>
+ %a = and i32 %p, 256<br>
+ %b = icmp eq i32 %a, 0<br>
+ br i1 %b, label %true, label %false<br>
+<br>
+true:<br>
+ ret i32 1<br>
+<br>
+false:<br>
+ ret i32 2<br>
+}<br>
+<br>
+; CHECK-LABEL: multi_bit_lsb_ubfx:<br>
+; CHECK: lsls r0, r0, #24<br>
+; T2-NEXT: mov<br>
+; T2-NEXT: it<br>
+; T1-NEXT: beq<br>
+define i32 @multi_bit_lsb_ubfx(i32 %p) {<br>
+ %a = and i32 %p, 255<br>
+ %b = icmp eq i32 %a, 0<br>
+ br i1 %b, label %true, label %false<br>
+<br>
+true:<br>
+ ret i32 1<br>
+<br>
+false:<br>
+ ret i32 2<br>
+}<br>
+<br>
+; CHECK-LABEL: multi_bit_msb:<br>
+; CHECK: lsrs r0, r0, #24<br>
+; T2-NEXT: mov<br>
+; T2-NEXT: it<br>
+; T1-NEXT: beq<br>
+define i32 @multi_bit_msb(i32 %p) {<br>
+ %a = and i32 %p, 4278190080 ; 0xff000000<br>
+ %b = icmp eq i32 %a, 0<br>
+ br i1 %b, label %true, label %false<br>
+<br>
+true:<br>
+ ret i32 1<br>
+<br>
+false:<br>
+ ret i32 2<br>
+}<br>
+<br>
+; CHECK-LABEL: multi_bit_nosb:<br>
+; T1: lsls r0, r0, #8<br>
+; T1-NEXT: lsrs r0, r0, #24<br>
+; T2: tst.w<br>
+; T2-NEXT: it<br>
+; T1-NEXT: beq<br>
+define i32 @multi_bit_nosb(i32 %p) {<br>
+ %a = and i32 %p, 16711680 ; 0x00ff0000<br>
+ %b = icmp eq i32 %a, 0<br>
+ br i1 %b, label %true, label %false<br>
+<br>
+true:<br>
+ ret i32 1<br>
+<br>
+false:<br>
+ ret i32 2<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>arm-and-tst-peephole.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-and-tst-peephole.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/arm-and-tst-<wbr>peephole.ll?rev=281323&r1=<wbr>281322&r2=281323&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>arm-and-tst-peephole.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>arm-and-tst-peephole.ll Tue Sep 13 07:12:32 2016<br>
@@ -28,12 +28,10 @@ tailrecurse:<br>
; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3<br>
; ARM-NEXT: beq<br>
<br>
-; THUMB: movs r[[R0:[0-9]+]], #3<br>
-; THUMB-NEXT: ands r[[R0]], r<br>
-; THUMB-NEXT: cmp r[[R0]], #0<br>
+; THUMB: lsls r[[R0:[0-9]+]], r{{.*}}, #30<br>
; THUMB-NEXT: beq<br>
<br>
-; T2: ands {{r[0-9]+}}, {{r[0-9]+}}, #3<br>
+; T2: lsls r[[R0:[0-9]+]], r{{.*}}, #30<br>
; T2-NEXT: beq<br>
<br>
%and = and i32 %0, 3<br>
@@ -93,7 +91,7 @@ entry:<br>
%1 = load i8, i8* %0, align 1<br>
%2 = zext i8 %1 to i32<br>
; ARM: ands<br>
-; THUMB: ands<br>
+; THUMB: lsls<br>
; T2: ands<br>
; V8: ands<br>
; V8-NEXT: beq<br>
@@ -150,10 +148,9 @@ define i32 @test_tst_assessment(i1 %lhs,<br>
%rhs32 = zext i1 %rhs to i32<br>
%diff = sub nsw i32 %lhs32, %rhs32<br>
; ARM: tst r1, #1<br>
-; THUMB: movs [[RTMP:r[0-9]+]], #1<br>
-; THUMB: tst r1, [[RTMP]]<br>
-; T2: tst.w r1, #1<br>
-; V8: tst.w r1, #1<br>
+; THUMB: lsls r1, r1, #31<br>
+; T2: lsls r1, r1, #31<br>
+; V8: lsls r1, r1, #31<br>
ret i32 %diff<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>arm-shrink-wrapping.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-shrink-wrapping.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/arm-shrink-<wbr>wrapping.ll?rev=281323&r1=<wbr>281322&r2=281323&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>arm-shrink-wrapping.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>arm-shrink-wrapping.ll Tue Sep 13 07:12:32 2016<br>
@@ -638,12 +638,12 @@ declare double @llvm.pow.f64(double, dou<br>
; during PEI with shrink-wrapping enable.<br>
; CHECK-LABEL: debug_info:<br>
;<br>
-; ENABLE: tst{{(\.w)?}} r2, #1<br>
+; ENABLE: {{tst r2, #1|lsls r1, r2, #31}}<br>
; ENABLE-NEXT: beq [[BB13:LBB[0-9_]+]]<br>
;<br>
; CHECK: push<br>
;<br>
-; DISABLE: tst{{(\.w)?}} r2, #1<br>
+; DISABLE: {{tst r2, #1|lsls r1, r2, #31}}<br>
; DISABLE-NEXT: beq [[BB13:LBB[0-9_]+]]<br>
;<br>
; CHECK: bl{{x?}} _pow<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>call-tc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/call-tc.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/call-tc.ll?rev=<wbr>281323&r1=281322&r2=281323&<wbr>view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>call-tc.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>call-tc.ll Tue Sep 13 07:12:32 2016<br>
@@ -120,7 +120,7 @@ if.end:<br>
br i1 %tobool2, label %if.end5, label %if.then3<br>
<br>
if.then3: ; preds = %if.end<br>
-; CHECKT2D: bne.w _b<br>
+; CHECKT2D: bmi.w _b<br>
%call4 = tail call i32 @b(i32 %x) nounwind<br>
br label %return<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/<wbr>debug-info-branch-folding.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/ARM/debug-info-branch-<wbr>folding.ll?rev=281323&r1=<wbr>281322&r2=281323&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/ARM/<wbr>debug-info-branch-folding.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/<wbr>debug-info-branch-folding.ll Tue Sep 13 07:12:32 2016<br>
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:3<br>
target triple = "thumbv7-apple-macosx10.6.7"<br>
<br>
;CHECK: vadd.f32 q4, q8, q8<br>
-;CHECK-NEXT: Ltmp1<br>
+;CHECK-NEXT: Ltmp<br>
;CHECK-NEXT: LBB0_1<br>
<br>
;CHECK:@DEBUG_VALUE: x <- %Q4{{$}}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Thumb/<wbr>thumb-shrink-wrapping.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Thumb/thumb-shrink-<wbr>wrapping.ll?rev=281323&r1=<wbr>281322&r2=281323&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/Thumb/<wbr>thumb-shrink-wrapping.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Thumb/<wbr>thumb-shrink-wrapping.ll Tue Sep 13 07:12:32 2016<br>
@@ -650,11 +650,14 @@ define i1 @beq_to_bx(i32* %y, i32 %head)<br>
<br>
; CHECK: tst r3, r4<br>
; ENABLE-NEXT: pop {r4}<br>
-; ENABLE-NEXT: pop {r3}<br>
-; ENABLE-NEXT: mov lr, r3<br>
+; ENABLE-NEXT: mov r12, r{{.*}}<br>
+; ENABLE-NEXT: pop {r0}<br>
+; ENABLE-NEXT: mov lr, r0<br>
+; ENABLE-NEXT: mov r0, r12<br>
; CHECK-NEXT: beq [[EXIT_LABEL]]<br>
<br>
; CHECK: str r1, [r2]<br>
+; CHECK: str r3, [r2]<br>
; CHECK-NEXT: movs r0, #0<br>
; CHECK-NEXT: [[EXIT_LABEL]]: @ %cleanup<br>
; ENABLE-NEXT: bx lr<br>
@@ -675,6 +678,7 @@ if.end:<br>
<br>
if.end4:<br>
store i32 %head, i32* %y, align 4<br>
+ store volatile i32 %z, i32* %y, align 4<br>
br label %cleanup<br>
<br>
cleanup:<br>
<br>
Modified: llvm/trunk/test/CodeGen/<wbr>Thumb2/float-ops.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/float-ops.ll?rev=281323&r1=281322&r2=281323&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-<wbr>project/llvm/trunk/test/<wbr>CodeGen/Thumb2/float-ops.ll?<wbr>rev=281323&r1=281322&r2=<wbr>281323&view=diff</a><br>
==============================<wbr>==============================<wbr>==================<br>
--- llvm/trunk/test/CodeGen/<wbr>Thumb2/float-ops.ll (original)<br>
+++ llvm/trunk/test/CodeGen/<wbr>Thumb2/float-ops.ll Tue Sep 13 07:12:32 2016<br>
@@ -259,9 +259,9 @@ define i64 @bitcast_d_to_i(double %a) {<br>
<br>
define float @select_f(float %a, float %b, i1 %c) {<br>
; CHECK-LABEL: select_f:<br>
-; NONE: tst.w r2, #1<br>
+; NONE: lsls r2, r2, #31<br>
; NONE: moveq r0, r1<br>
-; HARD: tst.w r0, #1<br>
+; HARD: lsls r0, r0, #31<br>
; VFP4-ALL: vmovne.f32 s1, s0<br>
; VFP4-ALL: vmov.f32 s0, s1<br>
; FP-ARMv8: vseleq.f32 s0, s1, s0<br>
@@ -271,18 +271,18 @@ define float @select_f(float %a, float %<br>
<br>
define double @select_d(double %a, double %b, i1 %c) {<br>
; CHECK-LABEL: select_d:<br>
-; NONE: ldr.w [[REG:r[0-9]+]], [sp]<br>
-; NONE: ands [[REG]], [[REG]], #1<br>
+; NONE: ldr{{(.w)?}} [[REG:r[0-9]+]], [sp]<br>
+; NONE: lsls{{(.w)?}} [[REG]], [[REG]], #31<br>
; NONE: moveq r0, r2<br>
; NONE: moveq r1, r3<br>
-; SP: ands r0, r0, #1<br>
+; SP: lsls r0, r0, #31<br>
; SP-DAG: vmov [[ALO:r[0-9]+]], [[AHI:r[0-9]+]], d0<br>
; SP-DAG: vmov [[BLO:r[0-9]+]], [[BHI:r[0-9]+]], d1<br>
; SP: itt ne<br>
; SP-DAG: movne [[BLO]], [[ALO]]<br>
; SP-DAG: movne [[BHI]], [[AHI]]<br>
; SP: vmov d0, [[BLO]], [[BHI]]<br>
-; DP: tst.w r0, #1<br>
+; DP: lsls r0, r0, #31<br>
; VFP4-DP: vmovne.f64 d1, d0<br>
; VFP4-DP: vmov.f64 d0, d1<br>
; FP-ARMV8: vseleq.f64 d0, d1, d0<br>
<br>
<br>
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