<html><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Hi Hal,<div class=""><br class=""></div><div class="">This is failing locally for me:</div><div class=""><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">FAIL: LLVM :: CodeGen/PowerPC/atomic-2.ll (6659 of 17802)</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">******************** TEST 'LLVM :: CodeGen/PowerPC/atomic-2.ll' FAILED ********************</span></div></div><div class=""><span style="font-variant-ligatures: no-common-ligatures" class=""><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">Command Output (stderr):</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">--</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">Assertion failed: (Section && "Cannot switch to a null section!"), function SwitchSection, file /Users/dexonsmith/data/llvm/staging/lib/MC/MCStreamer.cpp, line 805.</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">Stack dump:</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">0.<span class="Apple-tab-span" style="white-space:pre"> </span>Program arguments: /Users/dexonsmith/data/llvm.symbols+asserts/staging/./bin/llc -march=ppc64le </span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">FileCheck error: '-' is empty.</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">FileCheck command line: /Users/dexonsmith/data/llvm.symbols+asserts/staging/./bin/FileCheck /Users/dexonsmith/data/llvm/staging/test/CodeGen/PowerPC/atomic-2.ll -check-prefix=CHECK -check-prefix=CHECK-LE</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0); min-height: 14px;" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""></span><br class=""></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">--</span></div><div class=""><span style="font-variant-ligatures: no-common-ligatures" class=""><br class=""></span></div><div class=""><span style="font-variant-ligatures: no-common-ligatures" class="">Here's the backtrace:</span></div><div class=""><span style="font-variant-ligatures: no-common-ligatures" class=""><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(116, 116, 116); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">(lldb) </span><span style="font-variant-ligatures: no-common-ligatures; color: #f4f4f4" class="">bt</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class="">* thread #1: tid = 0x907b07, 0x00007ffface5bdda libsystem_kernel.dylib`__pthread_kill + 10, queue = 'com.apple.main-thread', stop reason = signal SIGABRT</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> * frame #0: 0x00007ffface5bdda libsystem_kernel.dylib`__pthread_kill + 10</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #1: 0x00007fffacf46797 libsystem_pthread.dylib`pthread_kill + 90</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #2: 0x00007fffacdc1440 libsystem_c.dylib`abort + 129</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #3: 0x00007fffacd888b3 libsystem_c.dylib`__assert_rtn + 320</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #4: 0x000000010106853f llc`llvm::MCStreamer::SwitchSection(this=0x0000000102e22880, Section=0x0000000000000000, Subsection=0x0000000000000000) + 399 at MCStreamer.cpp:805</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #5: 0x00000001006e887f llc`(anonymous namespace)::PPCDarwinAsmPrinter::EmitStartOfAsmFile(this=<unavailable>, M=<unavailable>) + 255 at PPCAsmPrinter.cpp:1324</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #6: 0x0000000100bdd2c6 llc`llvm::AsmPrinter::doInitialization(this=0x0000000102e22b30, M=0x0000000102e0d0d0) + 646 at AsmPrinter.cpp:221</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #7: 0x0000000100fa4ecb llc`llvm::FPPassManager::doInitialization(this=<unavailable>, M=<unavailable>) + 75 at LegacyPassManager.cpp:1552</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #8: 0x0000000100fa51c0 llc`llvm::legacy::PassManagerImpl::run(llvm::Module&) + 68 at LegacyPassManager.cpp:1584</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #9: 0x0000000100fa517c llc`llvm::legacy::PassManagerImpl::run(this=<unavailable>, M=<unavailable>) + 444 at LegacyPassManager.cpp:1702</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #10: 0x00000001000057c7 llc`compileModule(argv=0x00007fff5fbff9b0, Context=<unavailable>) + 10663 at llc.cpp:506</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #11: 0x0000000100002bdb llc`main(argc=<unavailable>, argv=<unavailable>) + 459 at llc.cpp:273</span></div><div style="margin: 0px; line-height: normal; font-family: Menlo; color: rgb(244, 244, 244); background-color: rgb(0, 0, 0);" class=""><span style="font-variant-ligatures: no-common-ligatures" class=""> frame #12: 0x00007fffacd2d255 libdyld.dylib`start + 1</span></div><div class=""><span style="font-variant-ligatures: no-common-ligatures" class=""><br class=""></span></div><div class=""><span style="font-variant-ligatures: no-common-ligatures" class="">It looks like it's also failing on at least one bot:</span></div><div class=""><span style="font-variant-ligatures: no-common-ligatures" class=""><a href="http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/21366/" class="">http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/21366/</a></span></div><div class=""><span style="font-variant-ligatures: no-common-ligatures" class=""><a href="http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/21366/testReport/junit/LLVM/CodeGen_PowerPC/atomic_2_ll/" class="">http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/21366/testReport/junit/LLVM/CodeGen_PowerPC/atomic_2_ll/</a></span></div></span></div></span></div><div class=""><br class=""><blockquote type="cite" class="">On 2016-Aug-29, at 15:25, Hal Finkel via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""><br class="">Author: hfinkel<br class="">Date: Mon Aug 29 17:25:36 2016<br class="">New Revision: 280022<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=280022&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=280022&view=rev</a><br class="">Log:<br class="">[PowerPC] Fix i8/i16 atomics for little-Endian targets without partword atomics<br class=""><br class="">For little-Endian PowerPC, we generally target only P8 and later by default.<br class="">However, generic (older) 64-bit configurations are still an option, and in that<br class="">case, partword atomics are not available (e.g. stbcx.). To lower i8/i16 atomics<br class="">without true i8/i16 atomic operations, we emulate using i32 atomics in<br class="">combination with a bunch of shifting and masking, etc. The amount by which to<br class="">shift in little-Endian mode is different from the amount in big-Endian mode (it<br class="">is inverted -- meaning we can leave off the xor when computing the amount).<br class=""><br class="">Fixes PR22923.<br class=""><br class="">Modified:<br class=""> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br class=""> llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll<br class=""><br class="">Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=280022&r1=280021&r2=280022&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=280022&r1=280021&r2=280022&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)<br class="">+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Aug 29 17:25:36 2016<br class="">@@ -8513,6 +8513,7 @@ PPCTargetLowering::EmitPartwordAtomicBin<br class=""> // registers without caring whether they're 32 or 64, but here we're<br class=""> // doing actual arithmetic on the addresses.<br class=""> bool is64bit = Subtarget.isPPC64();<br class="">+ bool isLittleEndian = Subtarget.isLittleEndian();<br class=""> unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;<br class=""><br class=""> const BasicBlock *LLVM_BB = BB->getBasicBlock();<br class="">@@ -8542,7 +8543,8 @@ PPCTargetLowering::EmitPartwordAtomicBin<br class=""> : &PPC::GPRCRegClass;<br class=""> unsigned PtrReg = RegInfo.createVirtualRegister(RC);<br class=""> unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);<br class="">- unsigned ShiftReg = RegInfo.createVirtualRegister(RC);<br class="">+ unsigned ShiftReg =<br class="">+ isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);<br class=""> unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);<br class=""> unsigned MaskReg = RegInfo.createVirtualRegister(RC);<br class=""> unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);<br class="">@@ -8587,8 +8589,9 @@ PPCTargetLowering::EmitPartwordAtomicBin<br class=""> }<br class=""> BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)<br class=""> .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);<br class="">- BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)<br class="">- .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);<br class="">+ if (!isLittleEndian)<br class="">+ BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)<br class="">+ .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);<br class=""> if (is64bit)<br class=""> BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)<br class=""> .addReg(Ptr1Reg).addImm(0).addImm(61);<br class="">@@ -9293,6 +9296,7 @@ PPCTargetLowering::EmitInstrWithCustomIn<br class=""> // since we're actually doing arithmetic on them. Other registers<br class=""> // can be 32-bit.<br class=""> bool is64bit = Subtarget.isPPC64();<br class="">+ bool isLittleEndian = Subtarget.isLittleEndian();<br class=""> bool is8bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;<br class=""><br class=""> unsigned dest = MI.getOperand(0).getReg();<br class="">@@ -9319,7 +9323,8 @@ PPCTargetLowering::EmitInstrWithCustomIn<br class=""> : &PPC::GPRCRegClass;<br class=""> unsigned PtrReg = RegInfo.createVirtualRegister(RC);<br class=""> unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);<br class="">- unsigned ShiftReg = RegInfo.createVirtualRegister(RC);<br class="">+ unsigned ShiftReg =<br class="">+ isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(RC);<br class=""> unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);<br class=""> unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);<br class=""> unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);<br class="">@@ -9374,8 +9379,9 @@ PPCTargetLowering::EmitInstrWithCustomIn<br class=""> }<br class=""> BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)<br class=""> .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);<br class="">- BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)<br class="">- .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);<br class="">+ if (!isLittleEndian)<br class="">+ BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)<br class="">+ .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);<br class=""> if (is64bit)<br class=""> BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)<br class=""> .addReg(Ptr1Reg).addImm(0).addImm(61);<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll<br class="">URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll?rev=280022&r1=280021&r2=280022&view=diff" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll?rev=280022&r1=280021&r2=280022&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll Mon Aug 29 17:25:36 2016<br class="">@@ -1,4 +1,5 @@<br class="">-; RUN: llc < %s -march=ppc64 | FileCheck %s<br class="">+; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE<br class="">+; RUN: llc < %s -march=ppc64le | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE<br class="">; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s<br class="">; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U<br class=""><br class="">@@ -12,6 +13,8 @@ define i64 @exchange_and_add(i64* %mem,<br class=""><br class="">define i8 @exchange_and_add8(i8* %mem, i8 %val) nounwind {<br class="">; CHECK-LABEL: exchange_and_add8:<br class="">+; CHECK-BE: xori<br class="">+; CHECK-LE-NOT: xori<br class="">; CHECK-P8U: lbarx<br class=""> %tmp = atomicrmw add i8* %mem, i8 %val monotonic<br class="">; CHECK-P8U: stbcx.<br class="">@@ -20,6 +23,8 @@ define i8 @exchange_and_add8(i8* %mem, i<br class=""><br class="">define i16 @exchange_and_add16(i16* %mem, i16 %val) nounwind {<br class="">; CHECK-LABEL: exchange_and_add16:<br class="">+; CHECK-BE: xori<br class="">+; CHECK-LE-NOT: xori<br class="">; CHECK-P8U: lharx<br class=""> %tmp = atomicrmw add i16* %mem, i16 %val monotonic<br class="">; CHECK-P8U: sthcx.<br class="">@@ -38,6 +43,8 @@ define i64 @exchange_and_cmp(i64* %mem)<br class=""><br class="">define i8 @exchange_and_cmp8(i8* %mem) nounwind {<br class="">; CHECK-LABEL: exchange_and_cmp8:<br class="">+; CHECK-BE: xori<br class="">+; CHECK-LE-NOT: xori<br class="">; CHECK-P8U: lbarx<br class=""> %tmppair = cmpxchg i8* %mem, i8 0, i8 1 monotonic monotonic<br class=""> %tmp = extractvalue { i8, i1 } %tmppair, 0<br class="">@@ -48,6 +55,8 @@ define i8 @exchange_and_cmp8(i8* %mem) n<br class=""><br class="">define i16 @exchange_and_cmp16(i16* %mem) nounwind {<br class="">; CHECK-LABEL: exchange_and_cmp16:<br class="">+; CHECK-BE: xori<br class="">+; CHECK-LE-NOT: xori<br class="">; CHECK-P8U: lharx<br class=""> %tmppair = cmpxchg i16* %mem, i16 0, i16 1 monotonic monotonic<br class=""> %tmp = extractvalue { i16, i1 } %tmppair, 0<br class="">@@ -66,6 +75,8 @@ define i64 @exchange(i64* %mem, i64 %val<br class=""><br class="">define i8 @exchange8(i8* %mem, i8 %val) nounwind {<br class="">; CHECK-LABEL: exchange8:<br class="">+; CHECK-BE: xori<br class="">+; CHECK-LE-NOT: xori<br class="">; CHECK-P8U: lbarx<br class=""> %tmp = atomicrmw xchg i8* %mem, i8 1 monotonic<br class="">; CHECK-P8U: stbcx.<br class="">@@ -74,6 +85,8 @@ define i8 @exchange8(i8* %mem, i8 %val)<br class=""><br class="">define i16 @exchange16(i16* %mem, i16 %val) nounwind {<br class="">; CHECK-LABEL: exchange16:<br class="">+; CHECK-BE: xori<br class="">+; CHECK-LE-NOT: xori<br class="">; CHECK-P8U: lharx<br class=""> %tmp = atomicrmw xchg i16* %mem, i16 1 monotonic<br class="">; CHECK-P8U: sthcx.<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a><br class="">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits<br class=""></blockquote><br class=""></div></body></html>