<div dir="ltr">Should be related to this patch: <a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15783/steps/check-llvm%20msan/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15783/steps/check-llvm%20msan/logs/stdio</a><br></div><br><div class="gmail_quote"><div dir="ltr">On Wed, Aug 24, 2016 at 3:25 PM Matthias Braun via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: matze<br>
Date: Wed Aug 24 17:17:45 2016<br>
New Revision: 279676<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=279676&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=279676&view=rev</a><br>
Log:<br>
MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it<br>
<br>
tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there<br>
is not need to change it or save/parse it in a .mir file.<br>
Make the field const and move the initialization LiveIntervalAnalysis to the<br>
MachineRegisterInfo constructor. Also cleanup some code and fix some<br>
instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead<br>
of TargetSubtargetInfo::enableSubRegLiveness().<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br>
llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h<br>
llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h<br>
llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp<br>
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp<br>
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br>
llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br>
llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp<br>
llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp<br>
llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir<br>
llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir<br>
llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir<br>
llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir<br>
llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir<br>
llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir<br>
llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir<br>
llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir<br>
llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir<br>
llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir<br>
llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir<br>
llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir<br>
llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir<br>
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir<br>
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Wed Aug 24 17:17:45 2016<br>
@@ -390,7 +390,6 @@ struct MachineFunction {<br>
bool Selected = false;<br>
// Register information<br>
bool TracksRegLiveness = false;<br>
- bool TracksSubRegLiveness = false;<br>
std::vector<VirtualRegisterDefinition> VirtualRegisters;<br>
std::vector<MachineFunctionLiveIn> LiveIns;<br>
Optional<std::vector<FlowStringValue>> CalleeSavedRegisters;<br>
@@ -415,7 +414,6 @@ template <> struct MappingTraits<Machine<br>
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);<br>
YamlIO.mapOptional("selected", MF.Selected);<br>
YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);<br>
- YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);<br>
YamlIO.mapOptional("registers", MF.VirtualRegisters);<br>
YamlIO.mapOptional("liveins", MF.LiveIns);<br>
YamlIO.mapOptional("calleeSavedRegisters", MF.CalleeSavedRegisters);<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Wed Aug 24 17:17:45 2016<br>
@@ -51,7 +51,7 @@ private:<br>
Delegate *TheDelegate;<br>
<br>
/// True if subregister liveness is tracked.<br>
- bool TracksSubRegLiveness;<br>
+ const bool TracksSubRegLiveness;<br>
<br>
/// VRegInfo - Information we keep for each virtual register.<br>
///<br>
@@ -199,10 +199,6 @@ public:<br>
return TracksSubRegLiveness;<br>
}<br>
<br>
- void enableSubRegLiveness(bool Enable = true) {<br>
- TracksSubRegLiveness = Enable;<br>
- }<br>
-<br>
//===--------------------------------------------------------------------===//<br>
// Register Info<br>
//===--------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Wed Aug 24 17:17:45 2016<br>
@@ -218,6 +218,8 @@ public:<br>
}<br>
<br>
/// Enable tracking of subregister liveness in register allocator.<br>
+ /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where<br>
+ /// possible.<br>
virtual bool enableSubRegLiveness() const { return false; }<br>
};<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp Wed Aug 24 17:17:45 2016<br>
@@ -577,12 +577,12 @@ bool DetectDeadLanes::runOnMachineFuncti<br>
// register coalescer cannot deal with hidden dead defs. However without<br>
// subregister liveness enabled, the expected benefits of this pass are small<br>
// so we safe the compile time.<br>
- if (!MF.getSubtarget().enableSubRegLiveness()) {<br>
+ MRI = &MF.getRegInfo();<br>
+ if (!MRI->subRegLivenessEnabled()) {<br>
DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");<br>
return false;<br>
}<br>
<br>
- MRI = &MF.getRegInfo();<br>
TRI = MRI->getTargetRegisterInfo();<br>
<br>
unsigned NumVirtRegs = MRI->getNumVirtRegs();<br>
<br>
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Aug 24 17:17:45 2016<br>
@@ -58,10 +58,6 @@ static cl::opt<bool> EnablePrecomputePhy<br>
static bool EnablePrecomputePhysRegs = false;<br>
#endif // NDEBUG<br>
<br>
-static cl::opt<bool> EnableSubRegLiveness(<br>
- "enable-subreg-liveness", cl::Hidden, cl::init(true),<br>
- cl::desc("Enable subregister liveness tracking."));<br>
-<br>
namespace llvm {<br>
cl::opt<bool> UseSegmentSetForPhysRegs(<br>
"use-segment-set-for-physregs", cl::Hidden, cl::init(true),<br>
@@ -119,9 +115,6 @@ bool LiveIntervals::runOnMachineFunction<br>
Indexes = &getAnalysis<SlotIndexes>();<br>
DomTree = &getAnalysis<MachineDominatorTree>();<br>
<br>
- if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())<br>
- MRI->enableSubRegLiveness(true);<br>
-<br>
if (!LRCalc)<br>
LRCalc = new LiveRangeCalc();<br>
<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Wed Aug 24 17:17:45 2016<br>
@@ -401,7 +401,6 @@ bool MIRParserImpl::initializeRegisterIn<br>
assert(RegInfo.tracksLiveness());<br>
if (!YamlMF.TracksRegLiveness)<br>
RegInfo.invalidateLiveness();<br>
- RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);<br>
<br>
SMDiagnostic Error;<br>
// Parse the virtual register information.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Wed Aug 24 17:17:45 2016<br>
@@ -213,7 +213,6 @@ void MIRPrinter::convert(yaml::MachineFu<br>
const MachineRegisterInfo &RegInfo,<br>
const TargetRegisterInfo *TRI) {<br>
MF.TracksRegLiveness = RegInfo.tracksLiveness();<br>
- MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();<br>
<br>
// Print the virtual register definitions.<br>
for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Wed Aug 24 17:17:45 2016<br>
@@ -21,11 +21,16 @@<br>
<br>
using namespace llvm;<br>
<br>
+static cl::opt<bool> EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden,<br>
+ cl::init(true), cl::desc("Enable subregister liveness tracking."));<br>
+<br>
// Pin the vtable to this file.<br>
void MachineRegisterInfo::Delegate::anchor() {}<br>
<br>
MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)<br>
- : MF(MF), TheDelegate(nullptr), TracksSubRegLiveness(false) {<br>
+ : MF(MF), TheDelegate(nullptr),<br>
+ TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&<br>
+ EnableSubRegLiveness) {<br>
unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();<br>
VRegInfo.reserve(256);<br>
RegAllocHints.reserve(256);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp Wed Aug 24 17:17:45 2016<br>
@@ -363,14 +363,14 @@ void RenameIndependentSubregs::computeMa<br>
<br>
bool RenameIndependentSubregs::runOnMachineFunction(MachineFunction &MF) {<br>
// Skip renaming if liveness of subregister is not tracked.<br>
- if (!MF.getSubtarget().enableSubRegLiveness())<br>
+ MRI = &MF.getRegInfo();<br>
+ if (!MRI->subRegLivenessEnabled())<br>
return false;<br>
<br>
DEBUG(dbgs() << "Renaming independent subregister live ranges in "<br>
<< MF.getName() << '\n');<br>
<br>
LIS = &getAnalysis<LiveIntervals>();<br>
- MRI = &MF.getRegInfo();<br>
TII = MF.getSubtarget().getInstrInfo();<br>
<br>
// Iterate over all vregs. Note that we query getNumVirtRegs() the newly<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir Wed Aug 24 17:17:45 2016<br>
@@ -31,7 +31,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: true<br>
tracksRegLiveness: false<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%x0' }<br>
- { reg: '%w1' }<br>
@@ -88,7 +87,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: true<br>
tracksRegLiveness: false<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%x0' }<br>
- { reg: '%w1' }<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir Wed Aug 24 17:17:45 2016<br>
@@ -18,7 +18,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: true<br>
tracksRegLiveness: false<br>
-tracksSubRegLiveness: false<br>
frameInfo:<br>
isFrameAddressTaken: false<br>
isReturnAddressTaken: false<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir Wed Aug 24 17:17:45 2016<br>
@@ -82,7 +82,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%r0' }<br>
- { reg: '%r1' }<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir Wed Aug 24 17:17:45 2016<br>
@@ -36,7 +36,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: true<br>
tracksRegLiveness: false<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%w0' }<br>
frameInfo:<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir Wed Aug 24 17:17:45 2016<br>
@@ -32,8 +32,7 @@<br>
<br>
...<br>
---<br>
-name: float<br>
-tracksSubRegLiveness: true<br>
+name: float<br>
liveins:<br>
- { reg: '%sgpr0_sgpr1' }<br>
frameInfo:<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir Wed Aug 24 17:17:45 2016<br>
@@ -32,8 +32,7 @@<br>
<br>
...<br>
---<br>
-name: float<br>
-tracksSubRegLiveness: true<br>
+name: float<br>
liveins:<br>
- { reg: '%sgpr0_sgpr1' }<br>
frameInfo:<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/target-index-operands.mir Wed Aug 24 17:17:45 2016<br>
@@ -41,8 +41,7 @@<br>
<br>
...<br>
---<br>
-name: float<br>
-tracksSubRegLiveness: true<br>
+name: float<br>
liveins:<br>
- { reg: '%sgpr0_sgpr1' }<br>
frameInfo:<br>
@@ -72,8 +71,7 @@ body: |<br>
S_ENDPGM<br>
...<br>
---<br>
-name: float2<br>
-tracksSubRegLiveness: true<br>
+name: float2<br>
liveins:<br>
- { reg: '%sgpr0_sgpr1' }<br>
frameInfo:<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir Wed Aug 24 17:17:45 2016<br>
@@ -93,7 +93,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%r0' }<br>
- { reg: '%r1' }<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Generic/register-info.mir Wed Aug 24 17:17:45 2016<br>
@@ -18,7 +18,6 @@<br>
---<br>
# CHECK: name: foo<br>
# CHECK: tracksRegLiveness: false<br>
-# CHECK-NEXT: tracksSubRegLiveness: false<br>
# CHECK: ...<br>
name: foo<br>
body: |<br>
@@ -27,11 +26,9 @@ body: |<br>
---<br>
# CHECK: name: bar<br>
# CHECK: tracksRegLiveness: true<br>
-# CHECK-NEXT: tracksSubRegLiveness: true<br>
# CHECK: ...<br>
name: bar<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: true<br>
body: |<br>
bb.0:<br>
...<br>
<br>
Modified: llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir (original)<br>
+++ llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir Wed Aug 24 17:17:45 2016<br>
@@ -178,7 +178,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: gpr }<br>
- { id: 1, class: gpr }<br>
@@ -225,7 +224,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: gpr }<br>
- { id: 1, class: gpr }<br>
@@ -270,7 +268,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: gpr }<br>
- { id: 1, class: gpr }<br>
@@ -319,7 +316,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: gpr }<br>
- { id: 1, class: gpr }<br>
@@ -368,7 +364,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: gpr }<br>
- { id: 1, class: gpr }<br>
@@ -417,7 +412,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: gpr }<br>
- { id: 1, class: gpr }<br>
@@ -466,7 +460,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: gpr }<br>
- { id: 1, class: gpr }<br>
@@ -515,7 +508,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: gpr }<br>
- { id: 1, class: gpr }<br>
@@ -628,7 +620,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: gpr }<br>
- { id: 1, class: gpr }<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir (original)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir Wed Aug 24 17:17:45 2016<br>
@@ -47,7 +47,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: true<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%x3' }<br>
- { reg: '%x4' }<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir (original)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir Wed Aug 24 17:17:45 2016<br>
@@ -29,7 +29,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
frameInfo:<br>
isFrameAddressTaken: false<br>
isReturnAddressTaken: false<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir (original)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir Wed Aug 24 17:17:45 2016<br>
@@ -41,7 +41,6 @@ alignment: 2<br>
exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: g8rc_and_g8rc_nox0 }<br>
- { id: 1, class: g8rc_and_g8rc_nox0 }<br>
<br>
Modified: llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir (original)<br>
+++ llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir Wed Aug 24 17:17:45 2016<br>
@@ -35,7 +35,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: false<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
registers:<br>
- { id: 0, class: g8rc }<br>
- { id: 1, class: g8rc }<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir (original)<br>
+++ llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir Wed Aug 24 17:17:45 2016<br>
@@ -87,7 +87,6 @@ name: imp_null_check_with_bit<br>
alignment: 4<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%rdi' }<br>
- { reg: '%esi' }<br>
@@ -131,7 +130,6 @@ name: imp_null_check_with_bit<br>
alignment: 4<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%rdi' }<br>
- { reg: '%esi' }<br>
@@ -180,7 +178,6 @@ name: imp_null_check_with_bit<br>
alignment: 4<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%rdi' }<br>
- { reg: '%esi' }<br>
@@ -225,7 +222,6 @@ name: imp_null_check_with_bit<br>
alignment: 4<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%rdi' }<br>
- { reg: '%rsi' }<br>
<br>
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir (original)<br>
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir Wed Aug 24 17:17:45 2016<br>
@@ -160,7 +160,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%edi' }<br>
- { reg: '%esi' }<br>
<br>
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=279676&r1=279675&r2=279676&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=279676&r1=279675&r2=279676&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir (original)<br>
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir Wed Aug 24 17:17:45 2016<br>
@@ -162,7 +162,6 @@ exposesReturnsTwice: false<br>
hasInlineAsm: false<br>
allVRegsAllocated: true<br>
tracksRegLiveness: true<br>
-tracksSubRegLiveness: false<br>
liveins:<br>
- { reg: '%edi' }<br>
- { reg: '%rsi' }<br>
<br>
<br>
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</blockquote></div>