<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><div class="">I don't see a connection between the changes and the error symptom... Do you have the possibility to revert just this patch to verify?</div><br class=""><div><blockquote type="cite" class=""><div class="">On Aug 23, 2016, at 3:13 PM, Vitaly Buka <<a href="mailto:vitalybuka@google.com" class="">vitalybuka@google.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">This patch? <a href="http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/9417/steps/ninja%20check%201/logs/stdio" class="">http://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/9417/steps/ninja%20check%201/logs/stdio</a></div><br class=""><div class="gmail_quote"><div dir="ltr" class="">On Tue, Aug 23, 2016 at 2:27 PM Matthias Braun via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" class="">llvm-commits@lists.llvm.org</a>> wrote:<br class=""></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: matze<br class="">
Date: Tue Aug 23 16:19:49 2016<br class="">
New Revision: 279573<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=279573&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=279573&view=rev</a><br class="">
Log:<br class="">
MachineFunction: Introduce NoPHIs property<br class="">
<br class="">
I want to compute the SSA property of .mir files automatically in<br class="">
upcoming patches. The problem with this is that some inputs will be<br class="">
reported as static single assignment with some passes claiming not to<br class="">
support SSA form. In reality though those passes do not support PHI<br class="">
instructions => Track the presence of PHI instructions separate from the<br class="">
SSA property.<br class="">
<br class="">
Differential Revision: <a href="https://reviews.llvm.org/D22719" rel="noreferrer" target="_blank" class="">https://reviews.llvm.org/D22719</a><br class="">
<br class="">
Modified:<br class="">
llvm/trunk/include/llvm/CodeGen/MachineFunction.h<br class="">
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br class="">
llvm/trunk/lib/CodeGen/MachineFunction.cpp<br class="">
llvm/trunk/lib/CodeGen/MachineVerifier.cpp<br class="">
llvm/trunk/lib/CodeGen/PHIElimination.cpp<br class="">
llvm/trunk/lib/CodeGen/RegAllocBasic.cpp<br class="">
llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br class="">
llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp<br class="">
llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp<br class="">
llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)<br class="">
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Aug 23 16:19:49 2016<br class="">
@@ -92,6 +92,7 @@ public:<br class="">
// Property descriptions:<br class="">
// IsSSA: True when the machine function is in SSA form and virtual registers<br class="">
// have a single def.<br class="">
+ // NoPHIs: The machine function does not contain any PHI instruction.<br class="">
// TracksLiveness: True when tracking register liveness accurately.<br class="">
// While this property is set, register liveness information in basic block<br class="">
// live-in lists and machine instruction operands (e.g. kill flags, implicit<br class="">
@@ -117,6 +118,7 @@ public:<br class="">
// all sizes attached to them have been eliminated.<br class="">
enum class Property : unsigned {<br class="">
IsSSA,<br class="">
+ NoPHIs,<br class="">
TracksLiveness,<br class="">
AllVRegsAllocated,<br class="">
Legalized,<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Tue Aug 23 16:19:49 2016<br class="">
@@ -160,6 +160,8 @@ private:<br class="">
///<br class="">
/// Return null if the name isn't a register bank.<br class="">
const RegisterBank *getRegBank(const MachineFunction &MF, StringRef Name);<br class="">
+<br class="">
+ void computeFunctionProperties(MachineFunction &MF);<br class="">
};<br class="">
<br class="">
} // end namespace llvm<br class="">
@@ -279,6 +281,19 @@ void MIRParserImpl::createDummyFunction(<br class="">
new UnreachableInst(Context, BB);<br class="">
}<br class="">
<br class="">
+static bool hasPHI(const MachineFunction &MF) {<br class="">
+ for (const MachineBasicBlock &MBB : MF)<br class="">
+ for (const MachineInstr &MI : MBB)<br class="">
+ if (MI.isPHI())<br class="">
+ return true;<br class="">
+ return false;<br class="">
+}<br class="">
+<br class="">
+void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {<br class="">
+ if (!hasPHI(MF))<br class="">
+ MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);<br class="">
+}<br class="">
+<br class="">
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {<br class="">
auto It = Functions.find(MF.getName());<br class="">
if (It == Functions.end())<br class="">
@@ -353,6 +368,9 @@ bool MIRParserImpl::initializeMachineFun<br class="">
<a href="http://pfs.sm/" rel="noreferrer" target="_blank" class="">PFS.SM</a> = &SM;<br class="">
<br class="">
inferRegisterInfo(PFS, YamlMF);<br class="">
+<br class="">
+ computeFunctionProperties(MF);<br class="">
+<br class="">
// FIXME: This is a temporary workaround until the reserved registers can be<br class="">
// serialized.<br class="">
MF.getRegInfo().freezeReservedRegs(MF);<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Aug 23 16:19:49 2016<br class="">
@@ -60,6 +60,7 @@ static const char *getPropertyName(Machi<br class="">
case P::AllVRegsAllocated: return "AllVRegsAllocated";<br class="">
case P::IsSSA: return "IsSSA";<br class="">
case P::Legalized: return "Legalized";<br class="">
+ case P::NoPHIs: return "NoPHIs";<br class="">
case P::RegBankSelected: return "RegBankSelected";<br class="">
case P::Selected: return "Selected";<br class="">
case P::TracksLiveness: return "TracksLiveness";<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Aug 23 16:19:49 2016<br class="">
@@ -858,6 +858,10 @@ void MachineVerifier::visitMachineInstrB<br class="">
<< MI->getNumOperands() << " given.\n";<br class="">
}<br class="">
<br class="">
+ if (MI->isPHI() && MF->getProperties().hasProperty(<br class="">
+ MachineFunctionProperties::Property::NoPHIs))<br class="">
+ report("Found PHI instruction with NoPHIs property set", MI);<br class="">
+<br class="">
// Check the tied operands.<br class="">
if (MI->isInlineAsm())<br class="">
verifyInlineAsm(MI);<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Tue Aug 23 16:19:49 2016<br class="">
@@ -175,6 +175,8 @@ bool PHIElimination::runOnMachineFunctio<br class="">
ImpDefs.clear();<br class="">
VRegPHIUseCount.clear();<br class="">
<br class="">
+ MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);<br class="">
+<br class="">
return Changed;<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Aug 23 16:19:49 2016<br class="">
@@ -105,6 +105,11 @@ public:<br class="">
/// Perform register allocation.<br class="">
bool runOnMachineFunction(MachineFunction &mf) override;<br class="">
<br class="">
+ MachineFunctionProperties getRequiredProperties() const override {<br class="">
+ return MachineFunctionProperties().set(<br class="">
+ MachineFunctionProperties::Property::NoPHIs);<br class="">
+ }<br class="">
+<br class="">
// Helper for spilling all live virtual registers currently unified under preg<br class="">
// that interfere with the most recently queried lvr. Return true if spilling<br class="">
// was successful, and append any new spilled/split intervals to splitLVRs.<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Aug 23 16:19:49 2016<br class="">
@@ -158,6 +158,11 @@ namespace {<br class="">
MachineFunctionPass::getAnalysisUsage(AU);<br class="">
}<br class="">
<br class="">
+ MachineFunctionProperties getRequiredProperties() const override {<br class="">
+ return MachineFunctionProperties().set(<br class="">
+ MachineFunctionProperties::Property::NoPHIs);<br class="">
+ }<br class="">
+<br class="">
MachineFunctionProperties getSetProperties() const override {<br class="">
return MachineFunctionProperties().set(<br class="">
MachineFunctionProperties::Property::AllVRegsAllocated);<br class="">
@@ -1093,8 +1098,6 @@ bool RAFast::runOnMachineFunction(Machin<br class="">
UsedInInstr.clear();<br class="">
UsedInInstr.setUniverse(TRI->getNumRegUnits());<br class="">
<br class="">
- assert(!MRI->isSSA() && "regalloc requires leaving SSA");<br class="">
-<br class="">
// initialize the virtual->physical register map to have a 'null'<br class="">
// mapping for all virtual registers<br class="">
StackSlotForVirtReg.resize(MRI->getNumVirtRegs());<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Aug 23 16:19:49 2016<br class="">
@@ -334,6 +334,11 @@ public:<br class="">
/// Perform register allocation.<br class="">
bool runOnMachineFunction(MachineFunction &mf) override;<br class="">
<br class="">
+ MachineFunctionProperties getRequiredProperties() const override {<br class="">
+ return MachineFunctionProperties().set(<br class="">
+ MachineFunctionProperties::Property::NoPHIs);<br class="">
+ }<br class="">
+<br class="">
static char ID;<br class="">
<br class="">
private:<br class="">
<br class="">
Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original)<br class="">
+++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Tue Aug 23 16:19:49 2016<br class="">
@@ -109,6 +109,11 @@ public:<br class="">
/// Perform register allocation<br class="">
bool runOnMachineFunction(MachineFunction &MF) override;<br class="">
<br class="">
+ MachineFunctionProperties getRequiredProperties() const override {<br class="">
+ return MachineFunctionProperties().set(<br class="">
+ MachineFunctionProperties::Property::NoPHIs);<br class="">
+ }<br class="">
+<br class="">
private:<br class="">
<br class="">
typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp?rev=279573&r1=279572&r2=279573&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp?rev=279573&r1=279572&r2=279573&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp Tue Aug 23 16:19:49 2016<br class="">
@@ -98,6 +98,11 @@ public:<br class="">
return "SI Load / Store Optimizer";<br class="">
}<br class="">
<br class="">
+ MachineFunctionProperties getRequiredProperties() const override {<br class="">
+ return MachineFunctionProperties().set(<br class="">
+ MachineFunctionProperties::Property::NoPHIs);<br class="">
+ }<br class="">
+<br class="">
void getAnalysisUsage(AnalysisUsage &AU) const override {<br class="">
AU.setPreservesCFG();<br class="">
AU.addPreserved<SlotIndexes>();<br class="">
@@ -425,8 +430,6 @@ bool SILoadStoreOptimizer::runOnMachineF<br class="">
<br class="">
DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");<br class="">
<br class="">
- assert(!MRI->isSSA());<br class="">
-<br class="">
bool Modified = false;<br class="">
<br class="">
for (MachineBasicBlock &MBB : MF)<br class="">
<br class="">
<br class="">
_______________________________________________<br class="">
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</blockquote></div>
</div></blockquote></div><br class=""></body></html>