<div dir="ltr"><div class="gmail_quote"><div dir="ltr">On Tue, Aug 16, 2016 at 11:59 PM Chandler Carruth <<a href="mailto:chandlerc@gmail.com">chandlerc@gmail.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_quote"><div dir="ltr">On Tue, Aug 16, 2016 at 10:18 PM Justin Bogner via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: bogner<br>
Date: Wed Aug 17 00:10:15 2016<br>
New Revision: 278902<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=278902&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=278902&view=rev</a><br>
Log:<br>
Replace "fallthrough" comments with LLVM_FALLTHROUGH<br>
<br>
This is a mechanical change of comments in switches like fallthrough,<br>
fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead.<br></blockquote><div><br></div></div></div><div dir="ltr"><div class="gmail_quote"><div>While I fully support the intent here, the current mechanism causes *tons* of -Wc++1z-extension warnings as a consequence of this patch...</div><div><br></div><div>If I can't figure out a reliable way to fix this, I'm gonna have to revert it or something. It's made the build somewhat unusable.</div></div></div></blockquote><div><br></div><div>I think I worked around this with r278909.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_quote"><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
Modified:<br>
llvm/trunk/lib/Analysis/InstructionSimplify.cpp<br>
llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp<br>
llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp<br>
llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br>
llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
llvm/trunk/lib/CodeGen/TargetPassConfig.cpp<br>
llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h<br>
llvm/trunk/lib/IR/ConstantFold.cpp<br>
llvm/trunk/lib/IR/InlineAsm.cpp<br>
llvm/trunk/lib/IR/Value.cpp<br>
llvm/trunk/lib/Object/SymbolicFile.cpp<br>
llvm/trunk/lib/Option/OptTable.cpp<br>
llvm/trunk/lib/TableGen/TGLexer.cpp<br>
llvm/trunk/lib/TableGen/TGParser.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp<br>
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp<br>
llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp<br>
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp<br>
llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp<br>
llvm/trunk/lib/Target/ARM/ARMFastISel.cpp<br>
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp<br>
llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp<br>
llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp<br>
llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp<br>
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp<br>
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp<br>
llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp<br>
llvm/trunk/lib/Target/X86/X86FastISel.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp<br>
llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp<br>
llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp<br>
llvm/trunk/lib/Transforms/Instrumentation/ThreadSanitizer.cpp<br>
llvm/trunk/lib/Transforms/ObjCARC/ObjCARCContract.cpp<br>
llvm/trunk/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp<br>
llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp<br>
llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp<br>
llvm/trunk/tools/dsymutil/DwarfLinker.cpp<br>
llvm/trunk/tools/llvm-readobj/ELFDumper.cpp<br>
<br>
Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)<br>
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Aug 17 00:10:15 2016<br>
@@ -2773,7 +2773,7 @@ static Value *SimplifyICmpInst(unsigned<br>
Q.CxtI, Q.DT);<br>
if (!KnownNonNegative)<br>
break;<br>
- // fall-through<br>
+ LLVM_FALLTHROUGH;<br>
case ICmpInst::ICMP_EQ:<br>
case ICmpInst::ICMP_UGT:<br>
case ICmpInst::ICMP_UGE:<br>
@@ -2784,7 +2784,7 @@ static Value *SimplifyICmpInst(unsigned<br>
Q.CxtI, Q.DT);<br>
if (!KnownNonNegative)<br>
break;<br>
- // fall-through<br>
+ LLVM_FALLTHROUGH;<br>
case ICmpInst::ICMP_NE:<br>
case ICmpInst::ICMP_ULT:<br>
case ICmpInst::ICMP_ULE:<br>
@@ -2804,7 +2804,7 @@ static Value *SimplifyICmpInst(unsigned<br>
Q.CxtI, Q.DT);<br>
if (!KnownNonNegative)<br>
break;<br>
- // fall-through<br>
+ LLVM_FALLTHROUGH;<br>
case ICmpInst::ICMP_NE:<br>
case ICmpInst::ICMP_UGT:<br>
case ICmpInst::ICMP_UGE:<br>
@@ -2815,7 +2815,7 @@ static Value *SimplifyICmpInst(unsigned<br>
Q.CxtI, Q.DT);<br>
if (!KnownNonNegative)<br>
break;<br>
- // fall-through<br>
+ LLVM_FALLTHROUGH;<br>
case ICmpInst::ICMP_EQ:<br>
case ICmpInst::ICMP_ULT:<br>
case ICmpInst::ICMP_ULE:<br>
@@ -2877,7 +2877,7 @@ static Value *SimplifyICmpInst(unsigned<br>
case Instruction::LShr:<br>
if (ICmpInst::isSigned(Pred))<br>
break;<br>
- // fall-through<br>
+ LLVM_FALLTHROUGH;<br>
case Instruction::SDiv:<br>
case Instruction::AShr:<br>
if (!LBO->isExact() || !RBO->isExact())<br>
<br>
Modified: llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp (original)<br>
+++ llvm/trunk/lib/Analysis/TargetLibraryInfo.cpp Wed Aug 17 00:10:15 2016<br>
@@ -537,7 +537,7 @@ bool TargetLibraryInfoImpl::isValidProto<br>
--NumParams;<br>
if (!IsSizeTTy(FTy.getParamType(NumParams)))<br>
return false;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case LibFunc::strcpy:<br>
case LibFunc::stpcpy:<br>
return (NumParams == 2 && FTy.getReturnType() == FTy.getParamType(0) &&<br>
@@ -549,7 +549,7 @@ bool TargetLibraryInfoImpl::isValidProto<br>
--NumParams;<br>
if (!IsSizeTTy(FTy.getParamType(NumParams)))<br>
return false;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case LibFunc::strncpy:<br>
case LibFunc::stpncpy:<br>
return (NumParams == 3 && FTy.getReturnType() == FTy.getParamType(0) &&<br>
@@ -642,7 +642,7 @@ bool TargetLibraryInfoImpl::isValidProto<br>
--NumParams;<br>
if (!IsSizeTTy(FTy.getParamType(NumParams)))<br>
return false;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case LibFunc::memcpy:<br>
case LibFunc::mempcpy:<br>
case LibFunc::memmove:<br>
@@ -655,7 +655,7 @@ bool TargetLibraryInfoImpl::isValidProto<br>
--NumParams;<br>
if (!IsSizeTTy(FTy.getParamType(NumParams)))<br>
return false;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case LibFunc::memset:<br>
return (NumParams == 3 && FTy.getReturnType() == FTy.getParamType(0) &&<br>
FTy.getParamType(0)->isPointerTy() &&<br>
<br>
Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)<br>
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Wed Aug 17 00:10:15 2016<br>
@@ -2271,7 +2271,7 @@ std::error_code BitcodeReader::parseMeta<br>
}<br>
case bitc::METADATA_DISTINCT_NODE:<br>
IsDistinct = true;<br>
- // fallthrough...<br>
+ LLVM_FALLTHROUGH;<br>
case bitc::METADATA_NODE: {<br>
SmallVector<Metadata *, 8> Elts;<br>
Elts.reserve(Record.size());<br>
@@ -3355,7 +3355,7 @@ std::error_code BitcodeReader::parseUseL<br>
break;<br>
case bitc::USELIST_CODE_BB:<br>
IsBB = true;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case bitc::USELIST_CODE_DEFAULT: {<br>
unsigned RecordLength = Record.size();<br>
if (RecordLength < 3)<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1583,7 +1583,7 @@ bool MIParser::parseMachineOperand(Machi<br>
lex();<br>
break;<br>
}<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
default:<br>
// FIXME: Parse the MCSymbol machine operand.<br>
return error("expected a machine operand");<br>
<br>
Modified: llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp Wed Aug 17 00:10:15 2016<br>
@@ -145,7 +145,7 @@ ScoreboardHazardRecognizer::getHazardTyp<br>
case InstrStage::Required:<br>
// Required FUs conflict with both reserved and required ones<br>
freeUnits &= ~ReservedScoreboard[StageCycle];<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case InstrStage::Reserved:<br>
// Reserved FUs can conflict only with required ones.<br>
freeUnits &= ~RequiredScoreboard[StageCycle];<br>
@@ -197,7 +197,7 @@ void ScoreboardHazardRecognizer::EmitIns<br>
case InstrStage::Required:<br>
// Required FUs conflict with both reserved and required ones<br>
freeUnits &= ~ReservedScoreboard[cycle + i];<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case InstrStage::Reserved:<br>
// Reserved FUs can conflict only with required ones.<br>
freeUnits &= ~RequiredScoreboard[cycle + i];<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Aug 17 00:10:15 2016<br>
@@ -801,7 +801,7 @@ void SelectionDAGLegalize::LegalizeLoadO<br>
default: llvm_unreachable("This action is not supported yet!");<br>
case TargetLowering::Custom:<br>
isCustom = true;<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case TargetLowering::Legal: {<br>
Value = SDValue(Node, 0);<br>
Chain = SDValue(Node, 1);<br>
@@ -1598,6 +1598,7 @@ bool SelectionDAGLegalize::LegalizeSetCC<br>
break;<br>
}<br>
// Fallthrough if we are unsigned integer.<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::SETLE:<br>
case ISD::SETGT:<br>
case ISD::SETGE:<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1776,7 +1776,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDS<br>
switch (BoolType) {<br>
case TargetLoweringBase::UndefinedBooleanContent:<br>
OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF);<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case TargetLoweringBase::ZeroOrOneBooleanContent:<br>
Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);<br>
break;<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Aug 17 00:10:15 2016<br>
@@ -2481,7 +2481,7 @@ void SelectionDAG::computeKnownBits(SDVa<br>
default:<br>
if (Op.getOpcode() < ISD::BUILTIN_OP_END)<br>
break;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::INTRINSIC_WO_CHAIN:<br>
case ISD::INTRINSIC_W_CHAIN:<br>
case ISD::INTRINSIC_VOID:<br>
@@ -3868,7 +3868,7 @@ SDValue SelectionDAG::getNode(unsigned O<br>
// Handle undef ^ undef -> 0 special case. This is a common<br>
// idiom (misuse).<br>
return getConstant(0, DL, VT);<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::ADD:<br>
case ISD::ADDC:<br>
case ISD::ADDE:<br>
<br>
Modified: llvm/trunk/lib/CodeGen/TargetPassConfig.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetPassConfig.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetPassConfig.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/TargetPassConfig.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/TargetPassConfig.cpp Wed Aug 17 00:10:15 2016<br>
@@ -483,7 +483,7 @@ void TargetPassConfig::addPassesToHandle<br>
// pad is shared by multiple invokes and is also a target of a normal<br>
// edge from elsewhere.<br>
addPass(createSjLjEHPreparePass());<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case ExceptionHandling::DwarfCFI:<br>
case ExceptionHandling::ARM:<br>
addPass(createDwarfEHPass(TM));<br>
<br>
Modified: llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h (original)<br>
+++ llvm/trunk/lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h Wed Aug 17 00:10:15 2016<br>
@@ -97,7 +97,8 @@ public:<br>
(void)p;<br>
assert((*p & 0x3B000000) == 0x39000000 &&<br>
"Only expected load / store instructions.");<br>
- } // fall-through<br>
+ LLVM_FALLTHROUGH;<br>
+ }<br>
case MachO::ARM64_RELOC_PAGEOFF12: {<br>
// Verify that the relocation points to one of the expected load / store<br>
// or add / sub instructions.<br>
@@ -196,7 +197,8 @@ public:<br>
assert((*p & 0x3B000000) == 0x39000000 &&<br>
"Only expected load / store instructions.");<br>
(void)p;<br>
- } // fall-through<br>
+ LLVM_FALLTHROUGH;<br>
+ }<br>
case MachO::ARM64_RELOC_PAGEOFF12: {<br>
// Verify that the relocation points to one of the expected load / store<br>
// or add / sub instructions.<br>
<br>
Modified: llvm/trunk/lib/IR/ConstantFold.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/ConstantFold.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/ConstantFold.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/IR/ConstantFold.cpp (original)<br>
+++ llvm/trunk/lib/IR/ConstantFold.cpp Wed Aug 17 00:10:15 2016<br>
@@ -925,7 +925,7 @@ Constant *llvm::ConstantFoldBinaryInstru<br>
// Handle undef ^ undef -> 0 special case. This is a common<br>
// idiom (misuse).<br>
return Constant::getNullValue(C1->getType());<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case Instruction::Add:<br>
case Instruction::Sub:<br>
return UndefValue::get(C1->getType());<br>
<br>
Modified: llvm/trunk/lib/IR/InlineAsm.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/InlineAsm.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/InlineAsm.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/IR/InlineAsm.cpp (original)<br>
+++ llvm/trunk/lib/IR/InlineAsm.cpp Wed Aug 17 00:10:15 2016<br>
@@ -265,7 +265,7 @@ bool InlineAsm::Verify(FunctionType *Ty,<br>
break;<br>
}<br>
++NumIndirect;<br>
- // FALLTHROUGH for Indirect Outputs.<br>
+ LLVM_FALLTHROUGH; // We fall through for Indirect Outputs.<br>
case InlineAsm::isInput:<br>
if (NumClobbers) return false; // inputs before clobbers.<br>
++NumInputs;<br>
<br>
Modified: llvm/trunk/lib/IR/Value.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/Value.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/Value.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/IR/Value.cpp (original)<br>
+++ llvm/trunk/lib/IR/Value.cpp Wed Aug 17 00:10:15 2016<br>
@@ -449,7 +449,7 @@ static Value *stripPointerCastsAndOffset<br>
case PSK_InBoundsConstantIndices:<br>
if (!GEP->hasAllConstantIndices())<br>
return V;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case PSK_InBounds:<br>
if (!GEP->isInBounds())<br>
return V;<br>
@@ -848,7 +848,7 @@ void ValueHandleBase::ValueIsRAUWd(Value<br>
// virtual (or inline) interface to handle this though, so instead we make<br>
// the TrackingVH accessors guarantee that a client never sees this value.<br>
<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case Weak:<br>
// Weak goes to the new value, which will unlink it from Old's list.<br>
Entry->operator=(New);<br>
<br>
Modified: llvm/trunk/lib/Object/SymbolicFile.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/SymbolicFile.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/SymbolicFile.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Object/SymbolicFile.cpp (original)<br>
+++ llvm/trunk/lib/Object/SymbolicFile.cpp Wed Aug 17 00:10:15 2016<br>
@@ -36,7 +36,7 @@ Expected<std::unique_ptr<SymbolicFile>><br>
case sys::fs::file_magic::bitcode:<br>
if (Context)<br>
return errorOrToExpected(IRObjectFile::create(Object, *Context));<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case sys::fs::file_magic::unknown:<br>
case sys::fs::file_magic::archive:<br>
case sys::fs::file_magic::macho_universal_binary:<br>
<br>
Modified: llvm/trunk/lib/Option/OptTable.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Option/OptTable.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Option/OptTable.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Option/OptTable.cpp (original)<br>
+++ llvm/trunk/lib/Option/OptTable.cpp Wed Aug 17 00:10:15 2016<br>
@@ -317,7 +317,7 @@ static std::string getOptionHelpName(con<br>
case Option::SeparateClass: case Option::JoinedOrSeparateClass:<br>
case Option::RemainingArgsClass: case Option::RemainingArgsJoinedClass:<br>
Name += ' ';<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case Option::JoinedClass: case Option::CommaJoinedClass:<br>
case Option::JoinedAndSeparateClass:<br>
if (const char *MetaVarName = Opts.getOptionMetaVar(Id))<br>
<br>
Modified: llvm/trunk/lib/TableGen/TGLexer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGLexer.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGLexer.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/TableGen/TGLexer.cpp (original)<br>
+++ llvm/trunk/lib/TableGen/TGLexer.cpp Wed Aug 17 00:10:15 2016<br>
@@ -155,7 +155,7 @@ tgtok::TokKind TGLexer::LexToken() {<br>
case '0': case '1':<br>
if (NextChar == 'b')<br>
return LexNumber();<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case '2': case '3': case '4': case '5':<br>
case '6': case '7': case '8': case '9':<br>
case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':<br>
<br>
Modified: llvm/trunk/lib/TableGen/TGParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGParser.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/TableGen/TGParser.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/TableGen/TGParser.cpp (original)<br>
+++ llvm/trunk/lib/TableGen/TGParser.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1286,6 +1286,7 @@ Init *TGParser::ParseSimpleValue(Record<br>
continue;<br>
}<br>
// Fallthrough to try convert this to a bit.<br>
+ LLVM_FALLTHROUGH;<br>
}<br>
// All other values must be convertible to just a single bit.<br>
Init *Bit = Vals[i]->convertInitializerTo(BitRecTy::get());<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1179,7 +1179,8 @@ static void changeVectorFPCCToAArch64CC(<br>
changeFPCCToAArch64CC(CC, CondCode, CondCode2);<br>
break;<br>
case ISD::SETUO:<br>
- Invert = true; // Fallthrough<br>
+ Invert = true;<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::SETO:<br>
CondCode = AArch64CC::MI;<br>
CondCode2 = AArch64CC::GE;<br>
@@ -6720,8 +6721,8 @@ static SDValue EmitVectorComparison(SDVa<br>
case AArch64CC::LT:<br>
if (!NoNans)<br>
return SDValue();<br>
- // If we ignore NaNs then we can use to the MI implementation.<br>
- // Fallthrough.<br>
+ // If we ignore NaNs then we can use to the MI implementation.<br>
+ LLVM_FALLTHROUGH;<br>
case AArch64CC::MI:<br>
if (IsZero)<br>
return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Wed Aug 17 00:10:15 2016<br>
@@ -375,7 +375,8 @@ static unsigned canFoldIntoCSel(const Ma<br>
// if NZCV is used, do not fold.<br>
if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)<br>
return 0;<br>
- // fall-through to ADDXri and ADDWri.<br>
+ // fall-through to ADDXri and ADDWri.<br>
+ LLVM_FALLTHROUGH;<br>
case AArch64::ADDXri:<br>
case AArch64::ADDWri:<br>
// add x, 1 -> csinc.<br>
@@ -402,7 +403,8 @@ static unsigned canFoldIntoCSel(const Ma<br>
// if NZCV is used, do not fold.<br>
if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)<br>
return 0;<br>
- // fall-through to SUBXrr and SUBWrr.<br>
+ // fall-through to SUBXrr and SUBWrr.<br>
+ LLVM_FALLTHROUGH;<br>
case AArch64::SUBXrr:<br>
case AArch64::SUBWrr: {<br>
// neg x -> csneg, represented as sub dst, xzr, src.<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Wed Aug 17 00:10:15 2016<br>
@@ -3455,7 +3455,7 @@ bool AArch64AsmParser::validateInstructi<br>
if (RI->isSubRegisterEq(Rn, Rt2))<br>
return Error(Loc[1], "unpredictable LDP instruction, writeback base "<br>
"is also a destination");<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
}<br>
case AArch64::LDPDi:<br>
case AArch64::LDPQi:<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1097,7 +1097,7 @@ static DecodeStatus DecodeExclusiveLdStI<br>
case AArch64::STXRB:<br>
case AArch64::STXRH:<br>
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case AArch64::LDARW:<br>
case AArch64::LDARB:<br>
case AArch64::LDARH:<br>
@@ -1121,7 +1121,7 @@ static DecodeStatus DecodeExclusiveLdStI<br>
case AArch64::STLXRX:<br>
case AArch64::STXRX:<br>
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case AArch64::LDARX:<br>
case AArch64::LDAXRX:<br>
case AArch64::LDXRX:<br>
@@ -1133,7 +1133,7 @@ static DecodeStatus DecodeExclusiveLdStI<br>
case AArch64::STLXPW:<br>
case AArch64::STXPW:<br>
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case AArch64::LDAXPW:<br>
case AArch64::LDXPW:<br>
DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);<br>
@@ -1142,7 +1142,7 @@ static DecodeStatus DecodeExclusiveLdStI<br>
case AArch64::STLXPX:<br>
case AArch64::STXPX:<br>
DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case AArch64::LDAXPX:<br>
case AArch64::LDXPX:<br>
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);<br>
@@ -1218,7 +1218,7 @@ static DecodeStatus DecodePairLdStInstru<br>
case AArch64::STPXpre:<br>
case AArch64::LDPSWpre:<br>
NeedsDisjointWritebackTransfer = true;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case AArch64::LDNPXi:<br>
case AArch64::STNPXi:<br>
case AArch64::LDPXi:<br>
@@ -1232,7 +1232,7 @@ static DecodeStatus DecodePairLdStInstru<br>
case AArch64::LDPWpre:<br>
case AArch64::STPWpre:<br>
NeedsDisjointWritebackTransfer = true;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case AArch64::LDNPWi:<br>
case AArch64::STNPWi:<br>
case AArch64::LDPWi:<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -586,9 +586,10 @@ void R600TargetLowering::ReplaceNodeResu<br>
Results.push_back(lowerFP_TO_UINT(N->getOperand(0), DAG));<br>
return;<br>
}<br>
- // Fall-through. Since we don't care about out of bounds values<br>
- // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint<br>
- // considers some extra cases which are not necessary here.<br>
+ // Since we don't care about out of bounds values we can use FP_TO_SINT for<br>
+ // uints too. The DAGLegalizer code for uint considers some extra cases<br>
+ // which are not necessary here.<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::FP_TO_SINT: {<br>
if (N->getValueType(0) == MVT::i1) {<br>
Results.push_back(lowerFP_TO_SINT(N->getOperand(0), DAG));<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -2389,7 +2389,7 @@ SDValue SITargetLowering::LowerLOAD(SDVa<br>
// have the same legalization requires ments as global and private<br>
// loads.<br>
//<br>
- // Fall-through<br>
+ LLVM_FALLTHROUGH;<br>
case AMDGPUAS::GLOBAL_ADDRESS:<br>
case AMDGPUAS::FLAT_ADDRESS:<br>
if (NumElements > 4)<br>
<br>
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1721,7 +1721,7 @@ bool SIInstrInfo::verifyInstruction(cons<br>
ErrInfo = "Expected immediate, but got non-immediate";<br>
return false;<br>
}<br>
- // Fall-through<br>
+ LLVM_FALLTHROUGH;<br>
default:<br>
continue;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Aug 17 00:10:15 2016<br>
@@ -249,7 +249,7 @@ bool ARMAsmPrinter::PrintAsmOperand(cons<br>
<< "]";<br>
return false;<br>
}<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case 'c': // Don't print "#" before an immediate operand.<br>
if (!MI->getOperand(OpNum).isImm())<br>
return true;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Wed Aug 17 00:10:15 2016<br>
@@ -684,7 +684,7 @@ initializeFunctionInfo(const std::vector<br>
case ARM::Bcc:<br>
isCond = true;<br>
UOpc = ARM::B;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ARM::B:<br>
Bits = 24;<br>
Scale = 4;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1075,7 +1075,8 @@ bool ARMFastISel::ARMEmitStore(MVT VT, u<br>
TII.get(Opc), Res)<br>
.addReg(SrcReg).addImm(1));<br>
SrcReg = Res;<br>
- } // Fallthrough here.<br>
+ LLVM_FALLTHROUGH;<br>
+ }<br>
case MVT::i8:<br>
if (isThumb2) {<br>
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())<br>
@@ -1848,7 +1849,7 @@ CCAssignFn *ARMFastISel::CCAssignFnForCa<br>
// For AAPCS ABI targets, just use VFP variant of the calling convention.<br>
return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);<br>
}<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case CallingConv::C:<br>
case CallingConv::CXX_FAST_TLS:<br>
// Use target triple & subtarget features to do actual dispatch.<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -356,7 +356,7 @@ void ARMFrameLowering::emitPrologue(Mach<br>
GPRCS2Size += 4;<br>
break;<br>
}<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ARM::R0:<br>
case ARM::R1:<br>
case ARM::R2:<br>
@@ -559,7 +559,7 @@ void ARMFrameLowering::emitPrologue(Mach<br>
case ARM::R12:<br>
if (STI.splitFramePushPop())<br>
break;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ARM::R0:<br>
case ARM::R1:<br>
case ARM::R2:<br>
@@ -1558,7 +1558,7 @@ void ARMFrameLowering::determineCalleeSa<br>
switch (Reg) {<br>
case ARM::LR:<br>
LRSpilled = true;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ARM::R0: case ARM::R1:<br>
case ARM::R2: case ARM::R3:<br>
case ARM::R4: case ARM::R5:<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Aug 17 00:10:15 2016<br>
@@ -4420,7 +4420,7 @@ SelectInlineAsmMemoryOperand(const SDVal<br>
case InlineAsm::Constraint_i:<br>
// FIXME: It seems strange that 'i' is needed here since it's supposed to<br>
// be an immediate and not a memory constraint.<br>
- // Fallthrough.<br>
+ LLVM_FALLTHROUGH;<br>
case InlineAsm::Constraint_m:<br>
case InlineAsm::Constraint_o:<br>
case InlineAsm::Constraint_Q:<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -4906,22 +4906,22 @@ static SDValue LowerVSETCC(SDValue Op, S<br>
switch (SetCCOpcode) {<br>
default: llvm_unreachable("Illegal FP comparison");<br>
case ISD::SETUNE:<br>
- case ISD::SETNE: Invert = true; // Fallthrough<br>
+ case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH;<br>
case ISD::SETOEQ:<br>
case ISD::SETEQ: Opc = ARMISD::VCEQ; break;<br>
case ISD::SETOLT:<br>
- case ISD::SETLT: Swap = true; // Fallthrough<br>
+ case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;<br>
case ISD::SETOGT:<br>
case ISD::SETGT: Opc = ARMISD::VCGT; break;<br>
case ISD::SETOLE:<br>
- case ISD::SETLE: Swap = true; // Fallthrough<br>
+ case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH;<br>
case ISD::SETOGE:<br>
case ISD::SETGE: Opc = ARMISD::VCGE; break;<br>
- case ISD::SETUGE: Swap = true; // Fallthrough<br>
+ case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH;<br>
case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;<br>
- case ISD::SETUGT: Swap = true; // Fallthrough<br>
+ case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH;<br>
case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;<br>
- case ISD::SETUEQ: Invert = true; // Fallthrough<br>
+ case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH;<br>
case ISD::SETONE:<br>
// Expand this to (OLT | OGT).<br>
TmpOp0 = Op0;<br>
@@ -4930,7 +4930,9 @@ static SDValue LowerVSETCC(SDValue Op, S<br>
Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);<br>
Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);<br>
break;<br>
- case ISD::SETUO: Invert = true; // Fallthrough<br>
+ case ISD::SETUO:<br>
+ Invert = true;<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::SETO:<br>
// Expand this to (OLT | OGE).<br>
TmpOp0 = Op0;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 17 00:10:15 2016<br>
@@ -5425,7 +5425,7 @@ bool ARMAsmParser::parseOperand(OperandV<br>
return false;<br>
}<br>
// w/ a ':' after the '#', it's just like a plain ':'.<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
}<br>
case AsmToken::Colon: {<br>
S = Parser.getTok().getLoc();<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp Wed Aug 17 00:10:15 2016<br>
@@ -375,7 +375,7 @@ unsigned ARMAsmBackend::adjustFixupValue<br>
case ARM::fixup_arm_movt_hi16:<br>
if (!IsPCRel)<br>
Value >>= 16;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ARM::fixup_arm_movw_lo16: {<br>
unsigned Hi4 = (Value & 0xF000) >> 12;<br>
unsigned Lo12 = Value & 0x0FFF;<br>
@@ -387,7 +387,7 @@ unsigned ARMAsmBackend::adjustFixupValue<br>
case ARM::fixup_t2_movt_hi16:<br>
if (!IsPCRel)<br>
Value >>= 16;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ARM::fixup_t2_movw_lo16: {<br>
unsigned Hi4 = (Value & 0xF000) >> 12;<br>
unsigned i = (Value & 0x800) >> 11;<br>
@@ -403,7 +403,7 @@ unsigned ARMAsmBackend::adjustFixupValue<br>
case ARM::fixup_arm_ldst_pcrel_12:<br>
// ARM PC-relative values are offset by 8.<br>
Value -= 4;<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case ARM::fixup_t2_ldst_pcrel_12: {<br>
// Offset by 4, adjusted by two due to the half-word ordering of thumb.<br>
Value -= 4;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1493,7 +1493,7 @@ getT2SORegOpValue(const MCInst &MI, unsi<br>
case ARM_AM::lsl: SBits = 0x0; break;<br>
case ARM_AM::lsr: SBits = 0x2; break;<br>
case ARM_AM::asr: SBits = 0x4; break;<br>
- case ARM_AM::rrx: // FALLTHROUGH<br>
+ case ARM_AM::rrx: LLVM_FALLTHROUGH;<br>
case ARM_AM::ror: SBits = 0x6; break;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp Wed Aug 17 00:10:15 2016<br>
@@ -208,7 +208,7 @@ RecordARMScatteredHalfRelocation(MachObj<br>
if (Asm.isThumbFunc(A))<br>
FixedValue &= 0xfffffffe;<br>
MovtBit = 1;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ARM::fixup_t2_movw_lo16:<br>
ThumbBit = 1;<br>
break;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -154,7 +154,7 @@ void Thumb1FrameLowering::emitPrologue(M<br>
GPRCS2Size += 4;<br>
break;<br>
}<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ARM::R4:<br>
case ARM::R5:<br>
case ARM::R6:<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Aug 17 00:10:15 2016<br>
@@ -651,7 +651,7 @@ Thumb2SizeReduce::ReduceSpecial(MachineB<br>
case ARM::t2ADDSri: {<br>
if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))<br>
return true;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
}<br>
case ARM::t2ADDSrr:<br>
return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);<br>
<br>
Modified: llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp Wed Aug 17 00:10:15 2016<br>
@@ -172,7 +172,7 @@ void AVRRegisterInfo::eliminateFrameInde<br>
Opcode = AVR::ADIWRdK;<br>
break;<br>
}<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
}<br>
default: {<br>
// This opcode will get expanded into a pair of subi/sbci.<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp Wed Aug 17 00:10:15 2016<br>
@@ -569,8 +569,8 @@ public:<br>
if (!Resolved) {<br>
switch ((unsigned)Fixup.getKind()) {<br>
case fixup_Hexagon_B22_PCREL:<br>
- // GetFixupCount assumes B22 won't relax<br>
- // Fallthrough<br>
+ // GetFixupCount assumes B22 won't relax<br>
+ LLVM_FALLTHROUGH;<br>
default:<br>
return false;<br>
break;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp Wed Aug 17 00:10:15 2016<br>
@@ -215,7 +215,7 @@ bool HexagonShuffler::check() {<br>
break;<br>
case HexagonII::TypeJR:<br>
++jumpr;<br>
- // Fall-through.<br>
+ LLVM_FALLTHROUGH;<br>
case HexagonII::TypeJ:<br>
++jumps;<br>
break;<br>
<br>
Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -807,7 +807,8 @@ static SDValue EmitCMP(SDValue &LHS, SDV<br>
std::swap(LHS, RHS);<br>
break;<br>
case ISD::SETULE:<br>
- std::swap(LHS, RHS); // FALLTHROUGH<br>
+ std::swap(LHS, RHS);<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::SETUGE:<br>
// Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to<br>
// fold constant into instruction.<br>
@@ -820,7 +821,8 @@ static SDValue EmitCMP(SDValue &LHS, SDV<br>
TCC = MSP430CC::COND_HS; // aka COND_C<br>
break;<br>
case ISD::SETUGT:<br>
- std::swap(LHS, RHS); // FALLTHROUGH<br>
+ std::swap(LHS, RHS);<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::SETULT:<br>
// Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to<br>
// fold constant into instruction.<br>
@@ -833,7 +835,8 @@ static SDValue EmitCMP(SDValue &LHS, SDV<br>
TCC = MSP430CC::COND_LO; // aka COND_NC<br>
break;<br>
case ISD::SETLE:<br>
- std::swap(LHS, RHS); // FALLTHROUGH<br>
+ std::swap(LHS, RHS);<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::SETGE:<br>
// Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to<br>
// fold constant into instruction.<br>
@@ -846,7 +849,8 @@ static SDValue EmitCMP(SDValue &LHS, SDV<br>
TCC = MSP430CC::COND_GE;<br>
break;<br>
case ISD::SETGT:<br>
- std::swap(LHS, RHS); // FALLTHROUGH<br>
+ std::swap(LHS, RHS);<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::SETLT:<br>
// Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to<br>
// fold constant into instruction.<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1662,7 +1662,7 @@ static DecodeStatus DecodeMemMMImm12(MCI<br>
break;<br>
case Mips::SC_MM:<br>
Inst.addOperand(MCOperand::createReg(Reg));<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
default:<br>
Inst.addOperand(MCOperand::createReg(Reg));<br>
if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM ||<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Wed Aug 17 00:10:15 2016<br>
@@ -531,7 +531,7 @@ bool MipsELFObjectWriter::needsRelocateW<br>
case ELF::R_MIPS_GPREL32:<br>
if (cast<MCSymbolELF>(Sym).getOther() & ELF::STO_MIPS_MICROMIPS)<br>
return true;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ELF::R_MIPS_26:<br>
case ELF::R_MIPS_64:<br>
case ELF::R_MIPS_GPREL16:<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -2765,19 +2765,19 @@ MipsTargetLowering::LowerCall(TargetLowe<br>
break;<br>
case CCValAssign::SExtUpper:<br>
UseUpperBits = true;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case CCValAssign::SExt:<br>
Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);<br>
break;<br>
case CCValAssign::ZExtUpper:<br>
UseUpperBits = true;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case CCValAssign::ZExt:<br>
Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);<br>
break;<br>
case CCValAssign::AExtUpper:<br>
UseUpperBits = true;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case CCValAssign::AExt:<br>
Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);<br>
break;<br>
@@ -3235,19 +3235,19 @@ MipsTargetLowering::LowerReturn(SDValue<br>
break;<br>
case CCValAssign::AExtUpper:<br>
UseUpperBits = true;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case CCValAssign::AExt:<br>
Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);<br>
break;<br>
case CCValAssign::ZExtUpper:<br>
UseUpperBits = true;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case CCValAssign::ZExt:<br>
Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);<br>
break;<br>
case CCValAssign::SExtUpper:<br>
UseUpperBits = true;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case CCValAssign::SExt:<br>
Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);<br>
break;<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1571,7 +1571,8 @@ bool PPCAsmParser::ParseOperand(OperandV<br>
return false;<br>
}<br>
}<br>
- // Fall-through to process non-register-name identifiers as expression.<br>
+ // Fall-through to process non-register-name identifiers as expression.<br>
+ LLVM_FALLTHROUGH;<br>
// All other expressions<br>
case AsmToken::LParen:<br>
case AsmToken::Plus:<br>
@@ -1644,7 +1645,7 @@ bool PPCAsmParser::ParseOperand(OperandV<br>
break;<br>
}<br>
}<br>
- // Fall-through..<br>
+ LLVM_FALLTHROUGH;<br>
<br>
default:<br>
return Error(S, "invalid memory operand");<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Aug 17 00:10:15 2016<br>
@@ -3575,7 +3575,8 @@ void PPCDAGToDAGISel::PeepholeCROps() {<br>
Op.getOperand(0) == Op.getOperand(1))<br>
Op2Not = true;<br>
}<br>
- } // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
+ }<br>
case PPC::BC:<br>
case PPC::BCn:<br>
case PPC::SELECT_I4:<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -3748,7 +3748,7 @@ SDValue PPCTargetLowering::LowerFormalAr<br>
ArgOffset += PtrByteSize;<br>
break;<br>
}<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case MVT::i64: // PPC64<br>
if (GPR_idx != Num_GPR_Regs) {<br>
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);<br>
<br>
Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/PowerPC/PPCTargetTransformInfo.cpp Wed Aug 17 00:10:15 2016<br>
@@ -131,12 +131,12 @@ int PPCTTIImpl::getIntImmCost(unsigned O<br>
return TTI::TCC_Free;<br>
case Instruction::And:<br>
RunFree = true; // (for the rotate-and-mask instructions)<br>
- // Fallthrough...<br>
+ LLVM_FALLTHROUGH;<br>
case Instruction::Add:<br>
case Instruction::Or:<br>
case Instruction::Xor:<br>
ShiftedFree = true;<br>
- // Fallthrough...<br>
+ LLVM_FALLTHROUGH;<br>
case Instruction::Sub:<br>
case Instruction::Mul:<br>
case Instruction::Shl:<br>
@@ -147,7 +147,8 @@ int PPCTTIImpl::getIntImmCost(unsigned O<br>
case Instruction::ICmp:<br>
UnsignedFree = true;<br>
ImmIdx = 1;<br>
- // Fallthrough... (zero comparisons can use record-form instructions)<br>
+ // Zero comparisons can use record-form instructions.<br>
+ LLVM_FALLTHROUGH;<br>
case Instruction::Select:<br>
ZeroFree = true;<br>
break;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Aug 17 00:10:15 2016<br>
@@ -182,18 +182,18 @@ getX86ConditionCode(CmpInst::Predicate P<br>
default: break;<br>
// Floating-point Predicates<br>
case CmpInst::FCMP_UEQ: CC = X86::COND_E; break;<br>
- case CmpInst::FCMP_OLT: NeedSwap = true; // fall-through<br>
+ case CmpInst::FCMP_OLT: NeedSwap = true; LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_OGT: CC = X86::COND_A; break;<br>
- case CmpInst::FCMP_OLE: NeedSwap = true; // fall-through<br>
+ case CmpInst::FCMP_OLE: NeedSwap = true; LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_OGE: CC = X86::COND_AE; break;<br>
- case CmpInst::FCMP_UGT: NeedSwap = true; // fall-through<br>
+ case CmpInst::FCMP_UGT: NeedSwap = true; LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_ULT: CC = X86::COND_B; break;<br>
- case CmpInst::FCMP_UGE: NeedSwap = true; // fall-through<br>
+ case CmpInst::FCMP_UGE: NeedSwap = true; LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_ULE: CC = X86::COND_BE; break;<br>
case CmpInst::FCMP_ONE: CC = X86::COND_NE; break;<br>
case CmpInst::FCMP_UNO: CC = X86::COND_P; break;<br>
case CmpInst::FCMP_ORD: CC = X86::COND_NP; break;<br>
- case CmpInst::FCMP_OEQ: // fall-through<br>
+ case CmpInst::FCMP_OEQ: LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_UNE: CC = X86::COND_INVALID; break;<br>
<br>
// Integer Predicates<br>
@@ -229,15 +229,15 @@ getX86SSEConditionCode(CmpInst::Predicat<br>
switch (Predicate) {<br>
default: llvm_unreachable("Unexpected predicate");<br>
case CmpInst::FCMP_OEQ: CC = 0; break;<br>
- case CmpInst::FCMP_OGT: NeedSwap = true; // fall-through<br>
+ case CmpInst::FCMP_OGT: NeedSwap = true; LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_OLT: CC = 1; break;<br>
- case CmpInst::FCMP_OGE: NeedSwap = true; // fall-through<br>
+ case CmpInst::FCMP_OGE: NeedSwap = true; LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_OLE: CC = 2; break;<br>
case CmpInst::FCMP_UNO: CC = 3; break;<br>
case CmpInst::FCMP_UNE: CC = 4; break;<br>
- case CmpInst::FCMP_ULE: NeedSwap = true; // fall-through<br>
+ case CmpInst::FCMP_ULE: NeedSwap = true; LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_UGE: CC = 5; break;<br>
- case CmpInst::FCMP_ULT: NeedSwap = true; // fall-through<br>
+ case CmpInst::FCMP_ULT: NeedSwap = true; LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_UGT: CC = 6; break;<br>
case CmpInst::FCMP_ORD: CC = 7; break;<br>
case CmpInst::FCMP_UEQ:<br>
@@ -518,8 +518,8 @@ bool X86FastISel::X86FastEmitStore(EVT V<br>
TII.get(X86::AND8ri), AndResult)<br>
.addReg(ValReg, getKillRegState(ValIsKill)).addImm(1);<br>
ValReg = AndResult;<br>
+ LLVM_FALLTHROUGH; // handle i1 as i8.<br>
}<br>
- // FALLTHROUGH, handling i1 as i8.<br>
case MVT::i8: Opc = X86::MOV8mr; break;<br>
case MVT::i16: Opc = X86::MOV16mr; break;<br>
case MVT::i32:<br>
@@ -659,7 +659,9 @@ bool X86FastISel::X86FastEmitStore(EVT V<br>
bool Signed = true;<br>
switch (VT.getSimpleVT().SimpleTy) {<br>
default: break;<br>
- case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.<br>
+ case MVT::i1:<br>
+ Signed = false;<br>
+ LLVM_FALLTHROUGH; // Handle as i8.<br>
case MVT::i8: Opc = X86::MOV8mi; break;<br>
case MVT::i16: Opc = X86::MOV16mi; break;<br>
case MVT::i32: Opc = X86::MOV32mi; break;<br>
@@ -1601,7 +1603,8 @@ bool X86FastISel::X86SelectBranch(const<br>
switch (Predicate) {<br>
default: break;<br>
case CmpInst::FCMP_OEQ:<br>
- std::swap(TrueMBB, FalseMBB); // fall-through<br>
+ std::swap(TrueMBB, FalseMBB);<br>
+ LLVM_FALLTHROUGH;<br>
case CmpInst::FCMP_UNE:<br>
NeedExtraBranch = true;<br>
Predicate = CmpInst::FCMP_ONE;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Aug 17 00:10:15 2016<br>
@@ -2700,7 +2700,7 @@ SelectInlineAsmMemoryOperand(const SDVal<br>
case InlineAsm::Constraint_i:<br>
// FIXME: It seems strange that 'i' is needed here since it's supposed to<br>
// be an immediate and not a memory constraint.<br>
- // Fallthrough.<br>
+ LLVM_FALLTHROUGH;<br>
case InlineAsm::Constraint_o: // offsetable ??<br>
case InlineAsm::Constraint_v: // not offsetable ??<br>
case InlineAsm::Constraint_m: // memory<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Aug 17 00:10:15 2016<br>
@@ -7567,7 +7567,7 @@ static SDValue lowerVectorShuffleAsBlend<br>
case MVT::v4i64:<br>
case MVT::v8i32:<br>
assert(Subtarget.hasAVX2() && "256-bit integer blends require AVX2!");<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case MVT::v2i64:<br>
case MVT::v4i32:<br>
// If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into<br>
@@ -7583,7 +7583,7 @@ static SDValue lowerVectorShuffleAsBlend<br>
VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,<br>
DAG.getConstant(BlendMask, DL, MVT::i8)));<br>
}<br>
- // FALLTHROUGH<br>
+ LLVM_FALLTHROUGH;<br>
case MVT::v8i16: {<br>
// For integer shuffles we need to expand the mask and cast the inputs to<br>
// v8i16s prior to blending.<br>
@@ -7609,8 +7609,8 @@ static SDValue lowerVectorShuffleAsBlend<br>
return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,<br>
DAG.getConstant(BlendMask, DL, MVT::i8));<br>
}<br>
+ LLVM_FALLTHROUGH;<br>
}<br>
- // FALLTHROUGH<br>
case MVT::v16i8:<br>
case MVT::v32i8: {<br>
assert((VT.is128BitVector() || Subtarget.hasAVX2()) &&<br>
@@ -15383,19 +15383,19 @@ static int translateX86FSETCC(ISD::CondC<br>
case ISD::SETOEQ:<br>
case ISD::SETEQ: SSECC = 0; break;<br>
case ISD::SETOGT:<br>
- case ISD::SETGT: Swap = true; // Fallthrough<br>
+ case ISD::SETGT: Swap = true; LLVM_FALLTHROUGH;<br>
case ISD::SETLT:<br>
case ISD::SETOLT: SSECC = 1; break;<br>
case ISD::SETOGE:<br>
- case ISD::SETGE: Swap = true; // Fallthrough<br>
+ case ISD::SETGE: Swap = true; LLVM_FALLTHROUGH;<br>
case ISD::SETLE:<br>
case ISD::SETOLE: SSECC = 2; break;<br>
case ISD::SETUO: SSECC = 3; break;<br>
case ISD::SETUNE:<br>
case ISD::SETNE: SSECC = 4; break;<br>
- case ISD::SETULE: Swap = true; // Fallthrough<br>
+ case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH;<br>
case ISD::SETUGE: SSECC = 5; break;<br>
- case ISD::SETULT: Swap = true; // Fallthrough<br>
+ case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH;<br>
case ISD::SETUGT: SSECC = 6; break;<br>
case ISD::SETO: SSECC = 7; break;<br>
case ISD::SETUEQ:<br>
@@ -15501,12 +15501,12 @@ static SDValue LowerIntVSETCC_AVX512(SDV<br>
case ISD::SETNE: SSECC = 4; break;<br>
case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;<br>
case ISD::SETUGT: SSECC = 6; Unsigned = true; break;<br>
- case ISD::SETLT: Swap = true; //fall-through<br>
+ case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;<br>
case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;<br>
case ISD::SETULT: SSECC = 1; Unsigned = true; break;<br>
case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT<br>
case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap<br>
- case ISD::SETULE: Unsigned = true; //fall-through<br>
+ case ISD::SETULE: Unsigned = true; LLVM_FALLTHROUGH;<br>
case ISD::SETLE: SSECC = 2; break;<br>
}<br>
<br>
@@ -18267,7 +18267,8 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
case Intrinsic::x86_avx_vtestz_pd:<br>
case Intrinsic::x86_avx_vtestz_ps_256:<br>
case Intrinsic::x86_avx_vtestz_pd_256:<br>
- IsTestPacked = true; // Fallthrough<br>
+ IsTestPacked = true;<br>
+ LLVM_FALLTHROUGH;<br>
case Intrinsic::x86_sse41_ptestz:<br>
case Intrinsic::x86_avx_ptestz_256:<br>
// ZF = 1<br>
@@ -18277,7 +18278,8 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
case Intrinsic::x86_avx_vtestc_pd:<br>
case Intrinsic::x86_avx_vtestc_ps_256:<br>
case Intrinsic::x86_avx_vtestc_pd_256:<br>
- IsTestPacked = true; // Fallthrough<br>
+ IsTestPacked = true;<br>
+ LLVM_FALLTHROUGH;<br>
case Intrinsic::x86_sse41_ptestc:<br>
case Intrinsic::x86_avx_ptestc_256:<br>
// CF = 1<br>
@@ -18287,7 +18289,8 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
case Intrinsic::x86_avx_vtestnzc_pd:<br>
case Intrinsic::x86_avx_vtestnzc_ps_256:<br>
case Intrinsic::x86_avx_vtestnzc_pd_256:<br>
- IsTestPacked = true; // Fallthrough<br>
+ IsTestPacked = true;<br>
+ LLVM_FALLTHROUGH;<br>
case Intrinsic::x86_sse41_ptestnzc:<br>
case Intrinsic::x86_avx_ptestnzc_256:<br>
// ZF and CF = 0<br>
@@ -24759,7 +24762,7 @@ void X86TargetLowering::computeKnownBits<br>
// These nodes' second result is a boolean.<br>
if (Op.getResNo() == 0)<br>
break;<br>
- // Fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case X86ISD::SETCC:<br>
KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);<br>
break;<br>
@@ -25946,7 +25949,7 @@ combineRedundantDWordShuffle(SDValue N,<br>
<br>
Chain.push_back(V);<br>
<br>
- // Fallthrough!<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::BITCAST:<br>
V = V.getOperand(0);<br>
continue;<br>
@@ -27705,7 +27708,7 @@ static bool checkBoolTestAndOrSetCCCombi<br>
case ISD::AND:<br>
case X86ISD::AND:<br>
isAnd = true;<br>
- // fallthru<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::OR:<br>
case X86ISD::OR:<br>
SetCC0 = Cond->getOperand(0);<br>
@@ -31675,7 +31678,7 @@ bool X86TargetLowering::IsDesirableToPro<br>
case ISD::OR:<br>
case ISD::XOR:<br>
Commute = true;<br>
- // fallthrough<br>
+ LLVM_FALLTHROUGH;<br>
case ISD::SUB: {<br>
SDValue N0 = Op.getOperand(0);<br>
SDValue N1 = Op.getOperand(1);<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Aug 17 00:10:15 2016<br>
@@ -151,13 +151,14 @@ X86RegisterInfo::getLargestLegalSuperCla<br>
// If VLX isn't support we shouldn't inflate to these classes.<br>
if (!Subtarget.hasVLX())<br>
break;<br>
- // Fallthrough. The VLX check above passed, AVX512 check below will pass.<br>
+ // The VLX check above passed, AVX512 check below will pass.<br>
+ LLVM_FALLTHROUGH;<br>
case X86::VR128XRegClassID:<br>
case X86::VR256XRegClassID:<br>
// If AVX-512 isn't support we shouldn't inflate to these classes.<br>
if (!Subtarget.hasAVX512())<br>
break;<br>
- // Fallthrough.<br>
+ LLVM_FALLTHROUGH;<br>
case X86::GR8RegClassID:<br>
case X86::GR16RegClassID:<br>
case X86::GR32RegClassID:<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp?rev=278902&r1=278901&r2=278902&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp Wed Aug 17 00:10:15 2016<br>
@@ -1413,7 +1413,7 @@ int X86TTIImpl::getIntImmCost(unsigned O<br>
// immediates here as the normal path expects bit 31 to be sign extended.<br>
if (Idx == 1 && Imm.getBitWidth() == 64 && isUInt<32</blockquote></div></div></blockquote></div></div>