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Hi,
<div class=""><br class="">
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<div class="">Surprised I didn’t get failmail about this - is it because WebAssembly is an experimental target?</div>
<div class=""><br class="">
</div>
<div class="">Test update is probably the right thing to do - when people write loops manually in IR they tend to write them head-tested, which would trigger this heuristic change. It’s simply changing from using a post-inc value to a pre-inc value which decreases
register pressure and is an all-round good thing, but does cause some test churn.</div>
<div class=""><br class="">
</div>
<div class="">Again, I’m worried that I didn’t notice this… :/</div>
<div class=""><br class="">
</div>
<div class="">Cheers,</div>
<div class=""><br class="">
</div>
<div class="">James<br class="">
<div>
<blockquote type="cite" class="">
<div class="">On 15 Aug 2016, at 19:42, Reid Kleckner <<a href="mailto:rnk@google.com" class="">rnk@google.com</a>> wrote:</div>
<br class="Apple-interchange-newline">
<div class="">
<div dir="ltr" class="">This broke test/CodeGen/WebAssembly/cfg-stackify.ll.
<div class=""><br class="">
</div>
<div class="">Is this correct behavior? Should I update the test?</div>
</div>
<div class="gmail_extra"><br class="">
<div class="gmail_quote">On Mon, Aug 15, 2016 at 12:53 AM, James Molloy via llvm-commits
<span dir="ltr" class=""><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>></span> wrote:<br class="">
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: jamesm<br class="">
Date: Mon Aug 15 02:53:03 2016<br class="">
New Revision: 278658<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=278658&view=rev" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project?rev=278658&view=rev</a><br class="">
Log:<br class="">
[LSR] Don't try and create post-inc expressions on non-rotated loops<br class="">
<br class="">
If a loop is not rotated (for example when optimizing for size), the latch is not the backedge. If we promote an expression to post-inc form, we not only increase register pressure and add a COPY for that IV expression but for all IVs!<br class="">
<br class="">
Motivating testcase:<br class="">
<br class="">
void f(float *a, float *b, float *c, int n) {<br class="">
while (n-- > 0)<br class="">
*c++ = *a++ + *b++;<br class="">
}<br class="">
<br class="">
It's imperative that the pointer increments be located in the latch block and not the header block; if not, we cannot use post-increment loads and stores and we have to keep both the post-inc and pre-inc values around until the end of the latch which bloats
register usage.<br class="">
<br class="">
Added:<br class="">
llvm/trunk/test/Transforms/<wbr class="">LoopStrengthReduce/post-inc-<wbr class="">optsize.ll<br class="">
Modified:<br class="">
llvm/trunk/lib/Transforms/<wbr class="">Scalar/LoopStrengthReduce.cpp<br class="">
llvm/trunk/test/CodeGen/<wbr class="">AMDGPU/wqm.ll<br class="">
llvm/trunk/test/CodeGen/ARM/<wbr class="">2011-03-23-PeepholeBug.ll<br class="">
llvm/trunk/test/CodeGen/<wbr class="">Hexagon/hwloop-crit-edge.ll<br class="">
llvm/trunk/test/CodeGen/<wbr class="">Hexagon/hwloop-loop1.ll<br class="">
llvm/trunk/test/CodeGen/X86/<wbr class="">lsr-loop-exit-cond.ll<br class="">
<br class="">
Modified: llvm/trunk/lib/Transforms/<wbr class="">Scalar/LoopStrengthReduce.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=278658&r1=278657&r2=278658&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/lib/<wbr class="">Transforms/Scalar/<wbr class="">LoopStrengthReduce.cpp?rev=<wbr class="">278658&r1=278657&r2=278658&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/lib/Transforms/<wbr class="">Scalar/LoopStrengthReduce.cpp (original)<br class="">
+++ llvm/trunk/lib/Transforms/<wbr class="">Scalar/LoopStrengthReduce.cpp Mon Aug 15 02:53:03 2016<br class="">
@@ -2069,10 +2069,30 @@ void<br class="">
LSRInstance::<wbr class="">OptimizeLoopTermCond() {<br class="">
SmallPtrSet<Instruction *, 4> PostIncs;<br class="">
<br class="">
+ // We need a different set of heuristics for rotated and non-rotated loops.<br class="">
+ // If a loop is rotated then the latch is also the backedge, so inserting<br class="">
+ // post-inc expressions just before the latch is ideal. To reduce live ranges<br class="">
+ // it also makes sense to rewrite terminating conditions to use post-inc<br class="">
+ // expressions.<br class="">
+ //<br class="">
+ // If the loop is not rotated then the latch is not a backedge; the latch<br class="">
+ // check is done in the loop head. Adding post-inc expressions before the<br class="">
+ // latch will cause overlapping live-ranges of pre-inc and post-inc expressions<br class="">
+ // in the loop body. In this case we do *not* want to use post-inc expressions<br class="">
+ // in the latch check, and we want to insert post-inc expressions before<br class="">
+ // the backedge.<br class="">
BasicBlock *LatchBlock = L->getLoopLatch();<br class="">
SmallVector<BasicBlock*, 8> ExitingBlocks;<br class="">
L->getExitingBlocks(<wbr class="">ExitingBlocks);<br class="">
+ if (llvm::all_of(ExitingBlocks, [&LatchBlock](const BasicBlock *BB) {<br class="">
+ return LatchBlock != BB;<br class="">
+ })) {<br class="">
+ // The backedge doesn't exit the loop; treat this as a head-tested loop.<br class="">
+ IVIncInsertPos = LatchBlock->getTerminator();<br class="">
+ return;<br class="">
+ }<br class="">
<br class="">
+ // Otherwise treat this as a rotated loop.<br class="">
for (BasicBlock *ExitingBlock : ExitingBlocks) {<br class="">
<br class="">
// Get the terminating condition for the loop if possible. If we<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/<wbr class="">AMDGPU/wqm.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/wqm.ll?rev=278658&r1=278657&r2=278658&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/AMDGPU/wqm.ll?rev=<wbr class="">278658&r1=278657&r2=278658&<wbr class="">view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/<wbr class="">AMDGPU/wqm.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/<wbr class="">AMDGPU/wqm.ll Mon Aug 15 02:53:03 2016<br class="">
@@ -343,11 +343,12 @@ main_body:<br class="">
; CHECK: s_and_b64 exec, exec, [[LIVE]]<br class="">
; CHECK: image_store<br class="">
; CHECK: s_wqm_b64 exec, exec<br class="">
-; CHECK: v_mov_b32_e32 [[CTR:v[0-9]+]], -2<br class="">
+; CHECK: v_mov_b32_e32 [[CTR:v[0-9]+]], 0<br class="">
; CHECK: s_branch [[LOOPHDR:BB[0-9]+_[0-9]+]]<br class="">
<br class="">
-; CHECK: [[LOOPHDR]]: ; %loop<br class="">
; CHECK: v_add_i32_e32 [[CTR]], vcc, 2, [[CTR]]<br class="">
+<br class="">
+; CHECK: [[LOOPHDR]]: ; %loop<br class="">
; CHECK: v_cmp_lt_i32_e32 vcc, 7, [[CTR]]<br class="">
; CHECK: s_cbranch_vccz<br class="">
; CHECK: ; %break<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/ARM/<wbr class="">2011-03-23-PeepholeBug.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll?rev=278658&r1=278657&r2=278658&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/ARM/2011-03-23-<wbr class="">PeepholeBug.ll?rev=278658&r1=<wbr class="">278657&r2=278658&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/ARM/<wbr class="">2011-03-23-PeepholeBug.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/ARM/<wbr class="">2011-03-23-PeepholeBug.ll Mon Aug 15 02:53:03 2016<br class="">
@@ -18,13 +18,14 @@ bb:<br class="">
br i1 %1, label %bb3, label %bb1<br class="">
<br class="">
bb1: ; preds = %bb<br class="">
+; CHECK: bb1<br class="">
+; CHECK: subs [[REG:r[0-9]+]], #1<br class="">
%tmp = tail call i32 @puts() nounwind<br class="">
%indvar.next = add i32 %indvar, 1<br class="">
br label %bb2<br class="">
<br class="">
bb2: ; preds = %bb1, %entry<br class="">
; CHECK: bb2<br class="">
-; CHECK: subs [[REG:r[0-9]+]], #1<br class="">
; CHECK: cmp [[REG]], #0<br class="">
; CHECK: ble<br class="">
%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/<wbr class="">Hexagon/hwloop-crit-edge.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop-crit-edge.ll?rev=278658&r1=278657&r2=278658&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/Hexagon/hwloop-crit-<wbr class="">edge.ll?rev=278658&r1=278657&<wbr class="">r2=278658&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/<wbr class="">Hexagon/hwloop-crit-edge.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/<wbr class="">Hexagon/hwloop-crit-edge.ll Mon Aug 15 02:53:03 2016<br class="">
@@ -1,4 +1,5 @@<br class="">
; RUN: llc -O3 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s<br class="">
+; XFAIL: *<br class="">
;<br class="">
; Generate hardware loop when loop 'latch' block is different<br class="">
; from the loop 'exiting' block.<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/<wbr class="">Hexagon/hwloop-loop1.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop-loop1.ll?rev=278658&r1=278657&r2=278658&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/Hexagon/hwloop-loop1.<wbr class="">ll?rev=278658&r1=278657&r2=<wbr class="">278658&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/<wbr class="">Hexagon/hwloop-loop1.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/<wbr class="">Hexagon/hwloop-loop1.ll Mon Aug 15 02:53:03 2016<br class="">
@@ -2,8 +2,6 @@<br class="">
;<br class="">
; Generate loop1 instruction for double loop sequence.<br class="">
<br class="">
-; CHECK: loop0(.LBB{{.}}_{{.}}, #100)<br class="">
-; CHECK: endloop0<br class="">
; CHECK: loop1(.LBB{{.}}_{{.}}, #100)<br class="">
; CHECK: loop0(.LBB{{.}}_{{.}}, #100)<br class="">
; CHECK: endloop0<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/<wbr class="">lsr-loop-exit-cond.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll?rev=278658&r1=278657&r2=278658&view=diff" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">CodeGen/X86/lsr-loop-exit-<wbr class="">cond.ll?rev=278658&r1=278657&<wbr class="">r2=278658&view=diff</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/CodeGen/X86/<wbr class="">lsr-loop-exit-cond.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/<wbr class="">lsr-loop-exit-cond.ll Mon Aug 15 02:53:03 2016<br class="">
@@ -3,12 +3,12 @@<br class="">
<br class="">
; CHECK-LABEL: t:<br class="">
; CHECK: movl (%r9,%rax,4), %e{{..}}<br class="">
-; CHECK-NEXT: decq<br class="">
+; CHECK-NEXT: testq<br class="">
; CHECK-NEXT: jne<br class="">
<br class="">
; ATOM-LABEL: t:<br class="">
; ATOM: movl (%r9,%r{{.+}},4), %e{{..}}<br class="">
-; ATOM-NEXT: decq<br class="">
+; ATOM-NEXT: testq<br class="">
; ATOM-NEXT: jne<br class="">
<br class="">
@Te0 = external global [256 x i32] ; <[256 x i32]*> [#uses=5]<br class="">
<br class="">
Added: llvm/trunk/test/Transforms/<wbr class="">LoopStrengthReduce/post-inc-<wbr class="">optsize.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-optsize.ll?rev=278658&view=auto" rel="noreferrer" target="_blank" class="">
http://llvm.org/viewvc/llvm-<wbr class="">project/llvm/trunk/test/<wbr class="">Transforms/LoopStrengthReduce/<wbr class="">post-inc-optsize.ll?rev=<wbr class="">278658&view=auto</a><br class="">
==============================<wbr class="">==============================<wbr class="">==================<br class="">
--- llvm/trunk/test/Transforms/<wbr class="">LoopStrengthReduce/post-inc-<wbr class="">optsize.ll (added)<br class="">
+++ llvm/trunk/test/Transforms/<wbr class="">LoopStrengthReduce/post-inc-<wbr class="">optsize.ll Mon Aug 15 02:53:03 2016<br class="">
@@ -0,0 +1,43 @@<br class="">
+; RUN: opt < %s -loop-reduce -S | FileCheck %s<br class="">
+<br class="">
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:<wbr class="">128-a:0:32-n32-S64"<br class="">
+target triple = "thumbv7m-arm-none-eabi"<br class="">
+<br class="">
+; Check that the IV updates (incdec.ptr{,1,2}) are kept in the latch block<br class="">
+; and not moved to the header/exiting block. Inserting them in the header<br class="">
+; doubles register pressure and adds moves.<br class="">
+<br class="">
+; CHECK-LABEL: @f<br class="">
+; CHECK: while.cond:<br class="">
+; CHECK: icmp sgt i32 %n.addr.0, 0<br class="">
+; CHECK: while.body:<br class="">
+; CHECK: incdec.ptr =<br class="">
+; CHECK: incdec.ptr1 =<br class="">
+; CHECK: incdec.ptr2 =<br class="">
+; CHECK: dec =<br class="">
+define void @f(float* nocapture readonly %a, float* nocapture readonly %b, float* nocapture %c, i32 %n) {<br class="">
+entry:<br class="">
+ br label %while.cond<br class="">
+<br class="">
+while.cond: ; preds = %while.body, %entry<br class="">
+ %a.addr.0 = phi float* [ %a, %entry ], [ %incdec.ptr, %while.body ]<br class="">
+ %b.addr.0 = phi float* [ %b, %entry ], [ %incdec.ptr1, %while.body ]<br class="">
+ %c.addr.0 = phi float* [ %c, %entry ], [ %incdec.ptr2, %while.body ]<br class="">
+ %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %while.body ]<br class="">
+ %cmp = icmp sgt i32 %n.addr.0, 0<br class="">
+ br i1 %cmp, label %while.body, label %while.end<br class="">
+<br class="">
+while.body: ; preds = %while.cond<br class="">
+ %incdec.ptr = getelementptr inbounds float, float* %a.addr.0, i32 1<br class="">
+ %tmp = load float, float* %a.addr.0, align 4<br class="">
+ %incdec.ptr1 = getelementptr inbounds float, float* %b.addr.0, i32 1<br class="">
+ %tmp1 = load float, float* %b.addr.0, align 4<br class="">
+ %add = fadd float %tmp, %tmp1<br class="">
+ %incdec.ptr2 = getelementptr inbounds float, float* %c.addr.0, i32 1<br class="">
+ store float %add, float* %c.addr.0, align 4<br class="">
+ %dec = add nsw i32 %n.addr.0, -1<br class="">
+ br label %while.cond<br class="">
+<br class="">
+while.end: ; preds = %while.cond<br class="">
+ ret void<br class="">
+}<br class="">
<br class="">
<br class="">
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</blockquote>
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