<div dir="ltr"><div><div><div>Hi Hans,<br><br></div>Simon fixed all the issues at revision 276740.<br><a href="http://llvm.org/viewvc/llvm-project?view=revision&revision=276740">http://llvm.org/viewvc/llvm-project?view=revision&revision=276740</a><br><br></div>Tablegen definitions for instructions Int_VCVTSD2SSrm and Int_CVTSD2SSrm had the wrong encoding format.<br></div><div>Before revision 276740, those instructions were defined with encoding format `MRMSrcReg` instead of `MRMSrcMem`. This was causing problems in the code emitter since the wrong logic was used to encode the memory operand of those instructions.<br><br>Basically, if we decide to integrate 275981, then we also have to integrate revision 276740.<br><br></div><div>-Andrea<br></div><div><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jul 28, 2016 at 12:53 AM, Hans Wennborg <span dir="ltr"><<a href="mailto:hans@chromium.org" target="_blank">hans@chromium.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">I'm holding off merging since there seems to be issues here. Has there<br>
been any progress?<br>
<br>
Thanks,<br>
Hans<br>
<div class="HOEnZb"><div class="h5"><br>
On Mon, Jul 25, 2016 at 6:06 AM, Andrea Di Biagio<br>
<<a href="mailto:andrea.dibiagio@gmail.com">andrea.dibiagio@gmail.com</a>> wrote:<br>
> For the record: the clang counterpart (revision 275981) introduced a<br>
> regression.<br>
><br>
> After revision 275981 the compiler fails to build this test:<br>
><br>
> ///////<br>
> target triple = "x86_64-unknown-unknown"<br>
><br>
> define <4 x float> @test(<4 x float> %a, <2 x double>* nocapture readonly<br>
> %b) {<br>
> entry:<br>
> %0 = load <2 x double>, <2 x double>* %b, align 16<br>
> %1 = tail call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a, <2 x<br>
> double> %0)<br>
> ret <4 x float> %1<br>
> }<br>
><br>
> declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>)<br>
> ////////<br>
><br>
>> llc test.ll -o - -mattr=+avx<br>
><br>
> in X86MCCodeEmitter::encodeInstruction<br>
> Cannot encode all operands of: <MCInst 1073 <MCOperand Reg:126> <MCOperand<br>
> Reg:126> <MCOperand Reg:39> <MCOperand Imm:1> <MCOperand Reg:0> <MCOperand<br>
> Imm:0> <MCOperand Reg:0>><br>
><br>
> I have already commented on the clang thread for revision 275981.<br>
><br>
> -Andrea<br>
><br>
> On Sat, Jul 23, 2016 at 5:15 PM, Nadav Rotem via llvm-commits<br>
> <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
>><br>
>> LGTM.<br>
>><br>
>><br>
>> > On Jul 22, 2016, at 6:14 AM, Hans Wennborg <<a href="mailto:hans@chromium.org">hans@chromium.org</a>> wrote:<br>
>> ><br>
>> > Nadav: you're the X86 owner. What do you think?<br>
>> ><br>
>> >> On Thu, Jul 21, 2016 at 5:41 PM, Eli Friedman <<a href="mailto:eli.friedman@gmail.com">eli.friedman@gmail.com</a>><br>
>> >> wrote:<br>
>> >> Nominating for backport to 3.9, so the intrinsics in question remain<br>
>> >> available.<br>
>> >><br>
>> >> -Eli<br>
>> >><br>
>> >><br>
>> >> On Tue, Jul 19, 2016 at 8:07 AM, Simon Pilgrim via llvm-commits<br>
>> >> <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br>
>> >>><br>
>> >>> Author: rksimon<br>
>> >>> Date: Tue Jul 19 10:07:43 2016<br>
>> >>> New Revision: 275981<br>
>> >>><br>
>> >>> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=275981&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=275981&view=rev</a><br>
>> >>> Log:<br>
>> >>> [X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of<br>
>> >>> using<br>
>> >>> generic IR<br>
>> >>><br>
>> >>> D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and<br>
>> >>> VCVTTPD2DQ<br>
>> >>> truncating conversions with generic IR instead.<br>
>> >>><br>
>> >>> It turns out that the behaviour of these intrinsics is different<br>
>> >>> enough<br>
>> >>> from generic IR that this will cause problems, INF/NAN/out of range<br>
>> >>> values<br>
>> >>> are guaranteed to result in a 0x80000000 value - which plays havoc<br>
>> >>> with<br>
>> >>> constant folding which converts them to either zero or UNDEF. This is<br>
>> >>> also<br>
>> >>> an issue with the scalar implementations (which were already generic<br>
>> >>> IR and<br>
>> >>> what I was trying to match).<br>
>> >>><br>
>> >>> This patch changes both scalar and packed versions back to using<br>
>> >>> x86-specific builtins.<br>
>> >>><br>
>> >>> It also deals with the other scalar conversion cases that are runtime<br>
>> >>> rounding mode dependent and can have similar issues with constant<br>
>> >>> folding.<br>
>> >>><br>
>> >>> A companion clang patch is at D22105<br>
>> >>><br>
>> >>> Differential Revision: <a href="https://reviews.llvm.org/D22106" rel="noreferrer" target="_blank">https://reviews.llvm.org/D22106</a><br>
>> >>><br>
>> >>> Modified:<br>
>> >>> llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
>> >>> llvm/trunk/lib/Analysis/ConstantFolding.cpp<br>
>> >>> llvm/trunk/lib/IR/AutoUpgrade.cpp<br>
>> >>> llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
>> >>> llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll<br>
>> >>> llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll<br>
>> >>> llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
>> >>> llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll<br>
>> >>> llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll<br>
>> >>> llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll<br>
>> >>> llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll<br>
>> >>> llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll<br>
>> >>> llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
>> >>> llvm/trunk/test/Transforms/ConstProp/calls.ll<br>
>> >>><br>
>> >>> Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br>
>> >>> +++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Tue Jul 19 10:07:43<br>
>> >>> 2016<br>
>> >>> @@ -479,6 +479,8 @@ let TargetPrefix = "x86" in { // All in<br>
>> >>> Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty],<br>
>> >>> [IntrNoMem]>;<br>
>> >>> def int_x86_sse2_cvtps2dq : GCCBuiltin<"__builtin_ia32_cvtps2dq">,<br>
>> >>> Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty],<br>
>> >>> [IntrNoMem]>;<br>
>> >>> + def int_x86_sse2_cvttps2dq :<br>
>> >>> GCCBuiltin<"__builtin_ia32_cvttps2dq">,<br>
>> >>> + Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty],<br>
>> >>> [IntrNoMem]>;<br>
>> >>> def int_x86_sse2_cvtsd2si : GCCBuiltin<"__builtin_ia32_cvtsd2si">,<br>
>> >>> Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;<br>
>> >>> def int_x86_sse2_cvtsd2si64 :<br>
>> >>> GCCBuiltin<"__builtin_ia32_cvtsd2si64">,<br>
>> >>> @@ -1512,8 +1514,12 @@ let TargetPrefix = "x86" in { // All in<br>
>> >>> Intrinsic<[llvm_v4f32_ty], [llvm_v4f64_ty], [IntrNoMem]>;<br>
>> >>> def int_x86_avx_cvt_ps2dq_256 :<br>
>> >>> GCCBuiltin<"__builtin_ia32_cvtps2dq256">,<br>
>> >>> Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;<br>
>> >>> + def int_x86_avx_cvtt_pd2dq_256 :<br>
>> >>> GCCBuiltin<"__builtin_ia32_cvttpd2dq256">,<br>
>> >>> + Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;<br>
>> >>> def int_x86_avx_cvt_pd2dq_256 :<br>
>> >>> GCCBuiltin<"__builtin_ia32_cvtpd2dq256">,<br>
>> >>> Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;<br>
>> >>> + def int_x86_avx_cvtt_ps2dq_256 :<br>
>> >>> GCCBuiltin<"__builtin_ia32_cvttps2dq256">,<br>
>> >>> + Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;<br>
>> >>> }<br>
>> >>><br>
>> >>> // Vector bit test<br>
>> >>><br>
>> >>> Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)<br>
>> >>> +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Jul 19 10:07:43<br>
>> >>> 2016<br>
>> >>> @@ -1424,8 +1424,8 @@ Constant *ConstantFoldBinaryFP(double (*<br>
>> >>> /// integer type Ty is used to select how many bits are available for<br>
>> >>> the<br>
>> >>> /// result. Returns null if the conversion cannot be performed,<br>
>> >>> otherwise<br>
>> >>> /// returns the Constant value resulting from the conversion.<br>
>> >>> -Constant *ConstantFoldConvertToInt(const APFloat &Val, bool<br>
>> >>> roundTowardZero,<br>
>> >>> - Type *Ty) {<br>
>> >>> +Constant *ConstantFoldSSEConvertToInt(const APFloat &Val, bool<br>
>> >>> roundTowardZero,<br>
>> >>> + Type *Ty) {<br>
>> >>> // All of these conversion intrinsics form an integer of at most<br>
>> >>> 64bits.<br>
>> >>> unsigned ResultWidth = Ty->getIntegerBitWidth();<br>
>> >>> assert(ResultWidth <= 64 &&<br>
>> >>> @@ -1438,7 +1438,8 @@ Constant *ConstantFoldConvertToInt(const<br>
>> >>> APFloat::opStatus status = Val.convertToInteger(&UIntVal,<br>
>> >>> ResultWidth,<br>
>> >>> /*isSigned=*/true,<br>
>> >>> mode,<br>
>> >>> &isExact);<br>
>> >>> - if (status != APFloat::opOK && status != APFloat::opInexact)<br>
>> >>> + if (status != APFloat::opOK &&<br>
>> >>> + (!roundTowardZero || status != APFloat::opInexact))<br>
>> >>> return nullptr;<br>
>> >>> return ConstantInt::get(Ty, UIntVal, /*isSigned=*/true);<br>
>> >>> }<br>
>> >>> @@ -1676,17 +1677,17 @@ Constant *ConstantFoldScalarCall(StringR<br>
>> >>> case Intrinsic::x86_sse2_cvtsd2si:<br>
>> >>> case Intrinsic::x86_sse2_cvtsd2si64:<br>
>> >>> if (ConstantFP *FPOp =<br>
>> >>> -<br>
>> >>> dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))<br>
>> >>> - return ConstantFoldConvertToInt(FPOp->getValueAPF(),<br>
>> >>> - /*roundTowardZero=*/false,<br>
>> >>> Ty);<br>
>> >>> +<br>
>> >>> dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))<br>
>> >>> + return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),<br>
>> >>> +<br>
>> >>> /*roundTowardZero=*/false,<br>
>> >>> Ty);<br>
>> >>> case Intrinsic::x86_sse_cvttss2si:<br>
>> >>> case Intrinsic::x86_sse_cvttss2si64:<br>
>> >>> case Intrinsic::x86_sse2_cvttsd2si:<br>
>> >>> case Intrinsic::x86_sse2_cvttsd2si64:<br>
>> >>> if (ConstantFP *FPOp =<br>
>> >>> -<br>
>> >>> dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))<br>
>> >>> - return ConstantFoldConvertToInt(FPOp->getValueAPF(),<br>
>> >>> - /*roundTowardZero=*/true,<br>
>> >>> Ty);<br>
>> >>> +<br>
>> >>> dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))<br>
>> >>> + return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),<br>
>> >>> +<br>
>> >>> /*roundTowardZero=*/true,<br>
>> >>> Ty);<br>
>> >>> }<br>
>> >>> }<br>
>> >>><br>
>> >>><br>
>> >>> Modified: llvm/trunk/lib/IR/AutoUpgrade.cpp<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/lib/IR/AutoUpgrade.cpp (original)<br>
>> >>> +++ llvm/trunk/lib/IR/AutoUpgrade.cpp Tue Jul 19 10:07:43 2016<br>
>> >>> @@ -251,8 +251,6 @@ static bool UpgradeIntrinsicFunction1(Fu<br>
>> >>> Name == "sse2.cvtps2pd" ||<br>
>> >>> Name == "avx.cvtdq2.pd.256" ||<br>
>> >>> Name == "avx.cvt.ps2.pd.256" ||<br>
>> >>> - Name == "sse2.cvttps2dq" ||<br>
>> >>> - Name.startswith("avx.cvtt.") ||<br>
>> >>> Name.startswith("avx.vinsertf128.") ||<br>
>> >>> Name == "avx2.vinserti128" ||<br>
>> >>> Name.startswith("avx.vextractf128.") ||<br>
>> >>> @@ -712,12 +710,6 @@ void llvm::UpgradeIntrinsicCall(CallInst<br>
>> >>> Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd");<br>
>> >>> else<br>
>> >>> Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd");<br>
>> >>> - } else if (IsX86 && (Name == "sse2.cvttps2dq" ||<br>
>> >>> - Name.startswith("avx.cvtt."))) {<br>
>> >>> - // Truncation (round to zero) float/double to i32 vector<br>
>> >>> conversion.<br>
>> >>> - Value *Src = CI->getArgOperand(0);<br>
>> >>> - VectorType *DstTy = cast<VectorType>(CI->getType());<br>
>> >>> - Rep = Builder.CreateFPToSI(Src, DstTy, "cvtt");<br>
>> >>> } else if (IsX86 && Name.startswith("sse4a.movnt.")) {<br>
>> >>> Module *M = F->getParent();<br>
>> >>> SmallVector<Metadata *, 1> Elts;<br>
>> >>><br>
>> >>> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
>> >>> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 19 10:07:43 2016<br>
>> >>> @@ -2009,24 +2009,35 @@ def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (<br>
>> >>> // SSE2 packed instructions with XS prefix<br>
>> >>> def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> >>> VR128:$src),<br>
>> >>> "cvttps2dq\t{$src, $dst|$dst, $src}",<br>
>> >>> - [], IIC_SSE_CVT_PS_RR>, VEX,<br>
>> >>> Sched<[WriteCvtF2I]>;<br>
>> >>> + [(set VR128:$dst,<br>
>> >>> + (int_x86_sse2_cvttps2dq VR128:$src))],<br>
>> >>> + IIC_SSE_CVT_PS_RR>, VEX,<br>
>> >>> Sched<[WriteCvtF2I]>;<br>
>> >>> def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> >>> f128mem:$src),<br>
>> >>> "cvttps2dq\t{$src, $dst|$dst, $src}",<br>
>> >>> - [], IIC_SSE_CVT_PS_RM>, VEX,<br>
>> >>> Sched<[WriteCvtF2ILd]>;<br>
>> >>> + [(set VR128:$dst, (int_x86_sse2_cvttps2dq<br>
>> >>> + (loadv4f32 addr:$src)))],<br>
>> >>> + IIC_SSE_CVT_PS_RM>, VEX,<br>
>> >>> Sched<[WriteCvtF2ILd]>;<br>
>> >>> def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins<br>
>> >>> VR256:$src),<br>
>> >>> "cvttps2dq\t{$src, $dst|$dst, $src}",<br>
>> >>> - [], IIC_SSE_CVT_PS_RR>, VEX, VEX_L,<br>
>> >>> Sched<[WriteCvtF2I]>;<br>
>> >>> + [(set VR256:$dst,<br>
>> >>> + (int_x86_avx_cvtt_ps2dq_256<br>
>> >>> VR256:$src))],<br>
>> >>> + IIC_SSE_CVT_PS_RR>, VEX, VEX_L,<br>
>> >>> Sched<[WriteCvtF2I]>;<br>
>> >>> def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins<br>
>> >>> f256mem:$src),<br>
>> >>> "cvttps2dq\t{$src, $dst|$dst, $src}",<br>
>> >>> - [], IIC_SSE_CVT_PS_RM>, VEX, VEX_L,<br>
>> >>> + [(set VR256:$dst,<br>
>> >>> (int_x86_avx_cvtt_ps2dq_256<br>
>> >>> + (loadv8f32<br>
>> >>> addr:$src)))],<br>
>> >>> + IIC_SSE_CVT_PS_RM>, VEX, VEX_L,<br>
>> >>> Sched<[WriteCvtF2ILd]>;<br>
>> >>><br>
>> >>> def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> >>> VR128:$src),<br>
>> >>> "cvttps2dq\t{$src, $dst|$dst, $src}",<br>
>> >>> - [], IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;<br>
>> >>> + [(set VR128:$dst, (int_x86_sse2_cvttps2dq<br>
>> >>> VR128:$src))],<br>
>> >>> + IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;<br>
>> >>> def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> >>> f128mem:$src),<br>
>> >>> "cvttps2dq\t{$src, $dst|$dst, $src}",<br>
>> >>> - [], IIC_SSE_CVT_PS_RM>,<br>
>> >>> Sched<[WriteCvtF2ILd]>;<br>
>> >>> + [(set VR128:$dst,<br>
>> >>> + (int_x86_sse2_cvttps2dq (memopv4f32<br>
>> >>> addr:$src)))],<br>
>> >>> + IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;<br>
>> >>><br>
>> >>> let Predicates = [HasAVX] in {<br>
>> >>> def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),<br>
>> >>> @@ -2096,10 +2107,14 @@ def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem<br>
>> >>> // YMM only<br>
>> >>> def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins<br>
>> >>> VR256:$src),<br>
>> >>> "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",<br>
>> >>> - [], IIC_SSE_CVT_PD_RR>, VEX, VEX_L,<br>
>> >>> Sched<[WriteCvtF2I]>;<br>
>> >>> + [(set VR128:$dst,<br>
>> >>> + (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],<br>
>> >>> + IIC_SSE_CVT_PD_RR>, VEX, VEX_L,<br>
>> >>> Sched<[WriteCvtF2I]>;<br>
>> >>> def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins<br>
>> >>> f256mem:$src),<br>
>> >>> "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",<br>
>> >>> - [], IIC_SSE_CVT_PD_RM>, VEX, VEX_L,<br>
>> >>> Sched<[WriteCvtF2ILd]>;<br>
>> >>> + [(set VR128:$dst,<br>
>> >>> + (int_x86_avx_cvtt_pd2dq_256 (loadv4f64<br>
>> >>> addr:$src)))],<br>
>> >>> + IIC_SSE_CVT_PD_RM>, VEX, VEX_L,<br>
>> >>> Sched<[WriteCvtF2ILd]>;<br>
>> >>> def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",<br>
>> >>> (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;<br>
>> >>><br>
>> >>><br>
>> >>> Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll (original)<br>
>> >>> +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll Tue Jul 19<br>
>> >>> 10:07:43 2016<br>
>> >>> @@ -681,10 +681,11 @@ define <2 x i64> @test_mm256_cvttpd_epi3<br>
>> >>> ; X64-NEXT: vcvttpd2dqy %ymm0, %xmm0<br>
>> >>> ; X64-NEXT: vzeroupper<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %cvt = fptosi <4 x double> %a0 to <4 x i32><br>
>> >>> + %cvt = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double><br>
>> >>> %a0)<br>
>> >>> %res = bitcast <4 x i32> %cvt to <2 x i64><br>
>> >>> ret <2 x i64> %res<br>
>> >>> }<br>
>> >>> +declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>> define <4 x i64> @test_mm256_cvttps_epi32(<8 x float> %a0) nounwind {<br>
>> >>> ; X32-LABEL: test_mm256_cvttps_epi32:<br>
>> >>> @@ -696,10 +697,11 @@ define <4 x i64> @test_mm256_cvttps_epi3<br>
>> >>> ; X64: # BB#0:<br>
>> >>> ; X64-NEXT: vcvttps2dq %ymm0, %ymm0<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %cvt = fptosi <8 x float> %a0 to <8 x i32><br>
>> >>> + %cvt = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0)<br>
>> >>> %res = bitcast <8 x i32> %cvt to <4 x i64><br>
>> >>> ret <4 x i64> %res<br>
>> >>> }<br>
>> >>> +declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>> define <4 x double> @test_mm256_div_pd(<4 x double> %a0, <4 x double><br>
>> >>> %a1) nounwind {<br>
>> >>> ; X32-LABEL: test_mm256_div_pd:<br>
>> >>><br>
>> >>> Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll<br>
>> >>> (original)<br>
>> >>> +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll Tue Jul<br>
>> >>> 19<br>
>> >>> 10:07:43 2016<br>
>> >>> @@ -359,35 +359,12 @@ define <4 x double> @test_x86_avx_cvt_ps<br>
>> >>> declare <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float>)<br>
>> >>> nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>><br>
>> >>> -define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {<br>
>> >>> -; CHECK-LABEL: test_x86_avx_cvtt_pd2dq_256:<br>
>> >>> -; CHECK: ## BB#0:<br>
>> >>> -; CHECK-NEXT: vcvttpd2dqy %ymm0, %xmm0<br>
>> >>> -; CHECK-NEXT: vzeroupper<br>
>> >>> -; CHECK-NEXT: retl<br>
>> >>> - %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double><br>
>> >>> %a0) ;<br>
>> >>> <<4 x i32>> [#uses=1]<br>
>> >>> - ret <4 x i32> %res<br>
>> >>> -}<br>
>> >>> -declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind<br>
>> >>> readnone<br>
>> >>> -<br>
>> >>> -<br>
>> >>> -define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {<br>
>> >>> -; CHECK-LABEL: test_x86_avx_cvtt_ps2dq_256:<br>
>> >>> -; CHECK: ## BB#0:<br>
>> >>> -; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0<br>
>> >>> -; CHECK-NEXT: retl<br>
>> >>> - %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0)<br>
>> >>> ;<br>
>> >>> <<8 x i32>> [#uses=1]<br>
>> >>> - ret <8 x i32> %res<br>
>> >>> -}<br>
>> >>> -declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind<br>
>> >>> readnone<br>
>> >>> -<br>
>> >>> -<br>
>> >>> define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) {<br>
>> >>> ; add operation forces the execution domain.<br>
>> >>> ; CHECK-LABEL: test_x86_sse2_storeu_dq:<br>
>> >>> ; CHECK: ## BB#0:<br>
>> >>> ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
>> >>> -; CHECK-NEXT: vpaddb LCPI34_0, %xmm0, %xmm0<br>
>> >>> +; CHECK-NEXT: vpaddb LCPI32_0, %xmm0, %xmm0<br>
>> >>> ; CHECK-NEXT: vmovdqu %xmm0, (%eax)<br>
>> >>> ; CHECK-NEXT: retl<br>
>> >>> %a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,<br>
>> >>> i8<br>
>> >>> 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1><br>
>> >>><br>
>> >>> Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)<br>
>> >>> +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Tue Jul 19<br>
>> >>> 10:07:43<br>
>> >>> 2016<br>
>> >>> @@ -3431,6 +3431,39 @@ define <8 x float> @test_x86_avx_cvtdq2_<br>
>> >>> declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>><br>
>> >>> +define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {<br>
>> >>> +; AVX-LABEL: test_x86_avx_cvtt_pd2dq_256:<br>
>> >>> +; AVX: ## BB#0:<br>
>> >>> +; AVX-NEXT: vcvttpd2dqy %ymm0, %xmm0<br>
>> >>> +; AVX-NEXT: vzeroupper<br>
>> >>> +; AVX-NEXT: retl<br>
>> >>> +;<br>
>> >>> +; AVX512VL-LABEL: test_x86_avx_cvtt_pd2dq_256:<br>
>> >>> +; AVX512VL: ## BB#0:<br>
>> >>> +; AVX512VL-NEXT: vcvttpd2dqy %ymm0, %xmm0<br>
>> >>> +; AVX512VL-NEXT: retl<br>
>> >>> + %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double><br>
>> >>> %a0) ;<br>
>> >>> <<4 x i32>> [#uses=1]<br>
>> >>> + ret <4 x i32> %res<br>
>> >>> +}<br>
>> >>> +declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind<br>
>> >>> readnone<br>
>> >>> +<br>
>> >>> +<br>
>> >>> +define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {<br>
>> >>> +; AVX-LABEL: test_x86_avx_cvtt_ps2dq_256:<br>
>> >>> +; AVX: ## BB#0:<br>
>> >>> +; AVX-NEXT: vcvttps2dq %ymm0, %ymm0<br>
>> >>> +; AVX-NEXT: retl<br>
>> >>> +;<br>
>> >>> +; AVX512VL-LABEL: test_x86_avx_cvtt_ps2dq_256:<br>
>> >>> +; AVX512VL: ## BB#0:<br>
>> >>> +; AVX512VL-NEXT: vcvttps2dq %ymm0, %ymm0<br>
>> >>> +; AVX512VL-NEXT: retl<br>
>> >>> + %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0)<br>
>> >>> ;<br>
>> >>> <<8 x i32>> [#uses=1]<br>
>> >>> + ret <8 x i32> %res<br>
>> >>> +}<br>
>> >>> +declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind<br>
>> >>> readnone<br>
>> >>> +<br>
>> >>> +<br>
>> >>> define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x<br>
>> >>> float><br>
>> >>> %a1) {<br>
>> >>> ; AVX-LABEL: test_x86_avx_dp_ps_256:<br>
>> >>> ; AVX: ## BB#0:<br>
>> >>> @@ -4552,7 +4585,7 @@ define void @movnt_dq(i8* %p, <2 x i64><br>
>> >>> ; AVX-LABEL: movnt_dq:<br>
>> >>> ; AVX: ## BB#0:<br>
>> >>> ; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
>> >>> -; AVX-NEXT: vpaddq LCPI254_0, %xmm0, %xmm0<br>
>> >>> +; AVX-NEXT: vpaddq LCPI256_0, %xmm0, %xmm0<br>
>> >>> ; AVX-NEXT: vmovntdq %ymm0, (%eax)<br>
>> >>> ; AVX-NEXT: vzeroupper<br>
>> >>> ; AVX-NEXT: retl<br>
>> >>> @@ -4560,7 +4593,7 @@ define void @movnt_dq(i8* %p, <2 x i64><br>
>> >>> ; AVX512VL-LABEL: movnt_dq:<br>
>> >>> ; AVX512VL: ## BB#0:<br>
>> >>> ; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
>> >>> -; AVX512VL-NEXT: vpaddq LCPI254_0, %xmm0, %xmm0<br>
>> >>> +; AVX512VL-NEXT: vpaddq LCPI256_0, %xmm0, %xmm0<br>
>> >>> ; AVX512VL-NEXT: vmovntdq %ymm0, (%eax)<br>
>> >>> ; AVX512VL-NEXT: retl<br>
>> >>> %a2 = add <2 x i64> %a1, <i64 1, i64 1><br>
>> >>><br>
>> >>> Modified:<br>
>> >>> llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll<br>
>> >>> (original)<br>
>> >>> +++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll Tue<br>
>> >>> Jul<br>
>> >>> 19 10:07:43 2016<br>
>> >>> @@ -6,13 +6,12 @@<br>
>> >>> define <4 x float> @test_mm_cvtsi64_ss(<4 x float> %a0, i64 %a1)<br>
>> >>> nounwind<br>
>> >>> {<br>
>> >>> ; X64-LABEL: test_mm_cvtsi64_ss:<br>
>> >>> ; X64: # BB#0:<br>
>> >>> -; X64-NEXT: cvtsi2ssq %rdi, %xmm1<br>
>> >>> -; X64-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]<br>
>> >>> +; X64-NEXT: cvtsi2ssq %rdi, %xmm0<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %cvt = sitofp i64 %a1 to float<br>
>> >>> - %res = insertelement <4 x float> %a0, float %cvt, i32 0<br>
>> >>> + %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0,<br>
>> >>> i64<br>
>> >>> %a1)<br>
>> >>> ret <4 x float> %res<br>
>> >>> }<br>
>> >>> +declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64)<br>
>> >>> nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>> define i64 @test_mm_cvtss_si64(<4 x float> %a0) nounwind {<br>
>> >>> ; X64-LABEL: test_mm_cvtss_si64:<br>
>> >>> @@ -29,7 +28,7 @@ define i64 @test_mm_cvttss_si64(<4 x flo<br>
>> >>> ; X64: # BB#0:<br>
>> >>> ; X64-NEXT: cvttss2si %xmm0, %rax<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %cvt = extractelement <4 x float> %a0, i32 0<br>
>> >>> - %res = fptosi float %cvt to i64<br>
>> >>> + %res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0)<br>
>> >>> ret i64 %res<br>
>> >>> }<br>
>> >>> +declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone<br>
>> >>><br>
>> >>> Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll (original)<br>
>> >>> +++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll Tue Jul 19<br>
>> >>> 10:07:43 2016<br>
>> >>> @@ -707,20 +707,17 @@ declare i32 @llvm.x86.sse.cvtss2si(<4 x<br>
>> >>> define <4 x float> @test_mm_cvtsi32_ss(<4 x float> %a0, i32 %a1)<br>
>> >>> nounwind<br>
>> >>> {<br>
>> >>> ; X32-LABEL: test_mm_cvtsi32_ss:<br>
>> >>> ; X32: # BB#0:<br>
>> >>> -; X32-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
>> >>> -; X32-NEXT: cvtsi2ssl %eax, %xmm1<br>
>> >>> -; X32-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]<br>
>> >>> +; X32-NEXT: cvtsi2ssl {{[0-9]+}}(%esp), %xmm0<br>
>> >>> ; X32-NEXT: retl<br>
>> >>> ;<br>
>> >>> ; X64-LABEL: test_mm_cvtsi32_ss:<br>
>> >>> ; X64: # BB#0:<br>
>> >>> -; X64-NEXT: cvtsi2ssl %edi, %xmm1<br>
>> >>> -; X64-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]<br>
>> >>> +; X64-NEXT: cvtsi2ssl %edi, %xmm0<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %cvt = sitofp i32 %a1 to float<br>
>> >>> - %res = insertelement <4 x float> %a0, float %cvt, i32 0<br>
>> >>> + %res = call <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float> %a0, i32<br>
>> >>> %a1)<br>
>> >>> ret <4 x float> %res<br>
>> >>> }<br>
>> >>> +declare <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float>, i32) nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>> define float @test_mm_cvtss_f32(<4 x float> %a0) nounwind {<br>
>> >>> ; X32-LABEL: test_mm_cvtss_f32:<br>
>> >>> @@ -762,10 +759,10 @@ define i32 @test_mm_cvttss_si(<4 x float<br>
>> >>> ; X64: # BB#0:<br>
>> >>> ; X64-NEXT: cvttss2si %xmm0, %eax<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %cvt = extractelement <4 x float> %a0, i32 0<br>
>> >>> - %res = fptosi float %cvt to i32<br>
>> >>> + %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0)<br>
>> >>> ret i32 %res<br>
>> >>> }<br>
>> >>> +declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone<br>
>> >>><br>
>> >>> define i32 @test_mm_cvttss_si32(<4 x float> %a0) nounwind {<br>
>> >>> ; X32-LABEL: test_mm_cvttss_si32:<br>
>> >>> @@ -777,8 +774,7 @@ define i32 @test_mm_cvttss_si32(<4 x flo<br>
>> >>> ; X64: # BB#0:<br>
>> >>> ; X64-NEXT: cvttss2si %xmm0, %eax<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %cvt = extractelement <4 x float> %a0, i32 0<br>
>> >>> - %res = fptosi float %cvt to i32<br>
>> >>> + %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0)<br>
>> >>> ret i32 %res<br>
>> >>> }<br>
>> >>><br>
>> >>><br>
>> >>> Modified:<br>
>> >>> llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll<br>
>> >>> (original)<br>
>> >>> +++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll<br>
>> >>> Tue<br>
>> >>> Jul 19 10:07:43 2016<br>
>> >>> @@ -25,13 +25,12 @@ define i64 @test_mm_cvtsi128_si64(<2 x i<br>
>> >>> define <2 x double> @test_mm_cvtsi64_sd(<2 x double> %a0, i64 %a1)<br>
>> >>> nounwind {<br>
>> >>> ; X64-LABEL: test_mm_cvtsi64_sd:<br>
>> >>> ; X64: # BB#0:<br>
>> >>> -; X64-NEXT: cvtsi2sdq %rdi, %xmm1<br>
>> >>> -; X64-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]<br>
>> >>> +; X64-NEXT: cvtsi2sdq %rdi, %xmm0<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %cvt = sitofp i64 %a1 to double<br>
>> >>> - %res = insertelement <2 x double> %a0, double %cvt, i32 0<br>
>> >>> + %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double><br>
>> >>> %a0,<br>
>> >>> i64 %a1)<br>
>> >>> ret <2 x double> %res<br>
>> >>> }<br>
>> >>> +declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64)<br>
>> >>> nounwind readnone<br>
>> >>><br>
>> >>> define <2 x i64> @test_mm_cvtsi64_si128(i64 %a0) nounwind {<br>
>> >>> ; X64-LABEL: test_mm_cvtsi64_si128:<br>
>> >>> @@ -48,10 +47,10 @@ define i64 @test_mm_cvttsd_si64(<2 x dou<br>
>> >>> ; X64: # BB#0:<br>
>> >>> ; X64-NEXT: cvttsd2si %xmm0, %rax<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %ext = extractelement <2 x double> %a0, i32 0<br>
>> >>> - %res = fptosi double %ext to i64<br>
>> >>> + %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0)<br>
>> >>> ret i64 %res<br>
>> >>> }<br>
>> >>> +declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>> define <2 x i64> @test_mm_loadu_si64(i64* %a0) nounwind {<br>
>> >>> ; X64-LABEL: test_mm_loadu_si64:<br>
>> >>><br>
>> >>> Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll<br>
>> >>> (original)<br>
>> >>> +++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll Tue Jul<br>
>> >>> 19<br>
>> >>> 10:07:43 2016<br>
>> >>> @@ -1208,6 +1208,21 @@ define i32 @test_mm_cvtsd_si32(<2 x doub<br>
>> >>> }<br>
>> >>> declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone<br>
>> >>><br>
>> >>> +define <4 x float> @test_mm_cvtsd_ss(<4 x float> %a0, <2 x double><br>
>> >>> %a1) {<br>
>> >>> +; X32-LABEL: test_mm_cvtsd_ss:<br>
>> >>> +; X32: # BB#0:<br>
>> >>> +; X32-NEXT: cvtsd2ss %xmm1, %xmm0<br>
>> >>> +; X32-NEXT: retl<br>
>> >>> +;<br>
>> >>> +; X64-LABEL: test_mm_cvtsd_ss:<br>
>> >>> +; X64: # BB#0:<br>
>> >>> +; X64-NEXT: cvtsd2ss %xmm1, %xmm0<br>
>> >>> +; X64-NEXT: retq<br>
>> >>> + %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2<br>
>> >>> x<br>
>> >>> double> %a1)<br>
>> >>> + ret <4 x float> %res<br>
>> >>> +}<br>
>> >>> +declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x<br>
>> >>> double>)<br>
>> >>> nounwind readnone<br>
>> >>> +<br>
>> >>> define i32 @test_mm_cvtsi128_si32(<2 x i64> %a0) nounwind {<br>
>> >>> ; X32-LABEL: test_mm_cvtsi128_si32:<br>
>> >>> ; X32: # BB#0:<br>
>> >>> @@ -1303,10 +1318,11 @@ define <2 x i64> @test_mm_cvttps_epi32(<<br>
>> >>> ; X64: # BB#0:<br>
>> >>> ; X64-NEXT: cvttps2dq %xmm0, %xmm0<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %res = fptosi <4 x float> %a0 to <4 x i32><br>
>> >>> + %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0)<br>
>> >>> %bc = bitcast <4 x i32> %res to <2 x i64><br>
>> >>> ret <2 x i64> %bc<br>
>> >>> }<br>
>> >>> +declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>> define i32 @test_mm_cvttsd_si32(<2 x double> %a0) nounwind {<br>
>> >>> ; X32-LABEL: test_mm_cvttsd_si32:<br>
>> >>> @@ -1318,10 +1334,10 @@ define i32 @test_mm_cvttsd_si32(<2 x dou<br>
>> >>> ; X64: # BB#0:<br>
>> >>> ; X64-NEXT: cvttsd2si %xmm0, %eax<br>
>> >>> ; X64-NEXT: retq<br>
>> >>> - %ext = extractelement <2 x double> %a0, i32 0<br>
>> >>> - %res = fptosi double %ext to i32<br>
>> >>> + %res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0)<br>
>> >>> ret i32 %res<br>
>> >>> }<br>
>> >>> +declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone<br>
>> >>><br>
>> >>> define <2 x double> @test_mm_div_pd(<2 x double> %a0, <2 x double><br>
>> >>> %a1)<br>
>> >>> nounwind {<br>
>> >>> ; X32-LABEL: test_mm_div_pd:<br>
>> >>><br>
>> >>> Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll<br>
>> >>> (original)<br>
>> >>> +++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll Tue Jul<br>
>> >>> 19<br>
>> >>> 10:07:43 2016<br>
>> >>> @@ -66,17 +66,6 @@ define <2 x double> @test_x86_sse2_cvtps<br>
>> >>> declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>><br>
>> >>> -define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) {<br>
>> >>> -; CHECK-LABEL: test_x86_sse2_cvttps2dq:<br>
>> >>> -; CHECK: ## BB#0:<br>
>> >>> -; CHECK-NEXT: cvttps2dq %xmm0, %xmm0<br>
>> >>> -; CHECK-NEXT: retl<br>
>> >>> - %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ;<br>
>> >>> <<4 x<br>
>> >>> i32>> [#uses=1]<br>
>> >>> - ret <4 x i32> %res<br>
>> >>> -}<br>
>> >>> -declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind<br>
>> >>> readnone<br>
>> >>> -<br>
>> >>> -<br>
>> >>> define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) {<br>
>> >>> ; CHECK-LABEL: test_x86_sse2_storel_dq:<br>
>> >>> ; CHECK: ## BB#0:<br>
>> >>> @@ -94,7 +83,7 @@ define void @test_x86_sse2_storeu_dq(i8*<br>
>> >>> ; CHECK-LABEL: test_x86_sse2_storeu_dq:<br>
>> >>> ; CHECK: ## BB#0:<br>
>> >>> ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br>
>> >>> -; CHECK-NEXT: paddb LCPI8_0, %xmm0<br>
>> >>> +; CHECK-NEXT: paddb LCPI7_0, %xmm0<br>
>> >>> ; CHECK-NEXT: movdqu %xmm0, (%eax)<br>
>> >>> ; CHECK-NEXT: retl<br>
>> >>> %a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1,<br>
>> >>> i8<br>
>> >>> 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1><br>
>> >>><br>
>> >>> Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)<br>
>> >>> +++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Tue Jul 19<br>
>> >>> 10:07:43<br>
>> >>> 2016<br>
>> >>> @@ -1,4 +1,4 @@<br>
>> >>> -; NOTE: Assertions have been autogenerated by<br>
>> >>> update_llc_test_checks.py<br>
>> >>> +; NOTE: Assertions have been autogenerated by<br>
>> >>> utils/update_llc_test_checks.py<br>
>> >>> ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse2 |<br>
>> >>> FileCheck<br>
>> >>> %s --check-prefix=SSE<br>
>> >>> ; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=knl | FileCheck %s<br>
>> >>> --check-prefix=KNL<br>
>> >>><br>
>> >>> @@ -322,6 +322,22 @@ define <4 x i32> @test_x86_sse2_cvttpd2d<br>
>> >>> declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind<br>
>> >>> readnone<br>
>> >>><br>
>> >>><br>
>> >>> +define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) {<br>
>> >>> +; SSE-LABEL: test_x86_sse2_cvttps2dq:<br>
>> >>> +; SSE: ## BB#0:<br>
>> >>> +; SSE-NEXT: cvttps2dq %xmm0, %xmm0<br>
>> >>> +; SSE-NEXT: retl<br>
>> >>> +;<br>
>> >>> +; KNL-LABEL: test_x86_sse2_cvttps2dq:<br>
>> >>> +; KNL: ## BB#0:<br>
>> >>> +; KNL-NEXT: vcvttps2dq %xmm0, %xmm0<br>
>> >>> +; KNL-NEXT: retl<br>
>> >>> + %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ;<br>
>> >>> <<4 x<br>
>> >>> i32>> [#uses=1]<br>
>> >>> + ret <4 x i32> %res<br>
>> >>> +}<br>
>> >>> +declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind<br>
>> >>> readnone<br>
>> >>> +<br>
>> >>> +<br>
>> >>> define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) {<br>
>> >>> ; SSE-LABEL: test_x86_sse2_cvttsd2si:<br>
>> >>> ; SSE: ## BB#0:<br>
>> >>><br>
>> >>> Modified: llvm/trunk/test/Transforms/ConstProp/calls.ll<br>
>> >>> URL:<br>
>> >>><br>
>> >>> <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstProp/calls.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstProp/calls.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br>
>> >>><br>
>> >>><br>
>> >>> ==============================================================================<br>
>> >>> --- llvm/trunk/test/Transforms/ConstProp/calls.ll (original)<br>
>> >>> +++ llvm/trunk/test/Transforms/ConstProp/calls.ll Tue Jul 19 10:07:43<br>
>> >>> 2016<br>
>> >>> @@ -193,11 +193,13 @@ entry:<br>
>> >>> ret i1 %b<br>
>> >>> }<br>
>> >>><br>
>> >>> -; TODO: Inexact values should not fold as they are dependent on<br>
>> >>> rounding<br>
>> >>> mode<br>
>> >>> +; Inexact values should not fold as they are dependent on rounding<br>
>> >>> mode<br>
>> >>> define i1 @test_sse_cvts_inexact() nounwind readnone {<br>
>> >>> ; CHECK-LABEL: @test_sse_cvts_inexact(<br>
>> >>> -; CHECK-NOT: call<br>
>> >>> -; CHECK: ret i1 true<br>
>> >>> +; CHECK: call<br>
>> >>> +; CHECK: call<br>
>> >>> +; CHECK: call<br>
>> >>> +; CHECK: call<br>
>> >>> entry:<br>
>> >>> %i0 = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> <float 1.75,<br>
>> >>> float undef, float undef, float undef>) nounwind<br>
>> >>> %i1 = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> <float<br>
>> >>> 1.75,<br>
>> >>> float undef, float undef, float undef>) nounwind<br>
>> >>><br>
>> >>><br>
>> >>> _______________________________________________<br>
>> >>> llvm-commits mailing list<br>
>> >>> <a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br>
>> >>> <a href="http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits</a><br>
>> >><br>
>> >><br>
>> _______________________________________________<br>
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>> <a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a><br>
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