<div dir="ltr">On Wed, Jul 6, 2016 at 7:15 AM, Elena Demikhovsky via llvm-commits <span dir="ltr"><<a target="_blank" href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>></span> wrote:<br><div class="gmail_extra"><div class="gmail_quote"><blockquote style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex" class="gmail_quote">Author: delena<br>
Date: Wed Jul  6 09:15:43 2016<br>
New Revision: 274626<br>
<br>
URL: <a target="_blank" rel="noreferrer" href="http://llvm.org/viewvc/llvm-project?rev=274626&view=rev">http://llvm.org/viewvc/llvm-project?rev=274626&view=rev</a><br>
Log:<br>
Re-commit of 274613.<br>
<br>
The prev commit failed on compilation.<br>
A minor change in one pattern in lib/Target/X86/X86InstrAVX512.td fixes the failure.<br>
<br>
<br>
Modified:<br>
    llvm/trunk/lib/Target/X86/X86FastISel.cpp<br>
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
    llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
    llvm/trunk/test/CodeGen/X86/avx512-cmp.ll<br>
    llvm/trunk/test/CodeGen/X86/avx512-ext.ll<br>
    llvm/trunk/test/CodeGen/X86/avx512-insert-extract.ll<br>
    llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
    llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll<br>
    llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll<br>
    llvm/trunk/test/CodeGen/X86/masked_gather_scatter.ll<br>
    llvm/trunk/test/CodeGen/X86/pr27591.ll<br>
    llvm/trunk/test/CodeGen/X86/pr28173.ll<br>
    llvm/trunk/test/CodeGen/X86/xaluo.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp<br>
URL: <a target="_blank" rel="noreferrer" href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=274626&r1=274625&r2=274626&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=274626&r1=274625&r2=274626&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Jul  6 09:15:43 2016<br>
@@ -1404,6 +1404,9 @@ bool X86FastISel::X86SelectCmp(const Ins<br>
   if (!isTypeLegal(I->getOperand(0)->getType(), VT))<br>
     return false;<br>
<br>
+  if (I->getType()->isIntegerTy(1) && Subtarget->hasAVX512())<br>
+    return false;<br>
+<br>
   // Try to optimize or fold the cmp.<br>
   CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);<br>
   unsigned ResultReg = 0;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a target="_blank" rel="noreferrer" href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=274626&r1=274625&r2=274626&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=274626&r1=274625&r2=274626&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul  6 09:15:43 2016<br>
@@ -15551,8 +15551,11 @@ SDValue X86TargetLowering::LowerSETCC(SD<br>
       isNullConstant(Op1) &&<br>
       (CC == ISD::SETEQ || CC == ISD::SETNE)) {<br>
     if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {<br>
-      if (VT == MVT::i1)<br>
+      if (VT == MVT::i1) {<br>
+        NewSetCC = DAG.getNode(ISD::AssertZext, dl, MVT::i8, NewSetCC,<br>
+                               DAG.getValueType(MVT::i1));<br>
         return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);<br>
+      }<br></blockquote><div><br>Why are we generating AssertZext(SETCC(...))? AssertZext is meant to be used in cases where SelectionDAG can't compute whether the upper bits are zero; inserting extra AssertZext nodes in places where we can trivially prove the top bits are zero just makes it more difficult to write optimizations.<br><br></div><div>-Eli<br></div></div></div></div>