<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="" dir="auto">Seconded - we should include the clang counterpart <span style="font-family: 'Helvetica Neue';" class="">r275981</span><span style="font-family: 'Helvetica Neue';" class=""> as well.</span><div class=""><br class=""></div><div class=""><div class=""><div><blockquote type="cite" class=""><div class="">On 21 Jul 2016, at 22:41, Eli Friedman <<a href="mailto:eli.friedman@gmail.com" class="">eli.friedman@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class=""><div class="">Nominating for backport to 3.9, so the intrinsics in question remain available.<br class=""><br class=""></div>-Eli<br class=""><div class="gmail_extra"><br class=""><div class="gmail_quote">On Tue, Jul 19, 2016 at 8:07 AM, Simon Pilgrim via llvm-commits <span dir="ltr" class=""><<a href="mailto:llvm-commits@lists.llvm.org" target="_blank" class="">llvm-commits@lists.llvm.org</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br class="">
Date: Tue Jul 19 10:07:43 2016<br class="">
New Revision: 275981<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=275981&view=rev" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=275981&view=rev</a><br class="">
Log:<br class="">
[X86][SSE] Reimplement SSE fp2si conversion intrinsics instead of using generic IR<br class="">
<br class="">
D20859 and D20860 attempted to replace the SSE (V)CVTTPS2DQ and VCVTTPD2DQ truncating conversions with generic IR instead.<br class="">
<br class="">
It turns out that the behaviour of these intrinsics is different enough from generic IR that this will cause problems, INF/NAN/out of range values are guaranteed to result in a 0x80000000 value - which plays havoc with constant folding which converts them to either zero or UNDEF. This is also an issue with the scalar implementations (which were already generic IR and what I was trying to match).<br class="">
<br class="">
This patch changes both scalar and packed versions back to using x86-specific builtins.<br class="">
<br class="">
It also deals with the other scalar conversion cases that are runtime rounding mode dependent and can have similar issues with constant folding.<br class="">
<br class="">
A companion clang patch is at D22105<br class="">
<br class="">
Differential Revision: <a href="https://reviews.llvm.org/D22106" rel="noreferrer" target="_blank" class="">https://reviews.llvm.org/D22106</a><br class="">
<br class="">
Modified:<br class="">
llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br class="">
llvm/trunk/lib/Analysis/ConstantFolding.cpp<br class="">
llvm/trunk/lib/IR/AutoUpgrade.cpp<br class="">
llvm/trunk/lib/Target/X86/X86InstrSSE.td<br class="">
llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll<br class="">
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll<br class="">
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br class="">
llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll<br class="">
llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll<br class="">
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll<br class="">
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll<br class="">
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll<br class="">
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br class="">
llvm/trunk/test/Transforms/ConstProp/calls.ll<br class="">
<br class="">
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br class="">
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Tue Jul 19 10:07:43 2016<br class="">
@@ -479,6 +479,8 @@ let TargetPrefix = "x86" in { // All in<br class="">
Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty], [IntrNoMem]>;<br class="">
def int_x86_sse2_cvtps2dq : GCCBuiltin<"__builtin_ia32_cvtps2dq">,<br class="">
Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;<br class="">
+ def int_x86_sse2_cvttps2dq : GCCBuiltin<"__builtin_ia32_cvttps2dq">,<br class="">
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;<br class="">
def int_x86_sse2_cvtsd2si : GCCBuiltin<"__builtin_ia32_cvtsd2si">,<br class="">
Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;<br class="">
def int_x86_sse2_cvtsd2si64 : GCCBuiltin<"__builtin_ia32_cvtsd2si64">,<br class="">
@@ -1512,8 +1514,12 @@ let TargetPrefix = "x86" in { // All in<br class="">
Intrinsic<[llvm_v4f32_ty], [llvm_v4f64_ty], [IntrNoMem]>;<br class="">
def int_x86_avx_cvt_ps2dq_256 : GCCBuiltin<"__builtin_ia32_cvtps2dq256">,<br class="">
Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;<br class="">
+ def int_x86_avx_cvtt_pd2dq_256 : GCCBuiltin<"__builtin_ia32_cvttpd2dq256">,<br class="">
+ Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;<br class="">
def int_x86_avx_cvt_pd2dq_256 : GCCBuiltin<"__builtin_ia32_cvtpd2dq256">,<br class="">
Intrinsic<[llvm_v4i32_ty], [llvm_v4f64_ty], [IntrNoMem]>;<br class="">
+ def int_x86_avx_cvtt_ps2dq_256 : GCCBuiltin<"__builtin_ia32_cvttps2dq256">,<br class="">
+ Intrinsic<[llvm_v8i32_ty], [llvm_v8f32_ty], [IntrNoMem]>;<br class="">
}<br class="">
<br class="">
// Vector bit test<br class="">
<br class="">
Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)<br class="">
+++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Tue Jul 19 10:07:43 2016<br class="">
@@ -1424,8 +1424,8 @@ Constant *ConstantFoldBinaryFP(double (*<br class="">
/// integer type Ty is used to select how many bits are available for the<br class="">
/// result. Returns null if the conversion cannot be performed, otherwise<br class="">
/// returns the Constant value resulting from the conversion.<br class="">
-Constant *ConstantFoldConvertToInt(const APFloat &Val, bool roundTowardZero,<br class="">
- Type *Ty) {<br class="">
+Constant *ConstantFoldSSEConvertToInt(const APFloat &Val, bool roundTowardZero,<br class="">
+ Type *Ty) {<br class="">
// All of these conversion intrinsics form an integer of at most 64bits.<br class="">
unsigned ResultWidth = Ty->getIntegerBitWidth();<br class="">
assert(ResultWidth <= 64 &&<br class="">
@@ -1438,7 +1438,8 @@ Constant *ConstantFoldConvertToInt(const<br class="">
APFloat::opStatus status = Val.convertToInteger(&UIntVal, ResultWidth,<br class="">
/*isSigned=*/true, mode,<br class="">
&isExact);<br class="">
- if (status != APFloat::opOK && status != APFloat::opInexact)<br class="">
+ if (status != APFloat::opOK &&<br class="">
+ (!roundTowardZero || status != APFloat::opInexact))<br class="">
return nullptr;<br class="">
return ConstantInt::get(Ty, UIntVal, /*isSigned=*/true);<br class="">
}<br class="">
@@ -1676,17 +1677,17 @@ Constant *ConstantFoldScalarCall(StringR<br class="">
case Intrinsic::x86_sse2_cvtsd2si:<br class="">
case Intrinsic::x86_sse2_cvtsd2si64:<br class="">
if (ConstantFP *FPOp =<br class="">
- dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))<br class="">
- return ConstantFoldConvertToInt(FPOp->getValueAPF(),<br class="">
- /*roundTowardZero=*/false, Ty);<br class="">
+ dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))<br class="">
+ return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),<br class="">
+ /*roundTowardZero=*/false, Ty);<br class="">
case Intrinsic::x86_sse_cvttss2si:<br class="">
case Intrinsic::x86_sse_cvttss2si64:<br class="">
case Intrinsic::x86_sse2_cvttsd2si:<br class="">
case Intrinsic::x86_sse2_cvttsd2si64:<br class="">
if (ConstantFP *FPOp =<br class="">
- dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))<br class="">
- return ConstantFoldConvertToInt(FPOp->getValueAPF(),<br class="">
- /*roundTowardZero=*/true, Ty);<br class="">
+ dyn_cast_or_null<ConstantFP>(Op->getAggregateElement(0U)))<br class="">
+ return ConstantFoldSSEConvertToInt(FPOp->getValueAPF(),<br class="">
+ /*roundTowardZero=*/true, Ty);<br class="">
}<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/lib/IR/AutoUpgrade.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AutoUpgrade.cpp?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/IR/AutoUpgrade.cpp (original)<br class="">
+++ llvm/trunk/lib/IR/AutoUpgrade.cpp Tue Jul 19 10:07:43 2016<br class="">
@@ -251,8 +251,6 @@ static bool UpgradeIntrinsicFunction1(Fu<br class="">
Name == "sse2.cvtps2pd" ||<br class="">
Name == "avx.cvtdq2.pd.256" ||<br class="">
Name == "avx.cvt.ps2.pd.256" ||<br class="">
- Name == "sse2.cvttps2dq" ||<br class="">
- Name.startswith("avx.cvtt.") ||<br class="">
Name.startswith("avx.vinsertf128.") ||<br class="">
Name == "avx2.vinserti128" ||<br class="">
Name.startswith("avx.vextractf128.") ||<br class="">
@@ -712,12 +710,6 @@ void llvm::UpgradeIntrinsicCall(CallInst<br class="">
Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd");<br class="">
else<br class="">
Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd");<br class="">
- } else if (IsX86 && (Name == "sse2.cvttps2dq" ||<br class="">
- Name.startswith("avx.cvtt."))) {<br class="">
- // Truncation (round to zero) float/double to i32 vector conversion.<br class="">
- Value *Src = CI->getArgOperand(0);<br class="">
- VectorType *DstTy = cast<VectorType>(CI->getType());<br class="">
- Rep = Builder.CreateFPToSI(Src, DstTy, "cvtt");<br class="">
} else if (IsX86 && Name.startswith("sse4a.movnt.")) {<br class="">
Module *M = F->getParent();<br class="">
SmallVector<Metadata *, 1> Elts;<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br class="">
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 19 10:07:43 2016<br class="">
@@ -2009,24 +2009,35 @@ def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (<br class="">
// SSE2 packed instructions with XS prefix<br class="">
def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),<br class="">
"cvttps2dq\t{$src, $dst|$dst, $src}",<br class="">
- [], IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;<br class="">
+ [(set VR128:$dst,<br class="">
+ (int_x86_sse2_cvttps2dq VR128:$src))],<br class="">
+ IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;<br class="">
def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),<br class="">
"cvttps2dq\t{$src, $dst|$dst, $src}",<br class="">
- [], IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;<br class="">
+ [(set VR128:$dst, (int_x86_sse2_cvttps2dq<br class="">
+ (loadv4f32 addr:$src)))],<br class="">
+ IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;<br class="">
def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),<br class="">
"cvttps2dq\t{$src, $dst|$dst, $src}",<br class="">
- [], IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;<br class="">
+ [(set VR256:$dst,<br class="">
+ (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],<br class="">
+ IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;<br class="">
def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),<br class="">
"cvttps2dq\t{$src, $dst|$dst, $src}",<br class="">
- [], IIC_SSE_CVT_PS_RM>, VEX, VEX_L,<br class="">
+ [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256<br class="">
+ (loadv8f32 addr:$src)))],<br class="">
+ IIC_SSE_CVT_PS_RM>, VEX, VEX_L,<br class="">
Sched<[WriteCvtF2ILd]>;<br class="">
<br class="">
def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),<br class="">
"cvttps2dq\t{$src, $dst|$dst, $src}",<br class="">
- [], IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;<br class="">
+ [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],<br class="">
+ IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;<br class="">
def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),<br class="">
"cvttps2dq\t{$src, $dst|$dst, $src}",<br class="">
- [], IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;<br class="">
+ [(set VR128:$dst,<br class="">
+ (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],<br class="">
+ IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;<br class="">
<br class="">
let Predicates = [HasAVX] in {<br class="">
def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),<br class="">
@@ -2096,10 +2107,14 @@ def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem<br class="">
// YMM only<br class="">
def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),<br class="">
"cvttpd2dq{y}\t{$src, $dst|$dst, $src}",<br class="">
- [], IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;<br class="">
+ [(set VR128:$dst,<br class="">
+ (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],<br class="">
+ IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;<br class="">
def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),<br class="">
"cvttpd2dq{y}\t{$src, $dst|$dst, $src}",<br class="">
- [], IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;<br class="">
+ [(set VR128:$dst,<br class="">
+ (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],<br class="">
+ IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;<br class="">
def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",<br class="">
(VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -681,10 +681,11 @@ define <2 x i64> @test_mm256_cvttpd_epi3<br class="">
; X64-NEXT: vcvttpd2dqy %ymm0, %xmm0<br class="">
; X64-NEXT: vzeroupper<br class="">
; X64-NEXT: retq<br class="">
- %cvt = fptosi <4 x double> %a0 to <4 x i32><br class="">
+ %cvt = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0)<br class="">
%res = bitcast <4 x i32> %cvt to <2 x i64><br class="">
ret <2 x i64> %res<br class="">
}<br class="">
+declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone<br class="">
<br class="">
define <4 x i64> @test_mm256_cvttps_epi32(<8 x float> %a0) nounwind {<br class="">
; X32-LABEL: test_mm256_cvttps_epi32:<br class="">
@@ -696,10 +697,11 @@ define <4 x i64> @test_mm256_cvttps_epi3<br class="">
; X64: # BB#0:<br class="">
; X64-NEXT: vcvttps2dq %ymm0, %ymm0<br class="">
; X64-NEXT: retq<br class="">
- %cvt = fptosi <8 x float> %a0 to <8 x i32><br class="">
+ %cvt = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0)<br class="">
%res = bitcast <8 x i32> %cvt to <4 x i64><br class="">
ret <4 x i64> %res<br class="">
}<br class="">
+declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone<br class="">
<br class="">
define <4 x double> @test_mm256_div_pd(<4 x double> %a0, <4 x double> %a1) nounwind {<br class="">
; X32-LABEL: test_mm256_div_pd:<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -359,35 +359,12 @@ define <4 x double> @test_x86_avx_cvt_ps<br class="">
declare <4 x double> @llvm.x86.avx.cvt.ps2.pd.256(<4 x float>) nounwind readnone<br class="">
<br class="">
<br class="">
-define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {<br class="">
-; CHECK-LABEL: test_x86_avx_cvtt_pd2dq_256:<br class="">
-; CHECK: ## BB#0:<br class="">
-; CHECK-NEXT: vcvttpd2dqy %ymm0, %xmm0<br class="">
-; CHECK-NEXT: vzeroupper<br class="">
-; CHECK-NEXT: retl<br class="">
- %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]<br class="">
- ret <4 x i32> %res<br class="">
-}<br class="">
-declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone<br class="">
-<br class="">
-<br class="">
-define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {<br class="">
-; CHECK-LABEL: test_x86_avx_cvtt_ps2dq_256:<br class="">
-; CHECK: ## BB#0:<br class="">
-; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0<br class="">
-; CHECK-NEXT: retl<br class="">
- %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]<br class="">
- ret <8 x i32> %res<br class="">
-}<br class="">
-declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone<br class="">
-<br class="">
-<br class="">
define void @test_x86_sse2_storeu_dq(i8* %a0, <16 x i8> %a1) {<br class="">
; add operation forces the execution domain.<br class="">
; CHECK-LABEL: test_x86_sse2_storeu_dq:<br class="">
; CHECK: ## BB#0:<br class="">
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br class="">
-; CHECK-NEXT: vpaddb LCPI34_0, %xmm0, %xmm0<br class="">
+; CHECK-NEXT: vpaddb LCPI32_0, %xmm0, %xmm0<br class="">
; CHECK-NEXT: vmovdqu %xmm0, (%eax)<br class="">
; CHECK-NEXT: retl<br class="">
%a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1><br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -3431,6 +3431,39 @@ define <8 x float> @test_x86_avx_cvtdq2_<br class="">
declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind readnone<br class="">
<br class="">
<br class="">
+define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {<br class="">
+; AVX-LABEL: test_x86_avx_cvtt_pd2dq_256:<br class="">
+; AVX: ## BB#0:<br class="">
+; AVX-NEXT: vcvttpd2dqy %ymm0, %xmm0<br class="">
+; AVX-NEXT: vzeroupper<br class="">
+; AVX-NEXT: retl<br class="">
+;<br class="">
+; AVX512VL-LABEL: test_x86_avx_cvtt_pd2dq_256:<br class="">
+; AVX512VL: ## BB#0:<br class="">
+; AVX512VL-NEXT: vcvttpd2dqy %ymm0, %xmm0<br class="">
+; AVX512VL-NEXT: retl<br class="">
+ %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]<br class="">
+ ret <4 x i32> %res<br class="">
+}<br class="">
+declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone<br class="">
+<br class="">
+<br class="">
+define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {<br class="">
+; AVX-LABEL: test_x86_avx_cvtt_ps2dq_256:<br class="">
+; AVX: ## BB#0:<br class="">
+; AVX-NEXT: vcvttps2dq %ymm0, %ymm0<br class="">
+; AVX-NEXT: retl<br class="">
+;<br class="">
+; AVX512VL-LABEL: test_x86_avx_cvtt_ps2dq_256:<br class="">
+; AVX512VL: ## BB#0:<br class="">
+; AVX512VL-NEXT: vcvttps2dq %ymm0, %ymm0<br class="">
+; AVX512VL-NEXT: retl<br class="">
+ %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]<br class="">
+ ret <8 x i32> %res<br class="">
+}<br class="">
+declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone<br class="">
+<br class="">
+<br class="">
define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) {<br class="">
; AVX-LABEL: test_x86_avx_dp_ps_256:<br class="">
; AVX: ## BB#0:<br class="">
@@ -4552,7 +4585,7 @@ define void @movnt_dq(i8* %p, <2 x i64><br class="">
; AVX-LABEL: movnt_dq:<br class="">
; AVX: ## BB#0:<br class="">
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax<br class="">
-; AVX-NEXT: vpaddq LCPI254_0, %xmm0, %xmm0<br class="">
+; AVX-NEXT: vpaddq LCPI256_0, %xmm0, %xmm0<br class="">
; AVX-NEXT: vmovntdq %ymm0, (%eax)<br class="">
; AVX-NEXT: vzeroupper<br class="">
; AVX-NEXT: retl<br class="">
@@ -4560,7 +4593,7 @@ define void @movnt_dq(i8* %p, <2 x i64><br class="">
; AVX512VL-LABEL: movnt_dq:<br class="">
; AVX512VL: ## BB#0:<br class="">
; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax<br class="">
-; AVX512VL-NEXT: vpaddq LCPI254_0, %xmm0, %xmm0<br class="">
+; AVX512VL-NEXT: vpaddq LCPI256_0, %xmm0, %xmm0<br class="">
; AVX512VL-NEXT: vmovntdq %ymm0, (%eax)<br class="">
; AVX512VL-NEXT: retl<br class="">
%a2 = add <2 x i64> %a1, <i64 1, i64 1><br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -6,13 +6,12 @@<br class="">
define <4 x float> @test_mm_cvtsi64_ss(<4 x float> %a0, i64 %a1) nounwind {<br class="">
; X64-LABEL: test_mm_cvtsi64_ss:<br class="">
; X64: # BB#0:<br class="">
-; X64-NEXT: cvtsi2ssq %rdi, %xmm1<br class="">
-; X64-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]<br class="">
+; X64-NEXT: cvtsi2ssq %rdi, %xmm0<br class="">
; X64-NEXT: retq<br class="">
- %cvt = sitofp i64 %a1 to float<br class="">
- %res = insertelement <4 x float> %a0, float %cvt, i32 0<br class="">
+ %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1)<br class="">
ret <4 x float> %res<br class="">
}<br class="">
+declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone<br class="">
<br class="">
define i64 @test_mm_cvtss_si64(<4 x float> %a0) nounwind {<br class="">
; X64-LABEL: test_mm_cvtss_si64:<br class="">
@@ -29,7 +28,7 @@ define i64 @test_mm_cvttss_si64(<4 x flo<br class="">
; X64: # BB#0:<br class="">
; X64-NEXT: cvttss2si %xmm0, %rax<br class="">
; X64-NEXT: retq<br class="">
- %cvt = extractelement <4 x float> %a0, i32 0<br class="">
- %res = fptosi float %cvt to i64<br class="">
+ %res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0)<br class="">
ret i64 %res<br class="">
}<br class="">
+declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -707,20 +707,17 @@ declare i32 @llvm.x86.sse.cvtss2si(<4 x<br class="">
define <4 x float> @test_mm_cvtsi32_ss(<4 x float> %a0, i32 %a1) nounwind {<br class="">
; X32-LABEL: test_mm_cvtsi32_ss:<br class="">
; X32: # BB#0:<br class="">
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax<br class="">
-; X32-NEXT: cvtsi2ssl %eax, %xmm1<br class="">
-; X32-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]<br class="">
+; X32-NEXT: cvtsi2ssl {{[0-9]+}}(%esp), %xmm0<br class="">
; X32-NEXT: retl<br class="">
;<br class="">
; X64-LABEL: test_mm_cvtsi32_ss:<br class="">
; X64: # BB#0:<br class="">
-; X64-NEXT: cvtsi2ssl %edi, %xmm1<br class="">
-; X64-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]<br class="">
+; X64-NEXT: cvtsi2ssl %edi, %xmm0<br class="">
; X64-NEXT: retq<br class="">
- %cvt = sitofp i32 %a1 to float<br class="">
- %res = insertelement <4 x float> %a0, float %cvt, i32 0<br class="">
+ %res = call <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float> %a0, i32 %a1)<br class="">
ret <4 x float> %res<br class="">
}<br class="">
+declare <4 x float> @llvm.x86.sse.cvtsi2ss(<4 x float>, i32) nounwind readnone<br class="">
<br class="">
define float @test_mm_cvtss_f32(<4 x float> %a0) nounwind {<br class="">
; X32-LABEL: test_mm_cvtss_f32:<br class="">
@@ -762,10 +759,10 @@ define i32 @test_mm_cvttss_si(<4 x float<br class="">
; X64: # BB#0:<br class="">
; X64-NEXT: cvttss2si %xmm0, %eax<br class="">
; X64-NEXT: retq<br class="">
- %cvt = extractelement <4 x float> %a0, i32 0<br class="">
- %res = fptosi float %cvt to i32<br class="">
+ %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0)<br class="">
ret i32 %res<br class="">
}<br class="">
+declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone<br class="">
<br class="">
define i32 @test_mm_cvttss_si32(<4 x float> %a0) nounwind {<br class="">
; X32-LABEL: test_mm_cvttss_si32:<br class="">
@@ -777,8 +774,7 @@ define i32 @test_mm_cvttss_si32(<4 x flo<br class="">
; X64: # BB#0:<br class="">
; X64-NEXT: cvttss2si %xmm0, %eax<br class="">
; X64-NEXT: retq<br class="">
- %cvt = extractelement <4 x float> %a0, i32 0<br class="">
- %res = fptosi float %cvt to i32<br class="">
+ %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0)<br class="">
ret i32 %res<br class="">
}<br class="">
<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -25,13 +25,12 @@ define i64 @test_mm_cvtsi128_si64(<2 x i<br class="">
define <2 x double> @test_mm_cvtsi64_sd(<2 x double> %a0, i64 %a1) nounwind {<br class="">
; X64-LABEL: test_mm_cvtsi64_sd:<br class="">
; X64: # BB#0:<br class="">
-; X64-NEXT: cvtsi2sdq %rdi, %xmm1<br class="">
-; X64-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]<br class="">
+; X64-NEXT: cvtsi2sdq %rdi, %xmm0<br class="">
; X64-NEXT: retq<br class="">
- %cvt = sitofp i64 %a1 to double<br class="">
- %res = insertelement <2 x double> %a0, double %cvt, i32 0<br class="">
+ %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1)<br class="">
ret <2 x double> %res<br class="">
}<br class="">
+declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone<br class="">
<br class="">
define <2 x i64> @test_mm_cvtsi64_si128(i64 %a0) nounwind {<br class="">
; X64-LABEL: test_mm_cvtsi64_si128:<br class="">
@@ -48,10 +47,10 @@ define i64 @test_mm_cvttsd_si64(<2 x dou<br class="">
; X64: # BB#0:<br class="">
; X64-NEXT: cvttsd2si %xmm0, %rax<br class="">
; X64-NEXT: retq<br class="">
- %ext = extractelement <2 x double> %a0, i32 0<br class="">
- %res = fptosi double %ext to i64<br class="">
+ %res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0)<br class="">
ret i64 %res<br class="">
}<br class="">
+declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone<br class="">
<br class="">
define <2 x i64> @test_mm_loadu_si64(i64* %a0) nounwind {<br class="">
; X64-LABEL: test_mm_loadu_si64:<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -1208,6 +1208,21 @@ define i32 @test_mm_cvtsd_si32(<2 x doub<br class="">
}<br class="">
declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone<br class="">
<br class="">
+define <4 x float> @test_mm_cvtsd_ss(<4 x float> %a0, <2 x double> %a1) {<br class="">
+; X32-LABEL: test_mm_cvtsd_ss:<br class="">
+; X32: # BB#0:<br class="">
+; X32-NEXT: cvtsd2ss %xmm1, %xmm0<br class="">
+; X32-NEXT: retl<br class="">
+;<br class="">
+; X64-LABEL: test_mm_cvtsd_ss:<br class="">
+; X64: # BB#0:<br class="">
+; X64-NEXT: cvtsd2ss %xmm1, %xmm0<br class="">
+; X64-NEXT: retq<br class="">
+ %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1)<br class="">
+ ret <4 x float> %res<br class="">
+}<br class="">
+declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone<br class="">
+<br class="">
define i32 @test_mm_cvtsi128_si32(<2 x i64> %a0) nounwind {<br class="">
; X32-LABEL: test_mm_cvtsi128_si32:<br class="">
; X32: # BB#0:<br class="">
@@ -1303,10 +1318,11 @@ define <2 x i64> @test_mm_cvttps_epi32(<<br class="">
; X64: # BB#0:<br class="">
; X64-NEXT: cvttps2dq %xmm0, %xmm0<br class="">
; X64-NEXT: retq<br class="">
- %res = fptosi <4 x float> %a0 to <4 x i32><br class="">
+ %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0)<br class="">
%bc = bitcast <4 x i32> %res to <2 x i64><br class="">
ret <2 x i64> %bc<br class="">
}<br class="">
+declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone<br class="">
<br class="">
define i32 @test_mm_cvttsd_si32(<2 x double> %a0) nounwind {<br class="">
; X32-LABEL: test_mm_cvttsd_si32:<br class="">
@@ -1318,10 +1334,10 @@ define i32 @test_mm_cvttsd_si32(<2 x dou<br class="">
; X64: # BB#0:<br class="">
; X64-NEXT: cvttsd2si %xmm0, %eax<br class="">
; X64-NEXT: retq<br class="">
- %ext = extractelement <2 x double> %a0, i32 0<br class="">
- %res = fptosi double %ext to i32<br class="">
+ %res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0)<br class="">
ret i32 %res<br class="">
}<br class="">
+declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone<br class="">
<br class="">
define <2 x double> @test_mm_div_pd(<2 x double> %a0, <2 x double> %a1) nounwind {<br class="">
; X32-LABEL: test_mm_div_pd:<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -66,17 +66,6 @@ define <2 x double> @test_x86_sse2_cvtps<br class="">
declare <2 x double> @llvm.x86.sse2.cvtps2pd(<4 x float>) nounwind readnone<br class="">
<br class="">
<br class="">
-define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) {<br class="">
-; CHECK-LABEL: test_x86_sse2_cvttps2dq:<br class="">
-; CHECK: ## BB#0:<br class="">
-; CHECK-NEXT: cvttps2dq %xmm0, %xmm0<br class="">
-; CHECK-NEXT: retl<br class="">
- %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]<br class="">
- ret <4 x i32> %res<br class="">
-}<br class="">
-declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone<br class="">
-<br class="">
-<br class="">
define void @test_x86_sse2_storel_dq(i8* %a0, <4 x i32> %a1) {<br class="">
; CHECK-LABEL: test_x86_sse2_storel_dq:<br class="">
; CHECK: ## BB#0:<br class="">
@@ -94,7 +83,7 @@ define void @test_x86_sse2_storeu_dq(i8*<br class="">
; CHECK-LABEL: test_x86_sse2_storeu_dq:<br class="">
; CHECK: ## BB#0:<br class="">
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax<br class="">
-; CHECK-NEXT: paddb LCPI8_0, %xmm0<br class="">
+; CHECK-NEXT: paddb LCPI7_0, %xmm0<br class="">
; CHECK-NEXT: movdqu %xmm0, (%eax)<br class="">
; CHECK-NEXT: retl<br class="">
%a2 = add <16 x i8> %a1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1><br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -1,4 +1,4 @@<br class="">
-; NOTE: Assertions have been autogenerated by update_llc_test_checks.py<br class="">
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py<br class="">
; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=-avx,+sse2 | FileCheck %s --check-prefix=SSE<br class="">
; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=KNL<br class="">
<br class="">
@@ -322,6 +322,22 @@ define <4 x i32> @test_x86_sse2_cvttpd2d<br class="">
declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone<br class="">
<br class="">
<br class="">
+define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) {<br class="">
+; SSE-LABEL: test_x86_sse2_cvttps2dq:<br class="">
+; SSE: ## BB#0:<br class="">
+; SSE-NEXT: cvttps2dq %xmm0, %xmm0<br class="">
+; SSE-NEXT: retl<br class="">
+;<br class="">
+; KNL-LABEL: test_x86_sse2_cvttps2dq:<br class="">
+; KNL: ## BB#0:<br class="">
+; KNL-NEXT: vcvttps2dq %xmm0, %xmm0<br class="">
+; KNL-NEXT: retl<br class="">
+ %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]<br class="">
+ ret <4 x i32> %res<br class="">
+}<br class="">
+declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone<br class="">
+<br class="">
+<br class="">
define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) {<br class="">
; SSE-LABEL: test_x86_sse2_cvttsd2si:<br class="">
; SSE: ## BB#0:<br class="">
<br class="">
Modified: llvm/trunk/test/Transforms/ConstProp/calls.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstProp/calls.ll?rev=275981&r1=275980&r2=275981&view=diff" rel="noreferrer" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstProp/calls.ll?rev=275981&r1=275980&r2=275981&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/test/Transforms/ConstProp/calls.ll (original)<br class="">
+++ llvm/trunk/test/Transforms/ConstProp/calls.ll Tue Jul 19 10:07:43 2016<br class="">
@@ -193,11 +193,13 @@ entry:<br class="">
ret i1 %b<br class="">
}<br class="">
<br class="">
-; TODO: Inexact values should not fold as they are dependent on rounding mode<br class="">
+; Inexact values should not fold as they are dependent on rounding mode<br class="">
define i1 @test_sse_cvts_inexact() nounwind readnone {<br class="">
; CHECK-LABEL: @test_sse_cvts_inexact(<br class="">
-; CHECK-NOT: call<br class="">
-; CHECK: ret i1 true<br class="">
+; CHECK: call<br class="">
+; CHECK: call<br class="">
+; CHECK: call<br class="">
+; CHECK: call<br class="">
entry:<br class="">
%i0 = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> <float 1.75, float undef, float undef, float undef>) nounwind<br class="">
%i1 = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> <float 1.75, float undef, float undef, float undef>) nounwind<br class="">
<br class="">
<br class="">
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