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<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Hi Andrea,
<o:p></o:p></span></a></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">I should understand what you mean by “switch”. An undocumented switch on the clang level? Does clang already have such flags for backward compatibly?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Or you mean an #ifdef around “comi” intrinsics in the header file? And user will define a VAR before including intrin.h<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D">Or #ifdef inside codegen and you’ll compile clang with this specific flag?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
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<![if !supportLists]><span style="font-family:"Calibri",sans-serif;color:#2F5496"><span style="mso-list:Ignore">-<span style="font:7.0pt "Times New Roman"">
</span></span></span><![endif]><span dir="LTR"></span><b><i><span style="color:#2F5496"> Elena<o:p></o:p></span></i></b></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><a name="_____replyseparator"></a><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Andrea Di Biagio [mailto:andrea.dibiagio@gmail.com]
<br>
<b>Sent:</b> Wednesday, July 20, 2016 15:05<br>
<b>To:</b> Demikhovsky, Elena <elena.demikhovsky@intel.com><br>
<b>Cc:</b> llvm-commits <llvm-commits@lists.llvm.org><br>
<b>Subject:</b> Re: [llvm] r269569 - Fixed lowering of _comi_ intrinsics from all sets - SSE/SSE2/AVX/AVX-512<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">Hi Elena,<o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">I agree that this patch is the correct thing to do.<br>
However, we at Sony are a bit concerned by this patch because it breaks some very important customer codebases which heavily rely on the old lowering behavior.<br>
<br>
What if we add a switch to enable the old lowering (as suggested in PR28510)? I think it would be very useful in the short term. Users that are stuck with old codebases would be able to pass that switch; other users will have a bit of time to upgrade their
codebases.<br>
What do you think?<o:p></o:p></p>
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<p class="MsoNormal">Cheers,<o:p></o:p></p>
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<p class="MsoNormal">Andrea<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">On Sat, May 14, 2016 at 4:06 PM, Elena Demikhovsky via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org" target="_blank">llvm-commits@lists.llvm.org</a>> wrote:<o:p></o:p></p>
<blockquote style="border:none;border-left:solid #CCCCCC 1.0pt;padding:0cm 0cm 0cm 6.0pt;margin-left:4.8pt;margin-right:0cm">
<p class="MsoNormal">Author: delena<br>
Date: Sat May 14 10:06:09 2016<br>
New Revision: 269569<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=269569&view=rev" target="_blank">
http://llvm.org/viewvc/llvm-project?rev=269569&view=rev</a><br>
Log:<br>
Fixed lowering of _comi_ intrinsics from all sets - SSE/SSE2/AVX/AVX-512<br>
<br>
Differential revision <a href="http://reviews.llvm.org/D19261" target="_blank">http://reviews.llvm.org/D19261</a><br>
<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h<br>
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll<br>
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=269569&r1=269568&r2=269569&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=269569&r1=269568&r2=269569&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat May 14 10:06:09 2016<br>
@@ -17503,30 +17503,66 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;<br>
SDValue LHS = Op.getOperand(1);<br>
SDValue RHS = Op.getOperand(2);<br>
- unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);<br>
- assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");<br>
- SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);<br>
- SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(X86CC, dl, MVT::i8), Cond);<br>
+ SDValue Comi = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);<br>
+ SDValue InvComi = DAG.getNode(IntrData->Opc0, dl, MVT::i32, RHS, LHS);<br>
+ SDValue SetCC;<br>
+ switch (CC) {<br>
+ case ISD::SETEQ: { // (ZF = 0 and PF = 0)<br>
+ SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
+ DAG.getConstant(X86::COND_E, dl, MVT::i8), Comi);<br>
+ SDValue SetNP = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
+ DAG.getConstant(X86::COND_NP, dl, MVT::i8),<br>
+ Comi);<br>
+ SetCC = DAG.getNode(ISD::AND, dl, MVT::i8, SetCC, SetNP);<br>
+ break;<br>
+ }<br>
+ case ISD::SETNE: { // (ZF = 1 or PF = 1)<br>
+ SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
+ DAG.getConstant(X86::COND_NE, dl, MVT::i8), Comi);<br>
+ SDValue SetP = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
+ DAG.getConstant(X86::COND_P, dl, MVT::i8),<br>
+ Comi);<br>
+ SetCC = DAG.getNode(ISD::OR, dl, MVT::i8, SetCC, SetP);<br>
+ break;<br>
+ }<br>
+ case ISD::SETGT: // (CF = 0 and ZF = 0)<br>
+ SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
+ DAG.getConstant(X86::COND_A, dl, MVT::i8), Comi);<br>
+ break;<br>
+ case ISD::SETLT: { // The condition is opposite to GT. Swap the operands.<br>
+ SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
+ DAG.getConstant(X86::COND_A, dl, MVT::i8), InvComi);<br>
+ break;<br>
+ }<br>
+ case ISD::SETGE: // CF = 0<br>
+ SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
+ DAG.getConstant(X86::COND_AE, dl, MVT::i8), Comi);<br>
+ break;<br>
+ case ISD::SETLE: // The condition is opposite to GE. Swap the operands.<br>
+ SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
+ DAG.getConstant(X86::COND_AE, dl, MVT::i8), InvComi);<br>
+ break;<br>
+ default:<br>
+ llvm_unreachable("Unexpected illegal condition!");<br>
+ }<br>
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);<br>
}<br>
case COMI_RM: { // Comparison intrinsics with Sae<br>
SDValue LHS = Op.getOperand(1);<br>
SDValue RHS = Op.getOperand(2);<br>
- SDValue CC = Op.getOperand(3);<br>
+ unsigned CondVal = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();<br>
SDValue Sae = Op.getOperand(4);<br>
- auto ComiType = TranslateX86ConstCondToX86CC(CC);<br>
- // choose between ordered and unordered (comi/ucomi)<br>
- unsigned comiOp = std::get<0>(ComiType) ? IntrData->Opc0 : IntrData->Opc1;<br>
- SDValue Cond;<br>
- if (cast<ConstantSDNode>(Sae)->getZExtValue() !=<br>
- X86::STATIC_ROUNDING::CUR_DIRECTION)<br>
- Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS, Sae);<br>
+<br>
+ SDValue FCmp;<br>
+ if (cast<ConstantSDNode>(Sae)->getZExtValue() ==<br>
+ X86::STATIC_ROUNDING::CUR_DIRECTION)<br>
+ FCmp = DAG.getNode(X86ISD::FSETCC, dl, MVT::i1, LHS, RHS,<br>
+ DAG.getConstant(CondVal, dl, MVT::i8));<br>
else<br>
- Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS);<br>
- SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(std::get<1>(ComiType), dl, MVT::i8), Cond);<br>
- return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);<br>
+ FCmp = DAG.getNode(X86ISD::FSETCC, dl, MVT::i1, LHS, RHS,<br>
+ DAG.getConstant(CondVal, dl, MVT::i8), Sae);<br>
+ // AnyExt just uses KMOVW %kreg, %r32; ZeroExt emits "and $1, %reg"<br>
+ return DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, FCmp);<br>
}<br>
case VSHIFT:<br>
return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=269569&r1=269568&r2=269569&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=269569&r1=269568&r2=269569&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h Sat May 14 10:06:09 2016<br>
@@ -2331,96 +2331,6 @@ static void verifyIntrinsicTables() {<br>
std::end(IntrinsicsWithChain)) &&<br>
"Intrinsic data tables should have unique entries");<br>
}<br>
-<br>
-// X86 specific compare constants.<br>
-// They must be kept in synch with avxintrin.h<br>
-#define _X86_CMP_EQ_OQ 0x00 /* Equal (ordered, non-signaling) */<br>
-#define _X86_CMP_LT_OS 0x01 /* Less-than (ordered, signaling) */<br>
-#define _X86_CMP_LE_OS 0x02 /* Less-than-or-equal (ordered, signaling) */<br>
-#define _X86_CMP_UNORD_Q 0x03 /* Unordered (non-signaling) */<br>
-#define _X86_CMP_NEQ_UQ 0x04 /* Not-equal (unordered, non-signaling) */<br>
-#define _X86_CMP_NLT_US 0x05 /* Not-less-than (unordered, signaling) */<br>
-#define _X86_CMP_NLE_US 0x06 /* Not-less-than-or-equal (unordered, signaling) */<br>
-#define _X86_CMP_ORD_Q 0x07 /* Ordered (nonsignaling) */<br>
-#define _X86_CMP_EQ_UQ 0x08 /* Equal (unordered, non-signaling) */<br>
-#define _X86_CMP_NGE_US 0x09 /* Not-greater-than-or-equal (unord, signaling) */<br>
-#define _X86_CMP_NGT_US 0x0a /* Not-greater-than (unordered, signaling) */<br>
-#define _X86_CMP_FALSE_OQ 0x0b /* False (ordered, non-signaling) */<br>
-#define _X86_CMP_NEQ_OQ 0x0c /* Not-equal (ordered, non-signaling) */<br>
-#define _X86_CMP_GE_OS 0x0d /* Greater-than-or-equal (ordered, signaling) */<br>
-#define _X86_CMP_GT_OS 0x0e /* Greater-than (ordered, signaling) */<br>
-#define _X86_CMP_TRUE_UQ 0x0f /* True (unordered, non-signaling) */<br>
-#define _X86_CMP_EQ_OS 0x10 /* Equal (ordered, signaling) */<br>
-#define _X86_CMP_LT_OQ 0x11 /* Less-than (ordered, non-signaling) */<br>
-#define _X86_CMP_LE_OQ 0x12 /* Less-than-or-equal (ordered, non-signaling) */<br>
-#define _X86_CMP_UNORD_S 0x13 /* Unordered (signaling) */<br>
-#define _X86_CMP_NEQ_US 0x14 /* Not-equal (unordered, signaling) */<br>
-#define _X86_CMP_NLT_UQ 0x15 /* Not-less-than (unordered, non-signaling) */<br>
-#define _X86_CMP_NLE_UQ 0x16 /* Not-less-than-or-equal (unord, non-signaling) */<br>
-#define _X86_CMP_ORD_S 0x17 /* Ordered (signaling) */<br>
-#define _X86_CMP_EQ_US 0x18 /* Equal (unordered, signaling) */<br>
-#define _X86_CMP_NGE_UQ 0x19 /* Not-greater-than-or-equal (unord, non-sign) */<br>
-#define _X86_CMP_NGT_UQ 0x1a /* Not-greater-than (unordered, non-signaling) */<br>
-#define _X86_CMP_FALSE_OS 0x1b /* False (ordered, signaling) */<br>
-#define _X86_CMP_NEQ_OS 0x1c /* Not-equal (ordered, signaling) */<br>
-#define _X86_CMP_GE_OQ 0x1d /* Greater-than-or-equal (ordered, non-signaling) */<br>
-#define _X86_CMP_GT_OQ 0x1e /* Greater-than (ordered, non-signaling) */<br>
-#define _X86_CMP_TRUE_US 0x1f /* True (unordered, signaling) */<br>
-<br>
-/*<br>
-* Get comparison modifier from _mm_comi_round_sd/ss intrinsic<br>
-* Return tuple <isOrdered, X86 condcode><br>
-*/<br>
-static std::tuple<bool,unsigned> TranslateX86ConstCondToX86CC(SDValue &imm) {<br>
- ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(imm);<br>
- unsigned IntImm = CImm->getZExtValue();<br>
- // On a floating point condition, the flags are set as follows:<br>
- // ZF PF CF op<br>
- // 0 | 0 | 0 | X > Y<br>
- // 0 | 0 | 1 | X < Y<br>
- // 1 | 0 | 0 | X == Y<br>
- // 1 | 1 | 1 | unordered<br>
- switch (IntImm) {<br>
- default: llvm_unreachable("Invalid floating point compare value for Comi!");<br>
- case _X86_CMP_EQ_OQ: // 0x00 - Equal (ordered, nonsignaling)<br>
- case _X86_CMP_EQ_OS: // 0x10 - Equal (ordered, signaling)<br>
- return std::make_tuple(true, X86::COND_E);<br>
- case _X86_CMP_EQ_UQ: // 0x08 - Equal (unordered, non-signaling)<br>
- case _X86_CMP_EQ_US: // 0x18 - Equal (unordered, signaling)<br>
- return std::make_tuple(false , X86::COND_E);<br>
- case _X86_CMP_LT_OS: // 0x01 - Less-than (ordered, signaling)<br>
- case _X86_CMP_LT_OQ: // 0x11 - Less-than (ordered, nonsignaling)<br>
- return std::make_tuple(true, X86::COND_B);<br>
- case _X86_CMP_NGE_US: // 0x09 - Not-greater-than-or-equal (unordered, signaling)<br>
- case _X86_CMP_NGE_UQ: // 0x19 - Not-greater-than-or-equal (unordered, nonsignaling)<br>
- return std::make_tuple(false , X86::COND_B);<br>
- case _X86_CMP_LE_OS: // 0x02 - Less-than-or-equal (ordered, signaling)<br>
- case _X86_CMP_LE_OQ: // 0x12 - Less-than-or-equal (ordered, nonsignaling)<br>
- return std::make_tuple(true, X86::COND_BE);<br>
- case _X86_CMP_NGT_US: // 0x0A - Not-greater-than (unordered, signaling)<br>
- case _X86_CMP_NGT_UQ: // 0x1A - Not-greater-than (unordered, nonsignaling)<br>
- return std::make_tuple(false, X86::COND_BE);<br>
- case _X86_CMP_GT_OS: // 0x0E - Greater-than (ordered, signaling)<br>
- case _X86_CMP_GT_OQ: // 0x1E - Greater-than (ordered, nonsignaling)<br>
- return std::make_tuple(true, X86::COND_A);<br>
- case _X86_CMP_NLE_US: // 0x06 - Not-less-than-or-equal (unordered,signaling)<br>
- case _X86_CMP_NLE_UQ: // 0x16 - Not-less-than-or-equal (unordered, nonsignaling)<br>
- return std::make_tuple(false, X86::COND_A);<br>
- case _X86_CMP_GE_OS: // 0x0D - Greater-than-or-equal (ordered, signaling)<br>
- case _X86_CMP_GE_OQ: // 0x1D - Greater-than-or-equal (ordered, nonsignaling)<br>
- return std::make_tuple(true, X86::COND_AE);<br>
- case _X86_CMP_NLT_US: // 0x05 - Not-less-than (unordered, signaling)<br>
- case _X86_CMP_NLT_UQ: // 0x15 - Not-less-than (unordered, nonsignaling)<br>
- return std::make_tuple(false, X86::COND_AE);<br>
- case _X86_CMP_NEQ_OQ: // 0x0C - Not-equal (ordered, non-signaling)<br>
- case _X86_CMP_NEQ_OS: // 0x1C - Not-equal (ordered, signaling)<br>
- return std::make_tuple(true, X86::COND_NE);<br>
- case _X86_CMP_NEQ_UQ: // 0x04 - Not-equal (unordered, nonsignaling)<br>
- case _X86_CMP_NEQ_US: // 0x14 - Not-equal (unordered, signaling)<br>
- return std::make_tuple(false, X86::COND_NE);<br>
- }<br>
-}<br>
-<br>
} // End llvm namespace<br>
<br>
#endif<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=269569&r1=269568&r2=269569&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=269569&r1=269568&r2=269569&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Sat May 14 10:06:09 2016<br>
@@ -104,8 +104,10 @@ define i32 @test_x86_sse2_comieq_sd(<2 x<br>
; CHECK-LABEL: test_x86_sse2_comieq_sd:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: vcomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: setnp %al<br>
+; CHECK-NEXT: sete %cl<br>
+; CHECK-NEXT: andb %al, %cl<br>
+; CHECK-NEXT: movzbl %cl, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comieq.sd" target="_blank">llvm.x86.sse2.comieq.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -142,8 +144,8 @@ declare i32 @<a href="http://llvm.x86.sse2.comigt.sd" target="_blank">llvm.x86.sse2.comigt.sd</a>(<2<br>
define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_sse2_comile_sd:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vcomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: setbe %al<br>
+; CHECK-NEXT: vcomisd %xmm0, %xmm1<br>
+; CHECK-NEXT: setae %al<br>
; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comile.sd" target="_blank">llvm.x86.sse2.comile.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
@@ -155,9 +157,9 @@ declare i32 @<a href="http://llvm.x86.sse2.comile.sd" target="_blank">llvm.x86.sse2.comile.sd</a>(<2<br>
define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_sse2_comilt_sd:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vcomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: sbbl %eax, %eax<br>
-; CHECK-NEXT: andl $1, %eax<br>
+; CHECK-NEXT: vcomisd %xmm0, %xmm1<br>
+; CHECK-NEXT: seta %al<br>
+; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comilt.sd" target="_blank">llvm.x86.sse2.comilt.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -169,8 +171,10 @@ define i32 @test_x86_sse2_comineq_sd(<2<br>
; CHECK-LABEL: test_x86_sse2_comineq_sd:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: vcomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: setne %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: setp %al<br>
+; CHECK-NEXT: setne %cl<br>
+; CHECK-NEXT: orb %al, %cl<br>
+; CHECK-NEXT: movzbl %cl, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comineq.sd" target="_blank">llvm.x86.sse2.comineq.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -912,8 +916,10 @@ define i32 @test_x86_sse2_ucomieq_sd(<2<br>
; CHECK-LABEL: test_x86_sse2_ucomieq_sd:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: vucomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: setnp %al<br>
+; CHECK-NEXT: sete %cl<br>
+; CHECK-NEXT: andb %al, %cl<br>
+; CHECK-NEXT: movzbl %cl, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomieq.sd" target="_blank">llvm.x86.sse2.ucomieq.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -950,8 +956,8 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomigt.sd" target="_blank">llvm.x86.sse2.ucomigt.sd</a>(<2<br>
define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_sse2_ucomile_sd:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vucomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: setbe %al<br>
+; CHECK-NEXT: vucomisd %xmm0, %xmm1<br>
+; CHECK-NEXT: setae %al<br>
; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomile.sd" target="_blank">llvm.x86.sse2.ucomile.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
@@ -963,9 +969,9 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomile.sd" target="_blank">llvm.x86.sse2.ucomile.sd</a>(<2<br>
define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_sse2_ucomilt_sd:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vucomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: sbbl %eax, %eax<br>
-; CHECK-NEXT: andl $1, %eax<br>
+; CHECK-NEXT: vucomisd %xmm0, %xmm1<br>
+; CHECK-NEXT: seta %al<br>
+; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomilt.sd" target="_blank">llvm.x86.sse2.ucomilt.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -977,8 +983,10 @@ define i32 @test_x86_sse2_ucomineq_sd(<2<br>
; CHECK-LABEL: test_x86_sse2_ucomineq_sd:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: vucomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: setne %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: setp %al<br>
+; CHECK-NEXT: setne %cl<br>
+; CHECK-NEXT: orb %al, %cl<br>
+; CHECK-NEXT: movzbl %cl, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomineq.sd" target="_blank">llvm.x86.sse2.ucomineq.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1699,8 +1707,10 @@ define i32 @test_x86_sse_comieq_ss(<4 x<br>
; CHECK-LABEL: test_x86_sse_comieq_ss:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: vcomiss %xmm1, %xmm0<br>
-; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: setnp %al<br>
+; CHECK-NEXT: sete %cl<br>
+; CHECK-NEXT: andb %al, %cl<br>
+; CHECK-NEXT: movzbl %cl, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1737,8 +1747,8 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x<br>
define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; CHECK-LABEL: test_x86_sse_comile_ss:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vcomiss %xmm1, %xmm0<br>
-; CHECK-NEXT: setbe %al<br>
+; CHECK-NEXT: vcomiss %xmm0, %xmm1<br>
+; CHECK-NEXT: setae %al<br>
; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
@@ -1750,9 +1760,9 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x<br>
define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; CHECK-LABEL: test_x86_sse_comilt_ss:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vcomiss %xmm1, %xmm0<br>
-; CHECK-NEXT: sbbl %eax, %eax<br>
-; CHECK-NEXT: andl $1, %eax<br>
+; CHECK-NEXT: vcomiss %xmm0, %xmm1<br>
+; CHECK-NEXT: seta %al<br>
+; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1764,8 +1774,10 @@ define i32 @test_x86_sse_comineq_ss(<4 x<br>
; CHECK-LABEL: test_x86_sse_comineq_ss:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: vcomiss %xmm1, %xmm0<br>
-; CHECK-NEXT: setne %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: setp %al<br>
+; CHECK-NEXT: setne %cl<br>
+; CHECK-NEXT: orb %al, %cl<br>
+; CHECK-NEXT: movzbl %cl, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2003,8 +2015,10 @@ define i32 @test_x86_sse_ucomieq_ss(<4 x<br>
; CHECK-LABEL: test_x86_sse_ucomieq_ss:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: vucomiss %xmm1, %xmm0<br>
-; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: setnp %al<br>
+; CHECK-NEXT: sete %cl<br>
+; CHECK-NEXT: andb %al, %cl<br>
+; CHECK-NEXT: movzbl %cl, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2041,8 +2055,8 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4<br>
define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; CHECK-LABEL: test_x86_sse_ucomile_ss:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vucomiss %xmm1, %xmm0<br>
-; CHECK-NEXT: setbe %al<br>
+; CHECK-NEXT: vucomiss %xmm0, %xmm1<br>
+; CHECK-NEXT: setae %al<br>
; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
@@ -2054,9 +2068,9 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4<br>
define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; CHECK-LABEL: test_x86_sse_ucomilt_ss:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vucomiss %xmm1, %xmm0<br>
-; CHECK-NEXT: sbbl %eax, %eax<br>
-; CHECK-NEXT: andl $1, %eax<br>
+; CHECK-NEXT: vucomiss %xmm0, %xmm1<br>
+; CHECK-NEXT: seta %al<br>
+; CHECK-NEXT: movzbl %al, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -2068,8 +2082,10 @@ define i32 @test_x86_sse_ucomineq_ss(<4<br>
; CHECK-LABEL: test_x86_sse_ucomineq_ss:<br>
; CHECK: ## BB#0:<br>
; CHECK-NEXT: vucomiss %xmm1, %xmm0<br>
-; CHECK-NEXT: setne %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: setp %al<br>
+; CHECK-NEXT: setne %cl<br>
+; CHECK-NEXT: orb %al, %cl<br>
+; CHECK-NEXT: movzbl %cl, %eax<br>
; CHECK-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=269569&r1=269568&r2=269569&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=269569&r1=269568&r2=269569&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Sat May 14 10:06:09 2016<br>
@@ -6307,9 +6307,8 @@ define <8 x double>@test_int_x86_avx512_<br>
define i32 @test_x86_avx512_comi_sd_eq_sae(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_comi_sd_eq_sae:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vcomisd {sae}, %xmm1, %xmm0<br>
-; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: vcmpeqsd {sae}, %xmm1, %xmm0, %k0<br>
+; CHECK-NEXT: kmovw %k0, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx512.vcomi.sd" target="_blank">llvm.x86.avx512.vcomi.sd</a>(<2 x double> %a0, <2 x double> %a1, i32 0, i32 8)<br>
ret i32 %res<br>
@@ -6318,9 +6317,8 @@ define i32 @test_x86_avx512_comi_sd_eq_s<br>
define i32 @test_x86_avx512_ucomi_sd_eq_sae(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_ucomi_sd_eq_sae:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vucomisd {sae}, %xmm1, %xmm0<br>
-; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: vcmpeq_uqsd {sae}, %xmm1, %xmm0, %k0<br>
+; CHECK-NEXT: kmovw %k0, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx512.vcomi.sd" target="_blank">llvm.x86.avx512.vcomi.sd</a>(<2 x double> %a0, <2 x double> %a1, i32 8, i32 8)<br>
ret i32 %res<br>
@@ -6329,9 +6327,8 @@ define i32 @test_x86_avx512_ucomi_sd_eq_<br>
define i32 @test_x86_avx512_comi_sd_eq(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_comi_sd_eq:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vcomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: vcmpeqsd %xmm1, %xmm0, %k0<br>
+; CHECK-NEXT: kmovw %k0, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx512.vcomi.sd" target="_blank">llvm.x86.avx512.vcomi.sd</a>(<2 x double> %a0, <2 x double> %a1, i32 0, i32 4)<br>
ret i32 %res<br>
@@ -6340,9 +6337,8 @@ define i32 @test_x86_avx512_comi_sd_eq(<<br>
define i32 @test_x86_avx512_ucomi_sd_eq(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_ucomi_sd_eq:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vucomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: sete %al<br>
-; CHECK-NEXT: movzbl %al, %eax<br>
+; CHECK-NEXT: vcmpeq_uqsd %xmm1, %xmm0, %k0<br>
+; CHECK-NEXT: kmovw %k0, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx512.vcomi.sd" target="_blank">llvm.x86.avx512.vcomi.sd</a>(<2 x double> %a0, <2 x double> %a1, i32 8, i32 4)<br>
ret i32 %res<br>
@@ -6351,9 +6347,8 @@ define i32 @test_x86_avx512_ucomi_sd_eq(<br>
define i32 @test_x86_avx512_comi_sd_lt_sae(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_comi_sd_lt_sae:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vcomisd {sae}, %xmm1, %xmm0<br>
-; CHECK-NEXT: sbbl %eax, %eax<br>
-; CHECK-NEXT: andl $1, %eax<br>
+; CHECK-NEXT: vcmpltsd {sae}, %xmm1, %xmm0, %k0<br>
+; CHECK-NEXT: kmovw %k0, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx512.vcomi.sd" target="_blank">llvm.x86.avx512.vcomi.sd</a>(<2 x double> %a0, <2 x double> %a1, i32 1, i32 8)<br>
ret i32 %res<br>
@@ -6362,9 +6357,8 @@ define i32 @test_x86_avx512_comi_sd_lt_s<br>
define i32 @test_x86_avx512_ucomi_sd_lt_sae(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_ucomi_sd_lt_sae:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vucomisd {sae}, %xmm1, %xmm0<br>
-; CHECK-NEXT: sbbl %eax, %eax<br>
-; CHECK-NEXT: andl $1, %eax<br>
+; CHECK-NEXT: vcmpngesd {sae}, %xmm1, %xmm0, %k0<br>
+; CHECK-NEXT: kmovw %k0, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx512.vcomi.sd" target="_blank">llvm.x86.avx512.vcomi.sd</a>(<2 x double> %a0, <2 x double> %a1, i32 9, i32 8)<br>
ret i32 %res<br>
@@ -6373,9 +6367,8 @@ define i32 @test_x86_avx512_ucomi_sd_lt_<br>
define i32 @test_x86_avx512_comi_sd_lt(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_comi_sd_lt:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vcomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: sbbl %eax, %eax<br>
-; CHECK-NEXT: andl $1, %eax<br>
+; CHECK-NEXT: vcmpltsd %xmm1, %xmm0, %k0<br>
+; CHECK-NEXT: kmovw %k0, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx512.vcomi.sd" target="_blank">llvm.x86.avx512.vcomi.sd</a>(<2 x double> %a0, <2 x double> %a1, i32 1, i32 4)<br>
ret i32 %res<br>
@@ -6384,9 +6377,8 @@ define i32 @test_x86_avx512_comi_sd_lt(<<br>
define i32 @test_x86_avx512_ucomi_sd_lt(<2 x double> %a0, <2 x double> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_ucomi_sd_lt:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vucomisd %xmm1, %xmm0<br>
-; CHECK-NEXT: sbbl %eax, %eax<br>
-; CHECK-NEXT: andl $1, %eax<br>
+; CHECK-NEXT: vcmpngesd %xmm1, %xmm0, %k0<br>
+; CHECK-NEXT: kmovw %k0, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @<a href="http://llvm.x86.avx512.vcomi.sd" target="_blank">llvm.x86.avx512.vcomi.sd</a>(<2 x double> %a0, <2 x double> %a1, i32 9, i32 4)<br>
ret i32 %res<br>
@@ -6397,9 +6389,8 @@ declare i32 @<a href="http://llvm.x86.avx512.vcomi.sd" target="_blank">llvm.x86.avx512.vcomi.sd</a>(<2<br>
define i32 @test_x86_avx512_ucomi_ss_lt(<4 x float> %a0, <4 x float> %a1) {<br>
; CHECK-LABEL: test_x86_avx512_ucomi_ss_lt:<br>
; CHECK: ## BB#0:<br>
-; CHECK-NEXT: vucomiss %xmm1, %xmm0<br>
-; CHECK-NEXT: sbbl %eax, %eax<br>
-; CHECK-NEXT: andl $1, %eax<br>
+; CHECK-NEXT: vcmpngess %xmm1, %xmm0, %k0<br>
+; CHECK-NEXT: kmovw %k0, %eax<br>
; CHECK-NEXT: retq<br>
%res = call i32 @llvm.x86.avx512.vcomi.ss(<4 x float> %a0, <4 x float> %a1, i32 9, i32 4)<br>
ret i32 %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll?rev=269569&r1=269568&r2=269569&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll?rev=269569&r1=269568&r2=269569&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-x86.ll Sat May 14 10:06:09 2016<br>
@@ -54,15 +54,19 @@ define i32 @test_x86_sse_comieq_ss(<4 x<br>
; SSE-LABEL: test_x86_sse_comieq_ss:<br>
; SSE: ## BB#0:<br>
; SSE-NEXT: comiss %xmm1, %xmm0<br>
-; SSE-NEXT: sete %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
+; SSE-NEXT: setnp %al<br>
+; SSE-NEXT: sete %cl<br>
+; SSE-NEXT: andb %al, %cl<br>
+; SSE-NEXT: movzbl %cl, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_comieq_ss:<br>
; KNL: ## BB#0:<br>
; KNL-NEXT: vcomiss %xmm1, %xmm0<br>
-; KNL-NEXT: sete %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
+; KNL-NEXT: setnp %al<br>
+; KNL-NEXT: sete %cl<br>
+; KNL-NEXT: andb %al, %cl<br>
+; KNL-NEXT: movzbl %cl, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -113,15 +117,15 @@ declare i32 @llvm.x86.sse.comigt.ss(<4 x<br>
define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_comile_ss:<br>
; SSE: ## BB#0:<br>
-; SSE-NEXT: comiss %xmm1, %xmm0<br>
-; SSE-NEXT: setbe %al<br>
+; SSE-NEXT: comiss %xmm0, %xmm1<br>
+; SSE-NEXT: setae %al<br>
; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_comile_ss:<br>
; KNL: ## BB#0:<br>
-; KNL-NEXT: vcomiss %xmm1, %xmm0<br>
-; KNL-NEXT: setbe %al<br>
+; KNL-NEXT: vcomiss %xmm0, %xmm1<br>
+; KNL-NEXT: setae %al<br>
; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
@@ -133,16 +137,16 @@ declare i32 @llvm.x86.sse.comile.ss(<4 x<br>
define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_comilt_ss:<br>
; SSE: ## BB#0:<br>
-; SSE-NEXT: comiss %xmm1, %xmm0<br>
-; SSE-NEXT: sbbl %eax, %eax<br>
-; SSE-NEXT: andl $1, %eax<br>
+; SSE-NEXT: comiss %xmm0, %xmm1<br>
+; SSE-NEXT: seta %al<br>
+; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_comilt_ss:<br>
; KNL: ## BB#0:<br>
-; KNL-NEXT: vcomiss %xmm1, %xmm0<br>
-; KNL-NEXT: sbbl %eax, %eax<br>
-; KNL-NEXT: andl $1, %eax<br>
+; KNL-NEXT: vcomiss %xmm0, %xmm1<br>
+; KNL-NEXT: seta %al<br>
+; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -154,15 +158,19 @@ define i32 @test_x86_sse_comineq_ss(<4 x<br>
; SSE-LABEL: test_x86_sse_comineq_ss:<br>
; SSE: ## BB#0:<br>
; SSE-NEXT: comiss %xmm1, %xmm0<br>
-; SSE-NEXT: setne %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
+; SSE-NEXT: setp %al<br>
+; SSE-NEXT: setne %cl<br>
+; SSE-NEXT: orb %al, %cl<br>
+; SSE-NEXT: movzbl %cl, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_comineq_ss:<br>
; KNL: ## BB#0:<br>
; KNL-NEXT: vcomiss %xmm1, %xmm0<br>
-; KNL-NEXT: setne %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
+; KNL-NEXT: setp %al<br>
+; KNL-NEXT: setne %cl<br>
+; KNL-NEXT: orb %al, %cl<br>
+; KNL-NEXT: movzbl %cl, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -504,15 +512,19 @@ define i32 @test_x86_sse_ucomieq_ss(<4 x<br>
; SSE-LABEL: test_x86_sse_ucomieq_ss:<br>
; SSE: ## BB#0:<br>
; SSE-NEXT: ucomiss %xmm1, %xmm0<br>
-; SSE-NEXT: sete %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
+; SSE-NEXT: setnp %al<br>
+; SSE-NEXT: sete %cl<br>
+; SSE-NEXT: andb %al, %cl<br>
+; SSE-NEXT: movzbl %cl, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_ucomieq_ss:<br>
; KNL: ## BB#0:<br>
; KNL-NEXT: vucomiss %xmm1, %xmm0<br>
-; KNL-NEXT: sete %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
+; KNL-NEXT: setnp %al<br>
+; KNL-NEXT: sete %cl<br>
+; KNL-NEXT: andb %al, %cl<br>
+; KNL-NEXT: movzbl %cl, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -563,15 +575,15 @@ declare i32 @llvm.x86.sse.ucomigt.ss(<4<br>
define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_ucomile_ss:<br>
; SSE: ## BB#0:<br>
-; SSE-NEXT: ucomiss %xmm1, %xmm0<br>
-; SSE-NEXT: setbe %al<br>
+; SSE-NEXT: ucomiss %xmm0, %xmm1<br>
+; SSE-NEXT: setae %al<br>
; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_ucomile_ss:<br>
; KNL: ## BB#0:<br>
-; KNL-NEXT: vucomiss %xmm1, %xmm0<br>
-; KNL-NEXT: setbe %al<br>
+; KNL-NEXT: vucomiss %xmm0, %xmm1<br>
+; KNL-NEXT: setae %al<br>
; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
@@ -583,16 +595,16 @@ declare i32 @llvm.x86.sse.ucomile.ss(<4<br>
define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) {<br>
; SSE-LABEL: test_x86_sse_ucomilt_ss:<br>
; SSE: ## BB#0:<br>
-; SSE-NEXT: ucomiss %xmm1, %xmm0<br>
-; SSE-NEXT: sbbl %eax, %eax<br>
-; SSE-NEXT: andl $1, %eax<br>
+; SSE-NEXT: ucomiss %xmm0, %xmm1<br>
+; SSE-NEXT: seta %al<br>
+; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_ucomilt_ss:<br>
; KNL: ## BB#0:<br>
-; KNL-NEXT: vucomiss %xmm1, %xmm0<br>
-; KNL-NEXT: sbbl %eax, %eax<br>
-; KNL-NEXT: andl $1, %eax<br>
+; KNL-NEXT: vucomiss %xmm0, %xmm1<br>
+; KNL-NEXT: seta %al<br>
+; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -604,15 +616,19 @@ define i32 @test_x86_sse_ucomineq_ss(<4<br>
; SSE-LABEL: test_x86_sse_ucomineq_ss:<br>
; SSE: ## BB#0:<br>
; SSE-NEXT: ucomiss %xmm1, %xmm0<br>
-; SSE-NEXT: setne %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
+; SSE-NEXT: setp %al<br>
+; SSE-NEXT: setne %cl<br>
+; SSE-NEXT: orb %al, %cl<br>
+; SSE-NEXT: movzbl %cl, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse_ucomineq_ss:<br>
; KNL: ## BB#0:<br>
; KNL-NEXT: vucomiss %xmm1, %xmm0<br>
-; KNL-NEXT: setne %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
+; KNL-NEXT: setp %al<br>
+; KNL-NEXT: setne %cl<br>
+; KNL-NEXT: orb %al, %cl<br>
+; KNL-NEXT: movzbl %cl, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=269569&r1=269568&r2=269569&view=diff" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll?rev=269569&r1=269568&r2=269569&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-x86.ll Sat May 14 10:06:09 2016<br>
@@ -54,15 +54,19 @@ define i32 @test_x86_sse2_comieq_sd(<2 x<br>
; SSE-LABEL: test_x86_sse2_comieq_sd:<br>
; SSE: ## BB#0:<br>
; SSE-NEXT: comisd %xmm1, %xmm0<br>
-; SSE-NEXT: sete %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
+; SSE-NEXT: setnp %al<br>
+; SSE-NEXT: sete %cl<br>
+; SSE-NEXT: andb %al, %cl<br>
+; SSE-NEXT: movzbl %cl, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse2_comieq_sd:<br>
; KNL: ## BB#0:<br>
; KNL-NEXT: vcomisd %xmm1, %xmm0<br>
-; KNL-NEXT: sete %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
+; KNL-NEXT: setnp %al<br>
+; KNL-NEXT: sete %cl<br>
+; KNL-NEXT: andb %al, %cl<br>
+; KNL-NEXT: movzbl %cl, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comieq.sd" target="_blank">llvm.x86.sse2.comieq.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -113,15 +117,15 @@ declare i32 @<a href="http://llvm.x86.sse2.comigt.sd" target="_blank">llvm.x86.sse2.comigt.sd</a>(<2<br>
define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; SSE-LABEL: test_x86_sse2_comile_sd:<br>
; SSE: ## BB#0:<br>
-; SSE-NEXT: comisd %xmm1, %xmm0<br>
-; SSE-NEXT: setbe %al<br>
+; SSE-NEXT: comisd %xmm0, %xmm1<br>
+; SSE-NEXT: setae %al<br>
; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse2_comile_sd:<br>
; KNL: ## BB#0:<br>
-; KNL-NEXT: vcomisd %xmm1, %xmm0<br>
-; KNL-NEXT: setbe %al<br>
+; KNL-NEXT: vcomisd %xmm0, %xmm1<br>
+; KNL-NEXT: setae %al<br>
; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comile.sd" target="_blank">llvm.x86.sse2.comile.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
@@ -133,16 +137,16 @@ declare i32 @<a href="http://llvm.x86.sse2.comile.sd" target="_blank">llvm.x86.sse2.comile.sd</a>(<2<br>
define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; SSE-LABEL: test_x86_sse2_comilt_sd:<br>
; SSE: ## BB#0:<br>
-; SSE-NEXT: comisd %xmm1, %xmm0<br>
-; SSE-NEXT: sbbl %eax, %eax<br>
-; SSE-NEXT: andl $1, %eax<br>
+; SSE-NEXT: comisd %xmm0, %xmm1<br>
+; SSE-NEXT: seta %al<br>
+; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse2_comilt_sd:<br>
; KNL: ## BB#0:<br>
-; KNL-NEXT: vcomisd %xmm1, %xmm0<br>
-; KNL-NEXT: sbbl %eax, %eax<br>
-; KNL-NEXT: andl $1, %eax<br>
+; KNL-NEXT: vcomisd %xmm0, %xmm1<br>
+; KNL-NEXT: seta %al<br>
+; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comilt.sd" target="_blank">llvm.x86.sse2.comilt.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -154,15 +158,19 @@ define i32 @test_x86_sse2_comineq_sd(<2<br>
; SSE-LABEL: test_x86_sse2_comineq_sd:<br>
; SSE: ## BB#0:<br>
; SSE-NEXT: comisd %xmm1, %xmm0<br>
-; SSE-NEXT: setne %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
+; SSE-NEXT: setp %al<br>
+; SSE-NEXT: setne %cl<br>
+; SSE-NEXT: orb %al, %cl<br>
+; SSE-NEXT: movzbl %cl, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse2_comineq_sd:<br>
; KNL: ## BB#0:<br>
; KNL-NEXT: vcomisd %xmm1, %xmm0<br>
-; KNL-NEXT: setne %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
+; KNL-NEXT: setp %al<br>
+; KNL-NEXT: setne %cl<br>
+; KNL-NEXT: orb %al, %cl<br>
+; KNL-NEXT: movzbl %cl, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.comineq.sd" target="_blank">llvm.x86.sse2.comineq.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1237,15 +1245,19 @@ define i32 @test_x86_sse2_ucomieq_sd(<2<br>
; SSE-LABEL: test_x86_sse2_ucomieq_sd:<br>
; SSE: ## BB#0:<br>
; SSE-NEXT: ucomisd %xmm1, %xmm0<br>
-; SSE-NEXT: sete %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
+; SSE-NEXT: setnp %al<br>
+; SSE-NEXT: sete %cl<br>
+; SSE-NEXT: andb %al, %cl<br>
+; SSE-NEXT: movzbl %cl, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse2_ucomieq_sd:<br>
; KNL: ## BB#0:<br>
; KNL-NEXT: vucomisd %xmm1, %xmm0<br>
-; KNL-NEXT: sete %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
+; KNL-NEXT: setnp %al<br>
+; KNL-NEXT: sete %cl<br>
+; KNL-NEXT: andb %al, %cl<br>
+; KNL-NEXT: movzbl %cl, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomieq.sd" target="_blank">llvm.x86.sse2.ucomieq.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1296,15 +1308,15 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomigt.sd" target="_blank">llvm.x86.sse2.ucomigt.sd</a>(<2<br>
define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; SSE-LABEL: test_x86_sse2_ucomile_sd:<br>
; SSE: ## BB#0:<br>
-; SSE-NEXT: ucomisd %xmm1, %xmm0<br>
-; SSE-NEXT: setbe %al<br>
+; SSE-NEXT: ucomisd %xmm0, %xmm1<br>
+; SSE-NEXT: setae %al<br>
; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse2_ucomile_sd:<br>
; KNL: ## BB#0:<br>
-; KNL-NEXT: vucomisd %xmm1, %xmm0<br>
-; KNL-NEXT: setbe %al<br>
+; KNL-NEXT: vucomisd %xmm0, %xmm1<br>
+; KNL-NEXT: setae %al<br>
; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomile.sd" target="_blank">llvm.x86.sse2.ucomile.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
@@ -1316,16 +1328,16 @@ declare i32 @<a href="http://llvm.x86.sse2.ucomile.sd" target="_blank">llvm.x86.sse2.ucomile.sd</a>(<2<br>
define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) {<br>
; SSE-LABEL: test_x86_sse2_ucomilt_sd:<br>
; SSE: ## BB#0:<br>
-; SSE-NEXT: ucomisd %xmm1, %xmm0<br>
-; SSE-NEXT: sbbl %eax, %eax<br>
-; SSE-NEXT: andl $1, %eax<br>
+; SSE-NEXT: ucomisd %xmm0, %xmm1<br>
+; SSE-NEXT: seta %al<br>
+; SSE-NEXT: movzbl %al, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse2_ucomilt_sd:<br>
; KNL: ## BB#0:<br>
-; KNL-NEXT: vucomisd %xmm1, %xmm0<br>
-; KNL-NEXT: sbbl %eax, %eax<br>
-; KNL-NEXT: andl $1, %eax<br>
+; KNL-NEXT: vucomisd %xmm0, %xmm1<br>
+; KNL-NEXT: seta %al<br>
+; KNL-NEXT: movzbl %al, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomilt.sd" target="_blank">llvm.x86.sse2.ucomilt.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
@@ -1337,15 +1349,19 @@ define i32 @test_x86_sse2_ucomineq_sd(<2<br>
; SSE-LABEL: test_x86_sse2_ucomineq_sd:<br>
; SSE: ## BB#0:<br>
; SSE-NEXT: ucomisd %xmm1, %xmm0<br>
-; SSE-NEXT: setne %al<br>
-; SSE-NEXT: movzbl %al, %eax<br>
+; SSE-NEXT: setp %al<br>
+; SSE-NEXT: setne %cl<br>
+; SSE-NEXT: orb %al, %cl<br>
+; SSE-NEXT: movzbl %cl, %eax<br>
; SSE-NEXT: retl<br>
;<br>
; KNL-LABEL: test_x86_sse2_ucomineq_sd:<br>
; KNL: ## BB#0:<br>
; KNL-NEXT: vucomisd %xmm1, %xmm0<br>
-; KNL-NEXT: setne %al<br>
-; KNL-NEXT: movzbl %al, %eax<br>
+; KNL-NEXT: setp %al<br>
+; KNL-NEXT: setne %cl<br>
+; KNL-NEXT: orb %al, %cl<br>
+; KNL-NEXT: movzbl %cl, %eax<br>
; KNL-NEXT: retl<br>
%res = call i32 @<a href="http://llvm.x86.sse2.ucomineq.sd" target="_blank">llvm.x86.sse2.ucomineq.sd</a>(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]<br>
ret i32 %res<br>
<br>
<br>
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